Annotation of qemu/target-mips/mips-defs.h, revision 1.1

1.1     ! root        1: #if !defined (__QEMU_MIPS_DEFS_H__)
        !             2: #define __QEMU_MIPS_DEFS_H__
        !             3: 
        !             4: /* If we want to use 64 bits host regs... */
        !             5: //#define USE_64BITS_REGS
        !             6: /* If we want to use host float regs... */
        !             7: //#define USE_HOST_FLOAT_REGS
        !             8: 
        !             9: enum {
        !            10:     MIPS_R4Kc = 0x00018000,
        !            11:     MIPS_R4Kp = 0x00018300,
        !            12: };
        !            13: 
        !            14: /* Emulate MIPS R4Kc for now */
        !            15: #define MIPS_CPU MIPS_R4Kc
        !            16: 
        !            17: #if (MIPS_CPU == MIPS_R4Kc)
        !            18: /* 32 bits target */
        !            19: #define TARGET_LONG_BITS 32
        !            20: /* real pages are variable size... */
        !            21: #define TARGET_PAGE_BITS 12
        !            22: /* Uses MIPS R4Kx ehancements to MIPS32 architecture */
        !            23: #define MIPS_USES_R4K_EXT
        !            24: /* Uses MIPS R4Kc TLB model */
        !            25: #define MIPS_USES_R4K_TLB
        !            26: #define MIPS_TLB_NB 16
        !            27: /* Have config1, runs in big-endian mode, uses TLB */
        !            28: #define MIPS_CONFIG0                                            \
        !            29: ((1 << CP0C0_M) | (0x000 << CP0C0_K23) | (0x000 << CP0C0_KU) |  \
        !            30:  (1 << CP0C0_BE) | (0x001 << CP0C0_MT) | (0x010 << CP0C0_K0))
        !            31: /* 16 TLBs, 64 sets Icache, 16 bytes Icache line, 2-way Icache,
        !            32:  * 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
        !            33:  * no performance counters, watch registers present, no code compression,
        !            34:  * EJTAG present, no FPU
        !            35:  */
        !            36: #define MIPS_CONFIG1                                            \
        !            37: ((15 << CP0C1_MMU) |                                            \
        !            38:  (0x000 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x01 << CP0C1_IA) | \
        !            39:  (0x000 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x01 << CP0C1_DA) | \
        !            40:  (0 << CP0C1_PC) | (1 << CP0C1_WR) | (0 << CP0C1_CA) |          \
        !            41:  (1 << CP0C1_EP) | (0 << CP0C1_FP))
        !            42: #elif defined (MIPS_CPU == MIPS_R4Kp)
        !            43: /* 32 bits target */
        !            44: #define TARGET_LONG_BITS 32
        !            45: /* real pages are variable size... */
        !            46: #define TARGET_PAGE_BITS 12
        !            47: /* Uses MIPS R4Kx ehancements to MIPS32 architecture */
        !            48: #define MIPS_USES_R4K_EXT
        !            49: /* Uses MIPS R4Km FPM MMU model */
        !            50: #define MIPS_USES_R4K_FPM
        !            51: #else
        !            52: #error "MIPS CPU not defined"
        !            53: /* Remainder for other flags */
        !            54: //#define TARGET_MIPS64
        !            55: //define MIPS_USES_FPU
        !            56: #endif
        !            57: 
        !            58: #endif /* !defined (__QEMU_MIPS_DEFS_H__) */

unix.superglobalmegacorp.com