File:  [Qemu by Fabrice Bellard] / qemu / target-mips / mips-defs.h
Revision 1.1.1.4 (vendor branch): download - view: text, annotated - select for diffs
Tue Apr 24 16:49:35 2018 UTC (2 years, 3 months ago) by root
Branches: qemu, MAIN
CVS tags: qemu0105, qemu0104, qemu0103, qemu0102, qemu0101, qemu0100, qemu0091, HEAD
qemu 0.9.1

    1: #if !defined (__QEMU_MIPS_DEFS_H__)
    2: #define __QEMU_MIPS_DEFS_H__
    3: 
    4: /* If we want to use host float regs... */
    5: //#define USE_HOST_FLOAT_REGS
    6: 
    7: /* Real pages are variable size... */
    8: #define TARGET_PAGE_BITS 12
    9: #define MIPS_TLB_MAX 128
   10: 
   11: #if defined(TARGET_MIPS64)
   12: #define TARGET_LONG_BITS 64
   13: #else
   14: #define TARGET_LONG_BITS 32
   15: #endif
   16: 
   17: /* Even MIPS32 can have 36 bits physical address space. */
   18: #define TARGET_PHYS_ADDR_BITS 64
   19: 
   20: /* Masks used to mark instructions to indicate which ISA level they
   21:    were introduced in. */
   22: #define		ISA_MIPS1	0x00000001
   23: #define		ISA_MIPS2	0x00000002
   24: #define		ISA_MIPS3	0x00000004
   25: #define		ISA_MIPS4	0x00000008
   26: #define		ISA_MIPS5	0x00000010
   27: #define		ISA_MIPS32	0x00000020
   28: #define		ISA_MIPS32R2	0x00000040
   29: #define		ISA_MIPS64	0x00000080
   30: #define		ISA_MIPS64R2	0x00000100
   31: 
   32: /* MIPS ASEs. */
   33: #define		ASE_MIPS16	0x00001000
   34: #define		ASE_MIPS3D	0x00002000
   35: #define		ASE_MDMX	0x00004000
   36: #define		ASE_DSP		0x00008000
   37: #define		ASE_DSPR2	0x00010000
   38: #define		ASE_MT		0x00020000
   39: #define		ASE_SMARTMIPS	0x00040000
   40: 
   41: /* Chip specific instructions. */
   42: #define		INSN_VR54XX	0x80000000
   43: 
   44: /* MIPS CPU defines. */
   45: #define		CPU_MIPS1	(ISA_MIPS1)
   46: #define		CPU_MIPS2	(CPU_MIPS1 | ISA_MIPS2)
   47: #define		CPU_MIPS3	(CPU_MIPS2 | ISA_MIPS3)
   48: #define		CPU_MIPS4	(CPU_MIPS3 | ISA_MIPS4)
   49: #define		CPU_VR54XX	(CPU_MIPS4 | INSN_VR54XX)
   50: 
   51: #define		CPU_MIPS5	(CPU_MIPS4 | ISA_MIPS5)
   52: 
   53: /* MIPS Technologies "Release 1" */
   54: #define		CPU_MIPS32	(CPU_MIPS2 | ISA_MIPS32)
   55: #define		CPU_MIPS64	(CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
   56: 
   57: /* MIPS Technologies "Release 2" */
   58: #define		CPU_MIPS32R2	(CPU_MIPS32 | ISA_MIPS32R2)
   59: #define		CPU_MIPS64R2	(CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
   60: 
   61: /* Strictly follow the architecture standard:
   62:    - Disallow "special" instruction handling for PMON/SPIM.
   63:    Note that we still maintain Count/Compare to match the host clock. */
   64: //#define MIPS_STRICT_STANDARD 1
   65: 
   66: #endif /* !defined (__QEMU_MIPS_DEFS_H__) */

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