--- qemu/target-mips/translate.c 2018/04/24 18:31:40 1.1.1.12 +++ qemu/target-mips/translate.c 2018/04/24 18:41:09 1.1.1.13 @@ -1066,7 +1066,7 @@ static void gen_ld (CPUState *env, Disas opn = "ld"; break; case OPC_LLD: - save_cpu_state(ctx, 0); + save_cpu_state(ctx, 1); op_ld_lld(t0, t0, ctx); gen_store_gpr(t0, rt); opn = "lld"; @@ -1086,7 +1086,7 @@ static void gen_ld (CPUState *env, Disas opn = "ldr"; break; case OPC_LDPC: - save_cpu_state(ctx, 1); + save_cpu_state(ctx, 0); tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); op_ld_ld(t0, t0, ctx); @@ -1095,7 +1095,7 @@ static void gen_ld (CPUState *env, Disas break; #endif case OPC_LWPC: - save_cpu_state(ctx, 1); + save_cpu_state(ctx, 0); tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); op_ld_lw(t0, t0, ctx); @@ -1153,6 +1153,7 @@ static void gen_ld (CPUState *env, Disas opn = "ll"; break; } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]); tcg_temp_free(t0); tcg_temp_free(t1); @@ -1212,6 +1213,7 @@ static void gen_st (DisasContext *ctx, u opn = "swr"; break; } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]); tcg_temp_free(t0); tcg_temp_free(t1); @@ -1236,7 +1238,7 @@ static void gen_st_cond (DisasContext *c switch (opc) { #if defined(TARGET_MIPS64) case OPC_SCD: - save_cpu_state(ctx, 0); + save_cpu_state(ctx, 1); op_st_scd(t1, t0, rt, ctx); opn = "scd"; break; @@ -1247,6 +1249,7 @@ static void gen_st_cond (DisasContext *c opn = "sc"; break; } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]); tcg_temp_free(t1); tcg_temp_free(t0); @@ -1312,6 +1315,7 @@ static void gen_flt_ldst (DisasContext * generate_exception(ctx, EXCP_RI); goto out; } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %d(%s)", opn, fregnames[ft], offset, regnames[base]); out: tcg_temp_free(t0); @@ -1412,6 +1416,7 @@ static void gen_arith_imm (CPUState *env break; #endif } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm); } @@ -1454,6 +1459,7 @@ static void gen_logic_imm (CPUState *env opn = "lui"; break; } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm); } @@ -1481,6 +1487,7 @@ static void gen_slt_imm (CPUState *env, opn = "sltiu"; break; } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm); tcg_temp_free(t0); } @@ -1572,6 +1579,7 @@ static void gen_shift_imm(CPUState *env, break; #endif } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm); tcg_temp_free(t0); } @@ -1752,6 +1760,7 @@ static void gen_arith (CPUState *env, Di opn = "mul"; break; } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); } @@ -1789,6 +1798,7 @@ static void gen_cond_move (CPUState *env tcg_gen_movi_tl(cpu_gpr[rd], 0); gen_set_label(l1); + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); } @@ -1849,6 +1859,7 @@ static void gen_logic (CPUState *env, ui opn = "xor"; break; } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); } @@ -1878,6 +1889,7 @@ static void gen_slt (CPUState *env, uint opn = "sltu"; break; } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); tcg_temp_free(t0); tcg_temp_free(t1); @@ -1958,6 +1970,7 @@ static void gen_shift (CPUState *env, Di break; #endif } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); tcg_temp_free(t0); tcg_temp_free(t1); @@ -1997,6 +2010,7 @@ static void gen_HILO (DisasContext *ctx, opn = "mtlo"; break; } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s", opn, regnames[reg]); } @@ -2229,6 +2243,7 @@ static void gen_muldiv (DisasContext *ct generate_exception(ctx, EXCP_RI); goto out; } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]); out: tcg_temp_free(t0); @@ -2308,6 +2323,7 @@ static void gen_mul_vr54xx (DisasContext goto out; } gen_store_gpr(t0, rd); + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); out: @@ -2348,6 +2364,7 @@ static void gen_cl (DisasContext *ctx, u break; #endif } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]); tcg_temp_free(t0); } @@ -2561,6 +2578,7 @@ static void gen_loongson_integer (DisasC #endif } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]); tcg_temp_free(t0); tcg_temp_free(t1); @@ -3392,8 +3410,10 @@ static void gen_mfc0 (CPUState *env, Dis gen_helper_mfc0_count(arg); if (use_icount) { gen_io_end(); - ctx->bstate = BS_STOP; } + /* Break the TB to be able to take timer interrupts immediately + after reading count. */ + ctx->bstate = BS_STOP; rn = "Count"; break; /* 6,7 are implementation dependent */ @@ -3730,6 +3750,7 @@ static void gen_mfc0 (CPUState *env, Dis default: goto die; } + (void)rn; /* avoid a compiler warning */ LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel); return; @@ -4320,6 +4341,7 @@ static void gen_mtc0 (CPUState *env, Dis default: goto die; } + (void)rn; /* avoid a compiler warning */ LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel); /* For simplicity assume that all writes can cause interrupts. */ if (use_icount) { @@ -4561,8 +4583,10 @@ static void gen_dmfc0 (CPUState *env, Di gen_helper_mfc0_count(arg); if (use_icount) { gen_io_end(); - ctx->bstate = BS_STOP; } + /* Break the TB to be able to take timer interrupts immediately + after reading count. */ + ctx->bstate = BS_STOP; rn = "Count"; break; /* 6,7 are implementation dependent */ @@ -4892,6 +4916,7 @@ static void gen_dmfc0 (CPUState *env, Di default: goto die; } + (void)rn; /* avoid a compiler warning */ LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel); return; @@ -5483,6 +5508,7 @@ static void gen_dmtc0 (CPUState *env, Di default: goto die; } + (void)rn; /* avoid a compiler warning */ LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel); /* For simplicity assume that all writes can cause interrupts. */ if (use_icount) { @@ -5943,6 +5969,7 @@ static void gen_cp0 (CPUState *env, Disa generate_exception(ctx, EXCP_RI); return; } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd); } #endif /* !CONFIG_USER_ONLY */ @@ -6052,6 +6079,7 @@ static void gen_compute_branch1 (CPUStat generate_exception (ctx, EXCP_RI); goto out; } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx, opn, ctx->hflags, btarget); ctx->btarget = btarget; @@ -6281,6 +6309,7 @@ static void gen_cp1 (DisasContext *ctx, generate_exception (ctx, EXCP_RI); goto out; } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s %s", opn, regnames[rt], fregnames[fs]); out: @@ -7608,6 +7637,7 @@ static void gen_farith (DisasContext *ct generate_exception (ctx, EXCP_RI); return; } + (void)opn; /* avoid a compiler warning */ switch (optype) { case BINOP: MIPS_DEBUG("%s %s, %s, %s", opn, fregnames[fd], fregnames[fs], fregnames[ft]); @@ -7720,6 +7750,7 @@ static void gen_flt3_ldst (DisasContext break; } tcg_temp_free(t0); + (void)opn; (void)store; /* avoid compiler warnings */ MIPS_DEBUG("%s %s, %s(%s)", opn, fregnames[store ? fs : fd], regnames[index], regnames[base]); } @@ -7993,6 +8024,7 @@ static void gen_flt3_arith (DisasContext generate_exception (ctx, EXCP_RI); return; } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %s, %s, %s", opn, fregnames[fd], fregnames[fr], fregnames[fs], fregnames[ft]); } @@ -9939,7 +9971,7 @@ static void gen_ldst_pair (DisasContext opn = "lwp"; break; case SWP: - save_cpu_state(ctx, 1); + save_cpu_state(ctx, 0); gen_load_gpr(t1, rd); op_st_sw(t1, t0, ctx); tcg_gen_movi_tl(t1, 4); @@ -9960,7 +9992,7 @@ static void gen_ldst_pair (DisasContext opn = "ldp"; break; case SDP: - save_cpu_state(ctx, 1); + save_cpu_state(ctx, 0); gen_load_gpr(t1, rd); op_st_sd(t1, t0, ctx); tcg_gen_movi_tl(t1, 8); @@ -9971,6 +10003,7 @@ static void gen_ldst_pair (DisasContext break; #endif } + (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s, %s, %d(%s)", opn, regnames[rd], offset, regnames[base]); tcg_temp_free(t0); tcg_temp_free(t1); @@ -12004,22 +12037,22 @@ static void decode_opc (CPUState *env, D switch (op2) { case OPC_DMT: check_insn(env, ctx, ASE_MT); - gen_helper_dmt(t0, t0); + gen_helper_dmt(t0); gen_store_gpr(t0, rt); break; case OPC_EMT: check_insn(env, ctx, ASE_MT); - gen_helper_emt(t0, t0); + gen_helper_emt(t0); gen_store_gpr(t0, rt); break; case OPC_DVPE: check_insn(env, ctx, ASE_MT); - gen_helper_dvpe(t0, t0); + gen_helper_dvpe(t0); gen_store_gpr(t0, rt); break; case OPC_EVPE: check_insn(env, ctx, ASE_MT); - gen_helper_evpe(t0, t0); + gen_helper_evpe(t0); gen_store_gpr(t0, rt); break; case OPC_DI: @@ -12421,8 +12454,7 @@ void gen_intermediate_code_pc (CPUState gen_intermediate_code_internal(env, tb, 1); } -static void fpu_dump_state(CPUState *env, FILE *f, - int (*fpu_fprintf)(FILE *f, const char *fmt, ...), +static void fpu_dump_state(CPUState *env, FILE *f, fprintf_function fpu_fprintf, int flags) { int i; @@ -12451,8 +12483,8 @@ static void fpu_dump_state(CPUState *env } while(0) - fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n", - env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, env->active_fpu.fp_status, + fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n", + env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, get_float_exception_flags(&env->active_fpu.fp_status)); for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { fpu_fprintf(f, "%3s: ", fregnames[i]); @@ -12470,7 +12502,7 @@ static void fpu_dump_state(CPUState *env static void cpu_mips_check_sign_extensions (CPUState *env, FILE *f, - int (*cpu_fprintf)(FILE *f, const char *fmt, ...), + fprintf_function cpu_fprintf, int flags) { int i; @@ -12496,8 +12528,7 @@ cpu_mips_check_sign_extensions (CPUState } #endif -void cpu_dump_state (CPUState *env, FILE *f, - int (*cpu_fprintf)(FILE *f, const char *fmt, ...), +void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf, int flags) { int i; @@ -12679,8 +12710,7 @@ void cpu_reset (CPUMIPSState *env) env->CP0_Random = env->tlb->nb_tlb - 1; env->tlb->tlb_in_use = env->tlb->nb_tlb; env->CP0_Wired = 0; - /* SMP not implemented */ - env->CP0_EBase = 0x80000000; + env->CP0_EBase = 0x80000000 | (env->cpu_index & 0x3FF); env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); /* vectored interrupts not implemented, timer on int 7, no performance counters. */