--- qemu/target-mips/translate.c 2018/04/24 18:31:40 1.1.1.12
+++ qemu/target-mips/translate.c 2018/04/24 19:52:19 1.1.1.16
@@ -20,17 +20,9 @@
* License along with this library; if not, see .
*/
-#include
-#include
-#include
-#include
-#include
-
#include "cpu.h"
-#include "exec-all.h"
#include "disas.h"
#include "tcg-op.h"
-#include "qemu-common.h"
#include "helper.h"
#define GEN_HELPER 1
@@ -610,7 +602,7 @@ static inline void gen_load_srsgpr (int
TCGv_i32 t2 = tcg_temp_new_i32();
TCGv_ptr addr = tcg_temp_new_ptr();
- tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
+ tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
tcg_gen_andi_i32(t2, t2, 0xf);
tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
@@ -633,7 +625,7 @@ static inline void gen_store_srsgpr (int
TCGv_ptr addr = tcg_temp_new_ptr();
gen_load_gpr(t0, from);
- tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
+ tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
tcg_gen_andi_i32(t2, t2, 0xf);
tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
@@ -650,28 +642,28 @@ static inline void gen_store_srsgpr (int
/* Floating point register moves. */
static inline void gen_load_fpr32 (TCGv_i32 t, int reg)
{
- tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
+ tcg_gen_ld_i32(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
}
static inline void gen_store_fpr32 (TCGv_i32 t, int reg)
{
- tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
+ tcg_gen_st_i32(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
}
static inline void gen_load_fpr32h (TCGv_i32 t, int reg)
{
- tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
+ tcg_gen_ld_i32(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
}
static inline void gen_store_fpr32h (TCGv_i32 t, int reg)
{
- tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
+ tcg_gen_st_i32(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
}
static inline void gen_load_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)
{
if (ctx->hflags & MIPS_HFLAG_F64) {
- tcg_gen_ld_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));
+ tcg_gen_ld_i64(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].d));
} else {
TCGv_i32 t0 = tcg_temp_new_i32();
TCGv_i32 t1 = tcg_temp_new_i32();
@@ -686,7 +678,7 @@ static inline void gen_load_fpr64 (Disas
static inline void gen_store_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)
{
if (ctx->hflags & MIPS_HFLAG_F64) {
- tcg_gen_st_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));
+ tcg_gen_st_i64(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].d));
} else {
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i32 t1 = tcg_temp_new_i32();
@@ -736,7 +728,7 @@ static inline void save_cpu_state (Disas
}
}
-static inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
+static inline void restore_cpu_state (CPUMIPSState *env, DisasContext *ctx)
{
ctx->saved_hflags = ctx->hflags;
switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
@@ -834,7 +826,7 @@ static inline void check_cp1_registers(D
/* This code generates a "reserved instruction" exception if the
CPU does not support the instruction set corresponding to flags. */
-static inline void check_insn(CPUState *env, DisasContext *ctx, int flags)
+static inline void check_insn(CPUMIPSState *env, DisasContext *ctx, int flags)
{
if (unlikely(!(env->insn_flags & flags)))
generate_exception(ctx, EXCP_RI);
@@ -948,8 +940,8 @@ static inline void op_ld_##insn(TCGv ret
TCGv t0 = tcg_temp_new(); \
tcg_gen_mov_tl(t0, arg1); \
tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
- tcg_gen_st_tl(ret, cpu_env, offsetof(CPUState, llval)); \
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \
+ tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); \
tcg_temp_free(t0); \
}
#else
@@ -975,14 +967,14 @@ static inline void op_st_##insn(TCGv arg
\
tcg_gen_andi_tl(t0, arg2, almask); \
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
- tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
+ tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); \
generate_exception(ctx, EXCP_AdES); \
gen_set_label(l1); \
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
+ tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \
tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \
- tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, llreg)); \
- tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUState, llnewval)); \
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, llreg)); \
+ tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUMIPSState, llnewval)); \
gen_helper_0i(raise_exception, EXCP_SC); \
gen_set_label(l2); \
tcg_gen_movi_tl(t0, 0); \
@@ -1033,7 +1025,7 @@ static target_ulong pc_relative_pc (Disa
}
/* Load */
-static void gen_ld (CPUState *env, DisasContext *ctx, uint32_t opc,
+static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
int rt, int base, int16_t offset)
{
const char *opn = "ld";
@@ -1066,7 +1058,7 @@ static void gen_ld (CPUState *env, Disas
opn = "ld";
break;
case OPC_LLD:
- save_cpu_state(ctx, 0);
+ save_cpu_state(ctx, 1);
op_ld_lld(t0, t0, ctx);
gen_store_gpr(t0, rt);
opn = "lld";
@@ -1086,7 +1078,7 @@ static void gen_ld (CPUState *env, Disas
opn = "ldr";
break;
case OPC_LDPC:
- save_cpu_state(ctx, 1);
+ save_cpu_state(ctx, 0);
tcg_gen_movi_tl(t1, pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
op_ld_ld(t0, t0, ctx);
@@ -1095,7 +1087,7 @@ static void gen_ld (CPUState *env, Disas
break;
#endif
case OPC_LWPC:
- save_cpu_state(ctx, 1);
+ save_cpu_state(ctx, 0);
tcg_gen_movi_tl(t1, pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
op_ld_lw(t0, t0, ctx);
@@ -1153,6 +1145,7 @@ static void gen_ld (CPUState *env, Disas
opn = "ll";
break;
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
tcg_temp_free(t0);
tcg_temp_free(t1);
@@ -1212,6 +1205,7 @@ static void gen_st (DisasContext *ctx, u
opn = "swr";
break;
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
tcg_temp_free(t0);
tcg_temp_free(t1);
@@ -1236,7 +1230,7 @@ static void gen_st_cond (DisasContext *c
switch (opc) {
#if defined(TARGET_MIPS64)
case OPC_SCD:
- save_cpu_state(ctx, 0);
+ save_cpu_state(ctx, 1);
op_st_scd(t1, t0, rt, ctx);
opn = "scd";
break;
@@ -1247,6 +1241,7 @@ static void gen_st_cond (DisasContext *c
opn = "sc";
break;
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
tcg_temp_free(t1);
tcg_temp_free(t0);
@@ -1312,12 +1307,13 @@ static void gen_flt_ldst (DisasContext *
generate_exception(ctx, EXCP_RI);
goto out;
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %d(%s)", opn, fregnames[ft], offset, regnames[base]);
out:
tcg_temp_free(t0);
}
-static void gen_cop1_ldst(CPUState *env, DisasContext *ctx,
+static void gen_cop1_ldst(CPUMIPSState *env, DisasContext *ctx,
uint32_t op, int rt, int rs, int16_t imm)
{
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
@@ -1329,7 +1325,7 @@ static void gen_cop1_ldst(CPUState *env,
}
/* Arithmetic with immediate operand */
-static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
+static void gen_arith_imm (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
int rt, int rs, int16_t imm)
{
target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
@@ -1412,11 +1408,12 @@ static void gen_arith_imm (CPUState *env
break;
#endif
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
}
/* Logic with immediate operand */
-static void gen_logic_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm)
+static void gen_logic_imm (CPUMIPSState *env, uint32_t opc, int rt, int rs, int16_t imm)
{
target_ulong uimm;
const char *opn = "imm logic";
@@ -1454,11 +1451,12 @@ static void gen_logic_imm (CPUState *env
opn = "lui";
break;
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
}
/* Set on less than with immediate operand */
-static void gen_slt_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm)
+static void gen_slt_imm (CPUMIPSState *env, uint32_t opc, int rt, int rs, int16_t imm)
{
target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
const char *opn = "imm arith";
@@ -1481,12 +1479,13 @@ static void gen_slt_imm (CPUState *env,
opn = "sltiu";
break;
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
tcg_temp_free(t0);
}
/* Shifts with immediate operand */
-static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
+static void gen_shift_imm(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
int rt, int rs, int16_t imm)
{
target_ulong uimm = ((uint16_t)imm) & 0x1f;
@@ -1572,12 +1571,13 @@ static void gen_shift_imm(CPUState *env,
break;
#endif
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
tcg_temp_free(t0);
}
/* Arithmetic */
-static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
+static void gen_arith (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
int rd, int rs, int rt)
{
const char *opn = "arith";
@@ -1752,11 +1752,12 @@ static void gen_arith (CPUState *env, Di
opn = "mul";
break;
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
}
/* Conditional move */
-static void gen_cond_move (CPUState *env, uint32_t opc, int rd, int rs, int rt)
+static void gen_cond_move (CPUMIPSState *env, uint32_t opc, int rd, int rs, int rt)
{
const char *opn = "cond move";
int l1;
@@ -1789,11 +1790,12 @@ static void gen_cond_move (CPUState *env
tcg_gen_movi_tl(cpu_gpr[rd], 0);
gen_set_label(l1);
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
}
/* Logic */
-static void gen_logic (CPUState *env, uint32_t opc, int rd, int rs, int rt)
+static void gen_logic (CPUMIPSState *env, uint32_t opc, int rd, int rs, int rt)
{
const char *opn = "logic";
@@ -1849,11 +1851,12 @@ static void gen_logic (CPUState *env, ui
opn = "xor";
break;
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
}
/* Set on lower than */
-static void gen_slt (CPUState *env, uint32_t opc, int rd, int rs, int rt)
+static void gen_slt (CPUMIPSState *env, uint32_t opc, int rd, int rs, int rt)
{
const char *opn = "slt";
TCGv t0, t1;
@@ -1878,13 +1881,14 @@ static void gen_slt (CPUState *env, uint
opn = "sltu";
break;
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
tcg_temp_free(t0);
tcg_temp_free(t1);
}
/* Shifts */
-static void gen_shift (CPUState *env, DisasContext *ctx, uint32_t opc,
+static void gen_shift (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
int rd, int rs, int rt)
{
const char *opn = "shifts";
@@ -1958,6 +1962,7 @@ static void gen_shift (CPUState *env, Di
break;
#endif
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
tcg_temp_free(t0);
tcg_temp_free(t1);
@@ -1997,6 +2002,7 @@ static void gen_HILO (DisasContext *ctx,
opn = "mtlo";
break;
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s", opn, regnames[reg]);
}
@@ -2229,6 +2235,7 @@ static void gen_muldiv (DisasContext *ct
generate_exception(ctx, EXCP_RI);
goto out;
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]);
out:
tcg_temp_free(t0);
@@ -2308,6 +2315,7 @@ static void gen_mul_vr54xx (DisasContext
goto out;
}
gen_store_gpr(t0, rd);
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
out:
@@ -2348,6 +2356,7 @@ static void gen_cl (DisasContext *ctx, u
break;
#endif
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]);
tcg_temp_free(t0);
}
@@ -2561,6 +2570,7 @@ static void gen_loongson_integer (DisasC
#endif
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]);
tcg_temp_free(t0);
tcg_temp_free(t1);
@@ -2668,7 +2678,7 @@ static inline void gen_goto_tb(DisasCont
likely(!ctx->singlestep_enabled)) {
tcg_gen_goto_tb(n);
gen_save_pc(dest);
- tcg_gen_exit_tb((long)tb + n);
+ tcg_gen_exit_tb((tcg_target_long)tb + n);
} else {
gen_save_pc(dest);
if (ctx->singlestep_enabled) {
@@ -3161,7 +3171,7 @@ static inline void gen_mtc0_store64 (TCG
tcg_gen_st_tl(arg, cpu_env, off);
}
-static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
+static void gen_mfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *rn = "invalid";
@@ -3172,7 +3182,7 @@ static void gen_mfc0 (CPUState *env, Dis
case 0:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
rn = "Index";
break;
case 1:
@@ -3202,37 +3212,37 @@ static void gen_mfc0 (CPUState *env, Dis
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
rn = "VPEControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
rn = "VPEConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
rn = "VPEConf1";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load64(arg, offsetof(CPUState, CP0_YQMask));
+ gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask));
rn = "YQMask";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPESchedule));
+ gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
rn = "VPESchedule";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPEScheFBack));
+ gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
rn = "VPEScheFBack";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
rn = "VPEOpt";
break;
default:
@@ -3242,7 +3252,7 @@ static void gen_mfc0 (CPUState *env, Dis
case 2:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
tcg_gen_ext32s_tl(arg, arg);
rn = "EntryLo0";
break;
@@ -3288,7 +3298,7 @@ static void gen_mfc0 (CPUState *env, Dis
case 3:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
tcg_gen_ext32s_tl(arg, arg);
rn = "EntryLo1";
break;
@@ -3299,7 +3309,7 @@ static void gen_mfc0 (CPUState *env, Dis
case 4:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
tcg_gen_ext32s_tl(arg, arg);
rn = "Context";
break;
@@ -3314,12 +3324,12 @@ static void gen_mfc0 (CPUState *env, Dis
case 5:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
rn = "PageMask";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
rn = "PageGrain";
break;
default:
@@ -3329,32 +3339,32 @@ static void gen_mfc0 (CPUState *env, Dis
case 6:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
rn = "Wired";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
rn = "SRSConf0";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
rn = "SRSConf1";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
rn = "SRSConf2";
break;
case 4:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
rn = "SRSConf3";
break;
case 5:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
rn = "SRSConf4";
break;
default:
@@ -3365,7 +3375,7 @@ static void gen_mfc0 (CPUState *env, Dis
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
rn = "HWREna";
break;
default:
@@ -3375,7 +3385,7 @@ static void gen_mfc0 (CPUState *env, Dis
case 8:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
tcg_gen_ext32s_tl(arg, arg);
rn = "BadVAddr";
break;
@@ -3392,8 +3402,10 @@ static void gen_mfc0 (CPUState *env, Dis
gen_helper_mfc0_count(arg);
if (use_icount) {
gen_io_end();
- ctx->bstate = BS_STOP;
}
+ /* Break the TB to be able to take timer interrupts immediately
+ after reading count. */
+ ctx->bstate = BS_STOP;
rn = "Count";
break;
/* 6,7 are implementation dependent */
@@ -3404,7 +3416,7 @@ static void gen_mfc0 (CPUState *env, Dis
case 10:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
tcg_gen_ext32s_tl(arg, arg);
rn = "EntryHi";
break;
@@ -3415,7 +3427,7 @@ static void gen_mfc0 (CPUState *env, Dis
case 11:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
rn = "Compare";
break;
/* 6,7 are implementation dependent */
@@ -3426,22 +3438,22 @@ static void gen_mfc0 (CPUState *env, Dis
case 12:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
rn = "Status";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
rn = "IntCtl";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
rn = "SRSCtl";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
rn = "SRSMap";
break;
default:
@@ -3451,7 +3463,7 @@ static void gen_mfc0 (CPUState *env, Dis
case 13:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
rn = "Cause";
break;
default:
@@ -3461,7 +3473,7 @@ static void gen_mfc0 (CPUState *env, Dis
case 14:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
tcg_gen_ext32s_tl(arg, arg);
rn = "EPC";
break;
@@ -3472,12 +3484,12 @@ static void gen_mfc0 (CPUState *env, Dis
case 15:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
rn = "PRid";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_EBase));
rn = "EBase";
break;
default:
@@ -3487,29 +3499,29 @@ static void gen_mfc0 (CPUState *env, Dis
case 16:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
rn = "Config";
break;
case 1:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
rn = "Config1";
break;
case 2:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
rn = "Config2";
break;
case 3:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
rn = "Config3";
break;
/* 4,5 are reserved */
/* 6,7 are implementation dependent */
case 6:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
rn = "Config6";
break;
case 7:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
rn = "Config7";
break;
default:
@@ -3551,7 +3563,7 @@ static void gen_mfc0 (CPUState *env, Dis
case 0:
#if defined(TARGET_MIPS64)
check_insn(env, ctx, ISA_MIPS3);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
tcg_gen_ext32s_tl(arg, arg);
rn = "XContext";
break;
@@ -3564,7 +3576,7 @@ static void gen_mfc0 (CPUState *env, Dis
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask));
rn = "Framemask";
break;
default:
@@ -3605,7 +3617,7 @@ static void gen_mfc0 (CPUState *env, Dis
switch (sel) {
case 0:
/* EJTAG support */
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
tcg_gen_ext32s_tl(arg, arg);
rn = "DEPC";
break;
@@ -3616,7 +3628,7 @@ static void gen_mfc0 (CPUState *env, Dis
case 25:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
rn = "Performance0";
break;
case 1:
@@ -3671,14 +3683,14 @@ static void gen_mfc0 (CPUState *env, Dis
case 2:
case 4:
case 6:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo));
rn = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
rn = "DataLo";
break;
default:
@@ -3691,14 +3703,14 @@ static void gen_mfc0 (CPUState *env, Dis
case 2:
case 4:
case 6:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
rn = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
rn = "DataHi";
break;
default:
@@ -3708,7 +3720,7 @@ static void gen_mfc0 (CPUState *env, Dis
case 30:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
tcg_gen_ext32s_tl(arg, arg);
rn = "ErrorEPC";
break;
@@ -3720,7 +3732,7 @@ static void gen_mfc0 (CPUState *env, Dis
switch (sel) {
case 0:
/* EJTAG support */
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
default:
@@ -3730,6 +3742,7 @@ static void gen_mfc0 (CPUState *env, Dis
default:
goto die;
}
+ (void)rn; /* avoid a compiler warning */
LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
return;
@@ -3738,7 +3751,7 @@ die:
generate_exception(ctx, EXCP_RI);
}
-static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
+static void gen_mtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *rn = "invalid";
@@ -3802,12 +3815,12 @@ static void gen_mtc0 (CPUState *env, Dis
break;
case 5:
check_insn(env, ctx, ASE_MT);
- gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPESchedule));
+ gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
rn = "VPESchedule";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPEScheFBack));
+ gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
rn = "VPEScheFBack";
break;
case 7:
@@ -4011,7 +4024,7 @@ static void gen_mtc0 (CPUState *env, Dis
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
+ gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "SRSMap";
@@ -4034,7 +4047,7 @@ static void gen_mtc0 (CPUState *env, Dis
case 14:
switch (sel) {
case 0:
- gen_mtc0_store64(arg, offsetof(CPUState, CP0_EPC));
+ gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_EPC));
rn = "EPC";
break;
default:
@@ -4194,7 +4207,7 @@ static void gen_mtc0 (CPUState *env, Dis
switch (sel) {
case 0:
/* EJTAG support */
- gen_mtc0_store64(arg, offsetof(CPUState, CP0_DEPC));
+ gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_DEPC));
rn = "DEPC";
break;
default:
@@ -4297,7 +4310,7 @@ static void gen_mtc0 (CPUState *env, Dis
case 30:
switch (sel) {
case 0:
- gen_mtc0_store64(arg, offsetof(CPUState, CP0_ErrorEPC));
+ gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_ErrorEPC));
rn = "ErrorEPC";
break;
default:
@@ -4308,7 +4321,7 @@ static void gen_mtc0 (CPUState *env, Dis
switch (sel) {
case 0:
/* EJTAG support */
- gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
+ gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
default:
@@ -4320,6 +4333,7 @@ static void gen_mtc0 (CPUState *env, Dis
default:
goto die;
}
+ (void)rn; /* avoid a compiler warning */
LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
/* For simplicity assume that all writes can cause interrupts. */
if (use_icount) {
@@ -4334,7 +4348,7 @@ die:
}
#if defined(TARGET_MIPS64)
-static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
+static void gen_dmfc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *rn = "invalid";
@@ -4345,7 +4359,7 @@ static void gen_dmfc0 (CPUState *env, Di
case 0:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
rn = "Index";
break;
case 1:
@@ -4375,37 +4389,37 @@ static void gen_dmfc0 (CPUState *env, Di
break;
case 1:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
rn = "VPEControl";
break;
case 2:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
rn = "VPEConf0";
break;
case 3:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
rn = "VPEConf1";
break;
case 4:
check_insn(env, ctx, ASE_MT);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_YQMask));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
rn = "YQMask";
break;
case 5:
check_insn(env, ctx, ASE_MT);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
rn = "VPESchedule";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
rn = "VPEScheFBack";
break;
case 7:
check_insn(env, ctx, ASE_MT);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
rn = "VPEOpt";
break;
default:
@@ -4415,7 +4429,7 @@ static void gen_dmfc0 (CPUState *env, Di
case 2:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
rn = "EntryLo0";
break;
case 1:
@@ -4460,7 +4474,7 @@ static void gen_dmfc0 (CPUState *env, Di
case 3:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
rn = "EntryLo1";
break;
default:
@@ -4470,7 +4484,7 @@ static void gen_dmfc0 (CPUState *env, Di
case 4:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
rn = "Context";
break;
case 1:
@@ -4484,12 +4498,12 @@ static void gen_dmfc0 (CPUState *env, Di
case 5:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
rn = "PageMask";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
rn = "PageGrain";
break;
default:
@@ -4499,32 +4513,32 @@ static void gen_dmfc0 (CPUState *env, Di
case 6:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
rn = "Wired";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
rn = "SRSConf0";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
rn = "SRSConf1";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
rn = "SRSConf2";
break;
case 4:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
rn = "SRSConf3";
break;
case 5:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
rn = "SRSConf4";
break;
default:
@@ -4535,7 +4549,7 @@ static void gen_dmfc0 (CPUState *env, Di
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
rn = "HWREna";
break;
default:
@@ -4545,7 +4559,7 @@ static void gen_dmfc0 (CPUState *env, Di
case 8:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
rn = "BadVAddr";
break;
default:
@@ -4561,8 +4575,10 @@ static void gen_dmfc0 (CPUState *env, Di
gen_helper_mfc0_count(arg);
if (use_icount) {
gen_io_end();
- ctx->bstate = BS_STOP;
}
+ /* Break the TB to be able to take timer interrupts immediately
+ after reading count. */
+ ctx->bstate = BS_STOP;
rn = "Count";
break;
/* 6,7 are implementation dependent */
@@ -4573,7 +4589,7 @@ static void gen_dmfc0 (CPUState *env, Di
case 10:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
rn = "EntryHi";
break;
default:
@@ -4583,7 +4599,7 @@ static void gen_dmfc0 (CPUState *env, Di
case 11:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
rn = "Compare";
break;
/* 6,7 are implementation dependent */
@@ -4594,22 +4610,22 @@ static void gen_dmfc0 (CPUState *env, Di
case 12:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
rn = "Status";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
rn = "IntCtl";
break;
case 2:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
rn = "SRSCtl";
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
rn = "SRSMap";
break;
default:
@@ -4619,7 +4635,7 @@ static void gen_dmfc0 (CPUState *env, Di
case 13:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
rn = "Cause";
break;
default:
@@ -4629,7 +4645,7 @@ static void gen_dmfc0 (CPUState *env, Di
case 14:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
rn = "EPC";
break;
default:
@@ -4639,12 +4655,12 @@ static void gen_dmfc0 (CPUState *env, Di
case 15:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
rn = "PRid";
break;
case 1:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_EBase));
rn = "EBase";
break;
default:
@@ -4654,28 +4670,28 @@ static void gen_dmfc0 (CPUState *env, Di
case 16:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
rn = "Config";
break;
case 1:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
rn = "Config1";
break;
case 2:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
rn = "Config2";
break;
case 3:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
rn = "Config3";
break;
/* 6,7 are implementation dependent */
case 6:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
rn = "Config6";
break;
case 7:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
rn = "Config7";
break;
default:
@@ -4716,7 +4732,7 @@ static void gen_dmfc0 (CPUState *env, Di
switch (sel) {
case 0:
check_insn(env, ctx, ISA_MIPS3);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
rn = "XContext";
break;
default:
@@ -4727,7 +4743,7 @@ static void gen_dmfc0 (CPUState *env, Di
/* Officially reserved, but sel 0 is used for R1x000 framemask */
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask));
rn = "Framemask";
break;
default:
@@ -4768,7 +4784,7 @@ static void gen_dmfc0 (CPUState *env, Di
switch (sel) {
case 0:
/* EJTAG support */
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
rn = "DEPC";
break;
default:
@@ -4778,7 +4794,7 @@ static void gen_dmfc0 (CPUState *env, Di
case 25:
switch (sel) {
case 0:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
rn = "Performance0";
break;
case 1:
@@ -4834,14 +4850,14 @@ static void gen_dmfc0 (CPUState *env, Di
case 2:
case 4:
case 6:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo));
rn = "TagLo";
break;
case 1:
case 3:
case 5:
case 7:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
rn = "DataLo";
break;
default:
@@ -4854,14 +4870,14 @@ static void gen_dmfc0 (CPUState *env, Di
case 2:
case 4:
case 6:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
rn = "TagHi";
break;
case 1:
case 3:
case 5:
case 7:
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
rn = "DataHi";
break;
default:
@@ -4871,7 +4887,7 @@ static void gen_dmfc0 (CPUState *env, Di
case 30:
switch (sel) {
case 0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
rn = "ErrorEPC";
break;
default:
@@ -4882,7 +4898,7 @@ static void gen_dmfc0 (CPUState *env, Di
switch (sel) {
case 0:
/* EJTAG support */
- gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
default:
@@ -4892,6 +4908,7 @@ static void gen_dmfc0 (CPUState *env, Di
default:
goto die;
}
+ (void)rn; /* avoid a compiler warning */
LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
return;
@@ -4900,7 +4917,7 @@ die:
generate_exception(ctx, EXCP_RI);
}
-static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
+static void gen_dmtc0 (CPUMIPSState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
{
const char *rn = "invalid";
@@ -4964,12 +4981,12 @@ static void gen_dmtc0 (CPUState *env, Di
break;
case 5:
check_insn(env, ctx, ASE_MT);
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
rn = "VPESchedule";
break;
case 6:
check_insn(env, ctx, ASE_MT);
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
rn = "VPEScheFBack";
break;
case 7:
@@ -5177,7 +5194,7 @@ static void gen_dmtc0 (CPUState *env, Di
break;
case 3:
check_insn(env, ctx, ISA_MIPS32R2);
- gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
+ gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "SRSMap";
@@ -5210,7 +5227,7 @@ static void gen_dmtc0 (CPUState *env, Di
case 14:
switch (sel) {
case 0:
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
rn = "EPC";
break;
default:
@@ -5357,7 +5374,7 @@ static void gen_dmtc0 (CPUState *env, Di
switch (sel) {
case 0:
/* EJTAG support */
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
rn = "DEPC";
break;
default:
@@ -5460,7 +5477,7 @@ static void gen_dmtc0 (CPUState *env, Di
case 30:
switch (sel) {
case 0:
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
rn = "ErrorEPC";
break;
default:
@@ -5471,7 +5488,7 @@ static void gen_dmtc0 (CPUState *env, Di
switch (sel) {
case 0:
/* EJTAG support */
- gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
+ gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
default:
@@ -5483,6 +5500,7 @@ static void gen_dmtc0 (CPUState *env, Di
default:
goto die;
}
+ (void)rn; /* avoid a compiler warning */
LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
/* For simplicity assume that all writes can cause interrupts. */
if (use_icount) {
@@ -5497,7 +5515,7 @@ die:
}
#endif /* TARGET_MIPS64 */
-static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
+static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
int u, int sel, int h)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
@@ -5512,6 +5530,19 @@ static void gen_mftr(CPUState *env, Disa
tcg_gen_movi_tl(t0, -1);
else if (u == 0) {
switch (rt) {
+ case 1:
+ switch (sel) {
+ case 1:
+ gen_helper_mftc0_vpecontrol(t0);
+ break;
+ case 2:
+ gen_helper_mftc0_vpeconf0(t0);
+ break;
+ default:
+ goto die;
+ break;
+ }
+ break;
case 2:
switch (sel) {
case 1:
@@ -5558,6 +5589,46 @@ static void gen_mftr(CPUState *env, Disa
gen_mfc0(env, ctx, t0, rt, sel);
break;
}
+ case 13:
+ switch (sel) {
+ case 0:
+ gen_helper_mftc0_cause(t0);
+ break;
+ default:
+ goto die;
+ break;
+ }
+ break;
+ case 14:
+ switch (sel) {
+ case 0:
+ gen_helper_mftc0_epc(t0);
+ break;
+ default:
+ goto die;
+ break;
+ }
+ break;
+ case 15:
+ switch (sel) {
+ case 1:
+ gen_helper_mftc0_ebase(t0);
+ break;
+ default:
+ goto die;
+ break;
+ }
+ break;
+ case 16:
+ switch (sel) {
+ case 0 ... 7:
+ gen_helper_mftc0_configx(t0, tcg_const_tl(sel));
+ break;
+ default:
+ goto die;
+ break;
+ }
+ break;
case 23:
switch (sel) {
case 0:
@@ -5661,7 +5732,7 @@ die:
generate_exception(ctx, EXCP_RI);
}
-static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
+static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
int u, int sel, int h)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
@@ -5677,6 +5748,19 @@ static void gen_mttr(CPUState *env, Disa
/* NOP */ ;
else if (u == 0) {
switch (rd) {
+ case 1:
+ switch (sel) {
+ case 1:
+ gen_helper_mttc0_vpecontrol(t0);
+ break;
+ case 2:
+ gen_helper_mttc0_vpeconf0(t0);
+ break;
+ default:
+ goto die;
+ break;
+ }
+ break;
case 2:
switch (sel) {
case 1:
@@ -5723,6 +5807,26 @@ static void gen_mttr(CPUState *env, Disa
gen_mtc0(env, ctx, t0, rd, sel);
break;
}
+ case 13:
+ switch (sel) {
+ case 0:
+ gen_helper_mttc0_cause(t0);
+ break;
+ default:
+ goto die;
+ break;
+ }
+ break;
+ case 15:
+ switch (sel) {
+ case 1:
+ gen_helper_mttc0_ebase(t0);
+ break;
+ default:
+ goto die;
+ break;
+ }
+ break;
case 23:
switch (sel) {
case 0:
@@ -5825,7 +5929,7 @@ die:
generate_exception(ctx, EXCP_RI);
}
-static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int rd)
+static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, int rd)
{
const char *opn = "ldst";
@@ -5943,12 +6047,13 @@ static void gen_cp0 (CPUState *env, Disa
generate_exception(ctx, EXCP_RI);
return;
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd);
}
#endif /* !CONFIG_USER_ONLY */
/* CP1 Branches (before delay slot) */
-static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
+static void gen_compute_branch1 (CPUMIPSState *env, DisasContext *ctx, uint32_t op,
int32_t cc, int32_t offset)
{
target_ulong btarget;
@@ -5994,7 +6099,7 @@ static void gen_compute_branch1 (CPUStat
TCGv_i32 t1 = tcg_temp_new_i32();
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
- tcg_gen_nor_i32(t0, t0, t1);
+ tcg_gen_nand_i32(t0, t0, t1);
tcg_temp_free_i32(t1);
tcg_gen_andi_i32(t0, t0, 1);
tcg_gen_extu_i32_tl(bcond, t0);
@@ -6018,11 +6123,11 @@ static void gen_compute_branch1 (CPUStat
TCGv_i32 t1 = tcg_temp_new_i32();
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
- tcg_gen_or_i32(t0, t0, t1);
+ tcg_gen_and_i32(t0, t0, t1);
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2));
- tcg_gen_or_i32(t0, t0, t1);
+ tcg_gen_and_i32(t0, t0, t1);
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3));
- tcg_gen_nor_i32(t0, t0, t1);
+ tcg_gen_nand_i32(t0, t0, t1);
tcg_temp_free_i32(t1);
tcg_gen_andi_i32(t0, t0, 1);
tcg_gen_extu_i32_tl(bcond, t0);
@@ -6052,6 +6157,7 @@ static void gen_compute_branch1 (CPUStat
generate_exception (ctx, EXCP_RI);
goto out;
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx, opn,
ctx->hflags, btarget);
ctx->btarget = btarget;
@@ -6281,6 +6387,7 @@ static void gen_cp1 (DisasContext *ctx,
generate_exception (ctx, EXCP_RI);
goto out;
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s %s", opn, regnames[rt], fregnames[fs]);
out:
@@ -7608,6 +7715,7 @@ static void gen_farith (DisasContext *ct
generate_exception (ctx, EXCP_RI);
return;
}
+ (void)opn; /* avoid a compiler warning */
switch (optype) {
case BINOP:
MIPS_DEBUG("%s %s, %s, %s", opn, fregnames[fd], fregnames[fs], fregnames[ft]);
@@ -7720,6 +7828,7 @@ static void gen_flt3_ldst (DisasContext
break;
}
tcg_temp_free(t0);
+ (void)opn; (void)store; /* avoid compiler warnings */
MIPS_DEBUG("%s %s, %s(%s)", opn, fregnames[store ? fs : fd],
regnames[index], regnames[base]);
}
@@ -7993,12 +8102,13 @@ static void gen_flt3_arith (DisasContext
generate_exception (ctx, EXCP_RI);
return;
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %s, %s, %s", opn, fregnames[fd], fregnames[fr],
fregnames[fs], fregnames[ft]);
}
static void
-gen_rdhwr (CPUState *env, DisasContext *ctx, int rt, int rd)
+gen_rdhwr (CPUMIPSState *env, DisasContext *ctx, int rt, int rd)
{
TCGv t0;
@@ -8028,7 +8138,7 @@ gen_rdhwr (CPUState *env, DisasContext *
break;
case 29:
#if defined(CONFIG_USER_ONLY)
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value));
+ tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUMIPSState, tls_value));
gen_store_gpr(t0, rt);
break;
#else
@@ -8043,7 +8153,7 @@ gen_rdhwr (CPUState *env, DisasContext *
tcg_temp_free(t0);
}
-static void handle_delay_slot (CPUState *env, DisasContext *ctx,
+static void handle_delay_slot (CPUMIPSState *env, DisasContext *ctx,
int insn_bytes)
{
if (ctx->hflags & MIPS_HFLAG_BMASK) {
@@ -8509,7 +8619,7 @@ static void gen_addiupc (DisasContext *c
}
#if defined(TARGET_MIPS64)
-static void decode_i64_mips16 (CPUState *env, DisasContext *ctx,
+static void decode_i64_mips16 (CPUMIPSState *env, DisasContext *ctx,
int ry, int funct, int16_t offset,
int extended)
{
@@ -8561,7 +8671,7 @@ static void decode_i64_mips16 (CPUState
}
#endif
-static int decode_extended_mips16_opc (CPUState *env, DisasContext *ctx,
+static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx,
int *is_branch)
{
int extend = lduw_code(ctx->pc + 2);
@@ -8753,7 +8863,7 @@ static int decode_extended_mips16_opc (C
return 4;
}
-static int decode_mips16_opc (CPUState *env, DisasContext *ctx,
+static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx,
int *is_branch)
{
int rx, ry;
@@ -9667,14 +9777,14 @@ static int mmreg2 (int r)
/* Zero-extended immediate */
#define ZIMM(op, start, width) ((op >> start) & ((~0U) >> (32-width)))
-static void gen_addiur1sp (CPUState *env, DisasContext *ctx)
+static void gen_addiur1sp (CPUMIPSState *env, DisasContext *ctx)
{
int rd = mmreg(uMIPS_RD(ctx->opcode));
gen_arith_imm(env, ctx, OPC_ADDIU, rd, 29, ((ctx->opcode >> 1) & 0x3f) << 2);
}
-static void gen_addiur2 (CPUState *env, DisasContext *ctx)
+static void gen_addiur2 (CPUMIPSState *env, DisasContext *ctx)
{
static const int decoded_imm[] = { 1, 4, 8, 12, 16, 20, 24, -1 };
int rd = mmreg(uMIPS_RD(ctx->opcode));
@@ -9683,7 +9793,7 @@ static void gen_addiur2 (CPUState *env,
gen_arith_imm(env, ctx, OPC_ADDIU, rd, rs, decoded_imm[ZIMM(ctx->opcode, 1, 3)]);
}
-static void gen_addiusp (CPUState *env, DisasContext *ctx)
+static void gen_addiusp (CPUMIPSState *env, DisasContext *ctx)
{
int encoded = ZIMM(ctx->opcode, 1, 9);
int decoded;
@@ -9701,7 +9811,7 @@ static void gen_addiusp (CPUState *env,
gen_arith_imm(env, ctx, OPC_ADDIU, 29, 29, decoded << 2);
}
-static void gen_addius5 (CPUState *env, DisasContext *ctx)
+static void gen_addius5 (CPUMIPSState *env, DisasContext *ctx)
{
int imm = SIMM(ctx->opcode, 1, 4);
int rd = (ctx->opcode >> 5) & 0x1f;
@@ -9709,7 +9819,7 @@ static void gen_addius5 (CPUState *env,
gen_arith_imm(env, ctx, OPC_ADDIU, rd, rd, imm);
}
-static void gen_andi16 (CPUState *env, DisasContext *ctx)
+static void gen_andi16 (CPUMIPSState *env, DisasContext *ctx)
{
static const int decoded_imm[] = { 128, 1, 2, 3, 4, 7, 8, 15, 16,
31, 32, 63, 64, 255, 32768, 65535 };
@@ -9762,7 +9872,7 @@ static void gen_ldst_multiple (DisasCont
}
-static void gen_pool16c_insn (CPUState *env, DisasContext *ctx, int *is_branch)
+static void gen_pool16c_insn (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
{
int rd = mmreg((ctx->opcode >> 3) & 0x7);
int rs = mmreg(ctx->opcode & 0x7);
@@ -9939,7 +10049,7 @@ static void gen_ldst_pair (DisasContext
opn = "lwp";
break;
case SWP:
- save_cpu_state(ctx, 1);
+ save_cpu_state(ctx, 0);
gen_load_gpr(t1, rd);
op_st_sw(t1, t0, ctx);
tcg_gen_movi_tl(t1, 4);
@@ -9960,7 +10070,7 @@ static void gen_ldst_pair (DisasContext
opn = "ldp";
break;
case SDP:
- save_cpu_state(ctx, 1);
+ save_cpu_state(ctx, 0);
gen_load_gpr(t1, rd);
op_st_sd(t1, t0, ctx);
tcg_gen_movi_tl(t1, 8);
@@ -9971,12 +10081,13 @@ static void gen_ldst_pair (DisasContext
break;
#endif
}
+ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s, %s, %d(%s)", opn, regnames[rd], offset, regnames[base]);
tcg_temp_free(t0);
tcg_temp_free(t1);
}
-static void gen_pool32axf (CPUState *env, DisasContext *ctx, int rt, int rs,
+static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs,
int *is_branch)
{
int extension = (ctx->opcode >> 6) & 0x3f;
@@ -10250,7 +10361,7 @@ enum {
FMT_DWL_L = 2
};
-static void gen_pool32fxf (CPUState *env, DisasContext *ctx, int rt, int rs)
+static void gen_pool32fxf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
{
int extension = (ctx->opcode >> 6) & 0x3ff;
uint32_t mips32_op;
@@ -10496,7 +10607,7 @@ static void gen_pool32fxf (CPUState *env
}
}
-static void decode_micromips32_opc (CPUState *env, DisasContext *ctx,
+static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx,
uint16_t insn_hw1, int *is_branch)
{
int32_t offset;
@@ -11254,7 +11365,7 @@ static void decode_micromips32_opc (CPUS
}
}
-static int decode_micromips_opc (CPUState *env, DisasContext *ctx, int *is_branch)
+static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
{
uint32_t op;
@@ -11571,7 +11682,7 @@ static int decode_micromips_opc (CPUStat
#endif
-static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch)
+static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
{
int32_t offset;
int rs, rt, rd, sa;
@@ -12004,22 +12115,22 @@ static void decode_opc (CPUState *env, D
switch (op2) {
case OPC_DMT:
check_insn(env, ctx, ASE_MT);
- gen_helper_dmt(t0, t0);
+ gen_helper_dmt(t0);
gen_store_gpr(t0, rt);
break;
case OPC_EMT:
check_insn(env, ctx, ASE_MT);
- gen_helper_emt(t0, t0);
+ gen_helper_emt(t0);
gen_store_gpr(t0, rt);
break;
case OPC_DVPE:
check_insn(env, ctx, ASE_MT);
- gen_helper_dvpe(t0, t0);
+ gen_helper_dvpe(t0);
gen_store_gpr(t0, rt);
break;
case OPC_EVPE:
check_insn(env, ctx, ASE_MT);
- gen_helper_evpe(t0, t0);
+ gen_helper_evpe(t0);
gen_store_gpr(t0, rt);
break;
case OPC_DI:
@@ -12258,7 +12369,7 @@ static void decode_opc (CPUState *env, D
}
static inline void
-gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
+gen_intermediate_code_internal (CPUMIPSState *env, TranslationBlock *tb,
int search_pc)
{
DisasContext ctx;
@@ -12411,18 +12522,17 @@ done_generating:
#endif
}
-void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
+void gen_intermediate_code (CPUMIPSState *env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 0);
}
-void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
+void gen_intermediate_code_pc (CPUMIPSState *env, struct TranslationBlock *tb)
{
gen_intermediate_code_internal(env, tb, 1);
}
-static void fpu_dump_state(CPUState *env, FILE *f,
- int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
+static void fpu_dump_state(CPUMIPSState *env, FILE *f, fprintf_function fpu_fprintf,
int flags)
{
int i;
@@ -12451,8 +12561,8 @@ static void fpu_dump_state(CPUState *env
} while(0)
- fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
- env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, env->active_fpu.fp_status,
+ fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n",
+ env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
get_float_exception_flags(&env->active_fpu.fp_status));
for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
fpu_fprintf(f, "%3s: ", fregnames[i]);
@@ -12469,8 +12579,8 @@ static void fpu_dump_state(CPUState *env
#define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
static void
-cpu_mips_check_sign_extensions (CPUState *env, FILE *f,
- int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
+cpu_mips_check_sign_extensions (CPUMIPSState *env, FILE *f,
+ fprintf_function cpu_fprintf,
int flags)
{
int i;
@@ -12496,8 +12606,7 @@ cpu_mips_check_sign_extensions (CPUState
}
#endif
-void cpu_dump_state (CPUState *env, FILE *f,
- int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
+void cpu_dump_state (CPUMIPSState *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
int i;
@@ -12539,36 +12648,36 @@ static void mips_tcg_init(void)
TCGV_UNUSED(cpu_gpr[0]);
for (i = 1; i < 32; i++)
cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, active_tc.gpr[i]),
+ offsetof(CPUMIPSState, active_tc.gpr[i]),
regnames[i]);
cpu_PC = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, active_tc.PC), "PC");
+ offsetof(CPUMIPSState, active_tc.PC), "PC");
for (i = 0; i < MIPS_DSP_ACC; i++) {
cpu_HI[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, active_tc.HI[i]),
+ offsetof(CPUMIPSState, active_tc.HI[i]),
regnames_HI[i]);
cpu_LO[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, active_tc.LO[i]),
+ offsetof(CPUMIPSState, active_tc.LO[i]),
regnames_LO[i]);
cpu_ACX[i] = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, active_tc.ACX[i]),
+ offsetof(CPUMIPSState, active_tc.ACX[i]),
regnames_ACX[i]);
}
cpu_dspctrl = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, active_tc.DSPControl),
+ offsetof(CPUMIPSState, active_tc.DSPControl),
"DSPControl");
bcond = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, bcond), "bcond");
+ offsetof(CPUMIPSState, bcond), "bcond");
btarget = tcg_global_mem_new(TCG_AREG0,
- offsetof(CPUState, btarget), "btarget");
+ offsetof(CPUMIPSState, btarget), "btarget");
hflags = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, hflags), "hflags");
+ offsetof(CPUMIPSState, hflags), "hflags");
fpu_fcr0 = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, active_fpu.fcr0),
+ offsetof(CPUMIPSState, active_fpu.fcr0),
"fcr0");
fpu_fcr31 = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUState, active_fpu.fcr31),
+ offsetof(CPUMIPSState, active_fpu.fcr31),
"fcr31");
/* register helpers */
@@ -12582,29 +12691,30 @@ static void mips_tcg_init(void)
CPUMIPSState *cpu_mips_init (const char *cpu_model)
{
+ MIPSCPU *cpu;
CPUMIPSState *env;
const mips_def_t *def;
def = cpu_mips_find_by_name(cpu_model);
if (!def)
return NULL;
- env = qemu_mallocz(sizeof(CPUMIPSState));
+ cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU));
+ env = &cpu->env;
env->cpu_model = def;
env->cpu_model_str = cpu_model;
- cpu_exec_init(env);
#ifndef CONFIG_USER_ONLY
mmu_init(env, def);
#endif
fpu_init(env, def);
mvp_init(env, def);
mips_tcg_init();
- cpu_reset(env);
+ cpu_state_reset(env);
qemu_init_vcpu(env);
return env;
}
-void cpu_reset (CPUMIPSState *env)
+void cpu_state_reset(CPUMIPSState *env)
{
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
@@ -12679,8 +12789,7 @@ void cpu_reset (CPUMIPSState *env)
env->CP0_Random = env->tlb->nb_tlb - 1;
env->tlb->tlb_in_use = env->tlb->nb_tlb;
env->CP0_Wired = 0;
- /* SMP not implemented */
- env->CP0_EBase = 0x80000000;
+ env->CP0_EBase = 0x80000000 | (env->cpu_index & 0x3FF);
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
/* vectored interrupts not implemented, timer on int 7,
no performance counters. */
@@ -12698,6 +12807,32 @@ void cpu_reset (CPUMIPSState *env)
/* Count register increments in debug mode, EJTAG version 1 */
env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
env->hflags = MIPS_HFLAG_CP0;
+
+ if (env->CP0_Config3 & (1 << CP0C3_MT)) {
+ int i;
+
+ /* Only TC0 on VPE 0 starts as active. */
+ for (i = 0; i < ARRAY_SIZE(env->tcs); i++) {
+ env->tcs[i].CP0_TCBind = env->cpu_index << CP0TCBd_CurVPE;
+ env->tcs[i].CP0_TCHalt = 1;
+ }
+ env->active_tc.CP0_TCHalt = 1;
+ env->halted = 1;
+
+ if (!env->cpu_index) {
+ /* VPE0 starts up enabled. */
+ env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
+ env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
+
+ /* TC0 starts up unhalted. */
+ env->halted = 0;
+ env->active_tc.CP0_TCHalt = 0;
+ env->tcs[0].CP0_TCHalt = 0;
+ /* With thread 0 active. */
+ env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A);
+ env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A);
+ }
+ }
#endif
#if defined(TARGET_MIPS64)
if (env->cpu_model->insn_flags & ISA_MIPS3) {
@@ -12707,8 +12842,7 @@ void cpu_reset (CPUMIPSState *env)
env->exception_index = EXCP_NONE;
}
-void gen_pc_load(CPUState *env, TranslationBlock *tb,
- unsigned long searched_pc, int pc_pos, void *puc)
+void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, int pc_pos)
{
env->active_tc.PC = gen_opc_pc[pc_pos];
env->hflags &= ~MIPS_HFLAG_BMASK;