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1.1 root 1: /*
2: * PowerPC emulation cpu definitions for qemu.
1.1.1.4 root 3: *
4: * Copyright (c) 2003-2007 Jocelyn Mayer
1.1 root 5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
1.1.1.6 root 17: * License along with this library; if not, see <http://www.gnu.org/licenses/>.
1.1 root 18: */
19: #if !defined (__CPU_PPC_H__)
20: #define __CPU_PPC_H__
21:
22: #include "config.h"
1.1.1.9 root 23: #include "qemu-common.h"
1.1.1.4 root 24:
25: //#define PPC_EMULATE_32BITS_HYPV
26:
27: #if defined (TARGET_PPC64)
28: /* PowerPC 64 definitions */
29: #define TARGET_LONG_BITS 64
30: #define TARGET_PAGE_BITS 12
31:
1.1.1.8 root 32: /* Note that the official physical address space bits is 62-M where M
33: is implementation dependent. I've not looked up M for the set of
34: cpus we emulate at the system level. */
35: #define TARGET_PHYS_ADDR_SPACE_BITS 62
36:
37: /* Note that the PPC environment architecture talks about 80 bit virtual
38: addresses, with segmentation. Obviously that's not all visible to a
39: single process, which is all we're concerned with here. */
40: #ifdef TARGET_ABI32
41: # define TARGET_VIRT_ADDR_SPACE_BITS 32
42: #else
43: # define TARGET_VIRT_ADDR_SPACE_BITS 64
44: #endif
45:
1.1.1.10 root 46: #define TARGET_PAGE_BITS_16M 24
47:
1.1.1.4 root 48: #else /* defined (TARGET_PPC64) */
49: /* PowerPC 32 definitions */
1.1 root 50: #define TARGET_LONG_BITS 32
51:
1.1.1.4 root 52: #if defined(TARGET_PPCEMB)
53: /* Specific definitions for PowerPC embedded */
54: /* BookE have 36 bits physical address space */
55: #if defined(CONFIG_USER_ONLY)
56: /* It looks like a lot of Linux programs assume page size
57: * is 4kB long. This is evil, but we have to deal with it...
58: */
59: #define TARGET_PAGE_BITS 12
60: #else /* defined(CONFIG_USER_ONLY) */
61: /* Pages can be 1 kB small */
62: #define TARGET_PAGE_BITS 10
63: #endif /* defined(CONFIG_USER_ONLY) */
64: #else /* defined(TARGET_PPCEMB) */
65: /* "standard" PowerPC 32 definitions */
66: #define TARGET_PAGE_BITS 12
67: #endif /* defined(TARGET_PPCEMB) */
68:
1.1.1.11 root 69: #define TARGET_PHYS_ADDR_SPACE_BITS 36
1.1.1.8 root 70: #define TARGET_VIRT_ADDR_SPACE_BITS 32
71:
1.1.1.4 root 72: #endif /* defined (TARGET_PPC64) */
73:
1.1.1.12! root 74: #define CPUArchState struct CPUPPCState
1.1.1.6 root 75:
1.1 root 76: #include "cpu-defs.h"
77:
78: #include "softfloat.h"
79:
80: #define TARGET_HAS_ICE 1
81:
1.1.1.6 root 82: #if defined (TARGET_PPC64)
1.1.1.4 root 83: #define ELF_MACHINE EM_PPC64
84: #else
85: #define ELF_MACHINE EM_PPC
86: #endif
1.1 root 87:
88: /*****************************************************************************/
1.1.1.4 root 89: /* MMU model */
90: typedef enum powerpc_mmu_t powerpc_mmu_t;
91: enum powerpc_mmu_t {
92: POWERPC_MMU_UNKNOWN = 0x00000000,
93: /* Standard 32 bits PowerPC MMU */
94: POWERPC_MMU_32B = 0x00000001,
95: /* PowerPC 6xx MMU with software TLB */
96: POWERPC_MMU_SOFT_6xx = 0x00000002,
97: /* PowerPC 74xx MMU with software TLB */
98: POWERPC_MMU_SOFT_74xx = 0x00000003,
99: /* PowerPC 4xx MMU with software TLB */
100: POWERPC_MMU_SOFT_4xx = 0x00000004,
101: /* PowerPC 4xx MMU with software TLB and zones protections */
102: POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
103: /* PowerPC MMU in real mode only */
104: POWERPC_MMU_REAL = 0x00000006,
105: /* Freescale MPC8xx MMU model */
106: POWERPC_MMU_MPC8xx = 0x00000007,
107: /* BookE MMU model */
108: POWERPC_MMU_BOOKE = 0x00000008,
1.1.1.10 root 109: /* BookE 2.06 MMU model */
110: POWERPC_MMU_BOOKE206 = 0x00000009,
1.1.1.4 root 111: /* PowerPC 601 MMU model (specific BATs format) */
112: POWERPC_MMU_601 = 0x0000000A,
113: #if defined(TARGET_PPC64)
114: #define POWERPC_MMU_64 0x00010000
1.1.1.10 root 115: #define POWERPC_MMU_1TSEG 0x00020000
1.1.1.4 root 116: /* 64 bits PowerPC MMU */
117: POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
118: /* 620 variant (no segment exceptions) */
119: POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
1.1.1.10 root 120: /* Architecture 2.06 variant */
121: POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | 0x00000003,
1.1.1.4 root 122: #endif /* defined(TARGET_PPC64) */
1.1 root 123: };
124:
1.1.1.4 root 125: /*****************************************************************************/
126: /* Exception model */
127: typedef enum powerpc_excp_t powerpc_excp_t;
128: enum powerpc_excp_t {
129: POWERPC_EXCP_UNKNOWN = 0,
130: /* Standard PowerPC exception model */
131: POWERPC_EXCP_STD,
132: /* PowerPC 40x exception model */
133: POWERPC_EXCP_40x,
134: /* PowerPC 601 exception model */
135: POWERPC_EXCP_601,
136: /* PowerPC 602 exception model */
137: POWERPC_EXCP_602,
138: /* PowerPC 603 exception model */
139: POWERPC_EXCP_603,
140: /* PowerPC 603e exception model */
141: POWERPC_EXCP_603E,
142: /* PowerPC G2 exception model */
143: POWERPC_EXCP_G2,
144: /* PowerPC 604 exception model */
145: POWERPC_EXCP_604,
146: /* PowerPC 7x0 exception model */
147: POWERPC_EXCP_7x0,
148: /* PowerPC 7x5 exception model */
149: POWERPC_EXCP_7x5,
150: /* PowerPC 74xx exception model */
151: POWERPC_EXCP_74xx,
152: /* BookE exception model */
153: POWERPC_EXCP_BOOKE,
154: #if defined(TARGET_PPC64)
155: /* PowerPC 970 exception model */
156: POWERPC_EXCP_970,
1.1.1.10 root 157: /* POWER7 exception model */
158: POWERPC_EXCP_POWER7,
1.1.1.4 root 159: #endif /* defined(TARGET_PPC64) */
1.1 root 160: };
161:
162: /*****************************************************************************/
1.1.1.4 root 163: /* Exception vectors definitions */
1.1 root 164: enum {
1.1.1.4 root 165: POWERPC_EXCP_NONE = -1,
166: /* The 64 first entries are used by the PowerPC embedded specification */
167: POWERPC_EXCP_CRITICAL = 0, /* Critical input */
168: POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
169: POWERPC_EXCP_DSI = 2, /* Data storage exception */
170: POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
171: POWERPC_EXCP_EXTERNAL = 4, /* External input */
172: POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
173: POWERPC_EXCP_PROGRAM = 6, /* Program exception */
174: POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
175: POWERPC_EXCP_SYSCALL = 8, /* System call exception */
176: POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
177: POWERPC_EXCP_DECR = 10, /* Decrementer exception */
178: POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
179: POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
180: POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
181: POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
182: POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
183: /* Vectors 16 to 31 are reserved */
184: POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
185: POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
186: POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
187: POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
188: POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
189: POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
1.1.1.12! root 190: POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
! 191: POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
! 192: POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
! 193: /* Vectors 42 to 63 are reserved */
1.1.1.4 root 194: /* Exceptions defined in the PowerPC server specification */
195: POWERPC_EXCP_RESET = 64, /* System reset exception */
196: POWERPC_EXCP_DSEG = 65, /* Data segment exception */
197: POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
198: POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
199: POWERPC_EXCP_TRACE = 68, /* Trace exception */
200: POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
201: POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
202: POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
203: POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
204: POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
205: /* 40x specific exceptions */
206: POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
207: /* 601 specific exceptions */
208: POWERPC_EXCP_IO = 75, /* IO error exception */
209: POWERPC_EXCP_RUNM = 76, /* Run mode exception */
210: /* 602 specific exceptions */
211: POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
212: /* 602/603 specific exceptions */
213: POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
214: POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
215: POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
216: /* Exceptions available on most PowerPC */
217: POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
218: POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
219: POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
220: POWERPC_EXCP_SMI = 84, /* System management interrupt */
221: POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
222: /* 7xx/74xx specific exceptions */
223: POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
224: /* 74xx specific exceptions */
225: POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
226: /* 970FX specific exceptions */
227: POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
228: POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
1.1.1.10 root 229: /* Freescale embedded cores specific exceptions */
1.1.1.4 root 230: POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
231: POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
232: POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
233: POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
234: /* EOL */
235: POWERPC_EXCP_NB = 96,
1.1.1.12! root 236: /* QEMU exceptions: used internally during code translation */
1.1.1.4 root 237: POWERPC_EXCP_STOP = 0x200, /* stop translation */
238: POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
1.1.1.12! root 239: /* QEMU exceptions: special cases we want to stop translation */
1.1.1.4 root 240: POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
241: POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
1.1.1.7 root 242: POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
1.1 root 243: };
244:
1.1.1.4 root 245: /* Exceptions error codes */
1.1 root 246: enum {
1.1.1.4 root 247: /* Exception subtypes for POWERPC_EXCP_ALIGN */
248: POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
249: POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
250: POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
251: POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
252: POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
253: POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
254: /* Exception subtypes for POWERPC_EXCP_PROGRAM */
255: /* FP exceptions */
256: POWERPC_EXCP_FP = 0x10,
257: POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
258: POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
259: POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
260: POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
261: POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
262: POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
263: POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
264: POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
265: POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
266: POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
267: POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
268: POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
269: POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
270: /* Invalid instruction */
271: POWERPC_EXCP_INVAL = 0x20,
272: POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
273: POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
274: POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
275: POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
276: /* Privileged instruction */
277: POWERPC_EXCP_PRIV = 0x30,
278: POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
279: POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
280: /* Trap */
281: POWERPC_EXCP_TRAP = 0x40,
282: };
283:
284: /*****************************************************************************/
285: /* Input pins model */
286: typedef enum powerpc_input_t powerpc_input_t;
287: enum powerpc_input_t {
288: PPC_FLAGS_INPUT_UNKNOWN = 0,
289: /* PowerPC 6xx bus */
290: PPC_FLAGS_INPUT_6xx,
291: /* BookE bus */
292: PPC_FLAGS_INPUT_BookE,
293: /* PowerPC 405 bus */
294: PPC_FLAGS_INPUT_405,
295: /* PowerPC 970 bus */
296: PPC_FLAGS_INPUT_970,
1.1.1.10 root 297: /* PowerPC POWER7 bus */
298: PPC_FLAGS_INPUT_POWER7,
1.1.1.4 root 299: /* PowerPC 401 bus */
300: PPC_FLAGS_INPUT_401,
301: /* Freescale RCPU bus */
302: PPC_FLAGS_INPUT_RCPU,
1.1 root 303: };
304:
1.1.1.4 root 305: #define PPC_INPUT(env) (env->bus_model)
1.1 root 306:
307: /*****************************************************************************/
308: typedef struct ppc_def_t ppc_def_t;
1.1.1.4 root 309: typedef struct opc_handler_t opc_handler_t;
1.1 root 310:
311: /*****************************************************************************/
312: /* Types used to describe some PowerPC registers */
313: typedef struct CPUPPCState CPUPPCState;
314: typedef struct ppc_tb_t ppc_tb_t;
315: typedef struct ppc_spr_t ppc_spr_t;
316: typedef struct ppc_dcr_t ppc_dcr_t;
1.1.1.4 root 317: typedef union ppc_avr_t ppc_avr_t;
318: typedef union ppc_tlb_t ppc_tlb_t;
1.1 root 319:
320: /* SPR access micro-ops generations callbacks */
321: struct ppc_spr_t {
1.1.1.5 root 322: void (*uea_read)(void *opaque, int gpr_num, int spr_num);
323: void (*uea_write)(void *opaque, int spr_num, int gpr_num);
1.1.1.4 root 324: #if !defined(CONFIG_USER_ONLY)
1.1.1.5 root 325: void (*oea_read)(void *opaque, int gpr_num, int spr_num);
326: void (*oea_write)(void *opaque, int spr_num, int gpr_num);
327: void (*hea_read)(void *opaque, int gpr_num, int spr_num);
328: void (*hea_write)(void *opaque, int spr_num, int gpr_num);
1.1.1.4 root 329: #endif
1.1.1.5 root 330: const char *name;
1.1 root 331: };
332:
333: /* Altivec registers (128 bits) */
1.1.1.4 root 334: union ppc_avr_t {
1.1.1.5 root 335: float32 f[4];
1.1.1.4 root 336: uint8_t u8[16];
337: uint16_t u16[8];
338: uint32_t u32[4];
1.1.1.5 root 339: int8_t s8[16];
340: int16_t s16[8];
341: int32_t s32[4];
1.1.1.4 root 342: uint64_t u64[2];
1.1 root 343: };
344:
1.1.1.8 root 345: #if !defined(CONFIG_USER_ONLY)
1.1 root 346: /* Software TLB cache */
1.1.1.4 root 347: typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
348: struct ppc6xx_tlb_t {
349: target_ulong pte0;
350: target_ulong pte1;
351: target_ulong EPN;
352: };
353:
354: typedef struct ppcemb_tlb_t ppcemb_tlb_t;
355: struct ppcemb_tlb_t {
1.1 root 356: target_phys_addr_t RPN;
1.1.1.4 root 357: target_ulong EPN;
358: target_ulong PID;
1.1 root 359: target_ulong size;
1.1.1.4 root 360: uint32_t prot;
361: uint32_t attr; /* Storage attributes */
362: };
363:
1.1.1.10 root 364: typedef struct ppcmas_tlb_t {
365: uint32_t mas8;
366: uint32_t mas1;
367: uint64_t mas2;
368: uint64_t mas7_3;
369: } ppcmas_tlb_t;
370:
1.1.1.4 root 371: union ppc_tlb_t {
1.1.1.10 root 372: ppc6xx_tlb_t *tlb6;
373: ppcemb_tlb_t *tlbe;
374: ppcmas_tlb_t *tlbm;
1.1 root 375: };
1.1.1.10 root 376:
377: /* possible TLB variants */
378: #define TLB_NONE 0
379: #define TLB_6XX 1
380: #define TLB_EMB 2
381: #define TLB_MAS 3
1.1.1.8 root 382: #endif
1.1 root 383:
1.1.1.10 root 384: #define SDR_32_HTABORG 0xFFFF0000UL
385: #define SDR_32_HTABMASK 0x000001FFUL
386:
387: #if defined(TARGET_PPC64)
388: #define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
389: #define SDR_64_HTABSIZE 0x000000000000001FULL
390: #endif /* defined(TARGET_PPC64 */
391:
392: #define HASH_PTE_SIZE_32 8
393: #define HASH_PTE_SIZE_64 16
394:
1.1.1.6 root 395: typedef struct ppc_slb_t ppc_slb_t;
396: struct ppc_slb_t {
1.1.1.10 root 397: uint64_t esid;
398: uint64_t vsid;
1.1.1.6 root 399: };
400:
1.1.1.10 root 401: /* Bits in the SLB ESID word */
402: #define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
403: #define SLB_ESID_V 0x0000000008000000ULL /* valid */
404:
405: /* Bits in the SLB VSID word */
406: #define SLB_VSID_SHIFT 12
407: #define SLB_VSID_SHIFT_1T 24
408: #define SLB_VSID_SSIZE_SHIFT 62
409: #define SLB_VSID_B 0xc000000000000000ULL
410: #define SLB_VSID_B_256M 0x0000000000000000ULL
411: #define SLB_VSID_B_1T 0x4000000000000000ULL
412: #define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
413: #define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID)
414: #define SLB_VSID_KS 0x0000000000000800ULL
415: #define SLB_VSID_KP 0x0000000000000400ULL
416: #define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
417: #define SLB_VSID_L 0x0000000000000100ULL
418: #define SLB_VSID_C 0x0000000000000080ULL /* class */
419: #define SLB_VSID_LP 0x0000000000000030ULL
420: #define SLB_VSID_ATTR 0x0000000000000FFFULL
421:
422: #define SEGMENT_SHIFT_256M 28
423: #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
424:
425: #define SEGMENT_SHIFT_1T 40
426: #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
427:
428:
1.1 root 429: /*****************************************************************************/
430: /* Machine state register bits definition */
1.1.1.4 root 431: #define MSR_SF 63 /* Sixty-four-bit mode hflags */
432: #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
1.1 root 433: #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
1.1.1.4 root 434: #define MSR_SHV 60 /* hypervisor state hflags */
435: #define MSR_CM 31 /* Computation mode for BookE hflags */
436: #define MSR_ICM 30 /* Interrupt computation mode for BookE */
437: #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
1.1.1.10 root 438: #define MSR_GS 28 /* guest state for BookE */
1.1.1.4 root 439: #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
440: #define MSR_VR 25 /* altivec available x hflags */
441: #define MSR_SPE 25 /* SPE enable for BookE x hflags */
442: #define MSR_AP 23 /* Access privilege state on 602 hflags */
443: #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
1.1 root 444: #define MSR_KEY 19 /* key bit on 603e */
445: #define MSR_POW 18 /* Power management */
1.1.1.4 root 446: #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
447: #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
1.1 root 448: #define MSR_ILE 16 /* Interrupt little-endian mode */
449: #define MSR_EE 15 /* External interrupt enable */
1.1.1.4 root 450: #define MSR_PR 14 /* Problem state hflags */
451: #define MSR_FP 13 /* Floating point available hflags */
1.1 root 452: #define MSR_ME 12 /* Machine check interrupt enable */
1.1.1.4 root 453: #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
454: #define MSR_SE 10 /* Single-step trace enable x hflags */
455: #define MSR_DWE 10 /* Debug wait enable on 405 x */
456: #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
457: #define MSR_BE 9 /* Branch trace enable x hflags */
458: #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
459: #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
1.1 root 460: #define MSR_AL 7 /* AL bit on POWER */
1.1.1.4 root 461: #define MSR_EP 6 /* Exception prefix on 601 */
1.1 root 462: #define MSR_IR 5 /* Instruction relocate */
463: #define MSR_DR 4 /* Data relocate */
464: #define MSR_PE 3 /* Protection enable on 403 */
1.1.1.4 root 465: #define MSR_PX 2 /* Protection exclusive on 403 x */
466: #define MSR_PMM 2 /* Performance monitor mark on POWER x */
467: #define MSR_RI 1 /* Recoverable interrupt 1 */
468: #define MSR_LE 0 /* Little-endian mode 1 hflags */
469:
470: #define msr_sf ((env->msr >> MSR_SF) & 1)
471: #define msr_isf ((env->msr >> MSR_ISF) & 1)
472: #define msr_shv ((env->msr >> MSR_SHV) & 1)
473: #define msr_cm ((env->msr >> MSR_CM) & 1)
474: #define msr_icm ((env->msr >> MSR_ICM) & 1)
475: #define msr_thv ((env->msr >> MSR_THV) & 1)
1.1.1.10 root 476: #define msr_gs ((env->msr >> MSR_GS) & 1)
1.1.1.4 root 477: #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
478: #define msr_vr ((env->msr >> MSR_VR) & 1)
1.1.1.5 root 479: #define msr_spe ((env->msr >> MSR_SPE) & 1)
1.1.1.4 root 480: #define msr_ap ((env->msr >> MSR_AP) & 1)
481: #define msr_sa ((env->msr >> MSR_SA) & 1)
482: #define msr_key ((env->msr >> MSR_KEY) & 1)
483: #define msr_pow ((env->msr >> MSR_POW) & 1)
484: #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
485: #define msr_ce ((env->msr >> MSR_CE) & 1)
486: #define msr_ile ((env->msr >> MSR_ILE) & 1)
487: #define msr_ee ((env->msr >> MSR_EE) & 1)
488: #define msr_pr ((env->msr >> MSR_PR) & 1)
489: #define msr_fp ((env->msr >> MSR_FP) & 1)
490: #define msr_me ((env->msr >> MSR_ME) & 1)
491: #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
492: #define msr_se ((env->msr >> MSR_SE) & 1)
493: #define msr_dwe ((env->msr >> MSR_DWE) & 1)
494: #define msr_uble ((env->msr >> MSR_UBLE) & 1)
495: #define msr_be ((env->msr >> MSR_BE) & 1)
496: #define msr_de ((env->msr >> MSR_DE) & 1)
497: #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
498: #define msr_al ((env->msr >> MSR_AL) & 1)
499: #define msr_ep ((env->msr >> MSR_EP) & 1)
500: #define msr_ir ((env->msr >> MSR_IR) & 1)
501: #define msr_dr ((env->msr >> MSR_DR) & 1)
502: #define msr_pe ((env->msr >> MSR_PE) & 1)
503: #define msr_px ((env->msr >> MSR_PX) & 1)
504: #define msr_pmm ((env->msr >> MSR_PMM) & 1)
505: #define msr_ri ((env->msr >> MSR_RI) & 1)
506: #define msr_le ((env->msr >> MSR_LE) & 1)
507: /* Hypervisor bit is more specific */
508: #if defined(TARGET_PPC64)
509: #define MSR_HVB (1ULL << MSR_SHV)
510: #define msr_hv msr_shv
511: #else
512: #if defined(PPC_EMULATE_32BITS_HYPV)
513: #define MSR_HVB (1ULL << MSR_THV)
514: #define msr_hv msr_thv
515: #else
516: #define MSR_HVB (0ULL)
517: #define msr_hv (0)
518: #endif
519: #endif
520:
1.1.1.9 root 521: /* Exception state register bits definition */
1.1.1.11 root 522: #define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
523: #define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
524: #define ESR_PTR (1 << (63 - 38)) /* Trap */
525: #define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
526: #define ESR_ST (1 << (63 - 40)) /* Store Operation */
527: #define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
528: #define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
529: #define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
530: #define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
531: #define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
532: #define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
533: #define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
534: #define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
535: #define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
536: #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
537: #define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
1.1.1.9 root 538:
1.1.1.4 root 539: enum {
540: POWERPC_FLAG_NONE = 0x00000000,
541: /* Flag for MSR bit 25 signification (VRE/SPE) */
542: POWERPC_FLAG_SPE = 0x00000001,
543: POWERPC_FLAG_VRE = 0x00000002,
544: /* Flag for MSR bit 17 signification (TGPR/CE) */
545: POWERPC_FLAG_TGPR = 0x00000004,
546: POWERPC_FLAG_CE = 0x00000008,
547: /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
548: POWERPC_FLAG_SE = 0x00000010,
549: POWERPC_FLAG_DWE = 0x00000020,
550: POWERPC_FLAG_UBLE = 0x00000040,
551: /* Flag for MSR bit 9 signification (BE/DE) */
552: POWERPC_FLAG_BE = 0x00000080,
553: POWERPC_FLAG_DE = 0x00000100,
554: /* Flag for MSR bit 2 signification (PX/PMM) */
555: POWERPC_FLAG_PX = 0x00000200,
556: POWERPC_FLAG_PMM = 0x00000400,
557: /* Flag for special features */
558: /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
559: POWERPC_FLAG_RTC_CLK = 0x00010000,
560: POWERPC_FLAG_BUS_CLK = 0x00020000,
1.1.1.11 root 561: /* Has CFAR */
562: POWERPC_FLAG_CFAR = 0x00040000,
1.1.1.4 root 563: };
564:
565: /*****************************************************************************/
566: /* Floating point status and control register */
567: #define FPSCR_FX 31 /* Floating-point exception summary */
568: #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
569: #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
570: #define FPSCR_OX 28 /* Floating-point overflow exception */
571: #define FPSCR_UX 27 /* Floating-point underflow exception */
572: #define FPSCR_ZX 26 /* Floating-point zero divide exception */
573: #define FPSCR_XX 25 /* Floating-point inexact exception */
574: #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
575: #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
576: #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
577: #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
578: #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
579: #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
580: #define FPSCR_FR 18 /* Floating-point fraction rounded */
581: #define FPSCR_FI 17 /* Floating-point fraction inexact */
582: #define FPSCR_C 16 /* Floating-point result class descriptor */
583: #define FPSCR_FL 15 /* Floating-point less than or negative */
584: #define FPSCR_FG 14 /* Floating-point greater than or negative */
585: #define FPSCR_FE 13 /* Floating-point equal or zero */
586: #define FPSCR_FU 12 /* Floating-point unordered or NaN */
587: #define FPSCR_FPCC 12 /* Floating-point condition code */
588: #define FPSCR_FPRF 12 /* Floating-point result flags */
589: #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
590: #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
591: #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
592: #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
593: #define FPSCR_OE 6 /* Floating-point overflow exception enable */
594: #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
595: #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
596: #define FPSCR_XE 3 /* Floating-point inexact exception enable */
597: #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
598: #define FPSCR_RN1 1
599: #define FPSCR_RN 0 /* Floating-point rounding control */
600: #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
601: #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
602: #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
603: #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
604: #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
605: #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
606: #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
607: #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
608: #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
609: #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
610: #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
611: #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
612: #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
613: #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
614: #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
615: #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
616: #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
617: #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
618: #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
619: #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
620: #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
621: #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
622: #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
623: /* Invalid operation exception summary */
624: #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
625: (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
626: (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
627: (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
628: (1 << FPSCR_VXCVI)))
629: /* exception summary */
630: #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
631: /* enabled exception summary */
632: #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
633: 0x1F)
1.1 root 634:
635: /*****************************************************************************/
1.1.1.5 root 636: /* Vector status and control register */
637: #define VSCR_NJ 16 /* Vector non-java */
638: #define VSCR_SAT 0 /* Vector saturation */
639: #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
640: #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
641:
642: /*****************************************************************************/
1.1.1.10 root 643: /* BookE e500 MMU registers */
644:
645: #define MAS0_NV_SHIFT 0
646: #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
647:
648: #define MAS0_WQ_SHIFT 12
649: #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
650: /* Write TLB entry regardless of reservation */
651: #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
652: /* Write TLB entry only already in use */
653: #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
654: /* Clear TLB entry */
655: #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
656:
657: #define MAS0_HES_SHIFT 14
658: #define MAS0_HES (1 << MAS0_HES_SHIFT)
659:
660: #define MAS0_ESEL_SHIFT 16
661: #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
662:
663: #define MAS0_TLBSEL_SHIFT 28
664: #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
665: #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
666: #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
667: #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
668: #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
669:
670: #define MAS0_ATSEL_SHIFT 31
671: #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
672: #define MAS0_ATSEL_TLB 0
673: #define MAS0_ATSEL_LRAT MAS0_ATSEL
674:
1.1.1.11 root 675: #define MAS1_TSIZE_SHIFT 7
676: #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
1.1.1.10 root 677:
678: #define MAS1_TS_SHIFT 12
679: #define MAS1_TS (1 << MAS1_TS_SHIFT)
680:
681: #define MAS1_IND_SHIFT 13
682: #define MAS1_IND (1 << MAS1_IND_SHIFT)
683:
684: #define MAS1_TID_SHIFT 16
685: #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
686:
687: #define MAS1_IPROT_SHIFT 30
688: #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
689:
690: #define MAS1_VALID_SHIFT 31
691: #define MAS1_VALID 0x80000000
692:
693: #define MAS2_EPN_SHIFT 12
694: #define MAS2_EPN_MASK (0xfffff << MAS2_EPN_SHIFT)
695:
696: #define MAS2_ACM_SHIFT 6
697: #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
698:
699: #define MAS2_VLE_SHIFT 5
700: #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
701:
702: #define MAS2_W_SHIFT 4
703: #define MAS2_W (1 << MAS2_W_SHIFT)
704:
705: #define MAS2_I_SHIFT 3
706: #define MAS2_I (1 << MAS2_I_SHIFT)
707:
708: #define MAS2_M_SHIFT 2
709: #define MAS2_M (1 << MAS2_M_SHIFT)
710:
711: #define MAS2_G_SHIFT 1
712: #define MAS2_G (1 << MAS2_G_SHIFT)
713:
714: #define MAS2_E_SHIFT 0
715: #define MAS2_E (1 << MAS2_E_SHIFT)
716:
717: #define MAS3_RPN_SHIFT 12
718: #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
719:
720: #define MAS3_U0 0x00000200
721: #define MAS3_U1 0x00000100
722: #define MAS3_U2 0x00000080
723: #define MAS3_U3 0x00000040
724: #define MAS3_UX 0x00000020
725: #define MAS3_SX 0x00000010
726: #define MAS3_UW 0x00000008
727: #define MAS3_SW 0x00000004
728: #define MAS3_UR 0x00000002
729: #define MAS3_SR 0x00000001
730: #define MAS3_SPSIZE_SHIFT 1
731: #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
732:
733: #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
734: #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
735: #define MAS4_TIDSELD_MASK 0x00030000
736: #define MAS4_TIDSELD_PID0 0x00000000
737: #define MAS4_TIDSELD_PID1 0x00010000
738: #define MAS4_TIDSELD_PID2 0x00020000
739: #define MAS4_TIDSELD_PIDZ 0x00030000
740: #define MAS4_INDD 0x00008000 /* Default IND */
741: #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
742: #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
743: #define MAS4_ACMD 0x00000040
744: #define MAS4_VLED 0x00000020
745: #define MAS4_WD 0x00000010
746: #define MAS4_ID 0x00000008
747: #define MAS4_MD 0x00000004
748: #define MAS4_GD 0x00000002
749: #define MAS4_ED 0x00000001
750: #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
751: #define MAS4_WIMGED_SHIFT 0
752:
753: #define MAS5_SGS 0x80000000
754: #define MAS5_SLPID_MASK 0x00000fff
755:
756: #define MAS6_SPID0 0x3fff0000
757: #define MAS6_SPID1 0x00007ffe
758: #define MAS6_ISIZE(x) MAS1_TSIZE(x)
759: #define MAS6_SAS 0x00000001
760: #define MAS6_SPID MAS6_SPID0
761: #define MAS6_SIND 0x00000002 /* Indirect page */
762: #define MAS6_SIND_SHIFT 1
763: #define MAS6_SPID_MASK 0x3fff0000
764: #define MAS6_SPID_SHIFT 16
765: #define MAS6_ISIZE_MASK 0x00000f80
766: #define MAS6_ISIZE_SHIFT 7
767:
768: #define MAS7_RPN 0xffffffff
769:
770: #define MAS8_TGS 0x80000000
771: #define MAS8_VF 0x40000000
772: #define MAS8_TLBPID 0x00000fff
773:
774: /* Bit definitions for MMUCFG */
775: #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
776: #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
777: #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
778: #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
779: #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
780: #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
781: #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
782: #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
783: #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
784:
785: /* Bit definitions for MMUCSR0 */
786: #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
787: #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
788: #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
789: #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
790: #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
791: MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
792: #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
793: #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
794: #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
795: #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
796:
797: /* TLBnCFG encoding */
798: #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
799: #define TLBnCFG_HES 0x00002000 /* HW select supported */
800: #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
801: #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
802: #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
803: #define TLBnCFG_IND 0x00020000 /* IND entries supported */
804: #define TLBnCFG_PT 0x00040000 /* Can load from page table */
805: #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
806: #define TLBnCFG_MINSIZE_SHIFT 20
807: #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
808: #define TLBnCFG_MAXSIZE_SHIFT 16
809: #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
810: #define TLBnCFG_ASSOC_SHIFT 24
811:
812: /* TLBnPS encoding */
813: #define TLBnPS_4K 0x00000004
814: #define TLBnPS_8K 0x00000008
815: #define TLBnPS_16K 0x00000010
816: #define TLBnPS_32K 0x00000020
817: #define TLBnPS_64K 0x00000040
818: #define TLBnPS_128K 0x00000080
819: #define TLBnPS_256K 0x00000100
820: #define TLBnPS_512K 0x00000200
821: #define TLBnPS_1M 0x00000400
822: #define TLBnPS_2M 0x00000800
823: #define TLBnPS_4M 0x00001000
824: #define TLBnPS_8M 0x00002000
825: #define TLBnPS_16M 0x00004000
826: #define TLBnPS_32M 0x00008000
827: #define TLBnPS_64M 0x00010000
828: #define TLBnPS_128M 0x00020000
829: #define TLBnPS_256M 0x00040000
830: #define TLBnPS_512M 0x00080000
831: #define TLBnPS_1G 0x00100000
832: #define TLBnPS_2G 0x00200000
833: #define TLBnPS_4G 0x00400000
834: #define TLBnPS_8G 0x00800000
835: #define TLBnPS_16G 0x01000000
836: #define TLBnPS_32G 0x02000000
837: #define TLBnPS_64G 0x04000000
838: #define TLBnPS_128G 0x08000000
839: #define TLBnPS_256G 0x10000000
840:
841: /* tlbilx action encoding */
842: #define TLBILX_T_ALL 0
843: #define TLBILX_T_TID 1
844: #define TLBILX_T_FULLMATCH 3
845: #define TLBILX_T_CLASS0 4
846: #define TLBILX_T_CLASS1 5
847: #define TLBILX_T_CLASS2 6
848: #define TLBILX_T_CLASS3 7
849:
850: /* BookE 2.06 helper defines */
851:
852: #define BOOKE206_FLUSH_TLB0 (1 << 0)
853: #define BOOKE206_FLUSH_TLB1 (1 << 1)
854: #define BOOKE206_FLUSH_TLB2 (1 << 2)
855: #define BOOKE206_FLUSH_TLB3 (1 << 3)
856:
857: /* number of possible TLBs */
858: #define BOOKE206_MAX_TLBN 4
859:
860: /*****************************************************************************/
1.1.1.12! root 861: /* Embedded.Processor Control */
! 862:
! 863: #define DBELL_TYPE_SHIFT 27
! 864: #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
! 865: #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
! 866: #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
! 867: #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
! 868: #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
! 869: #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
! 870:
! 871: #define DBELL_BRDCAST (1 << 26)
! 872: #define DBELL_LPIDTAG_SHIFT 14
! 873: #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
! 874: #define DBELL_PIRTAG_MASK 0x3fff
! 875:
! 876: /*****************************************************************************/
1.1 root 877: /* The whole PowerPC CPU context */
1.1.1.4 root 878: #define NB_MMU_MODES 3
879:
1.1.1.11 root 880: struct ppc_def_t {
881: const char *name;
882: uint32_t pvr;
883: uint32_t svr;
884: uint64_t insns_flags;
885: uint64_t insns_flags2;
886: uint64_t msr_mask;
887: powerpc_mmu_t mmu_model;
888: powerpc_excp_t excp_model;
889: powerpc_input_t bus_model;
890: uint32_t flags;
891: int bfd_mach;
892: void (*init_proc)(CPUPPCState *env);
893: int (*check_pow)(CPUPPCState *env);
894: };
895:
1.1 root 896: struct CPUPPCState {
897: /* First are the most commonly used resources
898: * during translated code execution
899: */
900: /* general purpose registers */
1.1.1.5 root 901: target_ulong gpr[32];
1.1.1.4 root 902: #if !defined(TARGET_PPC64)
903: /* Storage for GPR MSB, used by the SPE extension */
1.1.1.5 root 904: target_ulong gprh[32];
1.1.1.4 root 905: #endif
1.1 root 906: /* LR */
907: target_ulong lr;
908: /* CTR */
909: target_ulong ctr;
910: /* condition register */
1.1.1.5 root 911: uint32_t crf[8];
1.1.1.11 root 912: #if defined(TARGET_PPC64)
913: /* CFAR */
914: target_ulong cfar;
915: #endif
1.1 root 916: /* XER */
1.1.1.5 root 917: target_ulong xer;
1.1 root 918: /* Reservation address */
1.1.1.7 root 919: target_ulong reserve_addr;
920: /* Reservation value */
921: target_ulong reserve_val;
922: /* Reservation store address */
923: target_ulong reserve_ea;
924: /* Reserved store source register and size */
925: target_ulong reserve_info;
1.1 root 926:
927: /* Those ones are used in supervisor mode only */
928: /* machine state register */
1.1.1.4 root 929: target_ulong msr;
1.1 root 930: /* temporary general purpose registers */
1.1.1.5 root 931: target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
1.1 root 932:
933: /* Floating point execution context */
934: float_status fp_status;
935: /* floating point registers */
936: float64 fpr[32];
937: /* floating point status and control register */
1.1.1.4 root 938: uint32_t fpscr;
1.1 root 939:
1.1.1.7 root 940: /* Next instruction pointer */
941: target_ulong nip;
1.1.1.2 root 942:
1.1 root 943: int access_type; /* when a memory exception occurs, the access
944: type is stored here */
945:
1.1.1.7 root 946: CPU_COMMON
947:
1.1.1.4 root 948: /* MMU context - only relevant for full system emulation */
949: #if !defined(CONFIG_USER_ONLY)
950: #if defined(TARGET_PPC64)
1.1 root 951: /* Address space register */
952: target_ulong asr;
1.1.1.4 root 953: /* PowerPC 64 SLB area */
1.1.1.6 root 954: ppc_slb_t slb[64];
1.1.1.4 root 955: int slb_nr;
956: #endif
1.1 root 957: /* segment registers */
1.1.1.10 root 958: target_phys_addr_t htab_base;
959: target_phys_addr_t htab_mask;
1.1.1.5 root 960: target_ulong sr[32];
1.1.1.10 root 961: /* externally stored hash table */
962: uint8_t *external_htab;
1.1 root 963: /* BATs */
964: int nb_BATs;
965: target_ulong DBAT[2][8];
966: target_ulong IBAT[2][8];
1.1.1.10 root 967: /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1.1.1.4 root 968: int nb_tlb; /* Total number of TLB */
969: int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
970: int nb_ways; /* Number of ways in the TLB set */
971: int last_way; /* Last used way used to allocate TLB in a LRU way */
972: int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
973: int nb_pids; /* Number of available PID registers */
1.1.1.10 root 974: int tlb_type; /* Type of TLB we're dealing with */
975: ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
1.1.1.4 root 976: /* 403 dedicated access protection registers */
977: target_ulong pb[4];
1.1.1.11 root 978: bool tlb_dirty; /* Set to non-zero when modifying TLB */
979: bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1.1.1.4 root 980: #endif
1.1 root 981:
982: /* Other registers */
983: /* Special purpose registers */
984: target_ulong spr[1024];
1.1.1.4 root 985: ppc_spr_t spr_cb[1024];
1.1 root 986: /* Altivec registers */
987: ppc_avr_t avr[32];
988: uint32_t vscr;
1.1.1.4 root 989: /* SPE registers */
1.1.1.5 root 990: uint64_t spe_acc;
1.1.1.4 root 991: uint32_t spe_fscr;
1.1.1.5 root 992: /* SPE and Altivec can share a status since they will never be used
993: * simultaneously */
994: float_status vec_status;
1.1 root 995:
996: /* Internal devices resources */
997: /* Time base and decrementer */
998: ppc_tb_t *tb_env;
999: /* Device control registers */
1000: ppc_dcr_t *dcr_env;
1001:
1.1.1.4 root 1002: int dcache_line_size;
1003: int icache_line_size;
1.1 root 1004:
1005: /* Those resources are used during exception processing */
1006: /* CPU model definition */
1.1.1.4 root 1007: target_ulong msr_mask;
1008: powerpc_mmu_t mmu_model;
1009: powerpc_excp_t excp_model;
1010: powerpc_input_t bus_model;
1011: int bfd_mach;
1.1 root 1012: uint32_t flags;
1.1.1.6 root 1013: uint64_t insns_flags;
1.1.1.10 root 1014: uint64_t insns_flags2;
1015:
1016: #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1017: target_phys_addr_t vpa;
1018: target_phys_addr_t slb_shadow;
1019: target_phys_addr_t dispatch_trace_log;
1020: uint32_t dtl_size;
1021: #endif /* TARGET_PPC64 */
1.1 root 1022:
1023: int error_code;
1.1.1.4 root 1024: uint32_t pending_interrupts;
1025: #if !defined(CONFIG_USER_ONLY)
1.1.1.12! root 1026: /* This is the IRQ controller, which is implementation dependent
1.1.1.4 root 1027: * and only relevant when emulating a complete machine.
1028: */
1029: uint32_t irq_input_state;
1030: void **irq_inputs;
1031: /* Exception vectors */
1032: target_ulong excp_vectors[POWERPC_EXCP_NB];
1033: target_ulong excp_prefix;
1.1.1.6 root 1034: target_ulong hreset_excp_prefix;
1.1.1.4 root 1035: target_ulong ivor_mask;
1036: target_ulong ivpr_mask;
1037: target_ulong hreset_vector;
1038: #endif
1.1 root 1039:
1040: /* Those resources are used only during code translation */
1041: /* opcode handlers */
1042: opc_handler_t *opcodes[0x40];
1043:
1.1.1.12! root 1044: /* Those resources are used only in QEMU core */
1.1.1.4 root 1045: target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
1.1.1.12! root 1046: target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1.1.1.4 root 1047: int mmu_idx; /* precomputed MMU index to speed up mem accesses */
1.1 root 1048:
1049: /* Power management */
1050: int power_mode;
1.1.1.4 root 1051: int (*check_pow)(CPUPPCState *env);
1.1 root 1052:
1.1.1.9 root 1053: #if !defined(CONFIG_USER_ONLY)
1054: void *load_info; /* Holds boot loading state. */
1055: #endif
1.1.1.11 root 1056:
1057: /* booke timers */
1058:
1059: /* Specifies bit locations of the Time Base used to signal a fixed timer
1060: * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1061: *
1062: * 0 selects the least significant bit.
1063: * 63 selects the most significant bit.
1064: */
1065: uint8_t fit_period[4];
1066: uint8_t wdt_period[4];
1.1 root 1067: };
1068:
1.1.1.11 root 1069: #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1070: do { \
1071: env->fit_period[0] = (a_); \
1072: env->fit_period[1] = (b_); \
1073: env->fit_period[2] = (c_); \
1074: env->fit_period[3] = (d_); \
1075: } while (0)
1076:
1077: #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1078: do { \
1079: env->wdt_period[0] = (a_); \
1080: env->wdt_period[1] = (b_); \
1081: env->wdt_period[2] = (c_); \
1082: env->wdt_period[3] = (d_); \
1083: } while (0)
1084:
1.1.1.8 root 1085: #if !defined(CONFIG_USER_ONLY)
1.1.1.4 root 1086: /* Context used internally during MMU translations */
1087: typedef struct mmu_ctx_t mmu_ctx_t;
1088: struct mmu_ctx_t {
1089: target_phys_addr_t raddr; /* Real address */
1.1.1.6 root 1090: target_phys_addr_t eaddr; /* Effective address */
1.1.1.4 root 1091: int prot; /* Protection bits */
1.1.1.10 root 1092: target_phys_addr_t hash[2]; /* Pagetable hash values */
1.1.1.4 root 1093: target_ulong ptem; /* Virtual segment ID | API */
1094: int key; /* Access key */
1095: int nx; /* Non-execute area */
1096: };
1.1.1.8 root 1097: #endif
1.1.1.4 root 1098:
1.1.1.12! root 1099: #include "cpu-qom.h"
! 1100:
1.1 root 1101: /*****************************************************************************/
1.1.1.4 root 1102: CPUPPCState *cpu_ppc_init (const char *cpu_model);
1.1.1.5 root 1103: void ppc_translate_init(void);
1.1.1.4 root 1104: int cpu_ppc_exec (CPUPPCState *s);
1.1 root 1105: /* you can call this signal handler from your SIGBUS and SIGSEGV
1106: signal handlers to inform the virtual CPU of exceptions. non zero
1107: is returned if the signal was handled by the virtual CPU. */
1.1.1.4 root 1108: int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1109: void *puc);
1.1.1.5 root 1110: int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
1.1.1.11 root 1111: int mmu_idx);
1.1.1.7 root 1112: #define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
1.1.1.8 root 1113: #if !defined(CONFIG_USER_ONLY)
1.1.1.5 root 1114: int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,
1115: int rw, int access_type);
1.1.1.8 root 1116: #endif
1.1 root 1117: void do_interrupt (CPUPPCState *env);
1.1.1.4 root 1118: void ppc_hw_interrupt (CPUPPCState *env);
1.1 root 1119:
1.1.1.5 root 1120: void cpu_dump_rfi (target_ulong RA, target_ulong msr);
1.1 root 1121:
1.1.1.4 root 1122: #if !defined(CONFIG_USER_ONLY)
1.1.1.5 root 1123: void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code,
1124: target_ulong pte0, target_ulong pte1);
1125: void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
1126: void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
1127: void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
1128: void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
1129: void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
1130: void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
1131: void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1.1.1.4 root 1132: #if defined(TARGET_PPC64)
1133: void ppc_store_asr (CPUPPCState *env, target_ulong value);
1134: target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
1.1.1.6 root 1135: target_ulong ppc_load_sr (CPUPPCState *env, int sr_nr);
1.1.1.10 root 1136: int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
1137: int ppc_load_slb_esid (CPUPPCState *env, target_ulong rb, target_ulong *rt);
1138: int ppc_load_slb_vsid (CPUPPCState *env, target_ulong rb, target_ulong *rt);
1.1.1.4 root 1139: #endif /* defined(TARGET_PPC64) */
1.1.1.5 root 1140: void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value);
1.1.1.4 root 1141: #endif /* !defined(CONFIG_USER_ONLY) */
1142: void ppc_store_msr (CPUPPCState *env, target_ulong value);
1.1 root 1143:
1.1.1.9 root 1144: void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1.1.1.4 root 1145:
1.1.1.11 root 1146: const ppc_def_t *ppc_find_by_pvr(uint32_t pvr);
1.1.1.5 root 1147: const ppc_def_t *cpu_ppc_find_by_name (const char *name);
1.1.1.4 root 1148: int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
1.1 root 1149:
1150: /* Time-base and decrementer management */
1151: #ifndef NO_CPU_IO_DEFS
1.1.1.8 root 1152: uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1.1 root 1153: uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1154: void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1155: void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1.1.1.8 root 1156: uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1.1.1.4 root 1157: uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1158: void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1159: void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1.1 root 1160: uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1161: void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1.1.1.4 root 1162: uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1163: void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1164: uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1165: void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
1166: uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1167: uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1168: #if !defined(CONFIG_USER_ONLY)
1169: void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1170: void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1171: target_ulong load_40x_pit (CPUPPCState *env);
1172: void store_40x_pit (CPUPPCState *env, target_ulong val);
1173: void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1174: void store_40x_sler (CPUPPCState *env, uint32_t val);
1175: void store_booke_tcr (CPUPPCState *env, target_ulong val);
1176: void store_booke_tsr (CPUPPCState *env, target_ulong val);
1.1.1.12! root 1177: void booke206_flush_tlb(CPUPPCState *env, int flags, const int check_iprot);
! 1178: target_phys_addr_t booke206_tlb_to_page_size(CPUPPCState *env, ppcmas_tlb_t *tlb);
! 1179: int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb,
1.1.1.10 root 1180: target_phys_addr_t *raddrp, target_ulong address,
1181: uint32_t pid, int ext, int i);
1.1.1.12! root 1182: int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
1.1.1.10 root 1183: target_phys_addr_t *raddrp, target_ulong address,
1184: uint32_t pid);
1.1.1.4 root 1185: void ppc_tlb_invalidate_all (CPUPPCState *env);
1186: void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1187: #if defined(TARGET_PPC64)
1188: void ppc_slb_invalidate_all (CPUPPCState *env);
1189: void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
1190: #endif
1191: int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
1192: #endif
1.1 root 1193: #endif
1194:
1.1.1.7 root 1195: static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1.1.1.4 root 1196: {
1197: uint64_t gprv;
1198:
1199: gprv = env->gpr[gprn];
1200: #if !defined(TARGET_PPC64)
1201: if (env->flags & POWERPC_FLAG_SPE) {
1202: /* If the CPU implements the SPE extension, we have to get the
1203: * high bits of the GPR from the gprh storage area
1204: */
1205: gprv &= 0xFFFFFFFFULL;
1206: gprv |= (uint64_t)env->gprh[gprn] << 32;
1207: }
1208: #endif
1209:
1210: return gprv;
1211: }
1212:
1213: /* Device control registers */
1.1.1.8 root 1214: int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1215: int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1.1.1.4 root 1216:
1217: #define cpu_init cpu_ppc_init
1218: #define cpu_exec cpu_ppc_exec
1219: #define cpu_gen_code cpu_ppc_gen_code
1220: #define cpu_signal_handler cpu_ppc_signal_handler
1221: #define cpu_list ppc_cpu_list
1222:
1.1.1.6 root 1223: #define CPU_SAVE_VERSION 4
1.1.1.5 root 1224:
1.1.1.4 root 1225: /* MMU modes definitions */
1226: #define MMU_MODE0_SUFFIX _user
1227: #define MMU_MODE1_SUFFIX _kernel
1228: #define MMU_MODE2_SUFFIX _hypv
1229: #define MMU_USER_IDX 0
1.1.1.12! root 1230: static inline int cpu_mmu_index (CPUPPCState *env)
1.1.1.4 root 1231: {
1232: return env->mmu_idx;
1233: }
1234:
1.1.1.5 root 1235: #if defined(CONFIG_USER_ONLY)
1.1.1.12! root 1236: static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp)
1.1.1.5 root 1237: {
1238: if (newsp)
1239: env->gpr[1] = newsp;
1.1.1.7 root 1240: env->gpr[3] = 0;
1.1.1.5 root 1241: }
1242: #endif
1243:
1.1 root 1244: #include "cpu-all.h"
1245:
1246: /*****************************************************************************/
1.1.1.5 root 1247: /* CRF definitions */
1248: #define CRF_LT 3
1249: #define CRF_GT 2
1250: #define CRF_EQ 1
1251: #define CRF_SO 0
1.1.1.8 root 1252: #define CRF_CH (1 << CRF_LT)
1253: #define CRF_CL (1 << CRF_GT)
1254: #define CRF_CH_OR_CL (1 << CRF_EQ)
1255: #define CRF_CH_AND_CL (1 << CRF_SO)
1.1.1.5 root 1256:
1257: /* XER definitions */
1258: #define XER_SO 31
1259: #define XER_OV 30
1260: #define XER_CA 29
1261: #define XER_CMP 8
1262: #define XER_BC 0
1263: #define xer_so ((env->xer >> XER_SO) & 1)
1264: #define xer_ov ((env->xer >> XER_OV) & 1)
1265: #define xer_ca ((env->xer >> XER_CA) & 1)
1266: #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1267: #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1.1 root 1268:
1269: /* SPR definitions */
1.1.1.4 root 1270: #define SPR_MQ (0x000)
1271: #define SPR_XER (0x001)
1272: #define SPR_601_VRTCU (0x004)
1273: #define SPR_601_VRTCL (0x005)
1274: #define SPR_601_UDECR (0x006)
1275: #define SPR_LR (0x008)
1276: #define SPR_CTR (0x009)
1.1.1.11 root 1277: #define SPR_DSCR (0x011)
1.1.1.4 root 1278: #define SPR_DSISR (0x012)
1279: #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1280: #define SPR_601_RTCU (0x014)
1281: #define SPR_601_RTCL (0x015)
1282: #define SPR_DECR (0x016)
1283: #define SPR_SDR1 (0x019)
1284: #define SPR_SRR0 (0x01A)
1285: #define SPR_SRR1 (0x01B)
1.1.1.11 root 1286: #define SPR_CFAR (0x01C)
1.1.1.4 root 1287: #define SPR_AMR (0x01D)
1288: #define SPR_BOOKE_PID (0x030)
1289: #define SPR_BOOKE_DECAR (0x036)
1290: #define SPR_BOOKE_CSRR0 (0x03A)
1291: #define SPR_BOOKE_CSRR1 (0x03B)
1292: #define SPR_BOOKE_DEAR (0x03D)
1293: #define SPR_BOOKE_ESR (0x03E)
1294: #define SPR_BOOKE_IVPR (0x03F)
1295: #define SPR_MPC_EIE (0x050)
1296: #define SPR_MPC_EID (0x051)
1297: #define SPR_MPC_NRI (0x052)
1298: #define SPR_CTRL (0x088)
1299: #define SPR_MPC_CMPA (0x090)
1300: #define SPR_MPC_CMPB (0x091)
1301: #define SPR_MPC_CMPC (0x092)
1302: #define SPR_MPC_CMPD (0x093)
1303: #define SPR_MPC_ECR (0x094)
1304: #define SPR_MPC_DER (0x095)
1305: #define SPR_MPC_COUNTA (0x096)
1306: #define SPR_MPC_COUNTB (0x097)
1307: #define SPR_UCTRL (0x098)
1308: #define SPR_MPC_CMPE (0x098)
1309: #define SPR_MPC_CMPF (0x099)
1310: #define SPR_MPC_CMPG (0x09A)
1311: #define SPR_MPC_CMPH (0x09B)
1312: #define SPR_MPC_LCTRL1 (0x09C)
1313: #define SPR_MPC_LCTRL2 (0x09D)
1314: #define SPR_MPC_ICTRL (0x09E)
1315: #define SPR_MPC_BAR (0x09F)
1316: #define SPR_VRSAVE (0x100)
1317: #define SPR_USPRG0 (0x100)
1318: #define SPR_USPRG1 (0x101)
1319: #define SPR_USPRG2 (0x102)
1320: #define SPR_USPRG3 (0x103)
1321: #define SPR_USPRG4 (0x104)
1322: #define SPR_USPRG5 (0x105)
1323: #define SPR_USPRG6 (0x106)
1324: #define SPR_USPRG7 (0x107)
1325: #define SPR_VTBL (0x10C)
1326: #define SPR_VTBU (0x10D)
1327: #define SPR_SPRG0 (0x110)
1328: #define SPR_SPRG1 (0x111)
1329: #define SPR_SPRG2 (0x112)
1330: #define SPR_SPRG3 (0x113)
1331: #define SPR_SPRG4 (0x114)
1332: #define SPR_SCOMC (0x114)
1333: #define SPR_SPRG5 (0x115)
1334: #define SPR_SCOMD (0x115)
1335: #define SPR_SPRG6 (0x116)
1336: #define SPR_SPRG7 (0x117)
1337: #define SPR_ASR (0x118)
1338: #define SPR_EAR (0x11A)
1339: #define SPR_TBL (0x11C)
1340: #define SPR_TBU (0x11D)
1341: #define SPR_TBU40 (0x11E)
1342: #define SPR_SVR (0x11E)
1343: #define SPR_BOOKE_PIR (0x11E)
1344: #define SPR_PVR (0x11F)
1345: #define SPR_HSPRG0 (0x130)
1346: #define SPR_BOOKE_DBSR (0x130)
1347: #define SPR_HSPRG1 (0x131)
1348: #define SPR_HDSISR (0x132)
1349: #define SPR_HDAR (0x133)
1.1.1.10 root 1350: #define SPR_BOOKE_EPCR (0x133)
1351: #define SPR_SPURR (0x134)
1.1.1.4 root 1352: #define SPR_BOOKE_DBCR0 (0x134)
1353: #define SPR_IBCR (0x135)
1354: #define SPR_PURR (0x135)
1355: #define SPR_BOOKE_DBCR1 (0x135)
1356: #define SPR_DBCR (0x136)
1357: #define SPR_HDEC (0x136)
1358: #define SPR_BOOKE_DBCR2 (0x136)
1359: #define SPR_HIOR (0x137)
1360: #define SPR_MBAR (0x137)
1361: #define SPR_RMOR (0x138)
1362: #define SPR_BOOKE_IAC1 (0x138)
1363: #define SPR_HRMOR (0x139)
1364: #define SPR_BOOKE_IAC2 (0x139)
1365: #define SPR_HSRR0 (0x13A)
1366: #define SPR_BOOKE_IAC3 (0x13A)
1367: #define SPR_HSRR1 (0x13B)
1368: #define SPR_BOOKE_IAC4 (0x13B)
1369: #define SPR_LPCR (0x13C)
1370: #define SPR_BOOKE_DAC1 (0x13C)
1371: #define SPR_LPIDR (0x13D)
1372: #define SPR_DABR2 (0x13D)
1373: #define SPR_BOOKE_DAC2 (0x13D)
1374: #define SPR_BOOKE_DVC1 (0x13E)
1375: #define SPR_BOOKE_DVC2 (0x13F)
1376: #define SPR_BOOKE_TSR (0x150)
1377: #define SPR_BOOKE_TCR (0x154)
1.1.1.12! root 1378: #define SPR_BOOKE_TLB0PS (0x158)
! 1379: #define SPR_BOOKE_TLB1PS (0x159)
! 1380: #define SPR_BOOKE_TLB2PS (0x15A)
! 1381: #define SPR_BOOKE_TLB3PS (0x15B)
1.1.1.4 root 1382: #define SPR_BOOKE_IVOR0 (0x190)
1383: #define SPR_BOOKE_IVOR1 (0x191)
1384: #define SPR_BOOKE_IVOR2 (0x192)
1385: #define SPR_BOOKE_IVOR3 (0x193)
1386: #define SPR_BOOKE_IVOR4 (0x194)
1387: #define SPR_BOOKE_IVOR5 (0x195)
1388: #define SPR_BOOKE_IVOR6 (0x196)
1389: #define SPR_BOOKE_IVOR7 (0x197)
1390: #define SPR_BOOKE_IVOR8 (0x198)
1391: #define SPR_BOOKE_IVOR9 (0x199)
1392: #define SPR_BOOKE_IVOR10 (0x19A)
1393: #define SPR_BOOKE_IVOR11 (0x19B)
1394: #define SPR_BOOKE_IVOR12 (0x19C)
1395: #define SPR_BOOKE_IVOR13 (0x19D)
1396: #define SPR_BOOKE_IVOR14 (0x19E)
1397: #define SPR_BOOKE_IVOR15 (0x19F)
1.1.1.12! root 1398: #define SPR_BOOKE_IVOR38 (0x1B0)
! 1399: #define SPR_BOOKE_IVOR39 (0x1B1)
! 1400: #define SPR_BOOKE_IVOR40 (0x1B2)
! 1401: #define SPR_BOOKE_IVOR41 (0x1B3)
! 1402: #define SPR_BOOKE_IVOR42 (0x1B4)
1.1.1.4 root 1403: #define SPR_BOOKE_SPEFSCR (0x200)
1404: #define SPR_Exxx_BBEAR (0x201)
1405: #define SPR_Exxx_BBTAR (0x202)
1406: #define SPR_Exxx_L1CFG0 (0x203)
1407: #define SPR_Exxx_NPIDR (0x205)
1408: #define SPR_ATBL (0x20E)
1409: #define SPR_ATBU (0x20F)
1410: #define SPR_IBAT0U (0x210)
1411: #define SPR_BOOKE_IVOR32 (0x210)
1412: #define SPR_RCPU_MI_GRA (0x210)
1413: #define SPR_IBAT0L (0x211)
1414: #define SPR_BOOKE_IVOR33 (0x211)
1415: #define SPR_IBAT1U (0x212)
1416: #define SPR_BOOKE_IVOR34 (0x212)
1417: #define SPR_IBAT1L (0x213)
1418: #define SPR_BOOKE_IVOR35 (0x213)
1419: #define SPR_IBAT2U (0x214)
1420: #define SPR_BOOKE_IVOR36 (0x214)
1421: #define SPR_IBAT2L (0x215)
1422: #define SPR_BOOKE_IVOR37 (0x215)
1423: #define SPR_IBAT3U (0x216)
1424: #define SPR_IBAT3L (0x217)
1425: #define SPR_DBAT0U (0x218)
1426: #define SPR_RCPU_L2U_GRA (0x218)
1427: #define SPR_DBAT0L (0x219)
1428: #define SPR_DBAT1U (0x21A)
1429: #define SPR_DBAT1L (0x21B)
1430: #define SPR_DBAT2U (0x21C)
1431: #define SPR_DBAT2L (0x21D)
1432: #define SPR_DBAT3U (0x21E)
1433: #define SPR_DBAT3L (0x21F)
1434: #define SPR_IBAT4U (0x230)
1435: #define SPR_RPCU_BBCMCR (0x230)
1436: #define SPR_MPC_IC_CST (0x230)
1437: #define SPR_Exxx_CTXCR (0x230)
1438: #define SPR_IBAT4L (0x231)
1439: #define SPR_MPC_IC_ADR (0x231)
1440: #define SPR_Exxx_DBCR3 (0x231)
1441: #define SPR_IBAT5U (0x232)
1442: #define SPR_MPC_IC_DAT (0x232)
1443: #define SPR_Exxx_DBCNT (0x232)
1444: #define SPR_IBAT5L (0x233)
1445: #define SPR_IBAT6U (0x234)
1446: #define SPR_IBAT6L (0x235)
1447: #define SPR_IBAT7U (0x236)
1448: #define SPR_IBAT7L (0x237)
1449: #define SPR_DBAT4U (0x238)
1450: #define SPR_RCPU_L2U_MCR (0x238)
1451: #define SPR_MPC_DC_CST (0x238)
1452: #define SPR_Exxx_ALTCTXCR (0x238)
1453: #define SPR_DBAT4L (0x239)
1454: #define SPR_MPC_DC_ADR (0x239)
1455: #define SPR_DBAT5U (0x23A)
1456: #define SPR_BOOKE_MCSRR0 (0x23A)
1457: #define SPR_MPC_DC_DAT (0x23A)
1458: #define SPR_DBAT5L (0x23B)
1459: #define SPR_BOOKE_MCSRR1 (0x23B)
1460: #define SPR_DBAT6U (0x23C)
1461: #define SPR_BOOKE_MCSR (0x23C)
1462: #define SPR_DBAT6L (0x23D)
1463: #define SPR_Exxx_MCAR (0x23D)
1464: #define SPR_DBAT7U (0x23E)
1465: #define SPR_BOOKE_DSRR0 (0x23E)
1466: #define SPR_DBAT7L (0x23F)
1467: #define SPR_BOOKE_DSRR1 (0x23F)
1468: #define SPR_BOOKE_SPRG8 (0x25C)
1469: #define SPR_BOOKE_SPRG9 (0x25D)
1470: #define SPR_BOOKE_MAS0 (0x270)
1471: #define SPR_BOOKE_MAS1 (0x271)
1472: #define SPR_BOOKE_MAS2 (0x272)
1473: #define SPR_BOOKE_MAS3 (0x273)
1474: #define SPR_BOOKE_MAS4 (0x274)
1475: #define SPR_BOOKE_MAS5 (0x275)
1476: #define SPR_BOOKE_MAS6 (0x276)
1477: #define SPR_BOOKE_PID1 (0x279)
1478: #define SPR_BOOKE_PID2 (0x27A)
1479: #define SPR_MPC_DPDR (0x280)
1480: #define SPR_MPC_IMMR (0x288)
1481: #define SPR_BOOKE_TLB0CFG (0x2B0)
1482: #define SPR_BOOKE_TLB1CFG (0x2B1)
1483: #define SPR_BOOKE_TLB2CFG (0x2B2)
1484: #define SPR_BOOKE_TLB3CFG (0x2B3)
1485: #define SPR_BOOKE_EPR (0x2BE)
1486: #define SPR_PERF0 (0x300)
1487: #define SPR_RCPU_MI_RBA0 (0x300)
1488: #define SPR_MPC_MI_CTR (0x300)
1489: #define SPR_PERF1 (0x301)
1490: #define SPR_RCPU_MI_RBA1 (0x301)
1491: #define SPR_PERF2 (0x302)
1492: #define SPR_RCPU_MI_RBA2 (0x302)
1493: #define SPR_MPC_MI_AP (0x302)
1494: #define SPR_PERF3 (0x303)
1495: #define SPR_620_PMC1R (0x303)
1496: #define SPR_RCPU_MI_RBA3 (0x303)
1497: #define SPR_MPC_MI_EPN (0x303)
1498: #define SPR_PERF4 (0x304)
1499: #define SPR_620_PMC2R (0x304)
1500: #define SPR_PERF5 (0x305)
1501: #define SPR_MPC_MI_TWC (0x305)
1502: #define SPR_PERF6 (0x306)
1503: #define SPR_MPC_MI_RPN (0x306)
1504: #define SPR_PERF7 (0x307)
1505: #define SPR_PERF8 (0x308)
1506: #define SPR_RCPU_L2U_RBA0 (0x308)
1507: #define SPR_MPC_MD_CTR (0x308)
1508: #define SPR_PERF9 (0x309)
1509: #define SPR_RCPU_L2U_RBA1 (0x309)
1510: #define SPR_MPC_MD_CASID (0x309)
1511: #define SPR_PERFA (0x30A)
1512: #define SPR_RCPU_L2U_RBA2 (0x30A)
1513: #define SPR_MPC_MD_AP (0x30A)
1514: #define SPR_PERFB (0x30B)
1515: #define SPR_620_MMCR0R (0x30B)
1516: #define SPR_RCPU_L2U_RBA3 (0x30B)
1517: #define SPR_MPC_MD_EPN (0x30B)
1518: #define SPR_PERFC (0x30C)
1519: #define SPR_MPC_MD_TWB (0x30C)
1520: #define SPR_PERFD (0x30D)
1521: #define SPR_MPC_MD_TWC (0x30D)
1522: #define SPR_PERFE (0x30E)
1523: #define SPR_MPC_MD_RPN (0x30E)
1524: #define SPR_PERFF (0x30F)
1525: #define SPR_MPC_MD_TW (0x30F)
1526: #define SPR_UPERF0 (0x310)
1527: #define SPR_UPERF1 (0x311)
1528: #define SPR_UPERF2 (0x312)
1529: #define SPR_UPERF3 (0x313)
1530: #define SPR_620_PMC1W (0x313)
1531: #define SPR_UPERF4 (0x314)
1532: #define SPR_620_PMC2W (0x314)
1533: #define SPR_UPERF5 (0x315)
1534: #define SPR_UPERF6 (0x316)
1535: #define SPR_UPERF7 (0x317)
1536: #define SPR_UPERF8 (0x318)
1537: #define SPR_UPERF9 (0x319)
1538: #define SPR_UPERFA (0x31A)
1539: #define SPR_UPERFB (0x31B)
1540: #define SPR_620_MMCR0W (0x31B)
1541: #define SPR_UPERFC (0x31C)
1542: #define SPR_UPERFD (0x31D)
1543: #define SPR_UPERFE (0x31E)
1544: #define SPR_UPERFF (0x31F)
1545: #define SPR_RCPU_MI_RA0 (0x320)
1546: #define SPR_MPC_MI_DBCAM (0x320)
1547: #define SPR_RCPU_MI_RA1 (0x321)
1548: #define SPR_MPC_MI_DBRAM0 (0x321)
1549: #define SPR_RCPU_MI_RA2 (0x322)
1550: #define SPR_MPC_MI_DBRAM1 (0x322)
1551: #define SPR_RCPU_MI_RA3 (0x323)
1552: #define SPR_RCPU_L2U_RA0 (0x328)
1553: #define SPR_MPC_MD_DBCAM (0x328)
1554: #define SPR_RCPU_L2U_RA1 (0x329)
1555: #define SPR_MPC_MD_DBRAM0 (0x329)
1556: #define SPR_RCPU_L2U_RA2 (0x32A)
1557: #define SPR_MPC_MD_DBRAM1 (0x32A)
1558: #define SPR_RCPU_L2U_RA3 (0x32B)
1559: #define SPR_440_INV0 (0x370)
1560: #define SPR_440_INV1 (0x371)
1561: #define SPR_440_INV2 (0x372)
1562: #define SPR_440_INV3 (0x373)
1563: #define SPR_440_ITV0 (0x374)
1564: #define SPR_440_ITV1 (0x375)
1565: #define SPR_440_ITV2 (0x376)
1566: #define SPR_440_ITV3 (0x377)
1567: #define SPR_440_CCR1 (0x378)
1568: #define SPR_DCRIPR (0x37B)
1569: #define SPR_PPR (0x380)
1570: #define SPR_750_GQR0 (0x390)
1571: #define SPR_440_DNV0 (0x390)
1572: #define SPR_750_GQR1 (0x391)
1573: #define SPR_440_DNV1 (0x391)
1574: #define SPR_750_GQR2 (0x392)
1575: #define SPR_440_DNV2 (0x392)
1576: #define SPR_750_GQR3 (0x393)
1577: #define SPR_440_DNV3 (0x393)
1578: #define SPR_750_GQR4 (0x394)
1579: #define SPR_440_DTV0 (0x394)
1580: #define SPR_750_GQR5 (0x395)
1581: #define SPR_440_DTV1 (0x395)
1582: #define SPR_750_GQR6 (0x396)
1583: #define SPR_440_DTV2 (0x396)
1584: #define SPR_750_GQR7 (0x397)
1585: #define SPR_440_DTV3 (0x397)
1586: #define SPR_750_THRM4 (0x398)
1587: #define SPR_750CL_HID2 (0x398)
1588: #define SPR_440_DVLIM (0x398)
1589: #define SPR_750_WPAR (0x399)
1590: #define SPR_440_IVLIM (0x399)
1591: #define SPR_750_DMAU (0x39A)
1592: #define SPR_750_DMAL (0x39B)
1593: #define SPR_440_RSTCFG (0x39B)
1594: #define SPR_BOOKE_DCDBTRL (0x39C)
1595: #define SPR_BOOKE_DCDBTRH (0x39D)
1596: #define SPR_BOOKE_ICDBTRL (0x39E)
1597: #define SPR_BOOKE_ICDBTRH (0x39F)
1598: #define SPR_UMMCR2 (0x3A0)
1599: #define SPR_UPMC5 (0x3A1)
1600: #define SPR_UPMC6 (0x3A2)
1601: #define SPR_UBAMR (0x3A7)
1602: #define SPR_UMMCR0 (0x3A8)
1603: #define SPR_UPMC1 (0x3A9)
1604: #define SPR_UPMC2 (0x3AA)
1605: #define SPR_USIAR (0x3AB)
1606: #define SPR_UMMCR1 (0x3AC)
1607: #define SPR_UPMC3 (0x3AD)
1608: #define SPR_UPMC4 (0x3AE)
1609: #define SPR_USDA (0x3AF)
1610: #define SPR_40x_ZPR (0x3B0)
1611: #define SPR_BOOKE_MAS7 (0x3B0)
1612: #define SPR_620_PMR0 (0x3B0)
1613: #define SPR_MMCR2 (0x3B0)
1614: #define SPR_PMC5 (0x3B1)
1615: #define SPR_40x_PID (0x3B1)
1616: #define SPR_620_PMR1 (0x3B1)
1617: #define SPR_PMC6 (0x3B2)
1618: #define SPR_440_MMUCR (0x3B2)
1619: #define SPR_620_PMR2 (0x3B2)
1620: #define SPR_4xx_CCR0 (0x3B3)
1621: #define SPR_BOOKE_EPLC (0x3B3)
1622: #define SPR_620_PMR3 (0x3B3)
1623: #define SPR_405_IAC3 (0x3B4)
1624: #define SPR_BOOKE_EPSC (0x3B4)
1625: #define SPR_620_PMR4 (0x3B4)
1626: #define SPR_405_IAC4 (0x3B5)
1627: #define SPR_620_PMR5 (0x3B5)
1628: #define SPR_405_DVC1 (0x3B6)
1629: #define SPR_620_PMR6 (0x3B6)
1630: #define SPR_405_DVC2 (0x3B7)
1631: #define SPR_620_PMR7 (0x3B7)
1632: #define SPR_BAMR (0x3B7)
1633: #define SPR_MMCR0 (0x3B8)
1634: #define SPR_620_PMR8 (0x3B8)
1635: #define SPR_PMC1 (0x3B9)
1636: #define SPR_40x_SGR (0x3B9)
1637: #define SPR_620_PMR9 (0x3B9)
1638: #define SPR_PMC2 (0x3BA)
1639: #define SPR_40x_DCWR (0x3BA)
1640: #define SPR_620_PMRA (0x3BA)
1641: #define SPR_SIAR (0x3BB)
1642: #define SPR_405_SLER (0x3BB)
1643: #define SPR_620_PMRB (0x3BB)
1644: #define SPR_MMCR1 (0x3BC)
1645: #define SPR_405_SU0R (0x3BC)
1646: #define SPR_620_PMRC (0x3BC)
1647: #define SPR_401_SKR (0x3BC)
1648: #define SPR_PMC3 (0x3BD)
1649: #define SPR_405_DBCR1 (0x3BD)
1650: #define SPR_620_PMRD (0x3BD)
1651: #define SPR_PMC4 (0x3BE)
1652: #define SPR_620_PMRE (0x3BE)
1653: #define SPR_SDA (0x3BF)
1654: #define SPR_620_PMRF (0x3BF)
1655: #define SPR_403_VTBL (0x3CC)
1656: #define SPR_403_VTBU (0x3CD)
1657: #define SPR_DMISS (0x3D0)
1658: #define SPR_DCMP (0x3D1)
1659: #define SPR_HASH1 (0x3D2)
1660: #define SPR_HASH2 (0x3D3)
1661: #define SPR_BOOKE_ICDBDR (0x3D3)
1662: #define SPR_TLBMISS (0x3D4)
1663: #define SPR_IMISS (0x3D4)
1664: #define SPR_40x_ESR (0x3D4)
1665: #define SPR_PTEHI (0x3D5)
1666: #define SPR_ICMP (0x3D5)
1667: #define SPR_40x_DEAR (0x3D5)
1668: #define SPR_PTELO (0x3D6)
1669: #define SPR_RPA (0x3D6)
1670: #define SPR_40x_EVPR (0x3D6)
1671: #define SPR_L3PM (0x3D7)
1672: #define SPR_403_CDBCR (0x3D7)
1673: #define SPR_L3ITCR0 (0x3D8)
1674: #define SPR_TCR (0x3D8)
1675: #define SPR_40x_TSR (0x3D8)
1676: #define SPR_IBR (0x3DA)
1677: #define SPR_40x_TCR (0x3DA)
1678: #define SPR_ESASRR (0x3DB)
1679: #define SPR_40x_PIT (0x3DB)
1680: #define SPR_403_TBL (0x3DC)
1681: #define SPR_403_TBU (0x3DD)
1682: #define SPR_SEBR (0x3DE)
1683: #define SPR_40x_SRR2 (0x3DE)
1684: #define SPR_SER (0x3DF)
1685: #define SPR_40x_SRR3 (0x3DF)
1686: #define SPR_L3OHCR (0x3E8)
1687: #define SPR_L3ITCR1 (0x3E9)
1688: #define SPR_L3ITCR2 (0x3EA)
1689: #define SPR_L3ITCR3 (0x3EB)
1690: #define SPR_HID0 (0x3F0)
1691: #define SPR_40x_DBSR (0x3F0)
1692: #define SPR_HID1 (0x3F1)
1693: #define SPR_IABR (0x3F2)
1694: #define SPR_40x_DBCR0 (0x3F2)
1695: #define SPR_601_HID2 (0x3F2)
1696: #define SPR_Exxx_L1CSR0 (0x3F2)
1697: #define SPR_ICTRL (0x3F3)
1698: #define SPR_HID2 (0x3F3)
1699: #define SPR_750CL_HID4 (0x3F3)
1700: #define SPR_Exxx_L1CSR1 (0x3F3)
1701: #define SPR_440_DBDR (0x3F3)
1702: #define SPR_LDSTDB (0x3F4)
1703: #define SPR_750_TDCL (0x3F4)
1704: #define SPR_40x_IAC1 (0x3F4)
1705: #define SPR_MMUCSR0 (0x3F4)
1706: #define SPR_DABR (0x3F5)
1.1 root 1707: #define DABR_MASK (~(target_ulong)0x7)
1.1.1.4 root 1708: #define SPR_Exxx_BUCSR (0x3F5)
1709: #define SPR_40x_IAC2 (0x3F5)
1710: #define SPR_601_HID5 (0x3F5)
1711: #define SPR_40x_DAC1 (0x3F6)
1712: #define SPR_MSSCR0 (0x3F6)
1713: #define SPR_970_HID5 (0x3F6)
1714: #define SPR_MSSSR0 (0x3F7)
1715: #define SPR_MSSCR1 (0x3F7)
1716: #define SPR_DABRX (0x3F7)
1717: #define SPR_40x_DAC2 (0x3F7)
1718: #define SPR_MMUCFG (0x3F7)
1719: #define SPR_LDSTCR (0x3F8)
1720: #define SPR_L2PMCR (0x3F8)
1721: #define SPR_750FX_HID2 (0x3F8)
1722: #define SPR_620_BUSCSR (0x3F8)
1723: #define SPR_Exxx_L1FINV0 (0x3F8)
1724: #define SPR_L2CR (0x3F9)
1725: #define SPR_620_L2CR (0x3F9)
1726: #define SPR_L3CR (0x3FA)
1727: #define SPR_750_TDCH (0x3FA)
1728: #define SPR_IABR2 (0x3FA)
1729: #define SPR_40x_DCCR (0x3FA)
1730: #define SPR_620_L2SR (0x3FA)
1731: #define SPR_ICTC (0x3FB)
1732: #define SPR_40x_ICCR (0x3FB)
1733: #define SPR_THRM1 (0x3FC)
1734: #define SPR_403_PBL1 (0x3FC)
1735: #define SPR_SP (0x3FD)
1736: #define SPR_THRM2 (0x3FD)
1737: #define SPR_403_PBU1 (0x3FD)
1738: #define SPR_604_HID13 (0x3FD)
1739: #define SPR_LT (0x3FE)
1740: #define SPR_THRM3 (0x3FE)
1741: #define SPR_RCPU_FPECR (0x3FE)
1742: #define SPR_403_PBL2 (0x3FE)
1743: #define SPR_PIR (0x3FF)
1744: #define SPR_403_PBU2 (0x3FF)
1745: #define SPR_601_HID15 (0x3FF)
1746: #define SPR_604_HID15 (0x3FF)
1747: #define SPR_E500_SVR (0x3FF)
1.1 root 1748:
1.1.1.4 root 1749: /*****************************************************************************/
1.1.1.6 root 1750: /* PowerPC Instructions types definitions */
1751: enum {
1752: PPC_NONE = 0x0000000000000000ULL,
1753: /* PowerPC base instructions set */
1754: PPC_INSNS_BASE = 0x0000000000000001ULL,
1755: /* integer operations instructions */
1756: #define PPC_INTEGER PPC_INSNS_BASE
1757: /* flow control instructions */
1758: #define PPC_FLOW PPC_INSNS_BASE
1759: /* virtual memory instructions */
1760: #define PPC_MEM PPC_INSNS_BASE
1761: /* ld/st with reservation instructions */
1762: #define PPC_RES PPC_INSNS_BASE
1763: /* spr/msr access instructions */
1764: #define PPC_MISC PPC_INSNS_BASE
1765: /* Deprecated instruction sets */
1766: /* Original POWER instruction set */
1767: PPC_POWER = 0x0000000000000002ULL,
1768: /* POWER2 instruction set extension */
1769: PPC_POWER2 = 0x0000000000000004ULL,
1770: /* Power RTC support */
1771: PPC_POWER_RTC = 0x0000000000000008ULL,
1772: /* Power-to-PowerPC bridge (601) */
1773: PPC_POWER_BR = 0x0000000000000010ULL,
1774: /* 64 bits PowerPC instruction set */
1775: PPC_64B = 0x0000000000000020ULL,
1776: /* New 64 bits extensions (PowerPC 2.0x) */
1777: PPC_64BX = 0x0000000000000040ULL,
1778: /* 64 bits hypervisor extensions */
1779: PPC_64H = 0x0000000000000080ULL,
1780: /* New wait instruction (PowerPC 2.0x) */
1781: PPC_WAIT = 0x0000000000000100ULL,
1782: /* Time base mftb instruction */
1783: PPC_MFTB = 0x0000000000000200ULL,
1784:
1785: /* Fixed-point unit extensions */
1786: /* PowerPC 602 specific */
1787: PPC_602_SPEC = 0x0000000000000400ULL,
1788: /* isel instruction */
1789: PPC_ISEL = 0x0000000000000800ULL,
1790: /* popcntb instruction */
1791: PPC_POPCNTB = 0x0000000000001000ULL,
1792: /* string load / store */
1793: PPC_STRING = 0x0000000000002000ULL,
1794:
1795: /* Floating-point unit extensions */
1796: /* Optional floating point instructions */
1797: PPC_FLOAT = 0x0000000000010000ULL,
1798: /* New floating-point extensions (PowerPC 2.0x) */
1799: PPC_FLOAT_EXT = 0x0000000000020000ULL,
1800: PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1801: PPC_FLOAT_FRES = 0x0000000000080000ULL,
1802: PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1803: PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1804: PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1805: PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1806:
1807: /* Vector/SIMD extensions */
1808: /* Altivec support */
1809: PPC_ALTIVEC = 0x0000000001000000ULL,
1810: /* PowerPC 2.03 SPE extension */
1811: PPC_SPE = 0x0000000002000000ULL,
1812: /* PowerPC 2.03 SPE single-precision floating-point extension */
1813: PPC_SPE_SINGLE = 0x0000000004000000ULL,
1814: /* PowerPC 2.03 SPE double-precision floating-point extension */
1815: PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1816:
1817: /* Optional memory control instructions */
1818: PPC_MEM_TLBIA = 0x0000000010000000ULL,
1819: PPC_MEM_TLBIE = 0x0000000020000000ULL,
1820: PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1821: /* sync instruction */
1822: PPC_MEM_SYNC = 0x0000000080000000ULL,
1823: /* eieio instruction */
1824: PPC_MEM_EIEIO = 0x0000000100000000ULL,
1825:
1826: /* Cache control instructions */
1827: PPC_CACHE = 0x0000000200000000ULL,
1828: /* icbi instruction */
1829: PPC_CACHE_ICBI = 0x0000000400000000ULL,
1830: /* dcbz instruction with fixed cache line size */
1831: PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1832: /* dcbz instruction with tunable cache line size */
1833: PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1834: /* dcba instruction */
1835: PPC_CACHE_DCBA = 0x0000002000000000ULL,
1836: /* Freescale cache locking instructions */
1837: PPC_CACHE_LOCK = 0x0000004000000000ULL,
1838:
1839: /* MMU related extensions */
1840: /* external control instructions */
1841: PPC_EXTERN = 0x0000010000000000ULL,
1842: /* segment register access instructions */
1843: PPC_SEGMENT = 0x0000020000000000ULL,
1844: /* PowerPC 6xx TLB management instructions */
1845: PPC_6xx_TLB = 0x0000040000000000ULL,
1846: /* PowerPC 74xx TLB management instructions */
1847: PPC_74xx_TLB = 0x0000080000000000ULL,
1848: /* PowerPC 40x TLB management instructions */
1849: PPC_40x_TLB = 0x0000100000000000ULL,
1850: /* segment register access instructions for PowerPC 64 "bridge" */
1851: PPC_SEGMENT_64B = 0x0000200000000000ULL,
1852: /* SLB management */
1853: PPC_SLBI = 0x0000400000000000ULL,
1854:
1855: /* Embedded PowerPC dedicated instructions */
1856: PPC_WRTEE = 0x0001000000000000ULL,
1857: /* PowerPC 40x exception model */
1858: PPC_40x_EXCP = 0x0002000000000000ULL,
1859: /* PowerPC 405 Mac instructions */
1860: PPC_405_MAC = 0x0004000000000000ULL,
1861: /* PowerPC 440 specific instructions */
1862: PPC_440_SPEC = 0x0008000000000000ULL,
1863: /* BookE (embedded) PowerPC specification */
1864: PPC_BOOKE = 0x0010000000000000ULL,
1865: /* mfapidi instruction */
1866: PPC_MFAPIDI = 0x0020000000000000ULL,
1867: /* tlbiva instruction */
1868: PPC_TLBIVA = 0x0040000000000000ULL,
1869: /* tlbivax instruction */
1870: PPC_TLBIVAX = 0x0080000000000000ULL,
1871: /* PowerPC 4xx dedicated instructions */
1872: PPC_4xx_COMMON = 0x0100000000000000ULL,
1873: /* PowerPC 40x ibct instructions */
1874: PPC_40x_ICBT = 0x0200000000000000ULL,
1875: /* rfmci is not implemented in all BookE PowerPC */
1876: PPC_RFMCI = 0x0400000000000000ULL,
1877: /* rfdi instruction */
1878: PPC_RFDI = 0x0800000000000000ULL,
1879: /* DCR accesses */
1880: PPC_DCR = 0x1000000000000000ULL,
1881: /* DCR extended accesse */
1882: PPC_DCRX = 0x2000000000000000ULL,
1883: /* user-mode DCR access, implemented in PowerPC 460 */
1884: PPC_DCRUX = 0x4000000000000000ULL,
1.1.1.10 root 1885: /* popcntw and popcntd instructions */
1886: PPC_POPCNTWD = 0x8000000000000000ULL,
1887:
1.1.1.11 root 1888: #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
1889: | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
1890: | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
1891: | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
1892: | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
1893: | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
1894: | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
1895: | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
1896: | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
1897: | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
1898: | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
1899: | PPC_MEM_SYNC | PPC_MEM_EIEIO \
1900: | PPC_CACHE | PPC_CACHE_ICBI \
1901: | PPC_CACHE_DCBZ | PPC_CACHE_DCBZT \
1902: | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
1903: | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
1904: | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
1905: | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
1906: | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
1907: | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
1908: | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
1909: | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
1910: | PPC_POPCNTWD)
1911:
1.1.1.10 root 1912: /* extended type values */
1913:
1914: /* BookE 2.06 PowerPC specification */
1915: PPC2_BOOKE206 = 0x0000000000000001ULL,
1.1.1.11 root 1916: /* VSX (extensions to Altivec / VMX) */
1917: PPC2_VSX = 0x0000000000000002ULL,
1918: /* Decimal Floating Point (DFP) */
1919: PPC2_DFP = 0x0000000000000004ULL,
1.1.1.12! root 1920: /* Embedded.Processor Control */
! 1921: PPC2_PRCNTL = 0x0000000000000008ULL,
! 1922: /* Byte-reversed, indexed, double-word load and store */
! 1923: PPC2_DBRX = 0x0000000000000010ULL,
1.1.1.11 root 1924:
1.1.1.12! root 1925: #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX)
1.1.1.6 root 1926: };
1927:
1928: /*****************************************************************************/
1.1 root 1929: /* Memory access type :
1930: * may be needed for precise access rights control and precise exceptions.
1931: */
1932: enum {
1933: /* 1 bit to define user level / supervisor access */
1934: ACCESS_USER = 0x00,
1935: ACCESS_SUPER = 0x01,
1936: /* Type of instruction that generated the access */
1937: ACCESS_CODE = 0x10, /* Code fetch access */
1938: ACCESS_INT = 0x20, /* Integer load/store access */
1939: ACCESS_FLOAT = 0x30, /* floating point load/store access */
1940: ACCESS_RES = 0x40, /* load/store with reservation */
1941: ACCESS_EXT = 0x50, /* external access */
1942: ACCESS_CACHE = 0x60, /* Cache manipulation */
1943: };
1944:
1.1.1.4 root 1945: /* Hardware interruption sources:
1946: * all those exception can be raised simulteaneously
1947: */
1948: /* Input pins definitions */
1949: enum {
1950: /* 6xx bus input pins */
1951: PPC6xx_INPUT_HRESET = 0,
1952: PPC6xx_INPUT_SRESET = 1,
1953: PPC6xx_INPUT_CKSTP_IN = 2,
1954: PPC6xx_INPUT_MCP = 3,
1955: PPC6xx_INPUT_SMI = 4,
1956: PPC6xx_INPUT_INT = 5,
1957: PPC6xx_INPUT_TBEN = 6,
1958: PPC6xx_INPUT_WAKEUP = 7,
1959: PPC6xx_INPUT_NB,
1960: };
1961:
1962: enum {
1963: /* Embedded PowerPC input pins */
1964: PPCBookE_INPUT_HRESET = 0,
1965: PPCBookE_INPUT_SRESET = 1,
1966: PPCBookE_INPUT_CKSTP_IN = 2,
1967: PPCBookE_INPUT_MCP = 3,
1968: PPCBookE_INPUT_SMI = 4,
1969: PPCBookE_INPUT_INT = 5,
1970: PPCBookE_INPUT_CINT = 6,
1971: PPCBookE_INPUT_NB,
1972: };
1973:
1974: enum {
1.1.1.5 root 1975: /* PowerPC E500 input pins */
1976: PPCE500_INPUT_RESET_CORE = 0,
1977: PPCE500_INPUT_MCK = 1,
1978: PPCE500_INPUT_CINT = 3,
1979: PPCE500_INPUT_INT = 4,
1980: PPCE500_INPUT_DEBUG = 6,
1981: PPCE500_INPUT_NB,
1982: };
1983:
1984: enum {
1.1.1.4 root 1985: /* PowerPC 40x input pins */
1986: PPC40x_INPUT_RESET_CORE = 0,
1987: PPC40x_INPUT_RESET_CHIP = 1,
1988: PPC40x_INPUT_RESET_SYS = 2,
1989: PPC40x_INPUT_CINT = 3,
1990: PPC40x_INPUT_INT = 4,
1991: PPC40x_INPUT_HALT = 5,
1992: PPC40x_INPUT_DEBUG = 6,
1993: PPC40x_INPUT_NB,
1994: };
1995:
1996: enum {
1997: /* RCPU input pins */
1998: PPCRCPU_INPUT_PORESET = 0,
1999: PPCRCPU_INPUT_HRESET = 1,
2000: PPCRCPU_INPUT_SRESET = 2,
2001: PPCRCPU_INPUT_IRQ0 = 3,
2002: PPCRCPU_INPUT_IRQ1 = 4,
2003: PPCRCPU_INPUT_IRQ2 = 5,
2004: PPCRCPU_INPUT_IRQ3 = 6,
2005: PPCRCPU_INPUT_IRQ4 = 7,
2006: PPCRCPU_INPUT_IRQ5 = 8,
2007: PPCRCPU_INPUT_IRQ6 = 9,
2008: PPCRCPU_INPUT_IRQ7 = 10,
2009: PPCRCPU_INPUT_NB,
2010: };
2011:
2012: #if defined(TARGET_PPC64)
2013: enum {
2014: /* PowerPC 970 input pins */
2015: PPC970_INPUT_HRESET = 0,
2016: PPC970_INPUT_SRESET = 1,
2017: PPC970_INPUT_CKSTP = 2,
2018: PPC970_INPUT_TBEN = 3,
2019: PPC970_INPUT_MCP = 4,
2020: PPC970_INPUT_INT = 5,
2021: PPC970_INPUT_THINT = 6,
2022: PPC970_INPUT_NB,
2023: };
1.1.1.10 root 2024:
2025: enum {
2026: /* POWER7 input pins */
2027: POWER7_INPUT_INT = 0,
2028: /* POWER7 probably has other inputs, but we don't care about them
2029: * for any existing machine. We can wire these up when we need
2030: * them */
2031: POWER7_INPUT_NB,
2032: };
1.1.1.4 root 2033: #endif
1.1 root 2034:
1.1.1.4 root 2035: /* Hardware exceptions definitions */
1.1 root 2036: enum {
1.1.1.4 root 2037: /* External hardware exception sources */
2038: PPC_INTERRUPT_RESET = 0, /* Reset exception */
2039: PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2040: PPC_INTERRUPT_MCK, /* Machine check exception */
2041: PPC_INTERRUPT_EXT, /* External interrupt */
2042: PPC_INTERRUPT_SMI, /* System management interrupt */
2043: PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2044: PPC_INTERRUPT_DEBUG, /* External debug exception */
2045: PPC_INTERRUPT_THERM, /* Thermal exception */
2046: /* Internal hardware exception sources */
2047: PPC_INTERRUPT_DECR, /* Decrementer exception */
2048: PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2049: PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2050: PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2051: PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2052: PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2053: PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2054: PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
1.1 root 2055: };
2056:
1.1.1.12! root 2057: /* CPU should be reset next, restart from scratch afterwards */
! 2058: #define CPU_INTERRUPT_RESET CPU_INTERRUPT_TGT_INT_0
! 2059:
1.1 root 2060: /*****************************************************************************/
2061:
1.1.1.12! root 2062: static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
1.1.1.5 root 2063: target_ulong *cs_base, int *flags)
2064: {
2065: *pc = env->nip;
2066: *cs_base = 0;
2067: *flags = env->hflags;
2068: }
2069:
1.1.1.12! root 2070: static inline void cpu_set_tls(CPUPPCState *env, target_ulong newtls)
1.1.1.7 root 2071: {
2072: #if defined(TARGET_PPC64)
2073: /* The kernel checks TIF_32BIT here; we don't support loading 32-bit
2074: binaries on PPC64 yet. */
2075: env->gpr[13] = newtls;
2076: #else
2077: env->gpr[2] = newtls;
2078: #endif
2079: }
2080:
1.1.1.10 root 2081: #if !defined(CONFIG_USER_ONLY)
1.1.1.12! root 2082: static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
1.1.1.10 root 2083: {
2084: uintptr_t tlbml = (uintptr_t)tlbm;
2085: uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2086:
2087: return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2088: }
2089:
1.1.1.12! root 2090: static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
1.1.1.10 root 2091: {
2092: uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2093: int r = tlbncfg & TLBnCFG_N_ENTRY;
2094: return r;
2095: }
2096:
1.1.1.12! root 2097: static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
1.1.1.10 root 2098: {
2099: uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2100: int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2101: return r;
2102: }
2103:
1.1.1.12! root 2104: static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
1.1.1.10 root 2105: {
2106: int id = booke206_tlbm_id(env, tlbm);
2107: int end = 0;
2108: int i;
2109:
2110: for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2111: end += booke206_tlb_size(env, i);
2112: if (id < end) {
2113: return i;
2114: }
2115: }
2116:
2117: cpu_abort(env, "Unknown TLBe: %d\n", id);
2118: return 0;
2119: }
2120:
1.1.1.12! root 2121: static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
1.1.1.10 root 2122: {
2123: int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2124: int tlbid = booke206_tlbm_id(env, tlb);
2125: return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2126: }
2127:
1.1.1.12! root 2128: static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
1.1.1.10 root 2129: target_ulong ea, int way)
2130: {
2131: int r;
2132: uint32_t ways = booke206_tlb_ways(env, tlbn);
2133: int ways_bits = ffs(ways) - 1;
2134: int tlb_bits = ffs(booke206_tlb_size(env, tlbn)) - 1;
2135: int i;
2136:
2137: way &= ways - 1;
2138: ea >>= MAS2_EPN_SHIFT;
2139: ea &= (1 << (tlb_bits - ways_bits)) - 1;
2140: r = (ea << ways_bits) | way;
2141:
1.1.1.12! root 2142: if (r >= booke206_tlb_size(env, tlbn)) {
! 2143: return NULL;
! 2144: }
! 2145:
1.1.1.10 root 2146: /* bump up to tlbn index */
2147: for (i = 0; i < tlbn; i++) {
2148: r += booke206_tlb_size(env, i);
2149: }
2150:
2151: return &env->tlb.tlbm[r];
2152: }
2153:
1.1.1.12! root 2154: /* returns bitmap of supported page sizes for a given TLB */
! 2155: static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
! 2156: {
! 2157: bool mav2 = false;
! 2158: uint32_t ret = 0;
! 2159:
! 2160: if (mav2) {
! 2161: ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
! 2162: } else {
! 2163: uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
! 2164: uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
! 2165: uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
! 2166: int i;
! 2167: for (i = min; i <= max; i++) {
! 2168: ret |= (1 << (i << 1));
! 2169: }
! 2170: }
! 2171:
! 2172: return ret;
! 2173: }
! 2174:
1.1.1.10 root 2175: #endif
2176:
1.1.1.12! root 2177: extern void (*cpu_ppc_hypercall)(CPUPPCState *);
1.1.1.10 root 2178:
1.1.1.12! root 2179: static inline bool cpu_has_work(CPUPPCState *env)
1.1.1.10 root 2180: {
2181: return msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD);
2182: }
2183:
2184: #include "exec-all.h"
2185:
1.1.1.12! root 2186: static inline void cpu_pc_from_tb(CPUPPCState *env, TranslationBlock *tb)
1.1.1.10 root 2187: {
2188: env->nip = tb->pc;
2189: }
2190:
1.1.1.12! root 2191: void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
1.1.1.11 root 2192:
1.1 root 2193: #endif /* !defined (__CPU_PPC_H__) */
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