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1.1 root 1: /*
2: * PowerPC emulation cpu definitions for qemu.
3: *
4: * Copyright (c) 2003-2005 Jocelyn Mayer
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
17: * License along with this library; if not, write to the Free Software
18: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19: */
20: #if !defined (__CPU_PPC_H__)
21: #define __CPU_PPC_H__
22:
23: #include "config.h"
24:
25: #define TARGET_LONG_BITS 32
26:
27: #include "cpu-defs.h"
28:
29: #include <setjmp.h>
30:
31: #include "softfloat.h"
32:
33: #define TARGET_HAS_ICE 1
34:
35: /* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
36: * have different cache line sizes
37: */
38: #define ICACHE_LINE_SIZE 32
39: #define DCACHE_LINE_SIZE 32
40:
41: /* XXX: put this in a common place */
42: #define likely(x) __builtin_expect(!!(x), 1)
43:
44: /*****************************************************************************/
45: /* PVR definitions for most known PowerPC */
46: enum {
47: /* PowerPC 401 cores */
48: CPU_PPC_401A1 = 0x00210000,
49: CPU_PPC_401B2 = 0x00220000,
50: CPU_PPC_401C2 = 0x00230000,
51: CPU_PPC_401D2 = 0x00240000,
52: CPU_PPC_401E2 = 0x00250000,
53: CPU_PPC_401F2 = 0x00260000,
54: CPU_PPC_401G2 = 0x00270000,
55: CPU_PPC_IOP480 = 0x40100000,
56: /* PowerPC 403 cores */
57: CPU_PPC_403GA = 0x00200000,
58: CPU_PPC_403GB = 0x00200100,
59: CPU_PPC_403GC = 0x00200200,
60: CPU_PPC_403GCX = 0x00201400,
61: /* PowerPC 405 cores */
62: CPU_PPC_405 = 0x40110000,
63: CPU_PPC_405EP = 0x51210000,
64: CPU_PPC_405GPR = 0x50910000,
65: CPU_PPC_405D2 = 0x20010000,
66: CPU_PPC_405D4 = 0x41810000,
67: CPU_PPC_NPE405H = 0x41410000,
68: CPU_PPC_NPE405L = 0x41610000,
69: #if 0
70: CPU_PPC_STB02 = xxx,
71: #endif
72: CPU_PPC_STB03 = 0x40310000,
73: #if 0
74: CPU_PPC_STB04 = xxx,
75: #endif
76: CPU_PPC_STB25 = 0x51510000,
77: #if 0
78: CPU_PPC_STB130 = xxx,
79: #endif
80: /* PowerPC 440 cores */
81: CPU_PPC_440EP = 0x42220000,
82: CPU_PPC_440GP = 0x40120400,
83: CPU_PPC_440GX = 0x51B20000,
84: /* PowerPC MPC 8xx cores */
85: CPU_PPC_8540 = 0x80200000,
86: CPU_PPC_8xx = 0x00500000,
87: CPU_PPC_8240 = 0x00810100,
88: CPU_PPC_8245 = 0x00811014,
89: /* PowerPC 6xx cores */
90: CPU_PPC_601 = 0x00010000,
91: CPU_PPC_602 = 0x00050000,
92: CPU_PPC_603 = 0x00030000,
93: CPU_PPC_603E = 0x00060000,
94: CPU_PPC_603EV = 0x00070000,
95: CPU_PPC_603R = 0x00071000,
96: CPU_PPC_G2 = 0x80810000,
97: CPU_PPC_G2LE = 0x80820000,
98: CPU_PPC_604 = 0x00040000,
99: CPU_PPC_604E = 0x00090000,
100: CPU_PPC_604R = 0x000a0000,
101: /* PowerPC 74x/75x cores (aka G3) */
102: CPU_PPC_74x = 0x00080000,
103: CPU_PPC_755 = 0x00083000,
104: CPU_PPC_74xP = 0x10080000,
105: CPU_PPC_750CXE22 = 0x00082202,
106: CPU_PPC_750CXE24 = 0x00082214,
107: CPU_PPC_750CXE24b = 0x00083214,
108: CPU_PPC_750CXE31 = 0x00083211,
109: CPU_PPC_750CXE31b = 0x00083311,
110: #define CPU_PPC_750CXE CPU_PPC_750CXE31b
111: CPU_PPC_750FX = 0x70000000,
112: CPU_PPC_750GX = 0x70020000,
113: /* PowerPC 74xx cores (aka G4) */
114: CPU_PPC_7400 = 0x000C0000,
115: CPU_PPC_7410 = 0x800C0000,
116: CPU_PPC_7441 = 0x80000200,
117: CPU_PPC_7450 = 0x80000000,
118: CPU_PPC_7451 = 0x80000203,
119: CPU_PPC_7455 = 0x80010000,
120: CPU_PPC_7457 = 0x80020000,
121: CPU_PPC_7457A = 0x80030000,
122: /* 64 bits PowerPC */
123: CPU_PPC_620 = 0x00140000,
124: CPU_PPC_630 = 0x00400000,
125: CPU_PPC_631 = 0x00410000,
126: CPU_PPC_POWER4 = 0x00350000,
127: CPU_PPC_POWER4P = 0x00380000,
128: CPU_PPC_POWER5 = 0x003A0000,
129: CPU_PPC_POWER5P = 0x003B0000,
130: CPU_PPC_970 = 0x00390000,
131: CPU_PPC_970FX = 0x003C0000,
132: CPU_PPC_RS64 = 0x00330000,
133: CPU_PPC_RS64II = 0x00340000,
134: CPU_PPC_RS64III = 0x00360000,
135: CPU_PPC_RS64IV = 0x00370000,
136: /* Original POWER */
137: /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
138: * POWER2 (RIOS2) & RSC2 (P2SC) here
139: */
140: #if 0
141: CPU_POWER = xxx,
142: #endif
143: #if 0
144: CPU_POWER2 = xxx,
145: #endif
146: };
147:
148: /* System version register (used on MPC 8xx) */
149: enum {
150: PPC_SVR_8540 = 0x80300000,
151: PPC_SVR_8541E = 0x807A0000,
152: PPC_SVR_8555E = 0x80790000,
153: PPC_SVR_8560 = 0x80700000,
154: };
155:
156: /*****************************************************************************/
157: /* Instruction types */
158: enum {
159: PPC_NONE = 0x00000000,
160: /* integer operations instructions */
161: /* flow control instructions */
162: /* virtual memory instructions */
163: /* ld/st with reservation instructions */
164: /* cache control instructions */
165: /* spr/msr access instructions */
166: PPC_INSNS_BASE = 0x00000001,
167: #define PPC_INTEGER PPC_INSNS_BASE
168: #define PPC_FLOW PPC_INSNS_BASE
169: #define PPC_MEM PPC_INSNS_BASE
170: #define PPC_RES PPC_INSNS_BASE
171: #define PPC_CACHE PPC_INSNS_BASE
172: #define PPC_MISC PPC_INSNS_BASE
173: /* floating point operations instructions */
174: PPC_FLOAT = 0x00000002,
175: /* more floating point operations instructions */
176: PPC_FLOAT_EXT = 0x00000004,
177: /* external control instructions */
178: PPC_EXTERN = 0x00000008,
179: /* segment register access instructions */
180: PPC_SEGMENT = 0x00000010,
181: /* Optional cache control instructions */
182: PPC_CACHE_OPT = 0x00000020,
183: /* Optional floating point op instructions */
184: PPC_FLOAT_OPT = 0x00000040,
185: /* Optional memory control instructions */
186: PPC_MEM_TLBIA = 0x00000080,
187: PPC_MEM_TLBIE = 0x00000100,
188: PPC_MEM_TLBSYNC = 0x00000200,
189: /* eieio & sync */
190: PPC_MEM_SYNC = 0x00000400,
191: /* PowerPC 6xx TLB management instructions */
192: PPC_6xx_TLB = 0x00000800,
193: /* Altivec support */
194: PPC_ALTIVEC = 0x00001000,
195: /* Time base support */
196: PPC_TB = 0x00002000,
197: /* Embedded PowerPC dedicated instructions */
198: PPC_4xx_COMMON = 0x00004000,
199: /* PowerPC 40x exception model */
200: PPC_40x_EXCP = 0x00008000,
201: /* PowerPC 40x specific instructions */
202: PPC_40x_SPEC = 0x00010000,
203: /* PowerPC 405 Mac instructions */
204: PPC_405_MAC = 0x00020000,
205: /* PowerPC 440 specific instructions */
206: PPC_440_SPEC = 0x00040000,
207: /* Specific extensions */
208: /* Power-to-PowerPC bridge (601) */
209: PPC_POWER_BR = 0x00080000,
210: /* PowerPC 602 specific */
211: PPC_602_SPEC = 0x00100000,
212: /* Deprecated instructions */
213: /* Original POWER instruction set */
214: PPC_POWER = 0x00200000,
215: /* POWER2 instruction set extension */
216: PPC_POWER2 = 0x00400000,
217: /* Power RTC support */
218: PPC_POWER_RTC = 0x00800000,
219: /* 64 bits PowerPC instructions */
220: /* 64 bits PowerPC instruction set */
221: PPC_64B = 0x01000000,
222: /* 64 bits hypervisor extensions */
223: PPC_64H = 0x02000000,
224: /* 64 bits PowerPC "bridge" features */
225: PPC_64_BRIDGE = 0x04000000,
226: };
227:
228: /* CPU run-time flags (MMU and exception model) */
229: enum {
230: /* MMU model */
231: #define PPC_FLAGS_MMU_MASK (0x0000000F)
232: /* Standard 32 bits PowerPC MMU */
233: PPC_FLAGS_MMU_32B = 0x00000000,
234: /* Standard 64 bits PowerPC MMU */
235: PPC_FLAGS_MMU_64B = 0x00000001,
236: /* PowerPC 601 MMU */
237: PPC_FLAGS_MMU_601 = 0x00000002,
238: /* PowerPC 6xx MMU with software TLB */
239: PPC_FLAGS_MMU_SOFT_6xx = 0x00000003,
240: /* PowerPC 4xx MMU with software TLB */
241: PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
242: /* PowerPC 403 MMU */
243: PPC_FLAGS_MMU_403 = 0x00000005,
244: /* Exception model */
245: #define PPC_FLAGS_EXCP_MASK (0x000000F0)
246: /* Standard PowerPC exception model */
247: PPC_FLAGS_EXCP_STD = 0x00000000,
248: /* PowerPC 40x exception model */
249: PPC_FLAGS_EXCP_40x = 0x00000010,
250: /* PowerPC 601 exception model */
251: PPC_FLAGS_EXCP_601 = 0x00000020,
252: /* PowerPC 602 exception model */
253: PPC_FLAGS_EXCP_602 = 0x00000030,
254: /* PowerPC 603 exception model */
255: PPC_FLAGS_EXCP_603 = 0x00000040,
256: /* PowerPC 604 exception model */
257: PPC_FLAGS_EXCP_604 = 0x00000050,
258: /* PowerPC 7x0 exception model */
259: PPC_FLAGS_EXCP_7x0 = 0x00000060,
260: /* PowerPC 7x5 exception model */
261: PPC_FLAGS_EXCP_7x5 = 0x00000070,
262: /* PowerPC 74xx exception model */
263: PPC_FLAGS_EXCP_74xx = 0x00000080,
264: /* PowerPC 970 exception model */
265: PPC_FLAGS_EXCP_970 = 0x00000090,
266: };
267:
268: #define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)
269: #define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)
270:
271: /*****************************************************************************/
272: /* Supported instruction set definitions */
273: /* This generates an empty opcode table... */
274: #define PPC_INSNS_TODO (PPC_NONE)
275: #define PPC_FLAGS_TODO (0x00000000)
276:
277: /* PowerPC 40x instruction set */
278: #define PPC_INSNS_4xx (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_4xx_COMMON)
279: /* PowerPC 401 */
280: #define PPC_INSNS_401 (PPC_INSNS_TODO)
281: #define PPC_FLAGS_401 (PPC_FLAGS_TODO)
282: /* PowerPC 403 */
283: #define PPC_INSNS_403 (PPC_INSNS_4xx | PPC_MEM_SYNC | PPC_MEM_TLBIA | \
284: PPC_40x_EXCP | PPC_40x_SPEC)
285: #define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x)
286: /* PowerPC 405 */
287: #define PPC_INSNS_405 (PPC_INSNS_4xx | PPC_MEM_SYNC | PPC_CACHE_OPT | \
288: PPC_MEM_TLBIA | PPC_TB | PPC_40x_SPEC | PPC_40x_EXCP | \
289: PPC_405_MAC)
290: #define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
291: /* PowerPC 440 */
292: #define PPC_INSNS_440 (PPC_INSNS_4xx | PPC_CACHE_OPT | PPC_405_MAC | \
293: PPC_440_SPEC)
294: #define PPC_FLAGS_440 (PPC_FLAGS_TODO)
295: /* Non-embedded PowerPC */
296: #define PPC_INSNS_COMMON (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
297: PPC_SEGMENT | PPC_MEM_TLBIE)
298: /* PowerPC 601 */
299: #define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
300: #define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601)
301: /* PowerPC 602 */
302: #define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
303: PPC_MEM_TLBSYNC | PPC_TB)
304: #define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602)
305: /* PowerPC 603 */
306: #define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
307: PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
308: #define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
309: /* PowerPC G2 */
310: #define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
311: PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
312: #define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
313: /* PowerPC 604 */
314: #define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
315: PPC_MEM_TLBSYNC | PPC_TB)
316: #define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604)
317: /* PowerPC 740/750 (aka G3) */
318: #define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
319: PPC_MEM_TLBSYNC | PPC_TB)
320: #define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0)
321: /* PowerPC 745/755 */
322: #define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
323: PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB)
324: #define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5)
325: /* PowerPC 74xx (aka G4) */
326: #define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC | \
327: PPC_MEM_TLBSYNC | PPC_TB)
328: #define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx)
329:
330: /* Default PowerPC will be 604/970 */
331: #define PPC_INSNS_PPC32 PPC_INSNS_604
332: #define PPC_FLAGS_PPC32 PPC_FLAGS_604
333: #if 0
334: #define PPC_INSNS_PPC64 PPC_INSNS_970
335: #define PPC_FLAGS_PPC64 PPC_FLAGS_970
336: #endif
337: #define PPC_INSNS_DEFAULT PPC_INSNS_604
338: #define PPC_FLAGS_DEFAULT PPC_FLAGS_604
339: typedef struct ppc_def_t ppc_def_t;
340:
341: /*****************************************************************************/
342: /* Types used to describe some PowerPC registers */
343: typedef struct CPUPPCState CPUPPCState;
344: typedef struct opc_handler_t opc_handler_t;
345: typedef struct ppc_tb_t ppc_tb_t;
346: typedef struct ppc_spr_t ppc_spr_t;
347: typedef struct ppc_dcr_t ppc_dcr_t;
348: typedef struct ppc_avr_t ppc_avr_t;
349:
350: /* SPR access micro-ops generations callbacks */
351: struct ppc_spr_t {
352: void (*uea_read)(void *opaque, int spr_num);
353: void (*uea_write)(void *opaque, int spr_num);
354: void (*oea_read)(void *opaque, int spr_num);
355: void (*oea_write)(void *opaque, int spr_num);
356: const unsigned char *name;
357: };
358:
359: /* Altivec registers (128 bits) */
360: struct ppc_avr_t {
361: uint32_t u[4];
362: };
363:
364: /* Software TLB cache */
365: typedef struct ppc_tlb_t ppc_tlb_t;
366: struct ppc_tlb_t {
367: /* Physical page number */
368: target_phys_addr_t RPN;
369: /* Virtual page number */
370: target_ulong VPN;
371: /* Page size */
372: target_ulong size;
373: /* Protection bits */
374: int prot;
375: int is_user;
376: uint32_t private;
377: uint32_t flags;
378: };
379:
380: /*****************************************************************************/
381: /* Machine state register bits definition */
382: #define MSR_SF 63 /* Sixty-four-bit mode */
383: #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
384: #define MSR_HV 60 /* hypervisor state */
385: #define MSR_VR 25 /* altivec available */
386: #define MSR_AP 23 /* Access privilege state on 602 */
387: #define MSR_SA 22 /* Supervisor access mode on 602 */
388: #define MSR_KEY 19 /* key bit on 603e */
389: #define MSR_POW 18 /* Power management */
390: #define MSR_WE 18 /* Wait state enable on embedded PowerPC */
391: #define MSR_TGPR 17 /* TGPR usage on 602/603 */
392: #define MSR_TLB 17 /* TLB on ? */
393: #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC */
394: #define MSR_ILE 16 /* Interrupt little-endian mode */
395: #define MSR_EE 15 /* External interrupt enable */
396: #define MSR_PR 14 /* Problem state */
397: #define MSR_FP 13 /* Floating point available */
398: #define MSR_ME 12 /* Machine check interrupt enable */
399: #define MSR_FE0 11 /* Floating point exception mode 0 */
400: #define MSR_SE 10 /* Single-step trace enable */
401: #define MSR_DWE 10 /* Debug wait enable on 405 */
402: #define MSR_BE 9 /* Branch trace enable */
403: #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC */
404: #define MSR_FE1 8 /* Floating point exception mode 1 */
405: #define MSR_AL 7 /* AL bit on POWER */
406: #define MSR_IP 6 /* Interrupt prefix */
407: #define MSR_IR 5 /* Instruction relocate */
408: #define MSR_IS 5 /* Instruction address space on embedded PowerPC */
409: #define MSR_DR 4 /* Data relocate */
410: #define MSR_DS 4 /* Data address space on embedded PowerPC */
411: #define MSR_PE 3 /* Protection enable on 403 */
412: #define MSR_EP 3 /* Exception prefix on 601 */
413: #define MSR_PX 2 /* Protection exclusive on 403 */
414: #define MSR_PMM 2 /* Performance monitor mark on POWER */
415: #define MSR_RI 1 /* Recoverable interrupt */
416: #define MSR_LE 0 /* Little-endian mode */
417: #define msr_sf env->msr[MSR_SF]
418: #define msr_isf env->msr[MSR_ISF]
419: #define msr_hv env->msr[MSR_HV]
420: #define msr_vr env->msr[MSR_VR]
421: #define msr_ap env->msr[MSR_AP]
422: #define msr_sa env->msr[MSR_SA]
423: #define msr_key env->msr[MSR_KEY]
424: #define msr_pow env->msr[MSR_POW]
425: #define msr_we env->msr[MSR_WE]
426: #define msr_tgpr env->msr[MSR_TGPR]
427: #define msr_tlb env->msr[MSR_TLB]
428: #define msr_ce env->msr[MSR_CE]
429: #define msr_ile env->msr[MSR_ILE]
430: #define msr_ee env->msr[MSR_EE]
431: #define msr_pr env->msr[MSR_PR]
432: #define msr_fp env->msr[MSR_FP]
433: #define msr_me env->msr[MSR_ME]
434: #define msr_fe0 env->msr[MSR_FE0]
435: #define msr_se env->msr[MSR_SE]
436: #define msr_dwe env->msr[MSR_DWE]
437: #define msr_be env->msr[MSR_BE]
438: #define msr_de env->msr[MSR_DE]
439: #define msr_fe1 env->msr[MSR_FE1]
440: #define msr_al env->msr[MSR_AL]
441: #define msr_ip env->msr[MSR_IP]
442: #define msr_ir env->msr[MSR_IR]
443: #define msr_is env->msr[MSR_IS]
444: #define msr_dr env->msr[MSR_DR]
445: #define msr_ds env->msr[MSR_DS]
446: #define msr_pe env->msr[MSR_PE]
447: #define msr_ep env->msr[MSR_EP]
448: #define msr_px env->msr[MSR_PX]
449: #define msr_pmm env->msr[MSR_PMM]
450: #define msr_ri env->msr[MSR_RI]
451: #define msr_le env->msr[MSR_LE]
452:
453: /*****************************************************************************/
454: /* The whole PowerPC CPU context */
455: struct CPUPPCState {
456: /* First are the most commonly used resources
457: * during translated code execution
458: */
459: #if TARGET_LONG_BITS > HOST_LONG_BITS
460: /* temporary fixed-point registers
461: * used to emulate 64 bits target on 32 bits hosts
462: */
463: target_ulong t0, t1, t2;
464: #endif
465: /* general purpose registers */
466: target_ulong gpr[32];
467: /* LR */
468: target_ulong lr;
469: /* CTR */
470: target_ulong ctr;
471: /* condition register */
472: uint8_t crf[8];
473: /* XER */
474: /* XXX: We use only 5 fields, but we want to keep the structure aligned */
475: uint8_t xer[8];
476: /* Reservation address */
477: target_ulong reserve;
478:
479: /* Those ones are used in supervisor mode only */
480: /* machine state register */
481: uint8_t msr[64];
482: /* temporary general purpose registers */
483: target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
484:
485: /* Floating point execution context */
486: /* temporary float registers */
487: float64 ft0;
488: float64 ft1;
489: float64 ft2;
490: float_status fp_status;
491: /* floating point registers */
492: float64 fpr[32];
493: /* floating point status and control register */
494: uint8_t fpscr[8];
495:
1.1.1.2 ! root 496: CPU_COMMON
! 497:
! 498: int halted; /* TRUE if the CPU is in suspend state */
! 499:
1.1 root 500: int access_type; /* when a memory exception occurs, the access
501: type is stored here */
502:
503: /* MMU context */
504: /* Address space register */
505: target_ulong asr;
506: /* segment registers */
507: target_ulong sdr1;
508: target_ulong sr[16];
509: /* BATs */
510: int nb_BATs;
511: target_ulong DBAT[2][8];
512: target_ulong IBAT[2][8];
513:
514: /* Other registers */
515: /* Special purpose registers */
516: target_ulong spr[1024];
517: /* Altivec registers */
518: ppc_avr_t avr[32];
519: uint32_t vscr;
520:
521: /* Internal devices resources */
522: /* Time base and decrementer */
523: ppc_tb_t *tb_env;
524: /* Device control registers */
525: int (*dcr_read)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong *val);
526: int (*dcr_write)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong val);
527: ppc_dcr_t *dcr_env;
528:
529: /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
530: int nb_tlb;
531: int nb_ways, last_way;
532: ppc_tlb_t tlb[128];
533: /* Callbacks for specific checks on some implementations */
534: int (*tlb_check_more)(CPUPPCState *env, struct ppc_tlb_t *tlb, int *prot,
535: target_ulong vaddr, int rw, int acc_type,
536: int is_user);
537: /* 403 dedicated access protection registers */
538: target_ulong pb[4];
539:
540: /* Those resources are used during exception processing */
541: /* CPU model definition */
542: uint64_t msr_mask;
543: uint32_t flags;
544:
545: int exception_index;
546: int error_code;
547: int interrupt_request;
548:
549: /* Those resources are used only during code translation */
550: /* Next instruction pointer */
551: target_ulong nip;
552: /* SPR translation callbacks */
553: ppc_spr_t spr_cb[1024];
554: /* opcode handlers */
555: opc_handler_t *opcodes[0x40];
556:
557: /* Those resources are used only in Qemu core */
558: jmp_buf jmp_env;
559: int user_mode_only; /* user mode only simulation */
560: uint32_t hflags;
561:
562: /* Power management */
563: int power_mode;
564:
565: /* temporary hack to handle OSI calls (only used if non NULL) */
566: int (*osi_call)(struct CPUPPCState *env);
567: };
568:
569: /*****************************************************************************/
570: CPUPPCState *cpu_ppc_init(void);
571: int cpu_ppc_exec(CPUPPCState *s);
572: void cpu_ppc_close(CPUPPCState *s);
573: /* you can call this signal handler from your SIGBUS and SIGSEGV
574: signal handlers to inform the virtual CPU of exceptions. non zero
575: is returned if the signal was handled by the virtual CPU. */
576: struct siginfo;
577: int cpu_ppc_signal_handler(int host_signum, struct siginfo *info,
578: void *puc);
579:
580: void do_interrupt (CPUPPCState *env);
581: void cpu_loop_exit(void);
582:
583: void dump_stack (CPUPPCState *env);
584:
585: target_ulong do_load_ibatu (CPUPPCState *env, int nr);
586: target_ulong do_load_ibatl (CPUPPCState *env, int nr);
587: void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
588: void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
589: target_ulong do_load_dbatu (CPUPPCState *env, int nr);
590: target_ulong do_load_dbatl (CPUPPCState *env, int nr);
591: void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
592: void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
593:
594: target_ulong do_load_nip (CPUPPCState *env);
595: void do_store_nip (CPUPPCState *env, target_ulong value);
596: target_ulong do_load_sdr1 (CPUPPCState *env);
597: void do_store_sdr1 (CPUPPCState *env, target_ulong value);
598: target_ulong do_load_asr (CPUPPCState *env);
599: void do_store_asr (CPUPPCState *env, target_ulong value);
600: target_ulong do_load_sr (CPUPPCState *env, int srnum);
601: void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
602: uint32_t do_load_cr (CPUPPCState *env);
603: void do_store_cr (CPUPPCState *env, uint32_t value, uint32_t mask);
604: uint32_t do_load_xer (CPUPPCState *env);
605: void do_store_xer (CPUPPCState *env, uint32_t value);
606: target_ulong do_load_msr (CPUPPCState *env);
607: void do_store_msr (CPUPPCState *env, target_ulong value);
608: float64 do_load_fpscr (CPUPPCState *env);
609: void do_store_fpscr (CPUPPCState *env, float64 f, uint32_t mask);
610:
611: void do_compute_hflags (CPUPPCState *env);
612:
613: int ppc_find_by_name (const unsigned char *name, ppc_def_t **def);
614: int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
615: void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
616: int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
617:
618: /* Time-base and decrementer management */
619: #ifndef NO_CPU_IO_DEFS
620: uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
621: uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
622: void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
623: void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
624: uint32_t cpu_ppc_load_decr (CPUPPCState *env);
625: void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
626: #endif
627:
628: #define TARGET_PAGE_BITS 12
629: #include "cpu-all.h"
630:
631: /*****************************************************************************/
632: /* Registers definitions */
633: #define ugpr(n) (env->gpr[n])
634:
635: #define XER_SO 31
636: #define XER_OV 30
637: #define XER_CA 29
638: #define XER_CMP 8
639: #define XER_BC 0
640: #define xer_so env->xer[4]
641: #define xer_ov env->xer[6]
642: #define xer_ca env->xer[2]
643: #define xer_cmp env->xer[1]
644: #define xer_bc env->xer[0]
645:
646: /* SPR definitions */
647: #define SPR_MQ (0x000)
648: #define SPR_XER (0x001)
649: #define SPR_601_VRTCU (0x004)
650: #define SPR_601_VRTCL (0x005)
651: #define SPR_601_UDECR (0x006)
652: #define SPR_LR (0x008)
653: #define SPR_CTR (0x009)
654: #define SPR_DSISR (0x012)
655: #define SPR_DAR (0x013)
656: #define SPR_601_RTCU (0x014)
657: #define SPR_601_RTCL (0x015)
658: #define SPR_DECR (0x016)
659: #define SPR_SDR1 (0x019)
660: #define SPR_SRR0 (0x01A)
661: #define SPR_SRR1 (0x01B)
662: #define SPR_440_PID (0x030)
663: #define SPR_440_DECAR (0x036)
664: #define SPR_CSRR0 (0x03A)
665: #define SPR_CSRR1 (0x03B)
666: #define SPR_440_DEAR (0x03D)
667: #define SPR_440_ESR (0x03E)
668: #define SPR_440_IVPR (0x03F)
669: #define SPR_8xx_EIE (0x050)
670: #define SPR_8xx_EID (0x051)
671: #define SPR_8xx_NRE (0x052)
672: #define SPR_58x_CMPA (0x090)
673: #define SPR_58x_CMPB (0x091)
674: #define SPR_58x_CMPC (0x092)
675: #define SPR_58x_CMPD (0x093)
676: #define SPR_58x_ICR (0x094)
677: #define SPR_58x_DER (0x094)
678: #define SPR_58x_COUNTA (0x096)
679: #define SPR_58x_COUNTB (0x097)
680: #define SPR_58x_CMPE (0x098)
681: #define SPR_58x_CMPF (0x099)
682: #define SPR_58x_CMPG (0x09A)
683: #define SPR_58x_CMPH (0x09B)
684: #define SPR_58x_LCTRL1 (0x09C)
685: #define SPR_58x_LCTRL2 (0x09D)
686: #define SPR_58x_ICTRL (0x09E)
687: #define SPR_58x_BAR (0x09F)
688: #define SPR_VRSAVE (0x100)
689: #define SPR_USPRG0 (0x100)
690: #define SPR_USPRG4 (0x104)
691: #define SPR_USPRG5 (0x105)
692: #define SPR_USPRG6 (0x106)
693: #define SPR_USPRG7 (0x107)
694: #define SPR_VTBL (0x10C)
695: #define SPR_VTBU (0x10D)
696: #define SPR_SPRG0 (0x110)
697: #define SPR_SPRG1 (0x111)
698: #define SPR_SPRG2 (0x112)
699: #define SPR_SPRG3 (0x113)
700: #define SPR_SPRG4 (0x114)
701: #define SPR_SCOMC (0x114)
702: #define SPR_SPRG5 (0x115)
703: #define SPR_SCOMD (0x115)
704: #define SPR_SPRG6 (0x116)
705: #define SPR_SPRG7 (0x117)
706: #define SPR_ASR (0x118)
707: #define SPR_EAR (0x11A)
708: #define SPR_TBL (0x11C)
709: #define SPR_TBU (0x11D)
710: #define SPR_SVR (0x11E)
711: #define SPR_440_PIR (0x11E)
712: #define SPR_PVR (0x11F)
713: #define SPR_HSPRG0 (0x130)
714: #define SPR_440_DBSR (0x130)
715: #define SPR_HSPRG1 (0x131)
716: #define SPR_440_DBCR0 (0x134)
717: #define SPR_IBCR (0x135)
718: #define SPR_440_DBCR1 (0x135)
719: #define SPR_DBCR (0x136)
720: #define SPR_HDEC (0x136)
721: #define SPR_440_DBCR2 (0x136)
722: #define SPR_HIOR (0x137)
723: #define SPR_MBAR (0x137)
724: #define SPR_RMOR (0x138)
725: #define SPR_440_IAC1 (0x138)
726: #define SPR_HRMOR (0x139)
727: #define SPR_440_IAC2 (0x139)
728: #define SPR_HSSR0 (0x13A)
729: #define SPR_440_IAC3 (0x13A)
730: #define SPR_HSSR1 (0x13B)
731: #define SPR_440_IAC4 (0x13B)
732: #define SPR_LPCR (0x13C)
733: #define SPR_440_DAC1 (0x13C)
734: #define SPR_LPIDR (0x13D)
735: #define SPR_DABR2 (0x13D)
736: #define SPR_440_DAC2 (0x13D)
737: #define SPR_440_DVC1 (0x13E)
738: #define SPR_440_DVC2 (0x13F)
739: #define SPR_440_TSR (0x150)
740: #define SPR_440_TCR (0x154)
741: #define SPR_440_IVOR0 (0x190)
742: #define SPR_440_IVOR1 (0x191)
743: #define SPR_440_IVOR2 (0x192)
744: #define SPR_440_IVOR3 (0x193)
745: #define SPR_440_IVOR4 (0x194)
746: #define SPR_440_IVOR5 (0x195)
747: #define SPR_440_IVOR6 (0x196)
748: #define SPR_440_IVOR7 (0x197)
749: #define SPR_440_IVOR8 (0x198)
750: #define SPR_440_IVOR9 (0x199)
751: #define SPR_440_IVOR10 (0x19A)
752: #define SPR_440_IVOR11 (0x19B)
753: #define SPR_440_IVOR12 (0x19C)
754: #define SPR_440_IVOR13 (0x19D)
755: #define SPR_440_IVOR14 (0x19E)
756: #define SPR_440_IVOR15 (0x19F)
757: #define SPR_IBAT0U (0x210)
758: #define SPR_IBAT0L (0x211)
759: #define SPR_IBAT1U (0x212)
760: #define SPR_IBAT1L (0x213)
761: #define SPR_IBAT2U (0x214)
762: #define SPR_IBAT2L (0x215)
763: #define SPR_IBAT3U (0x216)
764: #define SPR_IBAT3L (0x217)
765: #define SPR_DBAT0U (0x218)
766: #define SPR_DBAT0L (0x219)
767: #define SPR_DBAT1U (0x21A)
768: #define SPR_DBAT1L (0x21B)
769: #define SPR_DBAT2U (0x21C)
770: #define SPR_DBAT2L (0x21D)
771: #define SPR_DBAT3U (0x21E)
772: #define SPR_DBAT3L (0x21F)
773: #define SPR_IBAT4U (0x230)
774: #define SPR_IBAT4L (0x231)
775: #define SPR_IBAT5U (0x232)
776: #define SPR_IBAT5L (0x233)
777: #define SPR_IBAT6U (0x234)
778: #define SPR_IBAT6L (0x235)
779: #define SPR_IBAT7U (0x236)
780: #define SPR_IBAT7L (0x237)
781: #define SPR_DBAT4U (0x238)
782: #define SPR_DBAT4L (0x239)
783: #define SPR_DBAT5U (0x23A)
784: #define SPR_DBAT5L (0x23B)
785: #define SPR_DBAT6U (0x23C)
786: #define SPR_DBAT6L (0x23D)
787: #define SPR_DBAT7U (0x23E)
788: #define SPR_DBAT7L (0x23F)
789: #define SPR_440_INV0 (0x370)
790: #define SPR_440_INV1 (0x371)
791: #define SPR_440_INV2 (0x372)
792: #define SPR_440_INV3 (0x373)
793: #define SPR_440_IVT0 (0x374)
794: #define SPR_440_IVT1 (0x375)
795: #define SPR_440_IVT2 (0x376)
796: #define SPR_440_IVT3 (0x377)
797: #define SPR_440_DNV0 (0x390)
798: #define SPR_440_DNV1 (0x391)
799: #define SPR_440_DNV2 (0x392)
800: #define SPR_440_DNV3 (0x393)
801: #define SPR_440_DVT0 (0x394)
802: #define SPR_440_DVT1 (0x395)
803: #define SPR_440_DVT2 (0x396)
804: #define SPR_440_DVT3 (0x397)
805: #define SPR_440_DVLIM (0x398)
806: #define SPR_440_IVLIM (0x399)
807: #define SPR_440_RSTCFG (0x39B)
808: #define SPR_440_DCBTRL (0x39C)
809: #define SPR_440_DCBTRH (0x39D)
810: #define SPR_440_ICBTRL (0x39E)
811: #define SPR_440_ICBTRH (0x39F)
812: #define SPR_UMMCR0 (0x3A8)
813: #define SPR_UPMC1 (0x3A9)
814: #define SPR_UPMC2 (0x3AA)
815: #define SPR_USIA (0x3AB)
816: #define SPR_UMMCR1 (0x3AC)
817: #define SPR_UPMC3 (0x3AD)
818: #define SPR_UPMC4 (0x3AE)
819: #define SPR_USDA (0x3AF)
820: #define SPR_40x_ZPR (0x3B0)
821: #define SPR_40x_PID (0x3B1)
822: #define SPR_440_MMUCR (0x3B2)
823: #define SPR_4xx_CCR0 (0x3B3)
824: #define SPR_405_IAC3 (0x3B4)
825: #define SPR_405_IAC4 (0x3B5)
826: #define SPR_405_DVC1 (0x3B6)
827: #define SPR_405_DVC2 (0x3B7)
828: #define SPR_MMCR0 (0x3B8)
829: #define SPR_PMC1 (0x3B9)
830: #define SPR_40x_SGR (0x3B9)
831: #define SPR_PMC2 (0x3BA)
832: #define SPR_40x_DCWR (0x3BA)
833: #define SPR_SIA (0x3BB)
834: #define SPR_405_SLER (0x3BB)
835: #define SPR_MMCR1 (0x3BC)
836: #define SPR_405_SU0R (0x3BC)
837: #define SPR_PMC3 (0x3BD)
838: #define SPR_405_DBCR1 (0x3BD)
839: #define SPR_PMC4 (0x3BE)
840: #define SPR_SDA (0x3BF)
841: #define SPR_403_VTBL (0x3CC)
842: #define SPR_403_VTBU (0x3CD)
843: #define SPR_DMISS (0x3D0)
844: #define SPR_DCMP (0x3D1)
845: #define SPR_DHASH1 (0x3D2)
846: #define SPR_DHASH2 (0x3D3)
847: #define SPR_4xx_ICDBDR (0x3D3)
848: #define SPR_IMISS (0x3D4)
849: #define SPR_40x_ESR (0x3D4)
850: #define SPR_ICMP (0x3D5)
851: #define SPR_40x_DEAR (0x3D5)
852: #define SPR_RPA (0x3D6)
853: #define SPR_40x_EVPR (0x3D6)
854: #define SPR_403_CDBCR (0x3D7)
855: #define SPR_TCR (0x3D8)
856: #define SPR_40x_TSR (0x3D8)
857: #define SPR_IBR (0x3DA)
858: #define SPR_40x_TCR (0x3DA)
859: #define SPR_ESASR (0x3DB)
860: #define SPR_40x_PIT (0x3DB)
861: #define SPR_403_TBL (0x3DC)
862: #define SPR_403_TBU (0x3DD)
863: #define SPR_SEBR (0x3DE)
864: #define SPR_40x_SRR2 (0x3DE)
865: #define SPR_SER (0x3DF)
866: #define SPR_40x_SRR3 (0x3DF)
867: #define SPR_HID0 (0x3F0)
868: #define SPR_40x_DBSR (0x3F0)
869: #define SPR_HID1 (0x3F1)
870: #define SPR_IABR (0x3F2)
871: #define SPR_40x_DBCR0 (0x3F2)
872: #define SPR_601_HID2 (0x3F2)
873: #define SPR_HID2 (0x3F3)
874: #define SPR_440_DBDR (0x3F3)
875: #define SPR_40x_IAC1 (0x3F4)
876: #define SPR_DABR (0x3F5)
877: #define DABR_MASK (~(target_ulong)0x7)
878: #define SPR_40x_IAC2 (0x3F5)
879: #define SPR_601_HID5 (0x3F5)
880: #define SPR_40x_DAC1 (0x3F6)
881: #define SPR_40x_DAC2 (0x3F7)
882: #define SPR_L2PM (0x3F8)
883: #define SPR_750_HID2 (0x3F8)
884: #define SPR_L2CR (0x3F9)
885: #define SPR_IABR2 (0x3FA)
886: #define SPR_40x_DCCR (0x3FA)
887: #define SPR_ICTC (0x3FB)
888: #define SPR_40x_ICCR (0x3FB)
889: #define SPR_THRM1 (0x3FC)
890: #define SPR_403_PBL1 (0x3FC)
891: #define SPR_SP (0x3FD)
892: #define SPR_THRM2 (0x3FD)
893: #define SPR_403_PBU1 (0x3FD)
894: #define SPR_LT (0x3FE)
895: #define SPR_THRM3 (0x3FE)
896: #define SPR_FPECR (0x3FE)
897: #define SPR_403_PBL2 (0x3FE)
898: #define SPR_PIR (0x3FF)
899: #define SPR_403_PBU2 (0x3FF)
900: #define SPR_601_HID15 (0x3FF)
901:
902: /* Memory access type :
903: * may be needed for precise access rights control and precise exceptions.
904: */
905: enum {
906: /* 1 bit to define user level / supervisor access */
907: ACCESS_USER = 0x00,
908: ACCESS_SUPER = 0x01,
909: /* Type of instruction that generated the access */
910: ACCESS_CODE = 0x10, /* Code fetch access */
911: ACCESS_INT = 0x20, /* Integer load/store access */
912: ACCESS_FLOAT = 0x30, /* floating point load/store access */
913: ACCESS_RES = 0x40, /* load/store with reservation */
914: ACCESS_EXT = 0x50, /* external access */
915: ACCESS_CACHE = 0x60, /* Cache manipulation */
916: };
917:
918: /*****************************************************************************/
919: /* Exceptions */
920: #define EXCP_NONE -1
921: /* PowerPC hardware exceptions : exception vectors defined in PowerPC book 3 */
922: #define EXCP_RESET 0x0100 /* System reset */
923: #define EXCP_MACHINE_CHECK 0x0200 /* Machine check exception */
924: #define EXCP_DSI 0x0300 /* Data storage exception */
925: #define EXCP_DSEG 0x0380 /* Data segment exception */
926: #define EXCP_ISI 0x0400 /* Instruction storage exception */
927: #define EXCP_ISEG 0x0480 /* Instruction segment exception */
928: #define EXCP_EXTERNAL 0x0500 /* External interruption */
929: #define EXCP_ALIGN 0x0600 /* Alignment exception */
930: #define EXCP_PROGRAM 0x0700 /* Program exception */
931: #define EXCP_NO_FP 0x0800 /* Floating point unavailable exception */
932: #define EXCP_DECR 0x0900 /* Decrementer exception */
933: #define EXCP_HDECR 0x0980 /* Hypervisor decrementer exception */
934: #define EXCP_SYSCALL 0x0C00 /* System call */
935: #define EXCP_TRACE 0x0D00 /* Trace exception */
936: #define EXCP_PERF 0x0F00 /* Performance monitor exception */
937: /* Exceptions defined in PowerPC 32 bits programming environment manual */
938: #define EXCP_FP_ASSIST 0x0E00 /* Floating-point assist */
939: /* Implementation specific exceptions */
940: /* 40x exceptions */
941: #define EXCP_40x_PIT 0x1000 /* Programmable interval timer interrupt */
942: #define EXCP_40x_FIT 0x1010 /* Fixed interval timer interrupt */
943: #define EXCP_40x_WATCHDOG 0x1020 /* Watchdog timer exception */
944: #define EXCP_40x_DTLBMISS 0x1100 /* Data TLB miss exception */
945: #define EXCP_40x_ITLBMISS 0x1200 /* Instruction TLB miss exception */
946: #define EXCP_40x_DEBUG 0x2000 /* Debug exception */
947: /* 405 specific exceptions */
948: #define EXCP_405_APU 0x0F20 /* APU unavailable exception */
949: /* TLB assist exceptions (602/603) */
950: #define EXCP_I_TLBMISS 0x1000 /* Instruction TLB miss */
951: #define EXCP_DL_TLBMISS 0x1100 /* Data load TLB miss */
952: #define EXCP_DS_TLBMISS 0x1200 /* Data store TLB miss */
953: /* Breakpoint exceptions (602/603/604/620/740/745/750/755...) */
954: #define EXCP_IABR 0x1300 /* Instruction address breakpoint */
955: #define EXCP_SMI 0x1400 /* System management interrupt */
956: /* Altivec related exceptions */
957: #define EXCP_VPU 0x0F20 /* VPU unavailable exception */
958: /* 601 specific exceptions */
959: #define EXCP_601_IO 0x0600 /* IO error exception */
960: #define EXCP_601_RUNM 0x2000 /* Run mode exception */
961: /* 602 specific exceptions */
962: #define EXCP_602_WATCHDOG 0x1500 /* Watchdog exception */
963: #define EXCP_602_EMUL 0x1600 /* Emulation trap exception */
964: /* G2 specific exceptions */
965: #define EXCP_G2_CRIT 0x0A00 /* Critical interrupt */
966: /* MPC740/745/750 & IBM 750 specific exceptions */
967: #define EXCP_THRM 0x1700 /* Thermal management interrupt */
968: /* 74xx specific exceptions */
969: #define EXCP_74xx_VPUA 0x1600 /* VPU assist exception */
970: /* 970FX specific exceptions */
971: #define EXCP_970_SOFTP 0x1500 /* Soft patch exception */
972: #define EXCP_970_MAINT 0x1600 /* Maintenance exception */
973: #define EXCP_970_THRM 0x1800 /* Thermal exception */
974: #define EXCP_970_VPUA 0x1700 /* VPU assist exception */
975: /* End of exception vectors area */
976: #define EXCP_PPC_MAX 0x4000
977: /* Qemu exceptions: special cases we want to stop translation */
978: #define EXCP_MTMSR 0x11000 /* mtmsr instruction: */
979: /* may change privilege level */
980: #define EXCP_BRANCH 0x11001 /* branch instruction */
981: #define EXCP_SYSCALL_USER 0x12000 /* System call in user mode only */
982: #define EXCP_INTERRUPT_CRITICAL 0x13000 /* critical IRQ */
983:
984: /* Error codes */
985: enum {
986: /* Exception subtypes for EXCP_ALIGN */
987: EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
988: EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
989: EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
990: EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
991: EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
992: EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
993: /* Exception subtypes for EXCP_PROGRAM */
994: /* FP exceptions */
995: EXCP_FP = 0x10,
996: EXCP_FP_OX = 0x01, /* FP overflow */
997: EXCP_FP_UX = 0x02, /* FP underflow */
998: EXCP_FP_ZX = 0x03, /* FP divide by zero */
999: EXCP_FP_XX = 0x04, /* FP inexact */
1000: EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */
1001: EXCP_FP_VXISI = 0x06, /* FP invalid infinite substraction */
1002: EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
1003: EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
1004: EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
1005: EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
1006: EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
1007: EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
1008: EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
1009: /* Invalid instruction */
1010: EXCP_INVAL = 0x20,
1011: EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
1012: EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
1013: EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
1014: EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
1015: /* Privileged instruction */
1016: EXCP_PRIV = 0x30,
1017: EXCP_PRIV_OPC = 0x01,
1018: EXCP_PRIV_REG = 0x02,
1019: /* Trap */
1020: EXCP_TRAP = 0x40,
1021: };
1022:
1023: /*****************************************************************************/
1024:
1025: #endif /* !defined (__CPU_PPC_H__) */
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