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1.1 root 1: /*
2: * PowerPC emulation cpu definitions for qemu.
1.1.1.4 ! root 3: *
! 4: * Copyright (c) 2003-2007 Jocelyn Mayer
1.1 root 5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
17: * License along with this library; if not, write to the Free Software
18: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19: */
20: #if !defined (__CPU_PPC_H__)
21: #define __CPU_PPC_H__
22:
23: #include "config.h"
1.1.1.4 ! root 24: #include <inttypes.h>
! 25:
! 26: //#define PPC_EMULATE_32BITS_HYPV
! 27:
! 28: #if defined (TARGET_PPC64)
! 29: /* PowerPC 64 definitions */
! 30: typedef uint64_t ppc_gpr_t;
! 31: #define TARGET_LONG_BITS 64
! 32: #define TARGET_PAGE_BITS 12
! 33:
! 34: #else /* defined (TARGET_PPC64) */
! 35: /* PowerPC 32 definitions */
! 36: #if (HOST_LONG_BITS >= 64)
! 37: /* When using 64 bits temporary registers,
! 38: * we can use 64 bits GPR with no extra cost
! 39: * It's even an optimization as this will prevent
! 40: * the compiler to do unuseful masking in the micro-ops.
! 41: */
! 42: typedef uint64_t ppc_gpr_t;
! 43: #else /* (HOST_LONG_BITS >= 64) */
! 44: typedef uint32_t ppc_gpr_t;
! 45: #endif /* (HOST_LONG_BITS >= 64) */
1.1 root 46:
47: #define TARGET_LONG_BITS 32
48:
1.1.1.4 ! root 49: #if defined(TARGET_PPCEMB)
! 50: /* Specific definitions for PowerPC embedded */
! 51: /* BookE have 36 bits physical address space */
! 52: #define TARGET_PHYS_ADDR_BITS 64
! 53: #if defined(CONFIG_USER_ONLY)
! 54: /* It looks like a lot of Linux programs assume page size
! 55: * is 4kB long. This is evil, but we have to deal with it...
! 56: */
! 57: #define TARGET_PAGE_BITS 12
! 58: #else /* defined(CONFIG_USER_ONLY) */
! 59: /* Pages can be 1 kB small */
! 60: #define TARGET_PAGE_BITS 10
! 61: #endif /* defined(CONFIG_USER_ONLY) */
! 62: #else /* defined(TARGET_PPCEMB) */
! 63: /* "standard" PowerPC 32 definitions */
! 64: #define TARGET_PAGE_BITS 12
! 65: #endif /* defined(TARGET_PPCEMB) */
! 66:
! 67: #endif /* defined (TARGET_PPC64) */
! 68:
1.1 root 69: #include "cpu-defs.h"
70:
1.1.1.4 ! root 71: #define REGX "%016" PRIx64
! 72: #define ADDRX TARGET_FMT_lx
! 73: #define PADDRX TARGET_FMT_plx
! 74:
1.1 root 75: #include <setjmp.h>
76:
77: #include "softfloat.h"
78:
79: #define TARGET_HAS_ICE 1
80:
1.1.1.4 ! root 81: #if defined (TARGET_PPC64)
! 82: #define ELF_MACHINE EM_PPC64
! 83: #else
! 84: #define ELF_MACHINE EM_PPC
! 85: #endif
1.1 root 86:
87: /*****************************************************************************/
1.1.1.4 ! root 88: /* MMU model */
! 89: typedef enum powerpc_mmu_t powerpc_mmu_t;
! 90: enum powerpc_mmu_t {
! 91: POWERPC_MMU_UNKNOWN = 0x00000000,
! 92: /* Standard 32 bits PowerPC MMU */
! 93: POWERPC_MMU_32B = 0x00000001,
! 94: /* PowerPC 6xx MMU with software TLB */
! 95: POWERPC_MMU_SOFT_6xx = 0x00000002,
! 96: /* PowerPC 74xx MMU with software TLB */
! 97: POWERPC_MMU_SOFT_74xx = 0x00000003,
! 98: /* PowerPC 4xx MMU with software TLB */
! 99: POWERPC_MMU_SOFT_4xx = 0x00000004,
! 100: /* PowerPC 4xx MMU with software TLB and zones protections */
! 101: POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
! 102: /* PowerPC MMU in real mode only */
! 103: POWERPC_MMU_REAL = 0x00000006,
! 104: /* Freescale MPC8xx MMU model */
! 105: POWERPC_MMU_MPC8xx = 0x00000007,
! 106: /* BookE MMU model */
! 107: POWERPC_MMU_BOOKE = 0x00000008,
! 108: /* BookE FSL MMU model */
! 109: POWERPC_MMU_BOOKE_FSL = 0x00000009,
! 110: /* PowerPC 601 MMU model (specific BATs format) */
! 111: POWERPC_MMU_601 = 0x0000000A,
! 112: #if defined(TARGET_PPC64)
! 113: #define POWERPC_MMU_64 0x00010000
! 114: /* 64 bits PowerPC MMU */
! 115: POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
! 116: /* 620 variant (no segment exceptions) */
! 117: POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
! 118: #endif /* defined(TARGET_PPC64) */
1.1 root 119: };
120:
1.1.1.4 ! root 121: /*****************************************************************************/
! 122: /* Exception model */
! 123: typedef enum powerpc_excp_t powerpc_excp_t;
! 124: enum powerpc_excp_t {
! 125: POWERPC_EXCP_UNKNOWN = 0,
! 126: /* Standard PowerPC exception model */
! 127: POWERPC_EXCP_STD,
! 128: /* PowerPC 40x exception model */
! 129: POWERPC_EXCP_40x,
! 130: /* PowerPC 601 exception model */
! 131: POWERPC_EXCP_601,
! 132: /* PowerPC 602 exception model */
! 133: POWERPC_EXCP_602,
! 134: /* PowerPC 603 exception model */
! 135: POWERPC_EXCP_603,
! 136: /* PowerPC 603e exception model */
! 137: POWERPC_EXCP_603E,
! 138: /* PowerPC G2 exception model */
! 139: POWERPC_EXCP_G2,
! 140: /* PowerPC 604 exception model */
! 141: POWERPC_EXCP_604,
! 142: /* PowerPC 7x0 exception model */
! 143: POWERPC_EXCP_7x0,
! 144: /* PowerPC 7x5 exception model */
! 145: POWERPC_EXCP_7x5,
! 146: /* PowerPC 74xx exception model */
! 147: POWERPC_EXCP_74xx,
! 148: /* BookE exception model */
! 149: POWERPC_EXCP_BOOKE,
! 150: #if defined(TARGET_PPC64)
! 151: /* PowerPC 970 exception model */
! 152: POWERPC_EXCP_970,
! 153: #endif /* defined(TARGET_PPC64) */
1.1 root 154: };
155:
156: /*****************************************************************************/
1.1.1.4 ! root 157: /* Exception vectors definitions */
1.1 root 158: enum {
1.1.1.4 ! root 159: POWERPC_EXCP_NONE = -1,
! 160: /* The 64 first entries are used by the PowerPC embedded specification */
! 161: POWERPC_EXCP_CRITICAL = 0, /* Critical input */
! 162: POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
! 163: POWERPC_EXCP_DSI = 2, /* Data storage exception */
! 164: POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
! 165: POWERPC_EXCP_EXTERNAL = 4, /* External input */
! 166: POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
! 167: POWERPC_EXCP_PROGRAM = 6, /* Program exception */
! 168: POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
! 169: POWERPC_EXCP_SYSCALL = 8, /* System call exception */
! 170: POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
! 171: POWERPC_EXCP_DECR = 10, /* Decrementer exception */
! 172: POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
! 173: POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
! 174: POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
! 175: POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
! 176: POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
! 177: /* Vectors 16 to 31 are reserved */
! 178: POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
! 179: POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
! 180: POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
! 181: POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
! 182: POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
! 183: POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
! 184: /* Vectors 38 to 63 are reserved */
! 185: /* Exceptions defined in the PowerPC server specification */
! 186: POWERPC_EXCP_RESET = 64, /* System reset exception */
! 187: POWERPC_EXCP_DSEG = 65, /* Data segment exception */
! 188: POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
! 189: POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
! 190: POWERPC_EXCP_TRACE = 68, /* Trace exception */
! 191: POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
! 192: POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
! 193: POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
! 194: POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
! 195: POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
! 196: /* 40x specific exceptions */
! 197: POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
! 198: /* 601 specific exceptions */
! 199: POWERPC_EXCP_IO = 75, /* IO error exception */
! 200: POWERPC_EXCP_RUNM = 76, /* Run mode exception */
! 201: /* 602 specific exceptions */
! 202: POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
! 203: /* 602/603 specific exceptions */
! 204: POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
! 205: POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
! 206: POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
! 207: /* Exceptions available on most PowerPC */
! 208: POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
! 209: POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
! 210: POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
! 211: POWERPC_EXCP_SMI = 84, /* System management interrupt */
! 212: POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
! 213: /* 7xx/74xx specific exceptions */
! 214: POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
! 215: /* 74xx specific exceptions */
! 216: POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
! 217: /* 970FX specific exceptions */
! 218: POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
! 219: POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
! 220: /* Freescale embeded cores specific exceptions */
! 221: POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
! 222: POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
! 223: POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
! 224: POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
! 225: /* EOL */
! 226: POWERPC_EXCP_NB = 96,
! 227: /* Qemu exceptions: used internally during code translation */
! 228: POWERPC_EXCP_STOP = 0x200, /* stop translation */
! 229: POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
! 230: /* Qemu exceptions: special cases we want to stop translation */
! 231: POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
! 232: POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
1.1 root 233: };
234:
1.1.1.4 ! root 235: /* Exceptions error codes */
1.1 root 236: enum {
1.1.1.4 ! root 237: /* Exception subtypes for POWERPC_EXCP_ALIGN */
! 238: POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
! 239: POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
! 240: POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
! 241: POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
! 242: POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
! 243: POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
! 244: /* Exception subtypes for POWERPC_EXCP_PROGRAM */
! 245: /* FP exceptions */
! 246: POWERPC_EXCP_FP = 0x10,
! 247: POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
! 248: POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
! 249: POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
! 250: POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
! 251: POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
! 252: POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
! 253: POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
! 254: POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
! 255: POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
! 256: POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
! 257: POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
! 258: POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
! 259: POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
! 260: /* Invalid instruction */
! 261: POWERPC_EXCP_INVAL = 0x20,
! 262: POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
! 263: POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
! 264: POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
! 265: POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
! 266: /* Privileged instruction */
! 267: POWERPC_EXCP_PRIV = 0x30,
! 268: POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
! 269: POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
! 270: /* Trap */
! 271: POWERPC_EXCP_TRAP = 0x40,
! 272: };
! 273:
! 274: /*****************************************************************************/
! 275: /* Input pins model */
! 276: typedef enum powerpc_input_t powerpc_input_t;
! 277: enum powerpc_input_t {
! 278: PPC_FLAGS_INPUT_UNKNOWN = 0,
! 279: /* PowerPC 6xx bus */
! 280: PPC_FLAGS_INPUT_6xx,
! 281: /* BookE bus */
! 282: PPC_FLAGS_INPUT_BookE,
! 283: /* PowerPC 405 bus */
! 284: PPC_FLAGS_INPUT_405,
! 285: /* PowerPC 970 bus */
! 286: PPC_FLAGS_INPUT_970,
! 287: /* PowerPC 401 bus */
! 288: PPC_FLAGS_INPUT_401,
! 289: /* Freescale RCPU bus */
! 290: PPC_FLAGS_INPUT_RCPU,
1.1 root 291: };
292:
1.1.1.4 ! root 293: #define PPC_INPUT(env) (env->bus_model)
1.1 root 294:
295: /*****************************************************************************/
296: typedef struct ppc_def_t ppc_def_t;
1.1.1.4 ! root 297: typedef struct opc_handler_t opc_handler_t;
1.1 root 298:
299: /*****************************************************************************/
300: /* Types used to describe some PowerPC registers */
301: typedef struct CPUPPCState CPUPPCState;
302: typedef struct ppc_tb_t ppc_tb_t;
303: typedef struct ppc_spr_t ppc_spr_t;
304: typedef struct ppc_dcr_t ppc_dcr_t;
1.1.1.4 ! root 305: typedef union ppc_avr_t ppc_avr_t;
! 306: typedef union ppc_tlb_t ppc_tlb_t;
1.1 root 307:
308: /* SPR access micro-ops generations callbacks */
309: struct ppc_spr_t {
310: void (*uea_read)(void *opaque, int spr_num);
311: void (*uea_write)(void *opaque, int spr_num);
1.1.1.4 ! root 312: #if !defined(CONFIG_USER_ONLY)
1.1 root 313: void (*oea_read)(void *opaque, int spr_num);
314: void (*oea_write)(void *opaque, int spr_num);
1.1.1.4 ! root 315: void (*hea_read)(void *opaque, int spr_num);
! 316: void (*hea_write)(void *opaque, int spr_num);
! 317: #endif
1.1 root 318: const unsigned char *name;
319: };
320:
321: /* Altivec registers (128 bits) */
1.1.1.4 ! root 322: union ppc_avr_t {
! 323: uint8_t u8[16];
! 324: uint16_t u16[8];
! 325: uint32_t u32[4];
! 326: uint64_t u64[2];
1.1 root 327: };
328:
329: /* Software TLB cache */
1.1.1.4 ! root 330: typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
! 331: struct ppc6xx_tlb_t {
! 332: target_ulong pte0;
! 333: target_ulong pte1;
! 334: target_ulong EPN;
! 335: };
! 336:
! 337: typedef struct ppcemb_tlb_t ppcemb_tlb_t;
! 338: struct ppcemb_tlb_t {
1.1 root 339: target_phys_addr_t RPN;
1.1.1.4 ! root 340: target_ulong EPN;
! 341: target_ulong PID;
1.1 root 342: target_ulong size;
1.1.1.4 ! root 343: uint32_t prot;
! 344: uint32_t attr; /* Storage attributes */
! 345: };
! 346:
! 347: union ppc_tlb_t {
! 348: ppc6xx_tlb_t tlb6;
! 349: ppcemb_tlb_t tlbe;
1.1 root 350: };
351:
352: /*****************************************************************************/
353: /* Machine state register bits definition */
1.1.1.4 ! root 354: #define MSR_SF 63 /* Sixty-four-bit mode hflags */
! 355: #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
1.1 root 356: #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
1.1.1.4 ! root 357: #define MSR_SHV 60 /* hypervisor state hflags */
! 358: #define MSR_CM 31 /* Computation mode for BookE hflags */
! 359: #define MSR_ICM 30 /* Interrupt computation mode for BookE */
! 360: #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
! 361: #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
! 362: #define MSR_VR 25 /* altivec available x hflags */
! 363: #define MSR_SPE 25 /* SPE enable for BookE x hflags */
! 364: #define MSR_AP 23 /* Access privilege state on 602 hflags */
! 365: #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
1.1 root 366: #define MSR_KEY 19 /* key bit on 603e */
367: #define MSR_POW 18 /* Power management */
1.1.1.4 ! root 368: #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
! 369: #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
1.1 root 370: #define MSR_ILE 16 /* Interrupt little-endian mode */
371: #define MSR_EE 15 /* External interrupt enable */
1.1.1.4 ! root 372: #define MSR_PR 14 /* Problem state hflags */
! 373: #define MSR_FP 13 /* Floating point available hflags */
1.1 root 374: #define MSR_ME 12 /* Machine check interrupt enable */
1.1.1.4 ! root 375: #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
! 376: #define MSR_SE 10 /* Single-step trace enable x hflags */
! 377: #define MSR_DWE 10 /* Debug wait enable on 405 x */
! 378: #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
! 379: #define MSR_BE 9 /* Branch trace enable x hflags */
! 380: #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
! 381: #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
1.1 root 382: #define MSR_AL 7 /* AL bit on POWER */
1.1.1.4 ! root 383: #define MSR_EP 6 /* Exception prefix on 601 */
1.1 root 384: #define MSR_IR 5 /* Instruction relocate */
385: #define MSR_DR 4 /* Data relocate */
386: #define MSR_PE 3 /* Protection enable on 403 */
1.1.1.4 ! root 387: #define MSR_PX 2 /* Protection exclusive on 403 x */
! 388: #define MSR_PMM 2 /* Performance monitor mark on POWER x */
! 389: #define MSR_RI 1 /* Recoverable interrupt 1 */
! 390: #define MSR_LE 0 /* Little-endian mode 1 hflags */
! 391:
! 392: #define msr_sf ((env->msr >> MSR_SF) & 1)
! 393: #define msr_isf ((env->msr >> MSR_ISF) & 1)
! 394: #define msr_shv ((env->msr >> MSR_SHV) & 1)
! 395: #define msr_cm ((env->msr >> MSR_CM) & 1)
! 396: #define msr_icm ((env->msr >> MSR_ICM) & 1)
! 397: #define msr_thv ((env->msr >> MSR_THV) & 1)
! 398: #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
! 399: #define msr_vr ((env->msr >> MSR_VR) & 1)
! 400: #define msr_spe ((env->msr >> MSR_SE) & 1)
! 401: #define msr_ap ((env->msr >> MSR_AP) & 1)
! 402: #define msr_sa ((env->msr >> MSR_SA) & 1)
! 403: #define msr_key ((env->msr >> MSR_KEY) & 1)
! 404: #define msr_pow ((env->msr >> MSR_POW) & 1)
! 405: #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
! 406: #define msr_ce ((env->msr >> MSR_CE) & 1)
! 407: #define msr_ile ((env->msr >> MSR_ILE) & 1)
! 408: #define msr_ee ((env->msr >> MSR_EE) & 1)
! 409: #define msr_pr ((env->msr >> MSR_PR) & 1)
! 410: #define msr_fp ((env->msr >> MSR_FP) & 1)
! 411: #define msr_me ((env->msr >> MSR_ME) & 1)
! 412: #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
! 413: #define msr_se ((env->msr >> MSR_SE) & 1)
! 414: #define msr_dwe ((env->msr >> MSR_DWE) & 1)
! 415: #define msr_uble ((env->msr >> MSR_UBLE) & 1)
! 416: #define msr_be ((env->msr >> MSR_BE) & 1)
! 417: #define msr_de ((env->msr >> MSR_DE) & 1)
! 418: #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
! 419: #define msr_al ((env->msr >> MSR_AL) & 1)
! 420: #define msr_ep ((env->msr >> MSR_EP) & 1)
! 421: #define msr_ir ((env->msr >> MSR_IR) & 1)
! 422: #define msr_dr ((env->msr >> MSR_DR) & 1)
! 423: #define msr_pe ((env->msr >> MSR_PE) & 1)
! 424: #define msr_px ((env->msr >> MSR_PX) & 1)
! 425: #define msr_pmm ((env->msr >> MSR_PMM) & 1)
! 426: #define msr_ri ((env->msr >> MSR_RI) & 1)
! 427: #define msr_le ((env->msr >> MSR_LE) & 1)
! 428: /* Hypervisor bit is more specific */
! 429: #if defined(TARGET_PPC64)
! 430: #define MSR_HVB (1ULL << MSR_SHV)
! 431: #define msr_hv msr_shv
! 432: #else
! 433: #if defined(PPC_EMULATE_32BITS_HYPV)
! 434: #define MSR_HVB (1ULL << MSR_THV)
! 435: #define msr_hv msr_thv
! 436: #else
! 437: #define MSR_HVB (0ULL)
! 438: #define msr_hv (0)
! 439: #endif
! 440: #endif
! 441:
! 442: enum {
! 443: POWERPC_FLAG_NONE = 0x00000000,
! 444: /* Flag for MSR bit 25 signification (VRE/SPE) */
! 445: POWERPC_FLAG_SPE = 0x00000001,
! 446: POWERPC_FLAG_VRE = 0x00000002,
! 447: /* Flag for MSR bit 17 signification (TGPR/CE) */
! 448: POWERPC_FLAG_TGPR = 0x00000004,
! 449: POWERPC_FLAG_CE = 0x00000008,
! 450: /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
! 451: POWERPC_FLAG_SE = 0x00000010,
! 452: POWERPC_FLAG_DWE = 0x00000020,
! 453: POWERPC_FLAG_UBLE = 0x00000040,
! 454: /* Flag for MSR bit 9 signification (BE/DE) */
! 455: POWERPC_FLAG_BE = 0x00000080,
! 456: POWERPC_FLAG_DE = 0x00000100,
! 457: /* Flag for MSR bit 2 signification (PX/PMM) */
! 458: POWERPC_FLAG_PX = 0x00000200,
! 459: POWERPC_FLAG_PMM = 0x00000400,
! 460: /* Flag for special features */
! 461: /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
! 462: POWERPC_FLAG_RTC_CLK = 0x00010000,
! 463: POWERPC_FLAG_BUS_CLK = 0x00020000,
! 464: };
! 465:
! 466: /*****************************************************************************/
! 467: /* Floating point status and control register */
! 468: #define FPSCR_FX 31 /* Floating-point exception summary */
! 469: #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
! 470: #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
! 471: #define FPSCR_OX 28 /* Floating-point overflow exception */
! 472: #define FPSCR_UX 27 /* Floating-point underflow exception */
! 473: #define FPSCR_ZX 26 /* Floating-point zero divide exception */
! 474: #define FPSCR_XX 25 /* Floating-point inexact exception */
! 475: #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
! 476: #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
! 477: #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
! 478: #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
! 479: #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
! 480: #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
! 481: #define FPSCR_FR 18 /* Floating-point fraction rounded */
! 482: #define FPSCR_FI 17 /* Floating-point fraction inexact */
! 483: #define FPSCR_C 16 /* Floating-point result class descriptor */
! 484: #define FPSCR_FL 15 /* Floating-point less than or negative */
! 485: #define FPSCR_FG 14 /* Floating-point greater than or negative */
! 486: #define FPSCR_FE 13 /* Floating-point equal or zero */
! 487: #define FPSCR_FU 12 /* Floating-point unordered or NaN */
! 488: #define FPSCR_FPCC 12 /* Floating-point condition code */
! 489: #define FPSCR_FPRF 12 /* Floating-point result flags */
! 490: #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
! 491: #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
! 492: #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
! 493: #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
! 494: #define FPSCR_OE 6 /* Floating-point overflow exception enable */
! 495: #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
! 496: #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
! 497: #define FPSCR_XE 3 /* Floating-point inexact exception enable */
! 498: #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
! 499: #define FPSCR_RN1 1
! 500: #define FPSCR_RN 0 /* Floating-point rounding control */
! 501: #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
! 502: #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
! 503: #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
! 504: #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
! 505: #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
! 506: #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
! 507: #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
! 508: #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
! 509: #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
! 510: #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
! 511: #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
! 512: #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
! 513: #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
! 514: #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
! 515: #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
! 516: #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
! 517: #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
! 518: #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
! 519: #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
! 520: #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
! 521: #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
! 522: #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
! 523: #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
! 524: /* Invalid operation exception summary */
! 525: #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
! 526: (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
! 527: (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
! 528: (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
! 529: (1 << FPSCR_VXCVI)))
! 530: /* exception summary */
! 531: #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
! 532: /* enabled exception summary */
! 533: #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
! 534: 0x1F)
1.1 root 535:
536: /*****************************************************************************/
537: /* The whole PowerPC CPU context */
1.1.1.4 ! root 538: #define NB_MMU_MODES 3
! 539:
1.1 root 540: struct CPUPPCState {
541: /* First are the most commonly used resources
542: * during translated code execution
543: */
1.1.1.4 ! root 544: #if (HOST_LONG_BITS == 32)
1.1 root 545: /* temporary fixed-point registers
1.1.1.4 ! root 546: * used to emulate 64 bits registers on 32 bits hosts
1.1 root 547: */
1.1.1.4 ! root 548: uint64_t t0, t1, t2;
1.1 root 549: #endif
1.1.1.4 ! root 550: ppc_avr_t avr0, avr1, avr2;
! 551:
1.1 root 552: /* general purpose registers */
1.1.1.4 ! root 553: ppc_gpr_t gpr[32];
! 554: #if !defined(TARGET_PPC64)
! 555: /* Storage for GPR MSB, used by the SPE extension */
! 556: ppc_gpr_t gprh[32];
! 557: #endif
1.1 root 558: /* LR */
559: target_ulong lr;
560: /* CTR */
561: target_ulong ctr;
562: /* condition register */
563: uint8_t crf[8];
564: /* XER */
565: /* XXX: We use only 5 fields, but we want to keep the structure aligned */
566: uint8_t xer[8];
567: /* Reservation address */
568: target_ulong reserve;
569:
570: /* Those ones are used in supervisor mode only */
571: /* machine state register */
1.1.1.4 ! root 572: target_ulong msr;
1.1 root 573: /* temporary general purpose registers */
1.1.1.4 ! root 574: ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
1.1 root 575:
576: /* Floating point execution context */
1.1.1.4 ! root 577: /* temporary float registers */
1.1 root 578: float64 ft0;
579: float64 ft1;
580: float64 ft2;
581: float_status fp_status;
582: /* floating point registers */
583: float64 fpr[32];
584: /* floating point status and control register */
1.1.1.4 ! root 585: uint32_t fpscr;
1.1 root 586:
1.1.1.2 root 587: CPU_COMMON
588:
589: int halted; /* TRUE if the CPU is in suspend state */
590:
1.1 root 591: int access_type; /* when a memory exception occurs, the access
592: type is stored here */
593:
1.1.1.4 ! root 594: /* MMU context - only relevant for full system emulation */
! 595: #if !defined(CONFIG_USER_ONLY)
! 596: #if defined(TARGET_PPC64)
1.1 root 597: /* Address space register */
598: target_ulong asr;
1.1.1.4 ! root 599: /* PowerPC 64 SLB area */
! 600: int slb_nr;
! 601: #endif
1.1 root 602: /* segment registers */
603: target_ulong sdr1;
604: target_ulong sr[16];
605: /* BATs */
606: int nb_BATs;
607: target_ulong DBAT[2][8];
608: target_ulong IBAT[2][8];
1.1.1.4 ! root 609: /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
! 610: int nb_tlb; /* Total number of TLB */
! 611: int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
! 612: int nb_ways; /* Number of ways in the TLB set */
! 613: int last_way; /* Last used way used to allocate TLB in a LRU way */
! 614: int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
! 615: int nb_pids; /* Number of available PID registers */
! 616: ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
! 617: /* 403 dedicated access protection registers */
! 618: target_ulong pb[4];
! 619: #endif
1.1 root 620:
621: /* Other registers */
622: /* Special purpose registers */
623: target_ulong spr[1024];
1.1.1.4 ! root 624: ppc_spr_t spr_cb[1024];
1.1 root 625: /* Altivec registers */
626: ppc_avr_t avr[32];
627: uint32_t vscr;
1.1.1.4 ! root 628: /* SPE registers */
! 629: ppc_gpr_t spe_acc;
! 630: float_status spe_status;
! 631: uint32_t spe_fscr;
1.1 root 632:
633: /* Internal devices resources */
634: /* Time base and decrementer */
635: ppc_tb_t *tb_env;
636: /* Device control registers */
637: ppc_dcr_t *dcr_env;
638:
1.1.1.4 ! root 639: int dcache_line_size;
! 640: int icache_line_size;
1.1 root 641:
642: /* Those resources are used during exception processing */
643: /* CPU model definition */
1.1.1.4 ! root 644: target_ulong msr_mask;
! 645: powerpc_mmu_t mmu_model;
! 646: powerpc_excp_t excp_model;
! 647: powerpc_input_t bus_model;
! 648: int bfd_mach;
1.1 root 649: uint32_t flags;
650:
651: int exception_index;
652: int error_code;
653: int interrupt_request;
1.1.1.4 ! root 654: uint32_t pending_interrupts;
! 655: #if !defined(CONFIG_USER_ONLY)
! 656: /* This is the IRQ controller, which is implementation dependant
! 657: * and only relevant when emulating a complete machine.
! 658: */
! 659: uint32_t irq_input_state;
! 660: void **irq_inputs;
! 661: /* Exception vectors */
! 662: target_ulong excp_vectors[POWERPC_EXCP_NB];
! 663: target_ulong excp_prefix;
! 664: target_ulong ivor_mask;
! 665: target_ulong ivpr_mask;
! 666: target_ulong hreset_vector;
! 667: #endif
1.1 root 668:
669: /* Those resources are used only during code translation */
670: /* Next instruction pointer */
671: target_ulong nip;
1.1.1.4 ! root 672:
1.1 root 673: /* opcode handlers */
674: opc_handler_t *opcodes[0x40];
675:
676: /* Those resources are used only in Qemu core */
677: jmp_buf jmp_env;
678: int user_mode_only; /* user mode only simulation */
1.1.1.4 ! root 679: target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
! 680: target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
! 681: int mmu_idx; /* precomputed MMU index to speed up mem accesses */
1.1 root 682:
683: /* Power management */
684: int power_mode;
1.1.1.4 ! root 685: int (*check_pow)(CPUPPCState *env);
1.1 root 686:
687: /* temporary hack to handle OSI calls (only used if non NULL) */
688: int (*osi_call)(struct CPUPPCState *env);
689: };
690:
1.1.1.4 ! root 691: /* Context used internally during MMU translations */
! 692: typedef struct mmu_ctx_t mmu_ctx_t;
! 693: struct mmu_ctx_t {
! 694: target_phys_addr_t raddr; /* Real address */
! 695: int prot; /* Protection bits */
! 696: target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
! 697: target_ulong ptem; /* Virtual segment ID | API */
! 698: int key; /* Access key */
! 699: int nx; /* Non-execute area */
! 700: };
! 701:
1.1 root 702: /*****************************************************************************/
1.1.1.4 ! root 703: CPUPPCState *cpu_ppc_init (const char *cpu_model);
! 704: int cpu_ppc_exec (CPUPPCState *s);
! 705: void cpu_ppc_close (CPUPPCState *s);
1.1 root 706: /* you can call this signal handler from your SIGBUS and SIGSEGV
707: signal handlers to inform the virtual CPU of exceptions. non zero
708: is returned if the signal was handled by the virtual CPU. */
1.1.1.4 ! root 709: int cpu_ppc_signal_handler (int host_signum, void *pinfo,
! 710: void *puc);
1.1 root 711:
712: void do_interrupt (CPUPPCState *env);
1.1.1.4 ! root 713: void ppc_hw_interrupt (CPUPPCState *env);
! 714: void cpu_loop_exit (void);
1.1 root 715:
716: void dump_stack (CPUPPCState *env);
717:
1.1.1.4 ! root 718: #if !defined(CONFIG_USER_ONLY)
1.1 root 719: target_ulong do_load_ibatu (CPUPPCState *env, int nr);
720: target_ulong do_load_ibatl (CPUPPCState *env, int nr);
721: void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
722: void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
723: target_ulong do_load_dbatu (CPUPPCState *env, int nr);
724: target_ulong do_load_dbatl (CPUPPCState *env, int nr);
725: void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
726: void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
1.1.1.4 ! root 727: void do_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
! 728: void do_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
1.1 root 729: target_ulong do_load_sdr1 (CPUPPCState *env);
730: void do_store_sdr1 (CPUPPCState *env, target_ulong value);
1.1.1.4 ! root 731: #if defined(TARGET_PPC64)
! 732: target_ulong ppc_load_asr (CPUPPCState *env);
! 733: void ppc_store_asr (CPUPPCState *env, target_ulong value);
! 734: target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
! 735: void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs);
! 736: #endif /* defined(TARGET_PPC64) */
! 737: #if 0 // Unused
1.1 root 738: target_ulong do_load_sr (CPUPPCState *env, int srnum);
1.1.1.4 ! root 739: #endif
1.1 root 740: void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
1.1.1.4 ! root 741: #endif /* !defined(CONFIG_USER_ONLY) */
! 742: target_ulong ppc_load_xer (CPUPPCState *env);
! 743: void ppc_store_xer (CPUPPCState *env, target_ulong value);
! 744: void ppc_store_msr (CPUPPCState *env, target_ulong value);
1.1 root 745:
1.1.1.4 ! root 746: void cpu_ppc_reset (void *opaque);
1.1 root 747:
748: void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
1.1.1.4 ! root 749:
! 750: const ppc_def_t *cpu_ppc_find_by_name (const unsigned char *name);
! 751: int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
1.1 root 752:
753: /* Time-base and decrementer management */
754: #ifndef NO_CPU_IO_DEFS
755: uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
756: uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
757: void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
758: void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1.1.1.4 ! root 759: uint32_t cpu_ppc_load_atbl (CPUPPCState *env);
! 760: uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
! 761: void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
! 762: void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1.1 root 763: uint32_t cpu_ppc_load_decr (CPUPPCState *env);
764: void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1.1.1.4 ! root 765: uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
! 766: void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
! 767: uint64_t cpu_ppc_load_purr (CPUPPCState *env);
! 768: void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
! 769: uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
! 770: uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
! 771: #if !defined(CONFIG_USER_ONLY)
! 772: void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
! 773: void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
! 774: target_ulong load_40x_pit (CPUPPCState *env);
! 775: void store_40x_pit (CPUPPCState *env, target_ulong val);
! 776: void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
! 777: void store_40x_sler (CPUPPCState *env, uint32_t val);
! 778: void store_booke_tcr (CPUPPCState *env, target_ulong val);
! 779: void store_booke_tsr (CPUPPCState *env, target_ulong val);
! 780: void ppc_tlb_invalidate_all (CPUPPCState *env);
! 781: void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
! 782: #if defined(TARGET_PPC64)
! 783: void ppc_slb_invalidate_all (CPUPPCState *env);
! 784: void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
! 785: #endif
! 786: int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
! 787: #endif
1.1 root 788: #endif
789:
1.1.1.4 ! root 790: static always_inline uint64_t ppc_dump_gpr (CPUPPCState *env, int gprn)
! 791: {
! 792: uint64_t gprv;
! 793:
! 794: gprv = env->gpr[gprn];
! 795: #if !defined(TARGET_PPC64)
! 796: if (env->flags & POWERPC_FLAG_SPE) {
! 797: /* If the CPU implements the SPE extension, we have to get the
! 798: * high bits of the GPR from the gprh storage area
! 799: */
! 800: gprv &= 0xFFFFFFFFULL;
! 801: gprv |= (uint64_t)env->gprh[gprn] << 32;
! 802: }
! 803: #endif
! 804:
! 805: return gprv;
! 806: }
! 807:
! 808: /* Device control registers */
! 809: int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
! 810: int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
! 811:
! 812: #define CPUState CPUPPCState
! 813: #define cpu_init cpu_ppc_init
! 814: #define cpu_exec cpu_ppc_exec
! 815: #define cpu_gen_code cpu_ppc_gen_code
! 816: #define cpu_signal_handler cpu_ppc_signal_handler
! 817: #define cpu_list ppc_cpu_list
! 818:
! 819: /* MMU modes definitions */
! 820: #define MMU_MODE0_SUFFIX _user
! 821: #define MMU_MODE1_SUFFIX _kernel
! 822: #define MMU_MODE2_SUFFIX _hypv
! 823: #define MMU_USER_IDX 0
! 824: static inline int cpu_mmu_index (CPUState *env)
! 825: {
! 826: return env->mmu_idx;
! 827: }
! 828:
1.1 root 829: #include "cpu-all.h"
830:
831: /*****************************************************************************/
832: /* Registers definitions */
833: #define XER_SO 31
834: #define XER_OV 30
835: #define XER_CA 29
836: #define XER_CMP 8
1.1.1.4 ! root 837: #define XER_BC 0
1.1 root 838: #define xer_so env->xer[4]
839: #define xer_ov env->xer[6]
840: #define xer_ca env->xer[2]
841: #define xer_cmp env->xer[1]
1.1.1.4 ! root 842: #define xer_bc env->xer[0]
1.1 root 843:
844: /* SPR definitions */
1.1.1.4 ! root 845: #define SPR_MQ (0x000)
! 846: #define SPR_XER (0x001)
! 847: #define SPR_601_VRTCU (0x004)
! 848: #define SPR_601_VRTCL (0x005)
! 849: #define SPR_601_UDECR (0x006)
! 850: #define SPR_LR (0x008)
! 851: #define SPR_CTR (0x009)
! 852: #define SPR_DSISR (0x012)
! 853: #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
! 854: #define SPR_601_RTCU (0x014)
! 855: #define SPR_601_RTCL (0x015)
! 856: #define SPR_DECR (0x016)
! 857: #define SPR_SDR1 (0x019)
! 858: #define SPR_SRR0 (0x01A)
! 859: #define SPR_SRR1 (0x01B)
! 860: #define SPR_AMR (0x01D)
! 861: #define SPR_BOOKE_PID (0x030)
! 862: #define SPR_BOOKE_DECAR (0x036)
! 863: #define SPR_BOOKE_CSRR0 (0x03A)
! 864: #define SPR_BOOKE_CSRR1 (0x03B)
! 865: #define SPR_BOOKE_DEAR (0x03D)
! 866: #define SPR_BOOKE_ESR (0x03E)
! 867: #define SPR_BOOKE_IVPR (0x03F)
! 868: #define SPR_MPC_EIE (0x050)
! 869: #define SPR_MPC_EID (0x051)
! 870: #define SPR_MPC_NRI (0x052)
! 871: #define SPR_CTRL (0x088)
! 872: #define SPR_MPC_CMPA (0x090)
! 873: #define SPR_MPC_CMPB (0x091)
! 874: #define SPR_MPC_CMPC (0x092)
! 875: #define SPR_MPC_CMPD (0x093)
! 876: #define SPR_MPC_ECR (0x094)
! 877: #define SPR_MPC_DER (0x095)
! 878: #define SPR_MPC_COUNTA (0x096)
! 879: #define SPR_MPC_COUNTB (0x097)
! 880: #define SPR_UCTRL (0x098)
! 881: #define SPR_MPC_CMPE (0x098)
! 882: #define SPR_MPC_CMPF (0x099)
! 883: #define SPR_MPC_CMPG (0x09A)
! 884: #define SPR_MPC_CMPH (0x09B)
! 885: #define SPR_MPC_LCTRL1 (0x09C)
! 886: #define SPR_MPC_LCTRL2 (0x09D)
! 887: #define SPR_MPC_ICTRL (0x09E)
! 888: #define SPR_MPC_BAR (0x09F)
! 889: #define SPR_VRSAVE (0x100)
! 890: #define SPR_USPRG0 (0x100)
! 891: #define SPR_USPRG1 (0x101)
! 892: #define SPR_USPRG2 (0x102)
! 893: #define SPR_USPRG3 (0x103)
! 894: #define SPR_USPRG4 (0x104)
! 895: #define SPR_USPRG5 (0x105)
! 896: #define SPR_USPRG6 (0x106)
! 897: #define SPR_USPRG7 (0x107)
! 898: #define SPR_VTBL (0x10C)
! 899: #define SPR_VTBU (0x10D)
! 900: #define SPR_SPRG0 (0x110)
! 901: #define SPR_SPRG1 (0x111)
! 902: #define SPR_SPRG2 (0x112)
! 903: #define SPR_SPRG3 (0x113)
! 904: #define SPR_SPRG4 (0x114)
! 905: #define SPR_SCOMC (0x114)
! 906: #define SPR_SPRG5 (0x115)
! 907: #define SPR_SCOMD (0x115)
! 908: #define SPR_SPRG6 (0x116)
! 909: #define SPR_SPRG7 (0x117)
! 910: #define SPR_ASR (0x118)
! 911: #define SPR_EAR (0x11A)
! 912: #define SPR_TBL (0x11C)
! 913: #define SPR_TBU (0x11D)
! 914: #define SPR_TBU40 (0x11E)
! 915: #define SPR_SVR (0x11E)
! 916: #define SPR_BOOKE_PIR (0x11E)
! 917: #define SPR_PVR (0x11F)
! 918: #define SPR_HSPRG0 (0x130)
! 919: #define SPR_BOOKE_DBSR (0x130)
! 920: #define SPR_HSPRG1 (0x131)
! 921: #define SPR_HDSISR (0x132)
! 922: #define SPR_HDAR (0x133)
! 923: #define SPR_BOOKE_DBCR0 (0x134)
! 924: #define SPR_IBCR (0x135)
! 925: #define SPR_PURR (0x135)
! 926: #define SPR_BOOKE_DBCR1 (0x135)
! 927: #define SPR_DBCR (0x136)
! 928: #define SPR_HDEC (0x136)
! 929: #define SPR_BOOKE_DBCR2 (0x136)
! 930: #define SPR_HIOR (0x137)
! 931: #define SPR_MBAR (0x137)
! 932: #define SPR_RMOR (0x138)
! 933: #define SPR_BOOKE_IAC1 (0x138)
! 934: #define SPR_HRMOR (0x139)
! 935: #define SPR_BOOKE_IAC2 (0x139)
! 936: #define SPR_HSRR0 (0x13A)
! 937: #define SPR_BOOKE_IAC3 (0x13A)
! 938: #define SPR_HSRR1 (0x13B)
! 939: #define SPR_BOOKE_IAC4 (0x13B)
! 940: #define SPR_LPCR (0x13C)
! 941: #define SPR_BOOKE_DAC1 (0x13C)
! 942: #define SPR_LPIDR (0x13D)
! 943: #define SPR_DABR2 (0x13D)
! 944: #define SPR_BOOKE_DAC2 (0x13D)
! 945: #define SPR_BOOKE_DVC1 (0x13E)
! 946: #define SPR_BOOKE_DVC2 (0x13F)
! 947: #define SPR_BOOKE_TSR (0x150)
! 948: #define SPR_BOOKE_TCR (0x154)
! 949: #define SPR_BOOKE_IVOR0 (0x190)
! 950: #define SPR_BOOKE_IVOR1 (0x191)
! 951: #define SPR_BOOKE_IVOR2 (0x192)
! 952: #define SPR_BOOKE_IVOR3 (0x193)
! 953: #define SPR_BOOKE_IVOR4 (0x194)
! 954: #define SPR_BOOKE_IVOR5 (0x195)
! 955: #define SPR_BOOKE_IVOR6 (0x196)
! 956: #define SPR_BOOKE_IVOR7 (0x197)
! 957: #define SPR_BOOKE_IVOR8 (0x198)
! 958: #define SPR_BOOKE_IVOR9 (0x199)
! 959: #define SPR_BOOKE_IVOR10 (0x19A)
! 960: #define SPR_BOOKE_IVOR11 (0x19B)
! 961: #define SPR_BOOKE_IVOR12 (0x19C)
! 962: #define SPR_BOOKE_IVOR13 (0x19D)
! 963: #define SPR_BOOKE_IVOR14 (0x19E)
! 964: #define SPR_BOOKE_IVOR15 (0x19F)
! 965: #define SPR_BOOKE_SPEFSCR (0x200)
! 966: #define SPR_Exxx_BBEAR (0x201)
! 967: #define SPR_Exxx_BBTAR (0x202)
! 968: #define SPR_Exxx_L1CFG0 (0x203)
! 969: #define SPR_Exxx_NPIDR (0x205)
! 970: #define SPR_ATBL (0x20E)
! 971: #define SPR_ATBU (0x20F)
! 972: #define SPR_IBAT0U (0x210)
! 973: #define SPR_BOOKE_IVOR32 (0x210)
! 974: #define SPR_RCPU_MI_GRA (0x210)
! 975: #define SPR_IBAT0L (0x211)
! 976: #define SPR_BOOKE_IVOR33 (0x211)
! 977: #define SPR_IBAT1U (0x212)
! 978: #define SPR_BOOKE_IVOR34 (0x212)
! 979: #define SPR_IBAT1L (0x213)
! 980: #define SPR_BOOKE_IVOR35 (0x213)
! 981: #define SPR_IBAT2U (0x214)
! 982: #define SPR_BOOKE_IVOR36 (0x214)
! 983: #define SPR_IBAT2L (0x215)
! 984: #define SPR_BOOKE_IVOR37 (0x215)
! 985: #define SPR_IBAT3U (0x216)
! 986: #define SPR_IBAT3L (0x217)
! 987: #define SPR_DBAT0U (0x218)
! 988: #define SPR_RCPU_L2U_GRA (0x218)
! 989: #define SPR_DBAT0L (0x219)
! 990: #define SPR_DBAT1U (0x21A)
! 991: #define SPR_DBAT1L (0x21B)
! 992: #define SPR_DBAT2U (0x21C)
! 993: #define SPR_DBAT2L (0x21D)
! 994: #define SPR_DBAT3U (0x21E)
! 995: #define SPR_DBAT3L (0x21F)
! 996: #define SPR_IBAT4U (0x230)
! 997: #define SPR_RPCU_BBCMCR (0x230)
! 998: #define SPR_MPC_IC_CST (0x230)
! 999: #define SPR_Exxx_CTXCR (0x230)
! 1000: #define SPR_IBAT4L (0x231)
! 1001: #define SPR_MPC_IC_ADR (0x231)
! 1002: #define SPR_Exxx_DBCR3 (0x231)
! 1003: #define SPR_IBAT5U (0x232)
! 1004: #define SPR_MPC_IC_DAT (0x232)
! 1005: #define SPR_Exxx_DBCNT (0x232)
! 1006: #define SPR_IBAT5L (0x233)
! 1007: #define SPR_IBAT6U (0x234)
! 1008: #define SPR_IBAT6L (0x235)
! 1009: #define SPR_IBAT7U (0x236)
! 1010: #define SPR_IBAT7L (0x237)
! 1011: #define SPR_DBAT4U (0x238)
! 1012: #define SPR_RCPU_L2U_MCR (0x238)
! 1013: #define SPR_MPC_DC_CST (0x238)
! 1014: #define SPR_Exxx_ALTCTXCR (0x238)
! 1015: #define SPR_DBAT4L (0x239)
! 1016: #define SPR_MPC_DC_ADR (0x239)
! 1017: #define SPR_DBAT5U (0x23A)
! 1018: #define SPR_BOOKE_MCSRR0 (0x23A)
! 1019: #define SPR_MPC_DC_DAT (0x23A)
! 1020: #define SPR_DBAT5L (0x23B)
! 1021: #define SPR_BOOKE_MCSRR1 (0x23B)
! 1022: #define SPR_DBAT6U (0x23C)
! 1023: #define SPR_BOOKE_MCSR (0x23C)
! 1024: #define SPR_DBAT6L (0x23D)
! 1025: #define SPR_Exxx_MCAR (0x23D)
! 1026: #define SPR_DBAT7U (0x23E)
! 1027: #define SPR_BOOKE_DSRR0 (0x23E)
! 1028: #define SPR_DBAT7L (0x23F)
! 1029: #define SPR_BOOKE_DSRR1 (0x23F)
! 1030: #define SPR_BOOKE_SPRG8 (0x25C)
! 1031: #define SPR_BOOKE_SPRG9 (0x25D)
! 1032: #define SPR_BOOKE_MAS0 (0x270)
! 1033: #define SPR_BOOKE_MAS1 (0x271)
! 1034: #define SPR_BOOKE_MAS2 (0x272)
! 1035: #define SPR_BOOKE_MAS3 (0x273)
! 1036: #define SPR_BOOKE_MAS4 (0x274)
! 1037: #define SPR_BOOKE_MAS5 (0x275)
! 1038: #define SPR_BOOKE_MAS6 (0x276)
! 1039: #define SPR_BOOKE_PID1 (0x279)
! 1040: #define SPR_BOOKE_PID2 (0x27A)
! 1041: #define SPR_MPC_DPDR (0x280)
! 1042: #define SPR_MPC_IMMR (0x288)
! 1043: #define SPR_BOOKE_TLB0CFG (0x2B0)
! 1044: #define SPR_BOOKE_TLB1CFG (0x2B1)
! 1045: #define SPR_BOOKE_TLB2CFG (0x2B2)
! 1046: #define SPR_BOOKE_TLB3CFG (0x2B3)
! 1047: #define SPR_BOOKE_EPR (0x2BE)
! 1048: #define SPR_PERF0 (0x300)
! 1049: #define SPR_RCPU_MI_RBA0 (0x300)
! 1050: #define SPR_MPC_MI_CTR (0x300)
! 1051: #define SPR_PERF1 (0x301)
! 1052: #define SPR_RCPU_MI_RBA1 (0x301)
! 1053: #define SPR_PERF2 (0x302)
! 1054: #define SPR_RCPU_MI_RBA2 (0x302)
! 1055: #define SPR_MPC_MI_AP (0x302)
! 1056: #define SPR_PERF3 (0x303)
! 1057: #define SPR_620_PMC1R (0x303)
! 1058: #define SPR_RCPU_MI_RBA3 (0x303)
! 1059: #define SPR_MPC_MI_EPN (0x303)
! 1060: #define SPR_PERF4 (0x304)
! 1061: #define SPR_620_PMC2R (0x304)
! 1062: #define SPR_PERF5 (0x305)
! 1063: #define SPR_MPC_MI_TWC (0x305)
! 1064: #define SPR_PERF6 (0x306)
! 1065: #define SPR_MPC_MI_RPN (0x306)
! 1066: #define SPR_PERF7 (0x307)
! 1067: #define SPR_PERF8 (0x308)
! 1068: #define SPR_RCPU_L2U_RBA0 (0x308)
! 1069: #define SPR_MPC_MD_CTR (0x308)
! 1070: #define SPR_PERF9 (0x309)
! 1071: #define SPR_RCPU_L2U_RBA1 (0x309)
! 1072: #define SPR_MPC_MD_CASID (0x309)
! 1073: #define SPR_PERFA (0x30A)
! 1074: #define SPR_RCPU_L2U_RBA2 (0x30A)
! 1075: #define SPR_MPC_MD_AP (0x30A)
! 1076: #define SPR_PERFB (0x30B)
! 1077: #define SPR_620_MMCR0R (0x30B)
! 1078: #define SPR_RCPU_L2U_RBA3 (0x30B)
! 1079: #define SPR_MPC_MD_EPN (0x30B)
! 1080: #define SPR_PERFC (0x30C)
! 1081: #define SPR_MPC_MD_TWB (0x30C)
! 1082: #define SPR_PERFD (0x30D)
! 1083: #define SPR_MPC_MD_TWC (0x30D)
! 1084: #define SPR_PERFE (0x30E)
! 1085: #define SPR_MPC_MD_RPN (0x30E)
! 1086: #define SPR_PERFF (0x30F)
! 1087: #define SPR_MPC_MD_TW (0x30F)
! 1088: #define SPR_UPERF0 (0x310)
! 1089: #define SPR_UPERF1 (0x311)
! 1090: #define SPR_UPERF2 (0x312)
! 1091: #define SPR_UPERF3 (0x313)
! 1092: #define SPR_620_PMC1W (0x313)
! 1093: #define SPR_UPERF4 (0x314)
! 1094: #define SPR_620_PMC2W (0x314)
! 1095: #define SPR_UPERF5 (0x315)
! 1096: #define SPR_UPERF6 (0x316)
! 1097: #define SPR_UPERF7 (0x317)
! 1098: #define SPR_UPERF8 (0x318)
! 1099: #define SPR_UPERF9 (0x319)
! 1100: #define SPR_UPERFA (0x31A)
! 1101: #define SPR_UPERFB (0x31B)
! 1102: #define SPR_620_MMCR0W (0x31B)
! 1103: #define SPR_UPERFC (0x31C)
! 1104: #define SPR_UPERFD (0x31D)
! 1105: #define SPR_UPERFE (0x31E)
! 1106: #define SPR_UPERFF (0x31F)
! 1107: #define SPR_RCPU_MI_RA0 (0x320)
! 1108: #define SPR_MPC_MI_DBCAM (0x320)
! 1109: #define SPR_RCPU_MI_RA1 (0x321)
! 1110: #define SPR_MPC_MI_DBRAM0 (0x321)
! 1111: #define SPR_RCPU_MI_RA2 (0x322)
! 1112: #define SPR_MPC_MI_DBRAM1 (0x322)
! 1113: #define SPR_RCPU_MI_RA3 (0x323)
! 1114: #define SPR_RCPU_L2U_RA0 (0x328)
! 1115: #define SPR_MPC_MD_DBCAM (0x328)
! 1116: #define SPR_RCPU_L2U_RA1 (0x329)
! 1117: #define SPR_MPC_MD_DBRAM0 (0x329)
! 1118: #define SPR_RCPU_L2U_RA2 (0x32A)
! 1119: #define SPR_MPC_MD_DBRAM1 (0x32A)
! 1120: #define SPR_RCPU_L2U_RA3 (0x32B)
! 1121: #define SPR_440_INV0 (0x370)
! 1122: #define SPR_440_INV1 (0x371)
! 1123: #define SPR_440_INV2 (0x372)
! 1124: #define SPR_440_INV3 (0x373)
! 1125: #define SPR_440_ITV0 (0x374)
! 1126: #define SPR_440_ITV1 (0x375)
! 1127: #define SPR_440_ITV2 (0x376)
! 1128: #define SPR_440_ITV3 (0x377)
! 1129: #define SPR_440_CCR1 (0x378)
! 1130: #define SPR_DCRIPR (0x37B)
! 1131: #define SPR_PPR (0x380)
! 1132: #define SPR_750_GQR0 (0x390)
! 1133: #define SPR_440_DNV0 (0x390)
! 1134: #define SPR_750_GQR1 (0x391)
! 1135: #define SPR_440_DNV1 (0x391)
! 1136: #define SPR_750_GQR2 (0x392)
! 1137: #define SPR_440_DNV2 (0x392)
! 1138: #define SPR_750_GQR3 (0x393)
! 1139: #define SPR_440_DNV3 (0x393)
! 1140: #define SPR_750_GQR4 (0x394)
! 1141: #define SPR_440_DTV0 (0x394)
! 1142: #define SPR_750_GQR5 (0x395)
! 1143: #define SPR_440_DTV1 (0x395)
! 1144: #define SPR_750_GQR6 (0x396)
! 1145: #define SPR_440_DTV2 (0x396)
! 1146: #define SPR_750_GQR7 (0x397)
! 1147: #define SPR_440_DTV3 (0x397)
! 1148: #define SPR_750_THRM4 (0x398)
! 1149: #define SPR_750CL_HID2 (0x398)
! 1150: #define SPR_440_DVLIM (0x398)
! 1151: #define SPR_750_WPAR (0x399)
! 1152: #define SPR_440_IVLIM (0x399)
! 1153: #define SPR_750_DMAU (0x39A)
! 1154: #define SPR_750_DMAL (0x39B)
! 1155: #define SPR_440_RSTCFG (0x39B)
! 1156: #define SPR_BOOKE_DCDBTRL (0x39C)
! 1157: #define SPR_BOOKE_DCDBTRH (0x39D)
! 1158: #define SPR_BOOKE_ICDBTRL (0x39E)
! 1159: #define SPR_BOOKE_ICDBTRH (0x39F)
! 1160: #define SPR_UMMCR2 (0x3A0)
! 1161: #define SPR_UPMC5 (0x3A1)
! 1162: #define SPR_UPMC6 (0x3A2)
! 1163: #define SPR_UBAMR (0x3A7)
! 1164: #define SPR_UMMCR0 (0x3A8)
! 1165: #define SPR_UPMC1 (0x3A9)
! 1166: #define SPR_UPMC2 (0x3AA)
! 1167: #define SPR_USIAR (0x3AB)
! 1168: #define SPR_UMMCR1 (0x3AC)
! 1169: #define SPR_UPMC3 (0x3AD)
! 1170: #define SPR_UPMC4 (0x3AE)
! 1171: #define SPR_USDA (0x3AF)
! 1172: #define SPR_40x_ZPR (0x3B0)
! 1173: #define SPR_BOOKE_MAS7 (0x3B0)
! 1174: #define SPR_620_PMR0 (0x3B0)
! 1175: #define SPR_MMCR2 (0x3B0)
! 1176: #define SPR_PMC5 (0x3B1)
! 1177: #define SPR_40x_PID (0x3B1)
! 1178: #define SPR_620_PMR1 (0x3B1)
! 1179: #define SPR_PMC6 (0x3B2)
! 1180: #define SPR_440_MMUCR (0x3B2)
! 1181: #define SPR_620_PMR2 (0x3B2)
! 1182: #define SPR_4xx_CCR0 (0x3B3)
! 1183: #define SPR_BOOKE_EPLC (0x3B3)
! 1184: #define SPR_620_PMR3 (0x3B3)
! 1185: #define SPR_405_IAC3 (0x3B4)
! 1186: #define SPR_BOOKE_EPSC (0x3B4)
! 1187: #define SPR_620_PMR4 (0x3B4)
! 1188: #define SPR_405_IAC4 (0x3B5)
! 1189: #define SPR_620_PMR5 (0x3B5)
! 1190: #define SPR_405_DVC1 (0x3B6)
! 1191: #define SPR_620_PMR6 (0x3B6)
! 1192: #define SPR_405_DVC2 (0x3B7)
! 1193: #define SPR_620_PMR7 (0x3B7)
! 1194: #define SPR_BAMR (0x3B7)
! 1195: #define SPR_MMCR0 (0x3B8)
! 1196: #define SPR_620_PMR8 (0x3B8)
! 1197: #define SPR_PMC1 (0x3B9)
! 1198: #define SPR_40x_SGR (0x3B9)
! 1199: #define SPR_620_PMR9 (0x3B9)
! 1200: #define SPR_PMC2 (0x3BA)
! 1201: #define SPR_40x_DCWR (0x3BA)
! 1202: #define SPR_620_PMRA (0x3BA)
! 1203: #define SPR_SIAR (0x3BB)
! 1204: #define SPR_405_SLER (0x3BB)
! 1205: #define SPR_620_PMRB (0x3BB)
! 1206: #define SPR_MMCR1 (0x3BC)
! 1207: #define SPR_405_SU0R (0x3BC)
! 1208: #define SPR_620_PMRC (0x3BC)
! 1209: #define SPR_401_SKR (0x3BC)
! 1210: #define SPR_PMC3 (0x3BD)
! 1211: #define SPR_405_DBCR1 (0x3BD)
! 1212: #define SPR_620_PMRD (0x3BD)
! 1213: #define SPR_PMC4 (0x3BE)
! 1214: #define SPR_620_PMRE (0x3BE)
! 1215: #define SPR_SDA (0x3BF)
! 1216: #define SPR_620_PMRF (0x3BF)
! 1217: #define SPR_403_VTBL (0x3CC)
! 1218: #define SPR_403_VTBU (0x3CD)
! 1219: #define SPR_DMISS (0x3D0)
! 1220: #define SPR_DCMP (0x3D1)
! 1221: #define SPR_HASH1 (0x3D2)
! 1222: #define SPR_HASH2 (0x3D3)
! 1223: #define SPR_BOOKE_ICDBDR (0x3D3)
! 1224: #define SPR_TLBMISS (0x3D4)
! 1225: #define SPR_IMISS (0x3D4)
! 1226: #define SPR_40x_ESR (0x3D4)
! 1227: #define SPR_PTEHI (0x3D5)
! 1228: #define SPR_ICMP (0x3D5)
! 1229: #define SPR_40x_DEAR (0x3D5)
! 1230: #define SPR_PTELO (0x3D6)
! 1231: #define SPR_RPA (0x3D6)
! 1232: #define SPR_40x_EVPR (0x3D6)
! 1233: #define SPR_L3PM (0x3D7)
! 1234: #define SPR_403_CDBCR (0x3D7)
! 1235: #define SPR_L3ITCR0 (0x3D8)
! 1236: #define SPR_TCR (0x3D8)
! 1237: #define SPR_40x_TSR (0x3D8)
! 1238: #define SPR_IBR (0x3DA)
! 1239: #define SPR_40x_TCR (0x3DA)
! 1240: #define SPR_ESASRR (0x3DB)
! 1241: #define SPR_40x_PIT (0x3DB)
! 1242: #define SPR_403_TBL (0x3DC)
! 1243: #define SPR_403_TBU (0x3DD)
! 1244: #define SPR_SEBR (0x3DE)
! 1245: #define SPR_40x_SRR2 (0x3DE)
! 1246: #define SPR_SER (0x3DF)
! 1247: #define SPR_40x_SRR3 (0x3DF)
! 1248: #define SPR_L3OHCR (0x3E8)
! 1249: #define SPR_L3ITCR1 (0x3E9)
! 1250: #define SPR_L3ITCR2 (0x3EA)
! 1251: #define SPR_L3ITCR3 (0x3EB)
! 1252: #define SPR_HID0 (0x3F0)
! 1253: #define SPR_40x_DBSR (0x3F0)
! 1254: #define SPR_HID1 (0x3F1)
! 1255: #define SPR_IABR (0x3F2)
! 1256: #define SPR_40x_DBCR0 (0x3F2)
! 1257: #define SPR_601_HID2 (0x3F2)
! 1258: #define SPR_Exxx_L1CSR0 (0x3F2)
! 1259: #define SPR_ICTRL (0x3F3)
! 1260: #define SPR_HID2 (0x3F3)
! 1261: #define SPR_750CL_HID4 (0x3F3)
! 1262: #define SPR_Exxx_L1CSR1 (0x3F3)
! 1263: #define SPR_440_DBDR (0x3F3)
! 1264: #define SPR_LDSTDB (0x3F4)
! 1265: #define SPR_750_TDCL (0x3F4)
! 1266: #define SPR_40x_IAC1 (0x3F4)
! 1267: #define SPR_MMUCSR0 (0x3F4)
! 1268: #define SPR_DABR (0x3F5)
1.1 root 1269: #define DABR_MASK (~(target_ulong)0x7)
1.1.1.4 ! root 1270: #define SPR_Exxx_BUCSR (0x3F5)
! 1271: #define SPR_40x_IAC2 (0x3F5)
! 1272: #define SPR_601_HID5 (0x3F5)
! 1273: #define SPR_40x_DAC1 (0x3F6)
! 1274: #define SPR_MSSCR0 (0x3F6)
! 1275: #define SPR_970_HID5 (0x3F6)
! 1276: #define SPR_MSSSR0 (0x3F7)
! 1277: #define SPR_MSSCR1 (0x3F7)
! 1278: #define SPR_DABRX (0x3F7)
! 1279: #define SPR_40x_DAC2 (0x3F7)
! 1280: #define SPR_MMUCFG (0x3F7)
! 1281: #define SPR_LDSTCR (0x3F8)
! 1282: #define SPR_L2PMCR (0x3F8)
! 1283: #define SPR_750FX_HID2 (0x3F8)
! 1284: #define SPR_620_BUSCSR (0x3F8)
! 1285: #define SPR_Exxx_L1FINV0 (0x3F8)
! 1286: #define SPR_L2CR (0x3F9)
! 1287: #define SPR_620_L2CR (0x3F9)
! 1288: #define SPR_L3CR (0x3FA)
! 1289: #define SPR_750_TDCH (0x3FA)
! 1290: #define SPR_IABR2 (0x3FA)
! 1291: #define SPR_40x_DCCR (0x3FA)
! 1292: #define SPR_620_L2SR (0x3FA)
! 1293: #define SPR_ICTC (0x3FB)
! 1294: #define SPR_40x_ICCR (0x3FB)
! 1295: #define SPR_THRM1 (0x3FC)
! 1296: #define SPR_403_PBL1 (0x3FC)
! 1297: #define SPR_SP (0x3FD)
! 1298: #define SPR_THRM2 (0x3FD)
! 1299: #define SPR_403_PBU1 (0x3FD)
! 1300: #define SPR_604_HID13 (0x3FD)
! 1301: #define SPR_LT (0x3FE)
! 1302: #define SPR_THRM3 (0x3FE)
! 1303: #define SPR_RCPU_FPECR (0x3FE)
! 1304: #define SPR_403_PBL2 (0x3FE)
! 1305: #define SPR_PIR (0x3FF)
! 1306: #define SPR_403_PBU2 (0x3FF)
! 1307: #define SPR_601_HID15 (0x3FF)
! 1308: #define SPR_604_HID15 (0x3FF)
! 1309: #define SPR_E500_SVR (0x3FF)
1.1 root 1310:
1.1.1.4 ! root 1311: /*****************************************************************************/
1.1 root 1312: /* Memory access type :
1313: * may be needed for precise access rights control and precise exceptions.
1314: */
1315: enum {
1316: /* 1 bit to define user level / supervisor access */
1317: ACCESS_USER = 0x00,
1318: ACCESS_SUPER = 0x01,
1319: /* Type of instruction that generated the access */
1320: ACCESS_CODE = 0x10, /* Code fetch access */
1321: ACCESS_INT = 0x20, /* Integer load/store access */
1322: ACCESS_FLOAT = 0x30, /* floating point load/store access */
1323: ACCESS_RES = 0x40, /* load/store with reservation */
1324: ACCESS_EXT = 0x50, /* external access */
1325: ACCESS_CACHE = 0x60, /* Cache manipulation */
1326: };
1327:
1.1.1.4 ! root 1328: /* Hardware interruption sources:
! 1329: * all those exception can be raised simulteaneously
! 1330: */
! 1331: /* Input pins definitions */
! 1332: enum {
! 1333: /* 6xx bus input pins */
! 1334: PPC6xx_INPUT_HRESET = 0,
! 1335: PPC6xx_INPUT_SRESET = 1,
! 1336: PPC6xx_INPUT_CKSTP_IN = 2,
! 1337: PPC6xx_INPUT_MCP = 3,
! 1338: PPC6xx_INPUT_SMI = 4,
! 1339: PPC6xx_INPUT_INT = 5,
! 1340: PPC6xx_INPUT_TBEN = 6,
! 1341: PPC6xx_INPUT_WAKEUP = 7,
! 1342: PPC6xx_INPUT_NB,
! 1343: };
! 1344:
! 1345: enum {
! 1346: /* Embedded PowerPC input pins */
! 1347: PPCBookE_INPUT_HRESET = 0,
! 1348: PPCBookE_INPUT_SRESET = 1,
! 1349: PPCBookE_INPUT_CKSTP_IN = 2,
! 1350: PPCBookE_INPUT_MCP = 3,
! 1351: PPCBookE_INPUT_SMI = 4,
! 1352: PPCBookE_INPUT_INT = 5,
! 1353: PPCBookE_INPUT_CINT = 6,
! 1354: PPCBookE_INPUT_NB,
! 1355: };
! 1356:
! 1357: enum {
! 1358: /* PowerPC 40x input pins */
! 1359: PPC40x_INPUT_RESET_CORE = 0,
! 1360: PPC40x_INPUT_RESET_CHIP = 1,
! 1361: PPC40x_INPUT_RESET_SYS = 2,
! 1362: PPC40x_INPUT_CINT = 3,
! 1363: PPC40x_INPUT_INT = 4,
! 1364: PPC40x_INPUT_HALT = 5,
! 1365: PPC40x_INPUT_DEBUG = 6,
! 1366: PPC40x_INPUT_NB,
! 1367: };
! 1368:
! 1369: enum {
! 1370: /* RCPU input pins */
! 1371: PPCRCPU_INPUT_PORESET = 0,
! 1372: PPCRCPU_INPUT_HRESET = 1,
! 1373: PPCRCPU_INPUT_SRESET = 2,
! 1374: PPCRCPU_INPUT_IRQ0 = 3,
! 1375: PPCRCPU_INPUT_IRQ1 = 4,
! 1376: PPCRCPU_INPUT_IRQ2 = 5,
! 1377: PPCRCPU_INPUT_IRQ3 = 6,
! 1378: PPCRCPU_INPUT_IRQ4 = 7,
! 1379: PPCRCPU_INPUT_IRQ5 = 8,
! 1380: PPCRCPU_INPUT_IRQ6 = 9,
! 1381: PPCRCPU_INPUT_IRQ7 = 10,
! 1382: PPCRCPU_INPUT_NB,
! 1383: };
! 1384:
! 1385: #if defined(TARGET_PPC64)
! 1386: enum {
! 1387: /* PowerPC 970 input pins */
! 1388: PPC970_INPUT_HRESET = 0,
! 1389: PPC970_INPUT_SRESET = 1,
! 1390: PPC970_INPUT_CKSTP = 2,
! 1391: PPC970_INPUT_TBEN = 3,
! 1392: PPC970_INPUT_MCP = 4,
! 1393: PPC970_INPUT_INT = 5,
! 1394: PPC970_INPUT_THINT = 6,
! 1395: PPC970_INPUT_NB,
! 1396: };
! 1397: #endif
1.1 root 1398:
1.1.1.4 ! root 1399: /* Hardware exceptions definitions */
1.1 root 1400: enum {
1.1.1.4 ! root 1401: /* External hardware exception sources */
! 1402: PPC_INTERRUPT_RESET = 0, /* Reset exception */
! 1403: PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
! 1404: PPC_INTERRUPT_MCK, /* Machine check exception */
! 1405: PPC_INTERRUPT_EXT, /* External interrupt */
! 1406: PPC_INTERRUPT_SMI, /* System management interrupt */
! 1407: PPC_INTERRUPT_CEXT, /* Critical external interrupt */
! 1408: PPC_INTERRUPT_DEBUG, /* External debug exception */
! 1409: PPC_INTERRUPT_THERM, /* Thermal exception */
! 1410: /* Internal hardware exception sources */
! 1411: PPC_INTERRUPT_DECR, /* Decrementer exception */
! 1412: PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
! 1413: PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
! 1414: PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
! 1415: PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
! 1416: PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
! 1417: PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
! 1418: PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
1.1 root 1419: };
1420:
1421: /*****************************************************************************/
1422:
1423: #endif /* !defined (__CPU_PPC_H__) */
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