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1.1 root 1: /*
2: * PowerPC emulation cpu definitions for qemu.
1.1.1.4 root 3: *
4: * Copyright (c) 2003-2007 Jocelyn Mayer
1.1 root 5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
17: * License along with this library; if not, write to the Free Software
1.1.1.5 ! root 18: * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
1.1 root 19: */
20: #if !defined (__CPU_PPC_H__)
21: #define __CPU_PPC_H__
22:
23: #include "config.h"
1.1.1.4 root 24: #include <inttypes.h>
25:
26: //#define PPC_EMULATE_32BITS_HYPV
27:
28: #if defined (TARGET_PPC64)
29: /* PowerPC 64 definitions */
30: #define TARGET_LONG_BITS 64
31: #define TARGET_PAGE_BITS 12
32:
33: #else /* defined (TARGET_PPC64) */
34: /* PowerPC 32 definitions */
1.1 root 35: #define TARGET_LONG_BITS 32
36:
1.1.1.4 root 37: #if defined(TARGET_PPCEMB)
38: /* Specific definitions for PowerPC embedded */
39: /* BookE have 36 bits physical address space */
40: #define TARGET_PHYS_ADDR_BITS 64
41: #if defined(CONFIG_USER_ONLY)
42: /* It looks like a lot of Linux programs assume page size
43: * is 4kB long. This is evil, but we have to deal with it...
44: */
45: #define TARGET_PAGE_BITS 12
46: #else /* defined(CONFIG_USER_ONLY) */
47: /* Pages can be 1 kB small */
48: #define TARGET_PAGE_BITS 10
49: #endif /* defined(CONFIG_USER_ONLY) */
50: #else /* defined(TARGET_PPCEMB) */
51: /* "standard" PowerPC 32 definitions */
52: #define TARGET_PAGE_BITS 12
53: #endif /* defined(TARGET_PPCEMB) */
54:
55: #endif /* defined (TARGET_PPC64) */
56:
1.1 root 57: #include "cpu-defs.h"
58:
1.1.1.4 root 59: #define REGX "%016" PRIx64
60: #define ADDRX TARGET_FMT_lx
61: #define PADDRX TARGET_FMT_plx
62:
1.1 root 63: #include <setjmp.h>
64:
65: #include "softfloat.h"
66:
67: #define TARGET_HAS_ICE 1
68:
1.1.1.5 ! root 69: /* Load a 32 bit BIOS also on 64 bit machines */
! 70: #if defined (TARGET_PPC64) && defined(CONFIG_USER_ONLY)
1.1.1.4 root 71: #define ELF_MACHINE EM_PPC64
72: #else
73: #define ELF_MACHINE EM_PPC
74: #endif
1.1 root 75:
76: /*****************************************************************************/
1.1.1.4 root 77: /* MMU model */
78: typedef enum powerpc_mmu_t powerpc_mmu_t;
79: enum powerpc_mmu_t {
80: POWERPC_MMU_UNKNOWN = 0x00000000,
81: /* Standard 32 bits PowerPC MMU */
82: POWERPC_MMU_32B = 0x00000001,
83: /* PowerPC 6xx MMU with software TLB */
84: POWERPC_MMU_SOFT_6xx = 0x00000002,
85: /* PowerPC 74xx MMU with software TLB */
86: POWERPC_MMU_SOFT_74xx = 0x00000003,
87: /* PowerPC 4xx MMU with software TLB */
88: POWERPC_MMU_SOFT_4xx = 0x00000004,
89: /* PowerPC 4xx MMU with software TLB and zones protections */
90: POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
91: /* PowerPC MMU in real mode only */
92: POWERPC_MMU_REAL = 0x00000006,
93: /* Freescale MPC8xx MMU model */
94: POWERPC_MMU_MPC8xx = 0x00000007,
95: /* BookE MMU model */
96: POWERPC_MMU_BOOKE = 0x00000008,
97: /* BookE FSL MMU model */
98: POWERPC_MMU_BOOKE_FSL = 0x00000009,
99: /* PowerPC 601 MMU model (specific BATs format) */
100: POWERPC_MMU_601 = 0x0000000A,
101: #if defined(TARGET_PPC64)
102: #define POWERPC_MMU_64 0x00010000
103: /* 64 bits PowerPC MMU */
104: POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
105: /* 620 variant (no segment exceptions) */
106: POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
107: #endif /* defined(TARGET_PPC64) */
1.1 root 108: };
109:
1.1.1.4 root 110: /*****************************************************************************/
111: /* Exception model */
112: typedef enum powerpc_excp_t powerpc_excp_t;
113: enum powerpc_excp_t {
114: POWERPC_EXCP_UNKNOWN = 0,
115: /* Standard PowerPC exception model */
116: POWERPC_EXCP_STD,
117: /* PowerPC 40x exception model */
118: POWERPC_EXCP_40x,
119: /* PowerPC 601 exception model */
120: POWERPC_EXCP_601,
121: /* PowerPC 602 exception model */
122: POWERPC_EXCP_602,
123: /* PowerPC 603 exception model */
124: POWERPC_EXCP_603,
125: /* PowerPC 603e exception model */
126: POWERPC_EXCP_603E,
127: /* PowerPC G2 exception model */
128: POWERPC_EXCP_G2,
129: /* PowerPC 604 exception model */
130: POWERPC_EXCP_604,
131: /* PowerPC 7x0 exception model */
132: POWERPC_EXCP_7x0,
133: /* PowerPC 7x5 exception model */
134: POWERPC_EXCP_7x5,
135: /* PowerPC 74xx exception model */
136: POWERPC_EXCP_74xx,
137: /* BookE exception model */
138: POWERPC_EXCP_BOOKE,
139: #if defined(TARGET_PPC64)
140: /* PowerPC 970 exception model */
141: POWERPC_EXCP_970,
142: #endif /* defined(TARGET_PPC64) */
1.1 root 143: };
144:
145: /*****************************************************************************/
1.1.1.4 root 146: /* Exception vectors definitions */
1.1 root 147: enum {
1.1.1.4 root 148: POWERPC_EXCP_NONE = -1,
149: /* The 64 first entries are used by the PowerPC embedded specification */
150: POWERPC_EXCP_CRITICAL = 0, /* Critical input */
151: POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
152: POWERPC_EXCP_DSI = 2, /* Data storage exception */
153: POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
154: POWERPC_EXCP_EXTERNAL = 4, /* External input */
155: POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
156: POWERPC_EXCP_PROGRAM = 6, /* Program exception */
157: POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
158: POWERPC_EXCP_SYSCALL = 8, /* System call exception */
159: POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
160: POWERPC_EXCP_DECR = 10, /* Decrementer exception */
161: POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
162: POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
163: POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
164: POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
165: POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
166: /* Vectors 16 to 31 are reserved */
167: POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
168: POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
169: POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
170: POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
171: POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
172: POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
173: /* Vectors 38 to 63 are reserved */
174: /* Exceptions defined in the PowerPC server specification */
175: POWERPC_EXCP_RESET = 64, /* System reset exception */
176: POWERPC_EXCP_DSEG = 65, /* Data segment exception */
177: POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
178: POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
179: POWERPC_EXCP_TRACE = 68, /* Trace exception */
180: POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
181: POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
182: POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
183: POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
184: POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
185: /* 40x specific exceptions */
186: POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
187: /* 601 specific exceptions */
188: POWERPC_EXCP_IO = 75, /* IO error exception */
189: POWERPC_EXCP_RUNM = 76, /* Run mode exception */
190: /* 602 specific exceptions */
191: POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
192: /* 602/603 specific exceptions */
193: POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
194: POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
195: POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
196: /* Exceptions available on most PowerPC */
197: POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
198: POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
199: POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
200: POWERPC_EXCP_SMI = 84, /* System management interrupt */
201: POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
202: /* 7xx/74xx specific exceptions */
203: POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
204: /* 74xx specific exceptions */
205: POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
206: /* 970FX specific exceptions */
207: POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
208: POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
209: /* Freescale embeded cores specific exceptions */
210: POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
211: POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
212: POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
213: POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
214: /* EOL */
215: POWERPC_EXCP_NB = 96,
216: /* Qemu exceptions: used internally during code translation */
217: POWERPC_EXCP_STOP = 0x200, /* stop translation */
218: POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
219: /* Qemu exceptions: special cases we want to stop translation */
220: POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
221: POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
1.1 root 222: };
223:
1.1.1.4 root 224: /* Exceptions error codes */
1.1 root 225: enum {
1.1.1.4 root 226: /* Exception subtypes for POWERPC_EXCP_ALIGN */
227: POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
228: POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
229: POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
230: POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
231: POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
232: POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
233: /* Exception subtypes for POWERPC_EXCP_PROGRAM */
234: /* FP exceptions */
235: POWERPC_EXCP_FP = 0x10,
236: POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
237: POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
238: POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
239: POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
240: POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
241: POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
242: POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
243: POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
244: POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
245: POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
246: POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
247: POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
248: POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
249: /* Invalid instruction */
250: POWERPC_EXCP_INVAL = 0x20,
251: POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
252: POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
253: POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
254: POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
255: /* Privileged instruction */
256: POWERPC_EXCP_PRIV = 0x30,
257: POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
258: POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
259: /* Trap */
260: POWERPC_EXCP_TRAP = 0x40,
261: };
262:
263: /*****************************************************************************/
264: /* Input pins model */
265: typedef enum powerpc_input_t powerpc_input_t;
266: enum powerpc_input_t {
267: PPC_FLAGS_INPUT_UNKNOWN = 0,
268: /* PowerPC 6xx bus */
269: PPC_FLAGS_INPUT_6xx,
270: /* BookE bus */
271: PPC_FLAGS_INPUT_BookE,
272: /* PowerPC 405 bus */
273: PPC_FLAGS_INPUT_405,
274: /* PowerPC 970 bus */
275: PPC_FLAGS_INPUT_970,
276: /* PowerPC 401 bus */
277: PPC_FLAGS_INPUT_401,
278: /* Freescale RCPU bus */
279: PPC_FLAGS_INPUT_RCPU,
1.1 root 280: };
281:
1.1.1.4 root 282: #define PPC_INPUT(env) (env->bus_model)
1.1 root 283:
284: /*****************************************************************************/
285: typedef struct ppc_def_t ppc_def_t;
1.1.1.4 root 286: typedef struct opc_handler_t opc_handler_t;
1.1 root 287:
288: /*****************************************************************************/
289: /* Types used to describe some PowerPC registers */
290: typedef struct CPUPPCState CPUPPCState;
291: typedef struct ppc_tb_t ppc_tb_t;
292: typedef struct ppc_spr_t ppc_spr_t;
293: typedef struct ppc_dcr_t ppc_dcr_t;
1.1.1.4 root 294: typedef union ppc_avr_t ppc_avr_t;
295: typedef union ppc_tlb_t ppc_tlb_t;
1.1 root 296:
297: /* SPR access micro-ops generations callbacks */
298: struct ppc_spr_t {
1.1.1.5 ! root 299: void (*uea_read)(void *opaque, int gpr_num, int spr_num);
! 300: void (*uea_write)(void *opaque, int spr_num, int gpr_num);
1.1.1.4 root 301: #if !defined(CONFIG_USER_ONLY)
1.1.1.5 ! root 302: void (*oea_read)(void *opaque, int gpr_num, int spr_num);
! 303: void (*oea_write)(void *opaque, int spr_num, int gpr_num);
! 304: void (*hea_read)(void *opaque, int gpr_num, int spr_num);
! 305: void (*hea_write)(void *opaque, int spr_num, int gpr_num);
1.1.1.4 root 306: #endif
1.1.1.5 ! root 307: const char *name;
1.1 root 308: };
309:
310: /* Altivec registers (128 bits) */
1.1.1.4 root 311: union ppc_avr_t {
1.1.1.5 ! root 312: float32 f[4];
1.1.1.4 root 313: uint8_t u8[16];
314: uint16_t u16[8];
315: uint32_t u32[4];
1.1.1.5 ! root 316: int8_t s8[16];
! 317: int16_t s16[8];
! 318: int32_t s32[4];
1.1.1.4 root 319: uint64_t u64[2];
1.1 root 320: };
321:
322: /* Software TLB cache */
1.1.1.4 root 323: typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
324: struct ppc6xx_tlb_t {
325: target_ulong pte0;
326: target_ulong pte1;
327: target_ulong EPN;
328: };
329:
330: typedef struct ppcemb_tlb_t ppcemb_tlb_t;
331: struct ppcemb_tlb_t {
1.1 root 332: target_phys_addr_t RPN;
1.1.1.4 root 333: target_ulong EPN;
334: target_ulong PID;
1.1 root 335: target_ulong size;
1.1.1.4 root 336: uint32_t prot;
337: uint32_t attr; /* Storage attributes */
338: };
339:
340: union ppc_tlb_t {
341: ppc6xx_tlb_t tlb6;
342: ppcemb_tlb_t tlbe;
1.1 root 343: };
344:
345: /*****************************************************************************/
346: /* Machine state register bits definition */
1.1.1.4 root 347: #define MSR_SF 63 /* Sixty-four-bit mode hflags */
348: #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
1.1 root 349: #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
1.1.1.4 root 350: #define MSR_SHV 60 /* hypervisor state hflags */
351: #define MSR_CM 31 /* Computation mode for BookE hflags */
352: #define MSR_ICM 30 /* Interrupt computation mode for BookE */
353: #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
354: #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
355: #define MSR_VR 25 /* altivec available x hflags */
356: #define MSR_SPE 25 /* SPE enable for BookE x hflags */
357: #define MSR_AP 23 /* Access privilege state on 602 hflags */
358: #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
1.1 root 359: #define MSR_KEY 19 /* key bit on 603e */
360: #define MSR_POW 18 /* Power management */
1.1.1.4 root 361: #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
362: #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
1.1 root 363: #define MSR_ILE 16 /* Interrupt little-endian mode */
364: #define MSR_EE 15 /* External interrupt enable */
1.1.1.4 root 365: #define MSR_PR 14 /* Problem state hflags */
366: #define MSR_FP 13 /* Floating point available hflags */
1.1 root 367: #define MSR_ME 12 /* Machine check interrupt enable */
1.1.1.4 root 368: #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
369: #define MSR_SE 10 /* Single-step trace enable x hflags */
370: #define MSR_DWE 10 /* Debug wait enable on 405 x */
371: #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
372: #define MSR_BE 9 /* Branch trace enable x hflags */
373: #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
374: #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
1.1 root 375: #define MSR_AL 7 /* AL bit on POWER */
1.1.1.4 root 376: #define MSR_EP 6 /* Exception prefix on 601 */
1.1 root 377: #define MSR_IR 5 /* Instruction relocate */
378: #define MSR_DR 4 /* Data relocate */
379: #define MSR_PE 3 /* Protection enable on 403 */
1.1.1.4 root 380: #define MSR_PX 2 /* Protection exclusive on 403 x */
381: #define MSR_PMM 2 /* Performance monitor mark on POWER x */
382: #define MSR_RI 1 /* Recoverable interrupt 1 */
383: #define MSR_LE 0 /* Little-endian mode 1 hflags */
384:
385: #define msr_sf ((env->msr >> MSR_SF) & 1)
386: #define msr_isf ((env->msr >> MSR_ISF) & 1)
387: #define msr_shv ((env->msr >> MSR_SHV) & 1)
388: #define msr_cm ((env->msr >> MSR_CM) & 1)
389: #define msr_icm ((env->msr >> MSR_ICM) & 1)
390: #define msr_thv ((env->msr >> MSR_THV) & 1)
391: #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
392: #define msr_vr ((env->msr >> MSR_VR) & 1)
1.1.1.5 ! root 393: #define msr_spe ((env->msr >> MSR_SPE) & 1)
1.1.1.4 root 394: #define msr_ap ((env->msr >> MSR_AP) & 1)
395: #define msr_sa ((env->msr >> MSR_SA) & 1)
396: #define msr_key ((env->msr >> MSR_KEY) & 1)
397: #define msr_pow ((env->msr >> MSR_POW) & 1)
398: #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
399: #define msr_ce ((env->msr >> MSR_CE) & 1)
400: #define msr_ile ((env->msr >> MSR_ILE) & 1)
401: #define msr_ee ((env->msr >> MSR_EE) & 1)
402: #define msr_pr ((env->msr >> MSR_PR) & 1)
403: #define msr_fp ((env->msr >> MSR_FP) & 1)
404: #define msr_me ((env->msr >> MSR_ME) & 1)
405: #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
406: #define msr_se ((env->msr >> MSR_SE) & 1)
407: #define msr_dwe ((env->msr >> MSR_DWE) & 1)
408: #define msr_uble ((env->msr >> MSR_UBLE) & 1)
409: #define msr_be ((env->msr >> MSR_BE) & 1)
410: #define msr_de ((env->msr >> MSR_DE) & 1)
411: #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
412: #define msr_al ((env->msr >> MSR_AL) & 1)
413: #define msr_ep ((env->msr >> MSR_EP) & 1)
414: #define msr_ir ((env->msr >> MSR_IR) & 1)
415: #define msr_dr ((env->msr >> MSR_DR) & 1)
416: #define msr_pe ((env->msr >> MSR_PE) & 1)
417: #define msr_px ((env->msr >> MSR_PX) & 1)
418: #define msr_pmm ((env->msr >> MSR_PMM) & 1)
419: #define msr_ri ((env->msr >> MSR_RI) & 1)
420: #define msr_le ((env->msr >> MSR_LE) & 1)
421: /* Hypervisor bit is more specific */
422: #if defined(TARGET_PPC64)
423: #define MSR_HVB (1ULL << MSR_SHV)
424: #define msr_hv msr_shv
425: #else
426: #if defined(PPC_EMULATE_32BITS_HYPV)
427: #define MSR_HVB (1ULL << MSR_THV)
428: #define msr_hv msr_thv
429: #else
430: #define MSR_HVB (0ULL)
431: #define msr_hv (0)
432: #endif
433: #endif
434:
435: enum {
436: POWERPC_FLAG_NONE = 0x00000000,
437: /* Flag for MSR bit 25 signification (VRE/SPE) */
438: POWERPC_FLAG_SPE = 0x00000001,
439: POWERPC_FLAG_VRE = 0x00000002,
440: /* Flag for MSR bit 17 signification (TGPR/CE) */
441: POWERPC_FLAG_TGPR = 0x00000004,
442: POWERPC_FLAG_CE = 0x00000008,
443: /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
444: POWERPC_FLAG_SE = 0x00000010,
445: POWERPC_FLAG_DWE = 0x00000020,
446: POWERPC_FLAG_UBLE = 0x00000040,
447: /* Flag for MSR bit 9 signification (BE/DE) */
448: POWERPC_FLAG_BE = 0x00000080,
449: POWERPC_FLAG_DE = 0x00000100,
450: /* Flag for MSR bit 2 signification (PX/PMM) */
451: POWERPC_FLAG_PX = 0x00000200,
452: POWERPC_FLAG_PMM = 0x00000400,
453: /* Flag for special features */
454: /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
455: POWERPC_FLAG_RTC_CLK = 0x00010000,
456: POWERPC_FLAG_BUS_CLK = 0x00020000,
457: };
458:
459: /*****************************************************************************/
460: /* Floating point status and control register */
461: #define FPSCR_FX 31 /* Floating-point exception summary */
462: #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
463: #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
464: #define FPSCR_OX 28 /* Floating-point overflow exception */
465: #define FPSCR_UX 27 /* Floating-point underflow exception */
466: #define FPSCR_ZX 26 /* Floating-point zero divide exception */
467: #define FPSCR_XX 25 /* Floating-point inexact exception */
468: #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
469: #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
470: #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
471: #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
472: #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
473: #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
474: #define FPSCR_FR 18 /* Floating-point fraction rounded */
475: #define FPSCR_FI 17 /* Floating-point fraction inexact */
476: #define FPSCR_C 16 /* Floating-point result class descriptor */
477: #define FPSCR_FL 15 /* Floating-point less than or negative */
478: #define FPSCR_FG 14 /* Floating-point greater than or negative */
479: #define FPSCR_FE 13 /* Floating-point equal or zero */
480: #define FPSCR_FU 12 /* Floating-point unordered or NaN */
481: #define FPSCR_FPCC 12 /* Floating-point condition code */
482: #define FPSCR_FPRF 12 /* Floating-point result flags */
483: #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
484: #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
485: #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
486: #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
487: #define FPSCR_OE 6 /* Floating-point overflow exception enable */
488: #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
489: #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
490: #define FPSCR_XE 3 /* Floating-point inexact exception enable */
491: #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
492: #define FPSCR_RN1 1
493: #define FPSCR_RN 0 /* Floating-point rounding control */
494: #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
495: #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
496: #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
497: #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
498: #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
499: #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
500: #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
501: #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
502: #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
503: #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
504: #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
505: #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
506: #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
507: #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
508: #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
509: #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
510: #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
511: #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
512: #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
513: #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
514: #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
515: #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
516: #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
517: /* Invalid operation exception summary */
518: #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
519: (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
520: (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
521: (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
522: (1 << FPSCR_VXCVI)))
523: /* exception summary */
524: #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
525: /* enabled exception summary */
526: #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
527: 0x1F)
1.1 root 528:
529: /*****************************************************************************/
1.1.1.5 ! root 530: /* Vector status and control register */
! 531: #define VSCR_NJ 16 /* Vector non-java */
! 532: #define VSCR_SAT 0 /* Vector saturation */
! 533: #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
! 534: #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
! 535:
! 536: /*****************************************************************************/
1.1 root 537: /* The whole PowerPC CPU context */
1.1.1.4 root 538: #define NB_MMU_MODES 3
539:
1.1 root 540: struct CPUPPCState {
541: /* First are the most commonly used resources
542: * during translated code execution
543: */
544: /* general purpose registers */
1.1.1.5 ! root 545: target_ulong gpr[32];
1.1.1.4 root 546: #if !defined(TARGET_PPC64)
547: /* Storage for GPR MSB, used by the SPE extension */
1.1.1.5 ! root 548: target_ulong gprh[32];
1.1.1.4 root 549: #endif
1.1 root 550: /* LR */
551: target_ulong lr;
552: /* CTR */
553: target_ulong ctr;
554: /* condition register */
1.1.1.5 ! root 555: uint32_t crf[8];
1.1 root 556: /* XER */
1.1.1.5 ! root 557: target_ulong xer;
1.1 root 558: /* Reservation address */
559: target_ulong reserve;
560:
561: /* Those ones are used in supervisor mode only */
562: /* machine state register */
1.1.1.4 root 563: target_ulong msr;
1.1 root 564: /* temporary general purpose registers */
1.1.1.5 ! root 565: target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
1.1 root 566:
567: /* Floating point execution context */
568: float_status fp_status;
569: /* floating point registers */
570: float64 fpr[32];
571: /* floating point status and control register */
1.1.1.4 root 572: uint32_t fpscr;
1.1 root 573:
1.1.1.2 root 574: CPU_COMMON
575:
1.1 root 576: int access_type; /* when a memory exception occurs, the access
577: type is stored here */
578:
1.1.1.4 root 579: /* MMU context - only relevant for full system emulation */
580: #if !defined(CONFIG_USER_ONLY)
581: #if defined(TARGET_PPC64)
1.1 root 582: /* Address space register */
583: target_ulong asr;
1.1.1.4 root 584: /* PowerPC 64 SLB area */
585: int slb_nr;
586: #endif
1.1 root 587: /* segment registers */
588: target_ulong sdr1;
1.1.1.5 ! root 589: target_ulong sr[32];
1.1 root 590: /* BATs */
591: int nb_BATs;
592: target_ulong DBAT[2][8];
593: target_ulong IBAT[2][8];
1.1.1.4 root 594: /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
595: int nb_tlb; /* Total number of TLB */
596: int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
597: int nb_ways; /* Number of ways in the TLB set */
598: int last_way; /* Last used way used to allocate TLB in a LRU way */
599: int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
600: int nb_pids; /* Number of available PID registers */
601: ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
602: /* 403 dedicated access protection registers */
603: target_ulong pb[4];
604: #endif
1.1 root 605:
606: /* Other registers */
607: /* Special purpose registers */
608: target_ulong spr[1024];
1.1.1.4 root 609: ppc_spr_t spr_cb[1024];
1.1 root 610: /* Altivec registers */
611: ppc_avr_t avr[32];
612: uint32_t vscr;
1.1.1.4 root 613: /* SPE registers */
1.1.1.5 ! root 614: uint64_t spe_acc;
1.1.1.4 root 615: uint32_t spe_fscr;
1.1.1.5 ! root 616: /* SPE and Altivec can share a status since they will never be used
! 617: * simultaneously */
! 618: float_status vec_status;
1.1 root 619:
620: /* Internal devices resources */
621: /* Time base and decrementer */
622: ppc_tb_t *tb_env;
623: /* Device control registers */
624: ppc_dcr_t *dcr_env;
625:
1.1.1.4 root 626: int dcache_line_size;
627: int icache_line_size;
1.1 root 628:
629: /* Those resources are used during exception processing */
630: /* CPU model definition */
1.1.1.4 root 631: target_ulong msr_mask;
632: powerpc_mmu_t mmu_model;
633: powerpc_excp_t excp_model;
634: powerpc_input_t bus_model;
635: int bfd_mach;
1.1 root 636: uint32_t flags;
637:
638: int error_code;
1.1.1.4 root 639: uint32_t pending_interrupts;
640: #if !defined(CONFIG_USER_ONLY)
641: /* This is the IRQ controller, which is implementation dependant
642: * and only relevant when emulating a complete machine.
643: */
644: uint32_t irq_input_state;
645: void **irq_inputs;
646: /* Exception vectors */
647: target_ulong excp_vectors[POWERPC_EXCP_NB];
648: target_ulong excp_prefix;
649: target_ulong ivor_mask;
650: target_ulong ivpr_mask;
651: target_ulong hreset_vector;
652: #endif
1.1 root 653:
654: /* Those resources are used only during code translation */
655: /* Next instruction pointer */
656: target_ulong nip;
1.1.1.4 root 657:
1.1 root 658: /* opcode handlers */
659: opc_handler_t *opcodes[0x40];
660:
661: /* Those resources are used only in Qemu core */
1.1.1.4 root 662: target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
663: target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
664: int mmu_idx; /* precomputed MMU index to speed up mem accesses */
1.1 root 665:
666: /* Power management */
667: int power_mode;
1.1.1.4 root 668: int (*check_pow)(CPUPPCState *env);
1.1 root 669:
670: /* temporary hack to handle OSI calls (only used if non NULL) */
671: int (*osi_call)(struct CPUPPCState *env);
672: };
673:
1.1.1.4 root 674: /* Context used internally during MMU translations */
675: typedef struct mmu_ctx_t mmu_ctx_t;
676: struct mmu_ctx_t {
677: target_phys_addr_t raddr; /* Real address */
678: int prot; /* Protection bits */
679: target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
680: target_ulong ptem; /* Virtual segment ID | API */
681: int key; /* Access key */
682: int nx; /* Non-execute area */
683: };
684:
1.1 root 685: /*****************************************************************************/
1.1.1.4 root 686: CPUPPCState *cpu_ppc_init (const char *cpu_model);
1.1.1.5 ! root 687: void ppc_translate_init(void);
1.1.1.4 root 688: int cpu_ppc_exec (CPUPPCState *s);
689: void cpu_ppc_close (CPUPPCState *s);
1.1 root 690: /* you can call this signal handler from your SIGBUS and SIGSEGV
691: signal handlers to inform the virtual CPU of exceptions. non zero
692: is returned if the signal was handled by the virtual CPU. */
1.1.1.4 root 693: int cpu_ppc_signal_handler (int host_signum, void *pinfo,
694: void *puc);
1.1.1.5 ! root 695: int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
! 696: int mmu_idx, int is_softmmu);
! 697: int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,
! 698: int rw, int access_type);
1.1 root 699: void do_interrupt (CPUPPCState *env);
1.1.1.4 root 700: void ppc_hw_interrupt (CPUPPCState *env);
1.1 root 701:
1.1.1.5 ! root 702: void cpu_dump_rfi (target_ulong RA, target_ulong msr);
1.1 root 703:
1.1.1.4 root 704: #if !defined(CONFIG_USER_ONLY)
1.1.1.5 ! root 705: void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code,
! 706: target_ulong pte0, target_ulong pte1);
! 707: void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
! 708: void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
! 709: void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
! 710: void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
! 711: void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
! 712: void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
! 713: void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1.1.1.4 root 714: #if defined(TARGET_PPC64)
715: void ppc_store_asr (CPUPPCState *env, target_ulong value);
716: target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
717: void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs);
718: #endif /* defined(TARGET_PPC64) */
1.1.1.5 ! root 719: void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value);
1.1.1.4 root 720: #endif /* !defined(CONFIG_USER_ONLY) */
721: void ppc_store_msr (CPUPPCState *env, target_ulong value);
1.1 root 722:
1.1.1.4 root 723: void cpu_ppc_reset (void *opaque);
1.1 root 724:
725: void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
1.1.1.4 root 726:
1.1.1.5 ! root 727: const ppc_def_t *cpu_ppc_find_by_name (const char *name);
1.1.1.4 root 728: int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
1.1 root 729:
730: /* Time-base and decrementer management */
731: #ifndef NO_CPU_IO_DEFS
732: uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
733: uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
734: void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
735: void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1.1.1.4 root 736: uint32_t cpu_ppc_load_atbl (CPUPPCState *env);
737: uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
738: void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
739: void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1.1 root 740: uint32_t cpu_ppc_load_decr (CPUPPCState *env);
741: void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1.1.1.4 root 742: uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
743: void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
744: uint64_t cpu_ppc_load_purr (CPUPPCState *env);
745: void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
746: uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
747: uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
748: #if !defined(CONFIG_USER_ONLY)
749: void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
750: void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
751: target_ulong load_40x_pit (CPUPPCState *env);
752: void store_40x_pit (CPUPPCState *env, target_ulong val);
753: void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
754: void store_40x_sler (CPUPPCState *env, uint32_t val);
755: void store_booke_tcr (CPUPPCState *env, target_ulong val);
756: void store_booke_tsr (CPUPPCState *env, target_ulong val);
757: void ppc_tlb_invalidate_all (CPUPPCState *env);
758: void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
759: #if defined(TARGET_PPC64)
760: void ppc_slb_invalidate_all (CPUPPCState *env);
761: void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
762: #endif
763: int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
764: #endif
1.1 root 765: #endif
766:
1.1.1.4 root 767: static always_inline uint64_t ppc_dump_gpr (CPUPPCState *env, int gprn)
768: {
769: uint64_t gprv;
770:
771: gprv = env->gpr[gprn];
772: #if !defined(TARGET_PPC64)
773: if (env->flags & POWERPC_FLAG_SPE) {
774: /* If the CPU implements the SPE extension, we have to get the
775: * high bits of the GPR from the gprh storage area
776: */
777: gprv &= 0xFFFFFFFFULL;
778: gprv |= (uint64_t)env->gprh[gprn] << 32;
779: }
780: #endif
781:
782: return gprv;
783: }
784:
785: /* Device control registers */
786: int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
787: int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
788:
789: #define CPUState CPUPPCState
790: #define cpu_init cpu_ppc_init
791: #define cpu_exec cpu_ppc_exec
792: #define cpu_gen_code cpu_ppc_gen_code
793: #define cpu_signal_handler cpu_ppc_signal_handler
794: #define cpu_list ppc_cpu_list
795:
1.1.1.5 ! root 796: #define CPU_SAVE_VERSION 3
! 797:
1.1.1.4 root 798: /* MMU modes definitions */
799: #define MMU_MODE0_SUFFIX _user
800: #define MMU_MODE1_SUFFIX _kernel
801: #define MMU_MODE2_SUFFIX _hypv
802: #define MMU_USER_IDX 0
803: static inline int cpu_mmu_index (CPUState *env)
804: {
805: return env->mmu_idx;
806: }
807:
1.1.1.5 ! root 808: #if defined(CONFIG_USER_ONLY)
! 809: static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
! 810: {
! 811: int i;
! 812: if (newsp)
! 813: env->gpr[1] = newsp;
! 814: for (i = 7; i < 32; i++)
! 815: env->gpr[i] = 0;
! 816: }
! 817: #endif
! 818:
1.1 root 819: #include "cpu-all.h"
1.1.1.5 ! root 820: #include "exec-all.h"
1.1 root 821:
822: /*****************************************************************************/
1.1.1.5 ! root 823: /* CRF definitions */
! 824: #define CRF_LT 3
! 825: #define CRF_GT 2
! 826: #define CRF_EQ 1
! 827: #define CRF_SO 0
! 828: #define CRF_CH (1 << 4)
! 829: #define CRF_CL (1 << 3)
! 830: #define CRF_CH_OR_CL (1 << 2)
! 831: #define CRF_CH_AND_CL (1 << 1)
! 832:
! 833: /* XER definitions */
! 834: #define XER_SO 31
! 835: #define XER_OV 30
! 836: #define XER_CA 29
! 837: #define XER_CMP 8
! 838: #define XER_BC 0
! 839: #define xer_so ((env->xer >> XER_SO) & 1)
! 840: #define xer_ov ((env->xer >> XER_OV) & 1)
! 841: #define xer_ca ((env->xer >> XER_CA) & 1)
! 842: #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
! 843: #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1.1 root 844:
845: /* SPR definitions */
1.1.1.4 root 846: #define SPR_MQ (0x000)
847: #define SPR_XER (0x001)
848: #define SPR_601_VRTCU (0x004)
849: #define SPR_601_VRTCL (0x005)
850: #define SPR_601_UDECR (0x006)
851: #define SPR_LR (0x008)
852: #define SPR_CTR (0x009)
853: #define SPR_DSISR (0x012)
854: #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
855: #define SPR_601_RTCU (0x014)
856: #define SPR_601_RTCL (0x015)
857: #define SPR_DECR (0x016)
858: #define SPR_SDR1 (0x019)
859: #define SPR_SRR0 (0x01A)
860: #define SPR_SRR1 (0x01B)
861: #define SPR_AMR (0x01D)
862: #define SPR_BOOKE_PID (0x030)
863: #define SPR_BOOKE_DECAR (0x036)
864: #define SPR_BOOKE_CSRR0 (0x03A)
865: #define SPR_BOOKE_CSRR1 (0x03B)
866: #define SPR_BOOKE_DEAR (0x03D)
867: #define SPR_BOOKE_ESR (0x03E)
868: #define SPR_BOOKE_IVPR (0x03F)
869: #define SPR_MPC_EIE (0x050)
870: #define SPR_MPC_EID (0x051)
871: #define SPR_MPC_NRI (0x052)
872: #define SPR_CTRL (0x088)
873: #define SPR_MPC_CMPA (0x090)
874: #define SPR_MPC_CMPB (0x091)
875: #define SPR_MPC_CMPC (0x092)
876: #define SPR_MPC_CMPD (0x093)
877: #define SPR_MPC_ECR (0x094)
878: #define SPR_MPC_DER (0x095)
879: #define SPR_MPC_COUNTA (0x096)
880: #define SPR_MPC_COUNTB (0x097)
881: #define SPR_UCTRL (0x098)
882: #define SPR_MPC_CMPE (0x098)
883: #define SPR_MPC_CMPF (0x099)
884: #define SPR_MPC_CMPG (0x09A)
885: #define SPR_MPC_CMPH (0x09B)
886: #define SPR_MPC_LCTRL1 (0x09C)
887: #define SPR_MPC_LCTRL2 (0x09D)
888: #define SPR_MPC_ICTRL (0x09E)
889: #define SPR_MPC_BAR (0x09F)
890: #define SPR_VRSAVE (0x100)
891: #define SPR_USPRG0 (0x100)
892: #define SPR_USPRG1 (0x101)
893: #define SPR_USPRG2 (0x102)
894: #define SPR_USPRG3 (0x103)
895: #define SPR_USPRG4 (0x104)
896: #define SPR_USPRG5 (0x105)
897: #define SPR_USPRG6 (0x106)
898: #define SPR_USPRG7 (0x107)
899: #define SPR_VTBL (0x10C)
900: #define SPR_VTBU (0x10D)
901: #define SPR_SPRG0 (0x110)
902: #define SPR_SPRG1 (0x111)
903: #define SPR_SPRG2 (0x112)
904: #define SPR_SPRG3 (0x113)
905: #define SPR_SPRG4 (0x114)
906: #define SPR_SCOMC (0x114)
907: #define SPR_SPRG5 (0x115)
908: #define SPR_SCOMD (0x115)
909: #define SPR_SPRG6 (0x116)
910: #define SPR_SPRG7 (0x117)
911: #define SPR_ASR (0x118)
912: #define SPR_EAR (0x11A)
913: #define SPR_TBL (0x11C)
914: #define SPR_TBU (0x11D)
915: #define SPR_TBU40 (0x11E)
916: #define SPR_SVR (0x11E)
917: #define SPR_BOOKE_PIR (0x11E)
918: #define SPR_PVR (0x11F)
919: #define SPR_HSPRG0 (0x130)
920: #define SPR_BOOKE_DBSR (0x130)
921: #define SPR_HSPRG1 (0x131)
922: #define SPR_HDSISR (0x132)
923: #define SPR_HDAR (0x133)
924: #define SPR_BOOKE_DBCR0 (0x134)
925: #define SPR_IBCR (0x135)
926: #define SPR_PURR (0x135)
927: #define SPR_BOOKE_DBCR1 (0x135)
928: #define SPR_DBCR (0x136)
929: #define SPR_HDEC (0x136)
930: #define SPR_BOOKE_DBCR2 (0x136)
931: #define SPR_HIOR (0x137)
932: #define SPR_MBAR (0x137)
933: #define SPR_RMOR (0x138)
934: #define SPR_BOOKE_IAC1 (0x138)
935: #define SPR_HRMOR (0x139)
936: #define SPR_BOOKE_IAC2 (0x139)
937: #define SPR_HSRR0 (0x13A)
938: #define SPR_BOOKE_IAC3 (0x13A)
939: #define SPR_HSRR1 (0x13B)
940: #define SPR_BOOKE_IAC4 (0x13B)
941: #define SPR_LPCR (0x13C)
942: #define SPR_BOOKE_DAC1 (0x13C)
943: #define SPR_LPIDR (0x13D)
944: #define SPR_DABR2 (0x13D)
945: #define SPR_BOOKE_DAC2 (0x13D)
946: #define SPR_BOOKE_DVC1 (0x13E)
947: #define SPR_BOOKE_DVC2 (0x13F)
948: #define SPR_BOOKE_TSR (0x150)
949: #define SPR_BOOKE_TCR (0x154)
950: #define SPR_BOOKE_IVOR0 (0x190)
951: #define SPR_BOOKE_IVOR1 (0x191)
952: #define SPR_BOOKE_IVOR2 (0x192)
953: #define SPR_BOOKE_IVOR3 (0x193)
954: #define SPR_BOOKE_IVOR4 (0x194)
955: #define SPR_BOOKE_IVOR5 (0x195)
956: #define SPR_BOOKE_IVOR6 (0x196)
957: #define SPR_BOOKE_IVOR7 (0x197)
958: #define SPR_BOOKE_IVOR8 (0x198)
959: #define SPR_BOOKE_IVOR9 (0x199)
960: #define SPR_BOOKE_IVOR10 (0x19A)
961: #define SPR_BOOKE_IVOR11 (0x19B)
962: #define SPR_BOOKE_IVOR12 (0x19C)
963: #define SPR_BOOKE_IVOR13 (0x19D)
964: #define SPR_BOOKE_IVOR14 (0x19E)
965: #define SPR_BOOKE_IVOR15 (0x19F)
966: #define SPR_BOOKE_SPEFSCR (0x200)
967: #define SPR_Exxx_BBEAR (0x201)
968: #define SPR_Exxx_BBTAR (0x202)
969: #define SPR_Exxx_L1CFG0 (0x203)
970: #define SPR_Exxx_NPIDR (0x205)
971: #define SPR_ATBL (0x20E)
972: #define SPR_ATBU (0x20F)
973: #define SPR_IBAT0U (0x210)
974: #define SPR_BOOKE_IVOR32 (0x210)
975: #define SPR_RCPU_MI_GRA (0x210)
976: #define SPR_IBAT0L (0x211)
977: #define SPR_BOOKE_IVOR33 (0x211)
978: #define SPR_IBAT1U (0x212)
979: #define SPR_BOOKE_IVOR34 (0x212)
980: #define SPR_IBAT1L (0x213)
981: #define SPR_BOOKE_IVOR35 (0x213)
982: #define SPR_IBAT2U (0x214)
983: #define SPR_BOOKE_IVOR36 (0x214)
984: #define SPR_IBAT2L (0x215)
985: #define SPR_BOOKE_IVOR37 (0x215)
986: #define SPR_IBAT3U (0x216)
987: #define SPR_IBAT3L (0x217)
988: #define SPR_DBAT0U (0x218)
989: #define SPR_RCPU_L2U_GRA (0x218)
990: #define SPR_DBAT0L (0x219)
991: #define SPR_DBAT1U (0x21A)
992: #define SPR_DBAT1L (0x21B)
993: #define SPR_DBAT2U (0x21C)
994: #define SPR_DBAT2L (0x21D)
995: #define SPR_DBAT3U (0x21E)
996: #define SPR_DBAT3L (0x21F)
997: #define SPR_IBAT4U (0x230)
998: #define SPR_RPCU_BBCMCR (0x230)
999: #define SPR_MPC_IC_CST (0x230)
1000: #define SPR_Exxx_CTXCR (0x230)
1001: #define SPR_IBAT4L (0x231)
1002: #define SPR_MPC_IC_ADR (0x231)
1003: #define SPR_Exxx_DBCR3 (0x231)
1004: #define SPR_IBAT5U (0x232)
1005: #define SPR_MPC_IC_DAT (0x232)
1006: #define SPR_Exxx_DBCNT (0x232)
1007: #define SPR_IBAT5L (0x233)
1008: #define SPR_IBAT6U (0x234)
1009: #define SPR_IBAT6L (0x235)
1010: #define SPR_IBAT7U (0x236)
1011: #define SPR_IBAT7L (0x237)
1012: #define SPR_DBAT4U (0x238)
1013: #define SPR_RCPU_L2U_MCR (0x238)
1014: #define SPR_MPC_DC_CST (0x238)
1015: #define SPR_Exxx_ALTCTXCR (0x238)
1016: #define SPR_DBAT4L (0x239)
1017: #define SPR_MPC_DC_ADR (0x239)
1018: #define SPR_DBAT5U (0x23A)
1019: #define SPR_BOOKE_MCSRR0 (0x23A)
1020: #define SPR_MPC_DC_DAT (0x23A)
1021: #define SPR_DBAT5L (0x23B)
1022: #define SPR_BOOKE_MCSRR1 (0x23B)
1023: #define SPR_DBAT6U (0x23C)
1024: #define SPR_BOOKE_MCSR (0x23C)
1025: #define SPR_DBAT6L (0x23D)
1026: #define SPR_Exxx_MCAR (0x23D)
1027: #define SPR_DBAT7U (0x23E)
1028: #define SPR_BOOKE_DSRR0 (0x23E)
1029: #define SPR_DBAT7L (0x23F)
1030: #define SPR_BOOKE_DSRR1 (0x23F)
1031: #define SPR_BOOKE_SPRG8 (0x25C)
1032: #define SPR_BOOKE_SPRG9 (0x25D)
1033: #define SPR_BOOKE_MAS0 (0x270)
1034: #define SPR_BOOKE_MAS1 (0x271)
1035: #define SPR_BOOKE_MAS2 (0x272)
1036: #define SPR_BOOKE_MAS3 (0x273)
1037: #define SPR_BOOKE_MAS4 (0x274)
1038: #define SPR_BOOKE_MAS5 (0x275)
1039: #define SPR_BOOKE_MAS6 (0x276)
1040: #define SPR_BOOKE_PID1 (0x279)
1041: #define SPR_BOOKE_PID2 (0x27A)
1042: #define SPR_MPC_DPDR (0x280)
1043: #define SPR_MPC_IMMR (0x288)
1044: #define SPR_BOOKE_TLB0CFG (0x2B0)
1045: #define SPR_BOOKE_TLB1CFG (0x2B1)
1046: #define SPR_BOOKE_TLB2CFG (0x2B2)
1047: #define SPR_BOOKE_TLB3CFG (0x2B3)
1048: #define SPR_BOOKE_EPR (0x2BE)
1049: #define SPR_PERF0 (0x300)
1050: #define SPR_RCPU_MI_RBA0 (0x300)
1051: #define SPR_MPC_MI_CTR (0x300)
1052: #define SPR_PERF1 (0x301)
1053: #define SPR_RCPU_MI_RBA1 (0x301)
1054: #define SPR_PERF2 (0x302)
1055: #define SPR_RCPU_MI_RBA2 (0x302)
1056: #define SPR_MPC_MI_AP (0x302)
1057: #define SPR_PERF3 (0x303)
1058: #define SPR_620_PMC1R (0x303)
1059: #define SPR_RCPU_MI_RBA3 (0x303)
1060: #define SPR_MPC_MI_EPN (0x303)
1061: #define SPR_PERF4 (0x304)
1062: #define SPR_620_PMC2R (0x304)
1063: #define SPR_PERF5 (0x305)
1064: #define SPR_MPC_MI_TWC (0x305)
1065: #define SPR_PERF6 (0x306)
1066: #define SPR_MPC_MI_RPN (0x306)
1067: #define SPR_PERF7 (0x307)
1068: #define SPR_PERF8 (0x308)
1069: #define SPR_RCPU_L2U_RBA0 (0x308)
1070: #define SPR_MPC_MD_CTR (0x308)
1071: #define SPR_PERF9 (0x309)
1072: #define SPR_RCPU_L2U_RBA1 (0x309)
1073: #define SPR_MPC_MD_CASID (0x309)
1074: #define SPR_PERFA (0x30A)
1075: #define SPR_RCPU_L2U_RBA2 (0x30A)
1076: #define SPR_MPC_MD_AP (0x30A)
1077: #define SPR_PERFB (0x30B)
1078: #define SPR_620_MMCR0R (0x30B)
1079: #define SPR_RCPU_L2U_RBA3 (0x30B)
1080: #define SPR_MPC_MD_EPN (0x30B)
1081: #define SPR_PERFC (0x30C)
1082: #define SPR_MPC_MD_TWB (0x30C)
1083: #define SPR_PERFD (0x30D)
1084: #define SPR_MPC_MD_TWC (0x30D)
1085: #define SPR_PERFE (0x30E)
1086: #define SPR_MPC_MD_RPN (0x30E)
1087: #define SPR_PERFF (0x30F)
1088: #define SPR_MPC_MD_TW (0x30F)
1089: #define SPR_UPERF0 (0x310)
1090: #define SPR_UPERF1 (0x311)
1091: #define SPR_UPERF2 (0x312)
1092: #define SPR_UPERF3 (0x313)
1093: #define SPR_620_PMC1W (0x313)
1094: #define SPR_UPERF4 (0x314)
1095: #define SPR_620_PMC2W (0x314)
1096: #define SPR_UPERF5 (0x315)
1097: #define SPR_UPERF6 (0x316)
1098: #define SPR_UPERF7 (0x317)
1099: #define SPR_UPERF8 (0x318)
1100: #define SPR_UPERF9 (0x319)
1101: #define SPR_UPERFA (0x31A)
1102: #define SPR_UPERFB (0x31B)
1103: #define SPR_620_MMCR0W (0x31B)
1104: #define SPR_UPERFC (0x31C)
1105: #define SPR_UPERFD (0x31D)
1106: #define SPR_UPERFE (0x31E)
1107: #define SPR_UPERFF (0x31F)
1108: #define SPR_RCPU_MI_RA0 (0x320)
1109: #define SPR_MPC_MI_DBCAM (0x320)
1110: #define SPR_RCPU_MI_RA1 (0x321)
1111: #define SPR_MPC_MI_DBRAM0 (0x321)
1112: #define SPR_RCPU_MI_RA2 (0x322)
1113: #define SPR_MPC_MI_DBRAM1 (0x322)
1114: #define SPR_RCPU_MI_RA3 (0x323)
1115: #define SPR_RCPU_L2U_RA0 (0x328)
1116: #define SPR_MPC_MD_DBCAM (0x328)
1117: #define SPR_RCPU_L2U_RA1 (0x329)
1118: #define SPR_MPC_MD_DBRAM0 (0x329)
1119: #define SPR_RCPU_L2U_RA2 (0x32A)
1120: #define SPR_MPC_MD_DBRAM1 (0x32A)
1121: #define SPR_RCPU_L2U_RA3 (0x32B)
1122: #define SPR_440_INV0 (0x370)
1123: #define SPR_440_INV1 (0x371)
1124: #define SPR_440_INV2 (0x372)
1125: #define SPR_440_INV3 (0x373)
1126: #define SPR_440_ITV0 (0x374)
1127: #define SPR_440_ITV1 (0x375)
1128: #define SPR_440_ITV2 (0x376)
1129: #define SPR_440_ITV3 (0x377)
1130: #define SPR_440_CCR1 (0x378)
1131: #define SPR_DCRIPR (0x37B)
1132: #define SPR_PPR (0x380)
1133: #define SPR_750_GQR0 (0x390)
1134: #define SPR_440_DNV0 (0x390)
1135: #define SPR_750_GQR1 (0x391)
1136: #define SPR_440_DNV1 (0x391)
1137: #define SPR_750_GQR2 (0x392)
1138: #define SPR_440_DNV2 (0x392)
1139: #define SPR_750_GQR3 (0x393)
1140: #define SPR_440_DNV3 (0x393)
1141: #define SPR_750_GQR4 (0x394)
1142: #define SPR_440_DTV0 (0x394)
1143: #define SPR_750_GQR5 (0x395)
1144: #define SPR_440_DTV1 (0x395)
1145: #define SPR_750_GQR6 (0x396)
1146: #define SPR_440_DTV2 (0x396)
1147: #define SPR_750_GQR7 (0x397)
1148: #define SPR_440_DTV3 (0x397)
1149: #define SPR_750_THRM4 (0x398)
1150: #define SPR_750CL_HID2 (0x398)
1151: #define SPR_440_DVLIM (0x398)
1152: #define SPR_750_WPAR (0x399)
1153: #define SPR_440_IVLIM (0x399)
1154: #define SPR_750_DMAU (0x39A)
1155: #define SPR_750_DMAL (0x39B)
1156: #define SPR_440_RSTCFG (0x39B)
1157: #define SPR_BOOKE_DCDBTRL (0x39C)
1158: #define SPR_BOOKE_DCDBTRH (0x39D)
1159: #define SPR_BOOKE_ICDBTRL (0x39E)
1160: #define SPR_BOOKE_ICDBTRH (0x39F)
1161: #define SPR_UMMCR2 (0x3A0)
1162: #define SPR_UPMC5 (0x3A1)
1163: #define SPR_UPMC6 (0x3A2)
1164: #define SPR_UBAMR (0x3A7)
1165: #define SPR_UMMCR0 (0x3A8)
1166: #define SPR_UPMC1 (0x3A9)
1167: #define SPR_UPMC2 (0x3AA)
1168: #define SPR_USIAR (0x3AB)
1169: #define SPR_UMMCR1 (0x3AC)
1170: #define SPR_UPMC3 (0x3AD)
1171: #define SPR_UPMC4 (0x3AE)
1172: #define SPR_USDA (0x3AF)
1173: #define SPR_40x_ZPR (0x3B0)
1174: #define SPR_BOOKE_MAS7 (0x3B0)
1175: #define SPR_620_PMR0 (0x3B0)
1176: #define SPR_MMCR2 (0x3B0)
1177: #define SPR_PMC5 (0x3B1)
1178: #define SPR_40x_PID (0x3B1)
1179: #define SPR_620_PMR1 (0x3B1)
1180: #define SPR_PMC6 (0x3B2)
1181: #define SPR_440_MMUCR (0x3B2)
1182: #define SPR_620_PMR2 (0x3B2)
1183: #define SPR_4xx_CCR0 (0x3B3)
1184: #define SPR_BOOKE_EPLC (0x3B3)
1185: #define SPR_620_PMR3 (0x3B3)
1186: #define SPR_405_IAC3 (0x3B4)
1187: #define SPR_BOOKE_EPSC (0x3B4)
1188: #define SPR_620_PMR4 (0x3B4)
1189: #define SPR_405_IAC4 (0x3B5)
1190: #define SPR_620_PMR5 (0x3B5)
1191: #define SPR_405_DVC1 (0x3B6)
1192: #define SPR_620_PMR6 (0x3B6)
1193: #define SPR_405_DVC2 (0x3B7)
1194: #define SPR_620_PMR7 (0x3B7)
1195: #define SPR_BAMR (0x3B7)
1196: #define SPR_MMCR0 (0x3B8)
1197: #define SPR_620_PMR8 (0x3B8)
1198: #define SPR_PMC1 (0x3B9)
1199: #define SPR_40x_SGR (0x3B9)
1200: #define SPR_620_PMR9 (0x3B9)
1201: #define SPR_PMC2 (0x3BA)
1202: #define SPR_40x_DCWR (0x3BA)
1203: #define SPR_620_PMRA (0x3BA)
1204: #define SPR_SIAR (0x3BB)
1205: #define SPR_405_SLER (0x3BB)
1206: #define SPR_620_PMRB (0x3BB)
1207: #define SPR_MMCR1 (0x3BC)
1208: #define SPR_405_SU0R (0x3BC)
1209: #define SPR_620_PMRC (0x3BC)
1210: #define SPR_401_SKR (0x3BC)
1211: #define SPR_PMC3 (0x3BD)
1212: #define SPR_405_DBCR1 (0x3BD)
1213: #define SPR_620_PMRD (0x3BD)
1214: #define SPR_PMC4 (0x3BE)
1215: #define SPR_620_PMRE (0x3BE)
1216: #define SPR_SDA (0x3BF)
1217: #define SPR_620_PMRF (0x3BF)
1218: #define SPR_403_VTBL (0x3CC)
1219: #define SPR_403_VTBU (0x3CD)
1220: #define SPR_DMISS (0x3D0)
1221: #define SPR_DCMP (0x3D1)
1222: #define SPR_HASH1 (0x3D2)
1223: #define SPR_HASH2 (0x3D3)
1224: #define SPR_BOOKE_ICDBDR (0x3D3)
1225: #define SPR_TLBMISS (0x3D4)
1226: #define SPR_IMISS (0x3D4)
1227: #define SPR_40x_ESR (0x3D4)
1228: #define SPR_PTEHI (0x3D5)
1229: #define SPR_ICMP (0x3D5)
1230: #define SPR_40x_DEAR (0x3D5)
1231: #define SPR_PTELO (0x3D6)
1232: #define SPR_RPA (0x3D6)
1233: #define SPR_40x_EVPR (0x3D6)
1234: #define SPR_L3PM (0x3D7)
1235: #define SPR_403_CDBCR (0x3D7)
1236: #define SPR_L3ITCR0 (0x3D8)
1237: #define SPR_TCR (0x3D8)
1238: #define SPR_40x_TSR (0x3D8)
1239: #define SPR_IBR (0x3DA)
1240: #define SPR_40x_TCR (0x3DA)
1241: #define SPR_ESASRR (0x3DB)
1242: #define SPR_40x_PIT (0x3DB)
1243: #define SPR_403_TBL (0x3DC)
1244: #define SPR_403_TBU (0x3DD)
1245: #define SPR_SEBR (0x3DE)
1246: #define SPR_40x_SRR2 (0x3DE)
1247: #define SPR_SER (0x3DF)
1248: #define SPR_40x_SRR3 (0x3DF)
1249: #define SPR_L3OHCR (0x3E8)
1250: #define SPR_L3ITCR1 (0x3E9)
1251: #define SPR_L3ITCR2 (0x3EA)
1252: #define SPR_L3ITCR3 (0x3EB)
1253: #define SPR_HID0 (0x3F0)
1254: #define SPR_40x_DBSR (0x3F0)
1255: #define SPR_HID1 (0x3F1)
1256: #define SPR_IABR (0x3F2)
1257: #define SPR_40x_DBCR0 (0x3F2)
1258: #define SPR_601_HID2 (0x3F2)
1259: #define SPR_Exxx_L1CSR0 (0x3F2)
1260: #define SPR_ICTRL (0x3F3)
1261: #define SPR_HID2 (0x3F3)
1262: #define SPR_750CL_HID4 (0x3F3)
1263: #define SPR_Exxx_L1CSR1 (0x3F3)
1264: #define SPR_440_DBDR (0x3F3)
1265: #define SPR_LDSTDB (0x3F4)
1266: #define SPR_750_TDCL (0x3F4)
1267: #define SPR_40x_IAC1 (0x3F4)
1268: #define SPR_MMUCSR0 (0x3F4)
1269: #define SPR_DABR (0x3F5)
1.1 root 1270: #define DABR_MASK (~(target_ulong)0x7)
1.1.1.4 root 1271: #define SPR_Exxx_BUCSR (0x3F5)
1272: #define SPR_40x_IAC2 (0x3F5)
1273: #define SPR_601_HID5 (0x3F5)
1274: #define SPR_40x_DAC1 (0x3F6)
1275: #define SPR_MSSCR0 (0x3F6)
1276: #define SPR_970_HID5 (0x3F6)
1277: #define SPR_MSSSR0 (0x3F7)
1278: #define SPR_MSSCR1 (0x3F7)
1279: #define SPR_DABRX (0x3F7)
1280: #define SPR_40x_DAC2 (0x3F7)
1281: #define SPR_MMUCFG (0x3F7)
1282: #define SPR_LDSTCR (0x3F8)
1283: #define SPR_L2PMCR (0x3F8)
1284: #define SPR_750FX_HID2 (0x3F8)
1285: #define SPR_620_BUSCSR (0x3F8)
1286: #define SPR_Exxx_L1FINV0 (0x3F8)
1287: #define SPR_L2CR (0x3F9)
1288: #define SPR_620_L2CR (0x3F9)
1289: #define SPR_L3CR (0x3FA)
1290: #define SPR_750_TDCH (0x3FA)
1291: #define SPR_IABR2 (0x3FA)
1292: #define SPR_40x_DCCR (0x3FA)
1293: #define SPR_620_L2SR (0x3FA)
1294: #define SPR_ICTC (0x3FB)
1295: #define SPR_40x_ICCR (0x3FB)
1296: #define SPR_THRM1 (0x3FC)
1297: #define SPR_403_PBL1 (0x3FC)
1298: #define SPR_SP (0x3FD)
1299: #define SPR_THRM2 (0x3FD)
1300: #define SPR_403_PBU1 (0x3FD)
1301: #define SPR_604_HID13 (0x3FD)
1302: #define SPR_LT (0x3FE)
1303: #define SPR_THRM3 (0x3FE)
1304: #define SPR_RCPU_FPECR (0x3FE)
1305: #define SPR_403_PBL2 (0x3FE)
1306: #define SPR_PIR (0x3FF)
1307: #define SPR_403_PBU2 (0x3FF)
1308: #define SPR_601_HID15 (0x3FF)
1309: #define SPR_604_HID15 (0x3FF)
1310: #define SPR_E500_SVR (0x3FF)
1.1 root 1311:
1.1.1.4 root 1312: /*****************************************************************************/
1.1 root 1313: /* Memory access type :
1314: * may be needed for precise access rights control and precise exceptions.
1315: */
1316: enum {
1317: /* 1 bit to define user level / supervisor access */
1318: ACCESS_USER = 0x00,
1319: ACCESS_SUPER = 0x01,
1320: /* Type of instruction that generated the access */
1321: ACCESS_CODE = 0x10, /* Code fetch access */
1322: ACCESS_INT = 0x20, /* Integer load/store access */
1323: ACCESS_FLOAT = 0x30, /* floating point load/store access */
1324: ACCESS_RES = 0x40, /* load/store with reservation */
1325: ACCESS_EXT = 0x50, /* external access */
1326: ACCESS_CACHE = 0x60, /* Cache manipulation */
1327: };
1328:
1.1.1.4 root 1329: /* Hardware interruption sources:
1330: * all those exception can be raised simulteaneously
1331: */
1332: /* Input pins definitions */
1333: enum {
1334: /* 6xx bus input pins */
1335: PPC6xx_INPUT_HRESET = 0,
1336: PPC6xx_INPUT_SRESET = 1,
1337: PPC6xx_INPUT_CKSTP_IN = 2,
1338: PPC6xx_INPUT_MCP = 3,
1339: PPC6xx_INPUT_SMI = 4,
1340: PPC6xx_INPUT_INT = 5,
1341: PPC6xx_INPUT_TBEN = 6,
1342: PPC6xx_INPUT_WAKEUP = 7,
1343: PPC6xx_INPUT_NB,
1344: };
1345:
1346: enum {
1347: /* Embedded PowerPC input pins */
1348: PPCBookE_INPUT_HRESET = 0,
1349: PPCBookE_INPUT_SRESET = 1,
1350: PPCBookE_INPUT_CKSTP_IN = 2,
1351: PPCBookE_INPUT_MCP = 3,
1352: PPCBookE_INPUT_SMI = 4,
1353: PPCBookE_INPUT_INT = 5,
1354: PPCBookE_INPUT_CINT = 6,
1355: PPCBookE_INPUT_NB,
1356: };
1357:
1358: enum {
1.1.1.5 ! root 1359: /* PowerPC E500 input pins */
! 1360: PPCE500_INPUT_RESET_CORE = 0,
! 1361: PPCE500_INPUT_MCK = 1,
! 1362: PPCE500_INPUT_CINT = 3,
! 1363: PPCE500_INPUT_INT = 4,
! 1364: PPCE500_INPUT_DEBUG = 6,
! 1365: PPCE500_INPUT_NB,
! 1366: };
! 1367:
! 1368: enum {
1.1.1.4 root 1369: /* PowerPC 40x input pins */
1370: PPC40x_INPUT_RESET_CORE = 0,
1371: PPC40x_INPUT_RESET_CHIP = 1,
1372: PPC40x_INPUT_RESET_SYS = 2,
1373: PPC40x_INPUT_CINT = 3,
1374: PPC40x_INPUT_INT = 4,
1375: PPC40x_INPUT_HALT = 5,
1376: PPC40x_INPUT_DEBUG = 6,
1377: PPC40x_INPUT_NB,
1378: };
1379:
1380: enum {
1381: /* RCPU input pins */
1382: PPCRCPU_INPUT_PORESET = 0,
1383: PPCRCPU_INPUT_HRESET = 1,
1384: PPCRCPU_INPUT_SRESET = 2,
1385: PPCRCPU_INPUT_IRQ0 = 3,
1386: PPCRCPU_INPUT_IRQ1 = 4,
1387: PPCRCPU_INPUT_IRQ2 = 5,
1388: PPCRCPU_INPUT_IRQ3 = 6,
1389: PPCRCPU_INPUT_IRQ4 = 7,
1390: PPCRCPU_INPUT_IRQ5 = 8,
1391: PPCRCPU_INPUT_IRQ6 = 9,
1392: PPCRCPU_INPUT_IRQ7 = 10,
1393: PPCRCPU_INPUT_NB,
1394: };
1395:
1396: #if defined(TARGET_PPC64)
1397: enum {
1398: /* PowerPC 970 input pins */
1399: PPC970_INPUT_HRESET = 0,
1400: PPC970_INPUT_SRESET = 1,
1401: PPC970_INPUT_CKSTP = 2,
1402: PPC970_INPUT_TBEN = 3,
1403: PPC970_INPUT_MCP = 4,
1404: PPC970_INPUT_INT = 5,
1405: PPC970_INPUT_THINT = 6,
1406: PPC970_INPUT_NB,
1407: };
1408: #endif
1.1 root 1409:
1.1.1.4 root 1410: /* Hardware exceptions definitions */
1.1 root 1411: enum {
1.1.1.4 root 1412: /* External hardware exception sources */
1413: PPC_INTERRUPT_RESET = 0, /* Reset exception */
1414: PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
1415: PPC_INTERRUPT_MCK, /* Machine check exception */
1416: PPC_INTERRUPT_EXT, /* External interrupt */
1417: PPC_INTERRUPT_SMI, /* System management interrupt */
1418: PPC_INTERRUPT_CEXT, /* Critical external interrupt */
1419: PPC_INTERRUPT_DEBUG, /* External debug exception */
1420: PPC_INTERRUPT_THERM, /* Thermal exception */
1421: /* Internal hardware exception sources */
1422: PPC_INTERRUPT_DECR, /* Decrementer exception */
1423: PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
1424: PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
1425: PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
1426: PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
1427: PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
1428: PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
1429: PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
1.1 root 1430: };
1431:
1432: /*****************************************************************************/
1433:
1.1.1.5 ! root 1434: static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
! 1435: {
! 1436: env->nip = tb->pc;
! 1437: }
! 1438:
! 1439: static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
! 1440: target_ulong *cs_base, int *flags)
! 1441: {
! 1442: *pc = env->nip;
! 1443: *cs_base = 0;
! 1444: *flags = env->hflags;
! 1445: }
! 1446:
1.1 root 1447: #endif /* !defined (__CPU_PPC_H__) */
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