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1.1 root 1: /*
2: * PowerPC emulation cpu definitions for qemu.
1.1.1.4 root 3: *
4: * Copyright (c) 2003-2007 Jocelyn Mayer
1.1 root 5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
1.1.1.6 root 17: * License along with this library; if not, see <http://www.gnu.org/licenses/>.
1.1 root 18: */
19: #if !defined (__CPU_PPC_H__)
20: #define __CPU_PPC_H__
21:
22: #include "config.h"
1.1.1.9 ! root 23: #include "qemu-common.h"
1.1.1.4 root 24:
25: //#define PPC_EMULATE_32BITS_HYPV
26:
27: #if defined (TARGET_PPC64)
28: /* PowerPC 64 definitions */
29: #define TARGET_LONG_BITS 64
30: #define TARGET_PAGE_BITS 12
31:
1.1.1.8 root 32: /* Note that the official physical address space bits is 62-M where M
33: is implementation dependent. I've not looked up M for the set of
34: cpus we emulate at the system level. */
35: #define TARGET_PHYS_ADDR_SPACE_BITS 62
36:
37: /* Note that the PPC environment architecture talks about 80 bit virtual
38: addresses, with segmentation. Obviously that's not all visible to a
39: single process, which is all we're concerned with here. */
40: #ifdef TARGET_ABI32
41: # define TARGET_VIRT_ADDR_SPACE_BITS 32
42: #else
43: # define TARGET_VIRT_ADDR_SPACE_BITS 64
44: #endif
45:
1.1.1.4 root 46: #else /* defined (TARGET_PPC64) */
47: /* PowerPC 32 definitions */
1.1 root 48: #define TARGET_LONG_BITS 32
49:
1.1.1.4 root 50: #if defined(TARGET_PPCEMB)
51: /* Specific definitions for PowerPC embedded */
52: /* BookE have 36 bits physical address space */
53: #if defined(CONFIG_USER_ONLY)
54: /* It looks like a lot of Linux programs assume page size
55: * is 4kB long. This is evil, but we have to deal with it...
56: */
57: #define TARGET_PAGE_BITS 12
58: #else /* defined(CONFIG_USER_ONLY) */
59: /* Pages can be 1 kB small */
60: #define TARGET_PAGE_BITS 10
61: #endif /* defined(CONFIG_USER_ONLY) */
62: #else /* defined(TARGET_PPCEMB) */
63: /* "standard" PowerPC 32 definitions */
64: #define TARGET_PAGE_BITS 12
65: #endif /* defined(TARGET_PPCEMB) */
66:
1.1.1.8 root 67: #define TARGET_PHYS_ADDR_SPACE_BITS 32
68: #define TARGET_VIRT_ADDR_SPACE_BITS 32
69:
1.1.1.4 root 70: #endif /* defined (TARGET_PPC64) */
71:
1.1.1.6 root 72: #define CPUState struct CPUPPCState
73:
1.1 root 74: #include "cpu-defs.h"
75:
76: #include <setjmp.h>
77:
78: #include "softfloat.h"
79:
80: #define TARGET_HAS_ICE 1
81:
1.1.1.6 root 82: #if defined (TARGET_PPC64)
1.1.1.4 root 83: #define ELF_MACHINE EM_PPC64
84: #else
85: #define ELF_MACHINE EM_PPC
86: #endif
1.1 root 87:
88: /*****************************************************************************/
1.1.1.4 root 89: /* MMU model */
90: typedef enum powerpc_mmu_t powerpc_mmu_t;
91: enum powerpc_mmu_t {
92: POWERPC_MMU_UNKNOWN = 0x00000000,
93: /* Standard 32 bits PowerPC MMU */
94: POWERPC_MMU_32B = 0x00000001,
95: /* PowerPC 6xx MMU with software TLB */
96: POWERPC_MMU_SOFT_6xx = 0x00000002,
97: /* PowerPC 74xx MMU with software TLB */
98: POWERPC_MMU_SOFT_74xx = 0x00000003,
99: /* PowerPC 4xx MMU with software TLB */
100: POWERPC_MMU_SOFT_4xx = 0x00000004,
101: /* PowerPC 4xx MMU with software TLB and zones protections */
102: POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
103: /* PowerPC MMU in real mode only */
104: POWERPC_MMU_REAL = 0x00000006,
105: /* Freescale MPC8xx MMU model */
106: POWERPC_MMU_MPC8xx = 0x00000007,
107: /* BookE MMU model */
108: POWERPC_MMU_BOOKE = 0x00000008,
109: /* BookE FSL MMU model */
110: POWERPC_MMU_BOOKE_FSL = 0x00000009,
111: /* PowerPC 601 MMU model (specific BATs format) */
112: POWERPC_MMU_601 = 0x0000000A,
113: #if defined(TARGET_PPC64)
114: #define POWERPC_MMU_64 0x00010000
115: /* 64 bits PowerPC MMU */
116: POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
117: /* 620 variant (no segment exceptions) */
118: POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
119: #endif /* defined(TARGET_PPC64) */
1.1 root 120: };
121:
1.1.1.4 root 122: /*****************************************************************************/
123: /* Exception model */
124: typedef enum powerpc_excp_t powerpc_excp_t;
125: enum powerpc_excp_t {
126: POWERPC_EXCP_UNKNOWN = 0,
127: /* Standard PowerPC exception model */
128: POWERPC_EXCP_STD,
129: /* PowerPC 40x exception model */
130: POWERPC_EXCP_40x,
131: /* PowerPC 601 exception model */
132: POWERPC_EXCP_601,
133: /* PowerPC 602 exception model */
134: POWERPC_EXCP_602,
135: /* PowerPC 603 exception model */
136: POWERPC_EXCP_603,
137: /* PowerPC 603e exception model */
138: POWERPC_EXCP_603E,
139: /* PowerPC G2 exception model */
140: POWERPC_EXCP_G2,
141: /* PowerPC 604 exception model */
142: POWERPC_EXCP_604,
143: /* PowerPC 7x0 exception model */
144: POWERPC_EXCP_7x0,
145: /* PowerPC 7x5 exception model */
146: POWERPC_EXCP_7x5,
147: /* PowerPC 74xx exception model */
148: POWERPC_EXCP_74xx,
149: /* BookE exception model */
150: POWERPC_EXCP_BOOKE,
151: #if defined(TARGET_PPC64)
152: /* PowerPC 970 exception model */
153: POWERPC_EXCP_970,
154: #endif /* defined(TARGET_PPC64) */
1.1 root 155: };
156:
157: /*****************************************************************************/
1.1.1.4 root 158: /* Exception vectors definitions */
1.1 root 159: enum {
1.1.1.4 root 160: POWERPC_EXCP_NONE = -1,
161: /* The 64 first entries are used by the PowerPC embedded specification */
162: POWERPC_EXCP_CRITICAL = 0, /* Critical input */
163: POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
164: POWERPC_EXCP_DSI = 2, /* Data storage exception */
165: POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
166: POWERPC_EXCP_EXTERNAL = 4, /* External input */
167: POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
168: POWERPC_EXCP_PROGRAM = 6, /* Program exception */
169: POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
170: POWERPC_EXCP_SYSCALL = 8, /* System call exception */
171: POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
172: POWERPC_EXCP_DECR = 10, /* Decrementer exception */
173: POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
174: POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
175: POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
176: POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
177: POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
178: /* Vectors 16 to 31 are reserved */
179: POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
180: POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
181: POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
182: POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
183: POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
184: POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
185: /* Vectors 38 to 63 are reserved */
186: /* Exceptions defined in the PowerPC server specification */
187: POWERPC_EXCP_RESET = 64, /* System reset exception */
188: POWERPC_EXCP_DSEG = 65, /* Data segment exception */
189: POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
190: POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
191: POWERPC_EXCP_TRACE = 68, /* Trace exception */
192: POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
193: POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
194: POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
195: POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
196: POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
197: /* 40x specific exceptions */
198: POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
199: /* 601 specific exceptions */
200: POWERPC_EXCP_IO = 75, /* IO error exception */
201: POWERPC_EXCP_RUNM = 76, /* Run mode exception */
202: /* 602 specific exceptions */
203: POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
204: /* 602/603 specific exceptions */
205: POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
206: POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
207: POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
208: /* Exceptions available on most PowerPC */
209: POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
210: POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
211: POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
212: POWERPC_EXCP_SMI = 84, /* System management interrupt */
213: POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
214: /* 7xx/74xx specific exceptions */
215: POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
216: /* 74xx specific exceptions */
217: POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
218: /* 970FX specific exceptions */
219: POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
220: POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
221: /* Freescale embeded cores specific exceptions */
222: POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
223: POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
224: POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
225: POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
226: /* EOL */
227: POWERPC_EXCP_NB = 96,
228: /* Qemu exceptions: used internally during code translation */
229: POWERPC_EXCP_STOP = 0x200, /* stop translation */
230: POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
231: /* Qemu exceptions: special cases we want to stop translation */
232: POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
233: POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
1.1.1.7 root 234: POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
1.1 root 235: };
236:
1.1.1.4 root 237: /* Exceptions error codes */
1.1 root 238: enum {
1.1.1.4 root 239: /* Exception subtypes for POWERPC_EXCP_ALIGN */
240: POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
241: POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
242: POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
243: POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
244: POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
245: POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
246: /* Exception subtypes for POWERPC_EXCP_PROGRAM */
247: /* FP exceptions */
248: POWERPC_EXCP_FP = 0x10,
249: POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
250: POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
251: POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
252: POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
253: POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
254: POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
255: POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
256: POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
257: POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
258: POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
259: POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
260: POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
261: POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
262: /* Invalid instruction */
263: POWERPC_EXCP_INVAL = 0x20,
264: POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
265: POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
266: POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
267: POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
268: /* Privileged instruction */
269: POWERPC_EXCP_PRIV = 0x30,
270: POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
271: POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
272: /* Trap */
273: POWERPC_EXCP_TRAP = 0x40,
274: };
275:
276: /*****************************************************************************/
277: /* Input pins model */
278: typedef enum powerpc_input_t powerpc_input_t;
279: enum powerpc_input_t {
280: PPC_FLAGS_INPUT_UNKNOWN = 0,
281: /* PowerPC 6xx bus */
282: PPC_FLAGS_INPUT_6xx,
283: /* BookE bus */
284: PPC_FLAGS_INPUT_BookE,
285: /* PowerPC 405 bus */
286: PPC_FLAGS_INPUT_405,
287: /* PowerPC 970 bus */
288: PPC_FLAGS_INPUT_970,
289: /* PowerPC 401 bus */
290: PPC_FLAGS_INPUT_401,
291: /* Freescale RCPU bus */
292: PPC_FLAGS_INPUT_RCPU,
1.1 root 293: };
294:
1.1.1.4 root 295: #define PPC_INPUT(env) (env->bus_model)
1.1 root 296:
297: /*****************************************************************************/
298: typedef struct ppc_def_t ppc_def_t;
1.1.1.4 root 299: typedef struct opc_handler_t opc_handler_t;
1.1 root 300:
301: /*****************************************************************************/
302: /* Types used to describe some PowerPC registers */
303: typedef struct CPUPPCState CPUPPCState;
304: typedef struct ppc_tb_t ppc_tb_t;
305: typedef struct ppc_spr_t ppc_spr_t;
306: typedef struct ppc_dcr_t ppc_dcr_t;
1.1.1.4 root 307: typedef union ppc_avr_t ppc_avr_t;
308: typedef union ppc_tlb_t ppc_tlb_t;
1.1 root 309:
310: /* SPR access micro-ops generations callbacks */
311: struct ppc_spr_t {
1.1.1.5 root 312: void (*uea_read)(void *opaque, int gpr_num, int spr_num);
313: void (*uea_write)(void *opaque, int spr_num, int gpr_num);
1.1.1.4 root 314: #if !defined(CONFIG_USER_ONLY)
1.1.1.5 root 315: void (*oea_read)(void *opaque, int gpr_num, int spr_num);
316: void (*oea_write)(void *opaque, int spr_num, int gpr_num);
317: void (*hea_read)(void *opaque, int gpr_num, int spr_num);
318: void (*hea_write)(void *opaque, int spr_num, int gpr_num);
1.1.1.4 root 319: #endif
1.1.1.5 root 320: const char *name;
1.1 root 321: };
322:
323: /* Altivec registers (128 bits) */
1.1.1.4 root 324: union ppc_avr_t {
1.1.1.5 root 325: float32 f[4];
1.1.1.4 root 326: uint8_t u8[16];
327: uint16_t u16[8];
328: uint32_t u32[4];
1.1.1.5 root 329: int8_t s8[16];
330: int16_t s16[8];
331: int32_t s32[4];
1.1.1.4 root 332: uint64_t u64[2];
1.1 root 333: };
334:
1.1.1.8 root 335: #if !defined(CONFIG_USER_ONLY)
1.1 root 336: /* Software TLB cache */
1.1.1.4 root 337: typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
338: struct ppc6xx_tlb_t {
339: target_ulong pte0;
340: target_ulong pte1;
341: target_ulong EPN;
342: };
343:
344: typedef struct ppcemb_tlb_t ppcemb_tlb_t;
345: struct ppcemb_tlb_t {
1.1 root 346: target_phys_addr_t RPN;
1.1.1.4 root 347: target_ulong EPN;
348: target_ulong PID;
1.1 root 349: target_ulong size;
1.1.1.4 root 350: uint32_t prot;
351: uint32_t attr; /* Storage attributes */
352: };
353:
354: union ppc_tlb_t {
355: ppc6xx_tlb_t tlb6;
356: ppcemb_tlb_t tlbe;
1.1 root 357: };
1.1.1.8 root 358: #endif
1.1 root 359:
1.1.1.6 root 360: typedef struct ppc_slb_t ppc_slb_t;
361: struct ppc_slb_t {
362: uint64_t tmp64;
363: uint32_t tmp;
364: };
365:
1.1 root 366: /*****************************************************************************/
367: /* Machine state register bits definition */
1.1.1.4 root 368: #define MSR_SF 63 /* Sixty-four-bit mode hflags */
369: #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
1.1 root 370: #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
1.1.1.4 root 371: #define MSR_SHV 60 /* hypervisor state hflags */
372: #define MSR_CM 31 /* Computation mode for BookE hflags */
373: #define MSR_ICM 30 /* Interrupt computation mode for BookE */
374: #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
375: #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
376: #define MSR_VR 25 /* altivec available x hflags */
377: #define MSR_SPE 25 /* SPE enable for BookE x hflags */
378: #define MSR_AP 23 /* Access privilege state on 602 hflags */
379: #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
1.1 root 380: #define MSR_KEY 19 /* key bit on 603e */
381: #define MSR_POW 18 /* Power management */
1.1.1.4 root 382: #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
383: #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
1.1 root 384: #define MSR_ILE 16 /* Interrupt little-endian mode */
385: #define MSR_EE 15 /* External interrupt enable */
1.1.1.4 root 386: #define MSR_PR 14 /* Problem state hflags */
387: #define MSR_FP 13 /* Floating point available hflags */
1.1 root 388: #define MSR_ME 12 /* Machine check interrupt enable */
1.1.1.4 root 389: #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
390: #define MSR_SE 10 /* Single-step trace enable x hflags */
391: #define MSR_DWE 10 /* Debug wait enable on 405 x */
392: #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
393: #define MSR_BE 9 /* Branch trace enable x hflags */
394: #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
395: #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
1.1 root 396: #define MSR_AL 7 /* AL bit on POWER */
1.1.1.4 root 397: #define MSR_EP 6 /* Exception prefix on 601 */
1.1 root 398: #define MSR_IR 5 /* Instruction relocate */
399: #define MSR_DR 4 /* Data relocate */
400: #define MSR_PE 3 /* Protection enable on 403 */
1.1.1.4 root 401: #define MSR_PX 2 /* Protection exclusive on 403 x */
402: #define MSR_PMM 2 /* Performance monitor mark on POWER x */
403: #define MSR_RI 1 /* Recoverable interrupt 1 */
404: #define MSR_LE 0 /* Little-endian mode 1 hflags */
405:
406: #define msr_sf ((env->msr >> MSR_SF) & 1)
407: #define msr_isf ((env->msr >> MSR_ISF) & 1)
408: #define msr_shv ((env->msr >> MSR_SHV) & 1)
409: #define msr_cm ((env->msr >> MSR_CM) & 1)
410: #define msr_icm ((env->msr >> MSR_ICM) & 1)
411: #define msr_thv ((env->msr >> MSR_THV) & 1)
412: #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
413: #define msr_vr ((env->msr >> MSR_VR) & 1)
1.1.1.5 root 414: #define msr_spe ((env->msr >> MSR_SPE) & 1)
1.1.1.4 root 415: #define msr_ap ((env->msr >> MSR_AP) & 1)
416: #define msr_sa ((env->msr >> MSR_SA) & 1)
417: #define msr_key ((env->msr >> MSR_KEY) & 1)
418: #define msr_pow ((env->msr >> MSR_POW) & 1)
419: #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
420: #define msr_ce ((env->msr >> MSR_CE) & 1)
421: #define msr_ile ((env->msr >> MSR_ILE) & 1)
422: #define msr_ee ((env->msr >> MSR_EE) & 1)
423: #define msr_pr ((env->msr >> MSR_PR) & 1)
424: #define msr_fp ((env->msr >> MSR_FP) & 1)
425: #define msr_me ((env->msr >> MSR_ME) & 1)
426: #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
427: #define msr_se ((env->msr >> MSR_SE) & 1)
428: #define msr_dwe ((env->msr >> MSR_DWE) & 1)
429: #define msr_uble ((env->msr >> MSR_UBLE) & 1)
430: #define msr_be ((env->msr >> MSR_BE) & 1)
431: #define msr_de ((env->msr >> MSR_DE) & 1)
432: #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
433: #define msr_al ((env->msr >> MSR_AL) & 1)
434: #define msr_ep ((env->msr >> MSR_EP) & 1)
435: #define msr_ir ((env->msr >> MSR_IR) & 1)
436: #define msr_dr ((env->msr >> MSR_DR) & 1)
437: #define msr_pe ((env->msr >> MSR_PE) & 1)
438: #define msr_px ((env->msr >> MSR_PX) & 1)
439: #define msr_pmm ((env->msr >> MSR_PMM) & 1)
440: #define msr_ri ((env->msr >> MSR_RI) & 1)
441: #define msr_le ((env->msr >> MSR_LE) & 1)
442: /* Hypervisor bit is more specific */
443: #if defined(TARGET_PPC64)
444: #define MSR_HVB (1ULL << MSR_SHV)
445: #define msr_hv msr_shv
446: #else
447: #if defined(PPC_EMULATE_32BITS_HYPV)
448: #define MSR_HVB (1ULL << MSR_THV)
449: #define msr_hv msr_thv
450: #else
451: #define MSR_HVB (0ULL)
452: #define msr_hv (0)
453: #endif
454: #endif
455:
1.1.1.9 ! root 456: /* Exception state register bits definition */
! 457: #define ESR_ST 23 /* Exception was caused by a store type access. */
! 458:
1.1.1.4 root 459: enum {
460: POWERPC_FLAG_NONE = 0x00000000,
461: /* Flag for MSR bit 25 signification (VRE/SPE) */
462: POWERPC_FLAG_SPE = 0x00000001,
463: POWERPC_FLAG_VRE = 0x00000002,
464: /* Flag for MSR bit 17 signification (TGPR/CE) */
465: POWERPC_FLAG_TGPR = 0x00000004,
466: POWERPC_FLAG_CE = 0x00000008,
467: /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
468: POWERPC_FLAG_SE = 0x00000010,
469: POWERPC_FLAG_DWE = 0x00000020,
470: POWERPC_FLAG_UBLE = 0x00000040,
471: /* Flag for MSR bit 9 signification (BE/DE) */
472: POWERPC_FLAG_BE = 0x00000080,
473: POWERPC_FLAG_DE = 0x00000100,
474: /* Flag for MSR bit 2 signification (PX/PMM) */
475: POWERPC_FLAG_PX = 0x00000200,
476: POWERPC_FLAG_PMM = 0x00000400,
477: /* Flag for special features */
478: /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
479: POWERPC_FLAG_RTC_CLK = 0x00010000,
480: POWERPC_FLAG_BUS_CLK = 0x00020000,
481: };
482:
483: /*****************************************************************************/
484: /* Floating point status and control register */
485: #define FPSCR_FX 31 /* Floating-point exception summary */
486: #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
487: #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
488: #define FPSCR_OX 28 /* Floating-point overflow exception */
489: #define FPSCR_UX 27 /* Floating-point underflow exception */
490: #define FPSCR_ZX 26 /* Floating-point zero divide exception */
491: #define FPSCR_XX 25 /* Floating-point inexact exception */
492: #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
493: #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
494: #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
495: #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
496: #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
497: #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
498: #define FPSCR_FR 18 /* Floating-point fraction rounded */
499: #define FPSCR_FI 17 /* Floating-point fraction inexact */
500: #define FPSCR_C 16 /* Floating-point result class descriptor */
501: #define FPSCR_FL 15 /* Floating-point less than or negative */
502: #define FPSCR_FG 14 /* Floating-point greater than or negative */
503: #define FPSCR_FE 13 /* Floating-point equal or zero */
504: #define FPSCR_FU 12 /* Floating-point unordered or NaN */
505: #define FPSCR_FPCC 12 /* Floating-point condition code */
506: #define FPSCR_FPRF 12 /* Floating-point result flags */
507: #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
508: #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
509: #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
510: #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
511: #define FPSCR_OE 6 /* Floating-point overflow exception enable */
512: #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
513: #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
514: #define FPSCR_XE 3 /* Floating-point inexact exception enable */
515: #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
516: #define FPSCR_RN1 1
517: #define FPSCR_RN 0 /* Floating-point rounding control */
518: #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
519: #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
520: #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
521: #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
522: #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
523: #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
524: #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
525: #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
526: #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
527: #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
528: #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
529: #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
530: #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
531: #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
532: #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
533: #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
534: #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
535: #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
536: #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
537: #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
538: #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
539: #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
540: #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
541: /* Invalid operation exception summary */
542: #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
543: (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
544: (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
545: (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
546: (1 << FPSCR_VXCVI)))
547: /* exception summary */
548: #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
549: /* enabled exception summary */
550: #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
551: 0x1F)
1.1 root 552:
553: /*****************************************************************************/
1.1.1.5 root 554: /* Vector status and control register */
555: #define VSCR_NJ 16 /* Vector non-java */
556: #define VSCR_SAT 0 /* Vector saturation */
557: #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
558: #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
559:
560: /*****************************************************************************/
1.1 root 561: /* The whole PowerPC CPU context */
1.1.1.4 root 562: #define NB_MMU_MODES 3
563:
1.1 root 564: struct CPUPPCState {
565: /* First are the most commonly used resources
566: * during translated code execution
567: */
568: /* general purpose registers */
1.1.1.5 root 569: target_ulong gpr[32];
1.1.1.4 root 570: #if !defined(TARGET_PPC64)
571: /* Storage for GPR MSB, used by the SPE extension */
1.1.1.5 root 572: target_ulong gprh[32];
1.1.1.4 root 573: #endif
1.1 root 574: /* LR */
575: target_ulong lr;
576: /* CTR */
577: target_ulong ctr;
578: /* condition register */
1.1.1.5 root 579: uint32_t crf[8];
1.1 root 580: /* XER */
1.1.1.5 root 581: target_ulong xer;
1.1 root 582: /* Reservation address */
1.1.1.7 root 583: target_ulong reserve_addr;
584: /* Reservation value */
585: target_ulong reserve_val;
586: /* Reservation store address */
587: target_ulong reserve_ea;
588: /* Reserved store source register and size */
589: target_ulong reserve_info;
1.1 root 590:
591: /* Those ones are used in supervisor mode only */
592: /* machine state register */
1.1.1.4 root 593: target_ulong msr;
1.1 root 594: /* temporary general purpose registers */
1.1.1.5 root 595: target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
1.1 root 596:
597: /* Floating point execution context */
598: float_status fp_status;
599: /* floating point registers */
600: float64 fpr[32];
601: /* floating point status and control register */
1.1.1.4 root 602: uint32_t fpscr;
1.1 root 603:
1.1.1.7 root 604: /* Next instruction pointer */
605: target_ulong nip;
1.1.1.2 root 606:
1.1 root 607: int access_type; /* when a memory exception occurs, the access
608: type is stored here */
609:
1.1.1.7 root 610: CPU_COMMON
611:
1.1.1.4 root 612: /* MMU context - only relevant for full system emulation */
613: #if !defined(CONFIG_USER_ONLY)
614: #if defined(TARGET_PPC64)
1.1 root 615: /* Address space register */
616: target_ulong asr;
1.1.1.4 root 617: /* PowerPC 64 SLB area */
1.1.1.6 root 618: ppc_slb_t slb[64];
1.1.1.4 root 619: int slb_nr;
620: #endif
1.1 root 621: /* segment registers */
622: target_ulong sdr1;
1.1.1.5 root 623: target_ulong sr[32];
1.1 root 624: /* BATs */
625: int nb_BATs;
626: target_ulong DBAT[2][8];
627: target_ulong IBAT[2][8];
1.1.1.4 root 628: /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
629: int nb_tlb; /* Total number of TLB */
630: int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
631: int nb_ways; /* Number of ways in the TLB set */
632: int last_way; /* Last used way used to allocate TLB in a LRU way */
633: int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
634: int nb_pids; /* Number of available PID registers */
635: ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
636: /* 403 dedicated access protection registers */
637: target_ulong pb[4];
638: #endif
1.1 root 639:
640: /* Other registers */
641: /* Special purpose registers */
642: target_ulong spr[1024];
1.1.1.4 root 643: ppc_spr_t spr_cb[1024];
1.1 root 644: /* Altivec registers */
645: ppc_avr_t avr[32];
646: uint32_t vscr;
1.1.1.4 root 647: /* SPE registers */
1.1.1.5 root 648: uint64_t spe_acc;
1.1.1.4 root 649: uint32_t spe_fscr;
1.1.1.5 root 650: /* SPE and Altivec can share a status since they will never be used
651: * simultaneously */
652: float_status vec_status;
1.1 root 653:
654: /* Internal devices resources */
655: /* Time base and decrementer */
656: ppc_tb_t *tb_env;
657: /* Device control registers */
658: ppc_dcr_t *dcr_env;
659:
1.1.1.4 root 660: int dcache_line_size;
661: int icache_line_size;
1.1 root 662:
663: /* Those resources are used during exception processing */
664: /* CPU model definition */
1.1.1.4 root 665: target_ulong msr_mask;
666: powerpc_mmu_t mmu_model;
667: powerpc_excp_t excp_model;
668: powerpc_input_t bus_model;
669: int bfd_mach;
1.1 root 670: uint32_t flags;
1.1.1.6 root 671: uint64_t insns_flags;
1.1 root 672:
673: int error_code;
1.1.1.4 root 674: uint32_t pending_interrupts;
675: #if !defined(CONFIG_USER_ONLY)
676: /* This is the IRQ controller, which is implementation dependant
677: * and only relevant when emulating a complete machine.
678: */
679: uint32_t irq_input_state;
680: void **irq_inputs;
681: /* Exception vectors */
682: target_ulong excp_vectors[POWERPC_EXCP_NB];
683: target_ulong excp_prefix;
1.1.1.6 root 684: target_ulong hreset_excp_prefix;
1.1.1.4 root 685: target_ulong ivor_mask;
686: target_ulong ivpr_mask;
687: target_ulong hreset_vector;
688: #endif
1.1 root 689:
690: /* Those resources are used only during code translation */
691: /* opcode handlers */
692: opc_handler_t *opcodes[0x40];
693:
694: /* Those resources are used only in Qemu core */
1.1.1.4 root 695: target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
696: target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
697: int mmu_idx; /* precomputed MMU index to speed up mem accesses */
1.1 root 698:
699: /* Power management */
700: int power_mode;
1.1.1.4 root 701: int (*check_pow)(CPUPPCState *env);
1.1 root 702:
1.1.1.9 ! root 703: #if !defined(CONFIG_USER_ONLY)
! 704: void *load_info; /* Holds boot loading state. */
! 705: #endif
1.1 root 706: };
707:
1.1.1.8 root 708: #if !defined(CONFIG_USER_ONLY)
1.1.1.4 root 709: /* Context used internally during MMU translations */
710: typedef struct mmu_ctx_t mmu_ctx_t;
711: struct mmu_ctx_t {
712: target_phys_addr_t raddr; /* Real address */
1.1.1.6 root 713: target_phys_addr_t eaddr; /* Effective address */
1.1.1.4 root 714: int prot; /* Protection bits */
715: target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
716: target_ulong ptem; /* Virtual segment ID | API */
717: int key; /* Access key */
718: int nx; /* Non-execute area */
719: };
1.1.1.8 root 720: #endif
1.1.1.4 root 721:
1.1 root 722: /*****************************************************************************/
1.1.1.4 root 723: CPUPPCState *cpu_ppc_init (const char *cpu_model);
1.1.1.5 root 724: void ppc_translate_init(void);
1.1.1.4 root 725: int cpu_ppc_exec (CPUPPCState *s);
726: void cpu_ppc_close (CPUPPCState *s);
1.1 root 727: /* you can call this signal handler from your SIGBUS and SIGSEGV
728: signal handlers to inform the virtual CPU of exceptions. non zero
729: is returned if the signal was handled by the virtual CPU. */
1.1.1.4 root 730: int cpu_ppc_signal_handler (int host_signum, void *pinfo,
731: void *puc);
1.1.1.5 root 732: int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
733: int mmu_idx, int is_softmmu);
1.1.1.7 root 734: #define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
1.1.1.8 root 735: #if !defined(CONFIG_USER_ONLY)
1.1.1.5 root 736: int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,
737: int rw, int access_type);
1.1.1.8 root 738: #endif
1.1 root 739: void do_interrupt (CPUPPCState *env);
1.1.1.4 root 740: void ppc_hw_interrupt (CPUPPCState *env);
1.1 root 741:
1.1.1.5 root 742: void cpu_dump_rfi (target_ulong RA, target_ulong msr);
1.1 root 743:
1.1.1.4 root 744: #if !defined(CONFIG_USER_ONLY)
1.1.1.5 root 745: void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code,
746: target_ulong pte0, target_ulong pte1);
747: void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
748: void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
749: void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
750: void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
751: void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
752: void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
753: void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1.1.1.4 root 754: #if defined(TARGET_PPC64)
755: void ppc_store_asr (CPUPPCState *env, target_ulong value);
756: target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
1.1.1.6 root 757: target_ulong ppc_load_sr (CPUPPCState *env, int sr_nr);
758: void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
1.1.1.4 root 759: #endif /* defined(TARGET_PPC64) */
1.1.1.5 root 760: void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value);
1.1.1.4 root 761: #endif /* !defined(CONFIG_USER_ONLY) */
762: void ppc_store_msr (CPUPPCState *env, target_ulong value);
1.1 root 763:
1.1.1.9 ! root 764: void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1.1.1.4 root 765:
1.1.1.5 root 766: const ppc_def_t *cpu_ppc_find_by_name (const char *name);
1.1.1.4 root 767: int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
1.1 root 768:
769: /* Time-base and decrementer management */
770: #ifndef NO_CPU_IO_DEFS
1.1.1.8 root 771: uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1.1 root 772: uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
773: void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
774: void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1.1.1.8 root 775: uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1.1.1.4 root 776: uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
777: void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
778: void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1.1 root 779: uint32_t cpu_ppc_load_decr (CPUPPCState *env);
780: void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1.1.1.4 root 781: uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
782: void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
783: uint64_t cpu_ppc_load_purr (CPUPPCState *env);
784: void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
785: uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
786: uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
787: #if !defined(CONFIG_USER_ONLY)
788: void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
789: void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
790: target_ulong load_40x_pit (CPUPPCState *env);
791: void store_40x_pit (CPUPPCState *env, target_ulong val);
792: void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
793: void store_40x_sler (CPUPPCState *env, uint32_t val);
794: void store_booke_tcr (CPUPPCState *env, target_ulong val);
795: void store_booke_tsr (CPUPPCState *env, target_ulong val);
796: void ppc_tlb_invalidate_all (CPUPPCState *env);
797: void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
798: #if defined(TARGET_PPC64)
799: void ppc_slb_invalidate_all (CPUPPCState *env);
800: void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
801: #endif
802: int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
803: #endif
1.1 root 804: #endif
805:
1.1.1.7 root 806: static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1.1.1.4 root 807: {
808: uint64_t gprv;
809:
810: gprv = env->gpr[gprn];
811: #if !defined(TARGET_PPC64)
812: if (env->flags & POWERPC_FLAG_SPE) {
813: /* If the CPU implements the SPE extension, we have to get the
814: * high bits of the GPR from the gprh storage area
815: */
816: gprv &= 0xFFFFFFFFULL;
817: gprv |= (uint64_t)env->gprh[gprn] << 32;
818: }
819: #endif
820:
821: return gprv;
822: }
823:
824: /* Device control registers */
1.1.1.8 root 825: int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
826: int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1.1.1.4 root 827:
828: #define cpu_init cpu_ppc_init
829: #define cpu_exec cpu_ppc_exec
830: #define cpu_gen_code cpu_ppc_gen_code
831: #define cpu_signal_handler cpu_ppc_signal_handler
832: #define cpu_list ppc_cpu_list
833:
1.1.1.6 root 834: #define CPU_SAVE_VERSION 4
1.1.1.5 root 835:
1.1.1.4 root 836: /* MMU modes definitions */
837: #define MMU_MODE0_SUFFIX _user
838: #define MMU_MODE1_SUFFIX _kernel
839: #define MMU_MODE2_SUFFIX _hypv
840: #define MMU_USER_IDX 0
841: static inline int cpu_mmu_index (CPUState *env)
842: {
843: return env->mmu_idx;
844: }
845:
1.1.1.5 root 846: #if defined(CONFIG_USER_ONLY)
847: static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
848: {
849: if (newsp)
850: env->gpr[1] = newsp;
1.1.1.7 root 851: env->gpr[3] = 0;
1.1.1.5 root 852: }
853: #endif
854:
1.1 root 855: #include "cpu-all.h"
856:
857: /*****************************************************************************/
1.1.1.5 root 858: /* CRF definitions */
859: #define CRF_LT 3
860: #define CRF_GT 2
861: #define CRF_EQ 1
862: #define CRF_SO 0
1.1.1.8 root 863: #define CRF_CH (1 << CRF_LT)
864: #define CRF_CL (1 << CRF_GT)
865: #define CRF_CH_OR_CL (1 << CRF_EQ)
866: #define CRF_CH_AND_CL (1 << CRF_SO)
1.1.1.5 root 867:
868: /* XER definitions */
869: #define XER_SO 31
870: #define XER_OV 30
871: #define XER_CA 29
872: #define XER_CMP 8
873: #define XER_BC 0
874: #define xer_so ((env->xer >> XER_SO) & 1)
875: #define xer_ov ((env->xer >> XER_OV) & 1)
876: #define xer_ca ((env->xer >> XER_CA) & 1)
877: #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
878: #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1.1 root 879:
880: /* SPR definitions */
1.1.1.4 root 881: #define SPR_MQ (0x000)
882: #define SPR_XER (0x001)
883: #define SPR_601_VRTCU (0x004)
884: #define SPR_601_VRTCL (0x005)
885: #define SPR_601_UDECR (0x006)
886: #define SPR_LR (0x008)
887: #define SPR_CTR (0x009)
888: #define SPR_DSISR (0x012)
889: #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
890: #define SPR_601_RTCU (0x014)
891: #define SPR_601_RTCL (0x015)
892: #define SPR_DECR (0x016)
893: #define SPR_SDR1 (0x019)
894: #define SPR_SRR0 (0x01A)
895: #define SPR_SRR1 (0x01B)
896: #define SPR_AMR (0x01D)
897: #define SPR_BOOKE_PID (0x030)
898: #define SPR_BOOKE_DECAR (0x036)
899: #define SPR_BOOKE_CSRR0 (0x03A)
900: #define SPR_BOOKE_CSRR1 (0x03B)
901: #define SPR_BOOKE_DEAR (0x03D)
902: #define SPR_BOOKE_ESR (0x03E)
903: #define SPR_BOOKE_IVPR (0x03F)
904: #define SPR_MPC_EIE (0x050)
905: #define SPR_MPC_EID (0x051)
906: #define SPR_MPC_NRI (0x052)
907: #define SPR_CTRL (0x088)
908: #define SPR_MPC_CMPA (0x090)
909: #define SPR_MPC_CMPB (0x091)
910: #define SPR_MPC_CMPC (0x092)
911: #define SPR_MPC_CMPD (0x093)
912: #define SPR_MPC_ECR (0x094)
913: #define SPR_MPC_DER (0x095)
914: #define SPR_MPC_COUNTA (0x096)
915: #define SPR_MPC_COUNTB (0x097)
916: #define SPR_UCTRL (0x098)
917: #define SPR_MPC_CMPE (0x098)
918: #define SPR_MPC_CMPF (0x099)
919: #define SPR_MPC_CMPG (0x09A)
920: #define SPR_MPC_CMPH (0x09B)
921: #define SPR_MPC_LCTRL1 (0x09C)
922: #define SPR_MPC_LCTRL2 (0x09D)
923: #define SPR_MPC_ICTRL (0x09E)
924: #define SPR_MPC_BAR (0x09F)
925: #define SPR_VRSAVE (0x100)
926: #define SPR_USPRG0 (0x100)
927: #define SPR_USPRG1 (0x101)
928: #define SPR_USPRG2 (0x102)
929: #define SPR_USPRG3 (0x103)
930: #define SPR_USPRG4 (0x104)
931: #define SPR_USPRG5 (0x105)
932: #define SPR_USPRG6 (0x106)
933: #define SPR_USPRG7 (0x107)
934: #define SPR_VTBL (0x10C)
935: #define SPR_VTBU (0x10D)
936: #define SPR_SPRG0 (0x110)
937: #define SPR_SPRG1 (0x111)
938: #define SPR_SPRG2 (0x112)
939: #define SPR_SPRG3 (0x113)
940: #define SPR_SPRG4 (0x114)
941: #define SPR_SCOMC (0x114)
942: #define SPR_SPRG5 (0x115)
943: #define SPR_SCOMD (0x115)
944: #define SPR_SPRG6 (0x116)
945: #define SPR_SPRG7 (0x117)
946: #define SPR_ASR (0x118)
947: #define SPR_EAR (0x11A)
948: #define SPR_TBL (0x11C)
949: #define SPR_TBU (0x11D)
950: #define SPR_TBU40 (0x11E)
951: #define SPR_SVR (0x11E)
952: #define SPR_BOOKE_PIR (0x11E)
953: #define SPR_PVR (0x11F)
954: #define SPR_HSPRG0 (0x130)
955: #define SPR_BOOKE_DBSR (0x130)
956: #define SPR_HSPRG1 (0x131)
957: #define SPR_HDSISR (0x132)
958: #define SPR_HDAR (0x133)
959: #define SPR_BOOKE_DBCR0 (0x134)
960: #define SPR_IBCR (0x135)
961: #define SPR_PURR (0x135)
962: #define SPR_BOOKE_DBCR1 (0x135)
963: #define SPR_DBCR (0x136)
964: #define SPR_HDEC (0x136)
965: #define SPR_BOOKE_DBCR2 (0x136)
966: #define SPR_HIOR (0x137)
967: #define SPR_MBAR (0x137)
968: #define SPR_RMOR (0x138)
969: #define SPR_BOOKE_IAC1 (0x138)
970: #define SPR_HRMOR (0x139)
971: #define SPR_BOOKE_IAC2 (0x139)
972: #define SPR_HSRR0 (0x13A)
973: #define SPR_BOOKE_IAC3 (0x13A)
974: #define SPR_HSRR1 (0x13B)
975: #define SPR_BOOKE_IAC4 (0x13B)
976: #define SPR_LPCR (0x13C)
977: #define SPR_BOOKE_DAC1 (0x13C)
978: #define SPR_LPIDR (0x13D)
979: #define SPR_DABR2 (0x13D)
980: #define SPR_BOOKE_DAC2 (0x13D)
981: #define SPR_BOOKE_DVC1 (0x13E)
982: #define SPR_BOOKE_DVC2 (0x13F)
983: #define SPR_BOOKE_TSR (0x150)
984: #define SPR_BOOKE_TCR (0x154)
985: #define SPR_BOOKE_IVOR0 (0x190)
986: #define SPR_BOOKE_IVOR1 (0x191)
987: #define SPR_BOOKE_IVOR2 (0x192)
988: #define SPR_BOOKE_IVOR3 (0x193)
989: #define SPR_BOOKE_IVOR4 (0x194)
990: #define SPR_BOOKE_IVOR5 (0x195)
991: #define SPR_BOOKE_IVOR6 (0x196)
992: #define SPR_BOOKE_IVOR7 (0x197)
993: #define SPR_BOOKE_IVOR8 (0x198)
994: #define SPR_BOOKE_IVOR9 (0x199)
995: #define SPR_BOOKE_IVOR10 (0x19A)
996: #define SPR_BOOKE_IVOR11 (0x19B)
997: #define SPR_BOOKE_IVOR12 (0x19C)
998: #define SPR_BOOKE_IVOR13 (0x19D)
999: #define SPR_BOOKE_IVOR14 (0x19E)
1000: #define SPR_BOOKE_IVOR15 (0x19F)
1001: #define SPR_BOOKE_SPEFSCR (0x200)
1002: #define SPR_Exxx_BBEAR (0x201)
1003: #define SPR_Exxx_BBTAR (0x202)
1004: #define SPR_Exxx_L1CFG0 (0x203)
1005: #define SPR_Exxx_NPIDR (0x205)
1006: #define SPR_ATBL (0x20E)
1007: #define SPR_ATBU (0x20F)
1008: #define SPR_IBAT0U (0x210)
1009: #define SPR_BOOKE_IVOR32 (0x210)
1010: #define SPR_RCPU_MI_GRA (0x210)
1011: #define SPR_IBAT0L (0x211)
1012: #define SPR_BOOKE_IVOR33 (0x211)
1013: #define SPR_IBAT1U (0x212)
1014: #define SPR_BOOKE_IVOR34 (0x212)
1015: #define SPR_IBAT1L (0x213)
1016: #define SPR_BOOKE_IVOR35 (0x213)
1017: #define SPR_IBAT2U (0x214)
1018: #define SPR_BOOKE_IVOR36 (0x214)
1019: #define SPR_IBAT2L (0x215)
1020: #define SPR_BOOKE_IVOR37 (0x215)
1021: #define SPR_IBAT3U (0x216)
1022: #define SPR_IBAT3L (0x217)
1023: #define SPR_DBAT0U (0x218)
1024: #define SPR_RCPU_L2U_GRA (0x218)
1025: #define SPR_DBAT0L (0x219)
1026: #define SPR_DBAT1U (0x21A)
1027: #define SPR_DBAT1L (0x21B)
1028: #define SPR_DBAT2U (0x21C)
1029: #define SPR_DBAT2L (0x21D)
1030: #define SPR_DBAT3U (0x21E)
1031: #define SPR_DBAT3L (0x21F)
1032: #define SPR_IBAT4U (0x230)
1033: #define SPR_RPCU_BBCMCR (0x230)
1034: #define SPR_MPC_IC_CST (0x230)
1035: #define SPR_Exxx_CTXCR (0x230)
1036: #define SPR_IBAT4L (0x231)
1037: #define SPR_MPC_IC_ADR (0x231)
1038: #define SPR_Exxx_DBCR3 (0x231)
1039: #define SPR_IBAT5U (0x232)
1040: #define SPR_MPC_IC_DAT (0x232)
1041: #define SPR_Exxx_DBCNT (0x232)
1042: #define SPR_IBAT5L (0x233)
1043: #define SPR_IBAT6U (0x234)
1044: #define SPR_IBAT6L (0x235)
1045: #define SPR_IBAT7U (0x236)
1046: #define SPR_IBAT7L (0x237)
1047: #define SPR_DBAT4U (0x238)
1048: #define SPR_RCPU_L2U_MCR (0x238)
1049: #define SPR_MPC_DC_CST (0x238)
1050: #define SPR_Exxx_ALTCTXCR (0x238)
1051: #define SPR_DBAT4L (0x239)
1052: #define SPR_MPC_DC_ADR (0x239)
1053: #define SPR_DBAT5U (0x23A)
1054: #define SPR_BOOKE_MCSRR0 (0x23A)
1055: #define SPR_MPC_DC_DAT (0x23A)
1056: #define SPR_DBAT5L (0x23B)
1057: #define SPR_BOOKE_MCSRR1 (0x23B)
1058: #define SPR_DBAT6U (0x23C)
1059: #define SPR_BOOKE_MCSR (0x23C)
1060: #define SPR_DBAT6L (0x23D)
1061: #define SPR_Exxx_MCAR (0x23D)
1062: #define SPR_DBAT7U (0x23E)
1063: #define SPR_BOOKE_DSRR0 (0x23E)
1064: #define SPR_DBAT7L (0x23F)
1065: #define SPR_BOOKE_DSRR1 (0x23F)
1066: #define SPR_BOOKE_SPRG8 (0x25C)
1067: #define SPR_BOOKE_SPRG9 (0x25D)
1068: #define SPR_BOOKE_MAS0 (0x270)
1069: #define SPR_BOOKE_MAS1 (0x271)
1070: #define SPR_BOOKE_MAS2 (0x272)
1071: #define SPR_BOOKE_MAS3 (0x273)
1072: #define SPR_BOOKE_MAS4 (0x274)
1073: #define SPR_BOOKE_MAS5 (0x275)
1074: #define SPR_BOOKE_MAS6 (0x276)
1075: #define SPR_BOOKE_PID1 (0x279)
1076: #define SPR_BOOKE_PID2 (0x27A)
1077: #define SPR_MPC_DPDR (0x280)
1078: #define SPR_MPC_IMMR (0x288)
1079: #define SPR_BOOKE_TLB0CFG (0x2B0)
1080: #define SPR_BOOKE_TLB1CFG (0x2B1)
1081: #define SPR_BOOKE_TLB2CFG (0x2B2)
1082: #define SPR_BOOKE_TLB3CFG (0x2B3)
1083: #define SPR_BOOKE_EPR (0x2BE)
1084: #define SPR_PERF0 (0x300)
1085: #define SPR_RCPU_MI_RBA0 (0x300)
1086: #define SPR_MPC_MI_CTR (0x300)
1087: #define SPR_PERF1 (0x301)
1088: #define SPR_RCPU_MI_RBA1 (0x301)
1089: #define SPR_PERF2 (0x302)
1090: #define SPR_RCPU_MI_RBA2 (0x302)
1091: #define SPR_MPC_MI_AP (0x302)
1092: #define SPR_PERF3 (0x303)
1093: #define SPR_620_PMC1R (0x303)
1094: #define SPR_RCPU_MI_RBA3 (0x303)
1095: #define SPR_MPC_MI_EPN (0x303)
1096: #define SPR_PERF4 (0x304)
1097: #define SPR_620_PMC2R (0x304)
1098: #define SPR_PERF5 (0x305)
1099: #define SPR_MPC_MI_TWC (0x305)
1100: #define SPR_PERF6 (0x306)
1101: #define SPR_MPC_MI_RPN (0x306)
1102: #define SPR_PERF7 (0x307)
1103: #define SPR_PERF8 (0x308)
1104: #define SPR_RCPU_L2U_RBA0 (0x308)
1105: #define SPR_MPC_MD_CTR (0x308)
1106: #define SPR_PERF9 (0x309)
1107: #define SPR_RCPU_L2U_RBA1 (0x309)
1108: #define SPR_MPC_MD_CASID (0x309)
1109: #define SPR_PERFA (0x30A)
1110: #define SPR_RCPU_L2U_RBA2 (0x30A)
1111: #define SPR_MPC_MD_AP (0x30A)
1112: #define SPR_PERFB (0x30B)
1113: #define SPR_620_MMCR0R (0x30B)
1114: #define SPR_RCPU_L2U_RBA3 (0x30B)
1115: #define SPR_MPC_MD_EPN (0x30B)
1116: #define SPR_PERFC (0x30C)
1117: #define SPR_MPC_MD_TWB (0x30C)
1118: #define SPR_PERFD (0x30D)
1119: #define SPR_MPC_MD_TWC (0x30D)
1120: #define SPR_PERFE (0x30E)
1121: #define SPR_MPC_MD_RPN (0x30E)
1122: #define SPR_PERFF (0x30F)
1123: #define SPR_MPC_MD_TW (0x30F)
1124: #define SPR_UPERF0 (0x310)
1125: #define SPR_UPERF1 (0x311)
1126: #define SPR_UPERF2 (0x312)
1127: #define SPR_UPERF3 (0x313)
1128: #define SPR_620_PMC1W (0x313)
1129: #define SPR_UPERF4 (0x314)
1130: #define SPR_620_PMC2W (0x314)
1131: #define SPR_UPERF5 (0x315)
1132: #define SPR_UPERF6 (0x316)
1133: #define SPR_UPERF7 (0x317)
1134: #define SPR_UPERF8 (0x318)
1135: #define SPR_UPERF9 (0x319)
1136: #define SPR_UPERFA (0x31A)
1137: #define SPR_UPERFB (0x31B)
1138: #define SPR_620_MMCR0W (0x31B)
1139: #define SPR_UPERFC (0x31C)
1140: #define SPR_UPERFD (0x31D)
1141: #define SPR_UPERFE (0x31E)
1142: #define SPR_UPERFF (0x31F)
1143: #define SPR_RCPU_MI_RA0 (0x320)
1144: #define SPR_MPC_MI_DBCAM (0x320)
1145: #define SPR_RCPU_MI_RA1 (0x321)
1146: #define SPR_MPC_MI_DBRAM0 (0x321)
1147: #define SPR_RCPU_MI_RA2 (0x322)
1148: #define SPR_MPC_MI_DBRAM1 (0x322)
1149: #define SPR_RCPU_MI_RA3 (0x323)
1150: #define SPR_RCPU_L2U_RA0 (0x328)
1151: #define SPR_MPC_MD_DBCAM (0x328)
1152: #define SPR_RCPU_L2U_RA1 (0x329)
1153: #define SPR_MPC_MD_DBRAM0 (0x329)
1154: #define SPR_RCPU_L2U_RA2 (0x32A)
1155: #define SPR_MPC_MD_DBRAM1 (0x32A)
1156: #define SPR_RCPU_L2U_RA3 (0x32B)
1157: #define SPR_440_INV0 (0x370)
1158: #define SPR_440_INV1 (0x371)
1159: #define SPR_440_INV2 (0x372)
1160: #define SPR_440_INV3 (0x373)
1161: #define SPR_440_ITV0 (0x374)
1162: #define SPR_440_ITV1 (0x375)
1163: #define SPR_440_ITV2 (0x376)
1164: #define SPR_440_ITV3 (0x377)
1165: #define SPR_440_CCR1 (0x378)
1166: #define SPR_DCRIPR (0x37B)
1167: #define SPR_PPR (0x380)
1168: #define SPR_750_GQR0 (0x390)
1169: #define SPR_440_DNV0 (0x390)
1170: #define SPR_750_GQR1 (0x391)
1171: #define SPR_440_DNV1 (0x391)
1172: #define SPR_750_GQR2 (0x392)
1173: #define SPR_440_DNV2 (0x392)
1174: #define SPR_750_GQR3 (0x393)
1175: #define SPR_440_DNV3 (0x393)
1176: #define SPR_750_GQR4 (0x394)
1177: #define SPR_440_DTV0 (0x394)
1178: #define SPR_750_GQR5 (0x395)
1179: #define SPR_440_DTV1 (0x395)
1180: #define SPR_750_GQR6 (0x396)
1181: #define SPR_440_DTV2 (0x396)
1182: #define SPR_750_GQR7 (0x397)
1183: #define SPR_440_DTV3 (0x397)
1184: #define SPR_750_THRM4 (0x398)
1185: #define SPR_750CL_HID2 (0x398)
1186: #define SPR_440_DVLIM (0x398)
1187: #define SPR_750_WPAR (0x399)
1188: #define SPR_440_IVLIM (0x399)
1189: #define SPR_750_DMAU (0x39A)
1190: #define SPR_750_DMAL (0x39B)
1191: #define SPR_440_RSTCFG (0x39B)
1192: #define SPR_BOOKE_DCDBTRL (0x39C)
1193: #define SPR_BOOKE_DCDBTRH (0x39D)
1194: #define SPR_BOOKE_ICDBTRL (0x39E)
1195: #define SPR_BOOKE_ICDBTRH (0x39F)
1196: #define SPR_UMMCR2 (0x3A0)
1197: #define SPR_UPMC5 (0x3A1)
1198: #define SPR_UPMC6 (0x3A2)
1199: #define SPR_UBAMR (0x3A7)
1200: #define SPR_UMMCR0 (0x3A8)
1201: #define SPR_UPMC1 (0x3A9)
1202: #define SPR_UPMC2 (0x3AA)
1203: #define SPR_USIAR (0x3AB)
1204: #define SPR_UMMCR1 (0x3AC)
1205: #define SPR_UPMC3 (0x3AD)
1206: #define SPR_UPMC4 (0x3AE)
1207: #define SPR_USDA (0x3AF)
1208: #define SPR_40x_ZPR (0x3B0)
1209: #define SPR_BOOKE_MAS7 (0x3B0)
1210: #define SPR_620_PMR0 (0x3B0)
1211: #define SPR_MMCR2 (0x3B0)
1212: #define SPR_PMC5 (0x3B1)
1213: #define SPR_40x_PID (0x3B1)
1214: #define SPR_620_PMR1 (0x3B1)
1215: #define SPR_PMC6 (0x3B2)
1216: #define SPR_440_MMUCR (0x3B2)
1217: #define SPR_620_PMR2 (0x3B2)
1218: #define SPR_4xx_CCR0 (0x3B3)
1219: #define SPR_BOOKE_EPLC (0x3B3)
1220: #define SPR_620_PMR3 (0x3B3)
1221: #define SPR_405_IAC3 (0x3B4)
1222: #define SPR_BOOKE_EPSC (0x3B4)
1223: #define SPR_620_PMR4 (0x3B4)
1224: #define SPR_405_IAC4 (0x3B5)
1225: #define SPR_620_PMR5 (0x3B5)
1226: #define SPR_405_DVC1 (0x3B6)
1227: #define SPR_620_PMR6 (0x3B6)
1228: #define SPR_405_DVC2 (0x3B7)
1229: #define SPR_620_PMR7 (0x3B7)
1230: #define SPR_BAMR (0x3B7)
1231: #define SPR_MMCR0 (0x3B8)
1232: #define SPR_620_PMR8 (0x3B8)
1233: #define SPR_PMC1 (0x3B9)
1234: #define SPR_40x_SGR (0x3B9)
1235: #define SPR_620_PMR9 (0x3B9)
1236: #define SPR_PMC2 (0x3BA)
1237: #define SPR_40x_DCWR (0x3BA)
1238: #define SPR_620_PMRA (0x3BA)
1239: #define SPR_SIAR (0x3BB)
1240: #define SPR_405_SLER (0x3BB)
1241: #define SPR_620_PMRB (0x3BB)
1242: #define SPR_MMCR1 (0x3BC)
1243: #define SPR_405_SU0R (0x3BC)
1244: #define SPR_620_PMRC (0x3BC)
1245: #define SPR_401_SKR (0x3BC)
1246: #define SPR_PMC3 (0x3BD)
1247: #define SPR_405_DBCR1 (0x3BD)
1248: #define SPR_620_PMRD (0x3BD)
1249: #define SPR_PMC4 (0x3BE)
1250: #define SPR_620_PMRE (0x3BE)
1251: #define SPR_SDA (0x3BF)
1252: #define SPR_620_PMRF (0x3BF)
1253: #define SPR_403_VTBL (0x3CC)
1254: #define SPR_403_VTBU (0x3CD)
1255: #define SPR_DMISS (0x3D0)
1256: #define SPR_DCMP (0x3D1)
1257: #define SPR_HASH1 (0x3D2)
1258: #define SPR_HASH2 (0x3D3)
1259: #define SPR_BOOKE_ICDBDR (0x3D3)
1260: #define SPR_TLBMISS (0x3D4)
1261: #define SPR_IMISS (0x3D4)
1262: #define SPR_40x_ESR (0x3D4)
1263: #define SPR_PTEHI (0x3D5)
1264: #define SPR_ICMP (0x3D5)
1265: #define SPR_40x_DEAR (0x3D5)
1266: #define SPR_PTELO (0x3D6)
1267: #define SPR_RPA (0x3D6)
1268: #define SPR_40x_EVPR (0x3D6)
1269: #define SPR_L3PM (0x3D7)
1270: #define SPR_403_CDBCR (0x3D7)
1271: #define SPR_L3ITCR0 (0x3D8)
1272: #define SPR_TCR (0x3D8)
1273: #define SPR_40x_TSR (0x3D8)
1274: #define SPR_IBR (0x3DA)
1275: #define SPR_40x_TCR (0x3DA)
1276: #define SPR_ESASRR (0x3DB)
1277: #define SPR_40x_PIT (0x3DB)
1278: #define SPR_403_TBL (0x3DC)
1279: #define SPR_403_TBU (0x3DD)
1280: #define SPR_SEBR (0x3DE)
1281: #define SPR_40x_SRR2 (0x3DE)
1282: #define SPR_SER (0x3DF)
1283: #define SPR_40x_SRR3 (0x3DF)
1284: #define SPR_L3OHCR (0x3E8)
1285: #define SPR_L3ITCR1 (0x3E9)
1286: #define SPR_L3ITCR2 (0x3EA)
1287: #define SPR_L3ITCR3 (0x3EB)
1288: #define SPR_HID0 (0x3F0)
1289: #define SPR_40x_DBSR (0x3F0)
1290: #define SPR_HID1 (0x3F1)
1291: #define SPR_IABR (0x3F2)
1292: #define SPR_40x_DBCR0 (0x3F2)
1293: #define SPR_601_HID2 (0x3F2)
1294: #define SPR_Exxx_L1CSR0 (0x3F2)
1295: #define SPR_ICTRL (0x3F3)
1296: #define SPR_HID2 (0x3F3)
1297: #define SPR_750CL_HID4 (0x3F3)
1298: #define SPR_Exxx_L1CSR1 (0x3F3)
1299: #define SPR_440_DBDR (0x3F3)
1300: #define SPR_LDSTDB (0x3F4)
1301: #define SPR_750_TDCL (0x3F4)
1302: #define SPR_40x_IAC1 (0x3F4)
1303: #define SPR_MMUCSR0 (0x3F4)
1304: #define SPR_DABR (0x3F5)
1.1 root 1305: #define DABR_MASK (~(target_ulong)0x7)
1.1.1.4 root 1306: #define SPR_Exxx_BUCSR (0x3F5)
1307: #define SPR_40x_IAC2 (0x3F5)
1308: #define SPR_601_HID5 (0x3F5)
1309: #define SPR_40x_DAC1 (0x3F6)
1310: #define SPR_MSSCR0 (0x3F6)
1311: #define SPR_970_HID5 (0x3F6)
1312: #define SPR_MSSSR0 (0x3F7)
1313: #define SPR_MSSCR1 (0x3F7)
1314: #define SPR_DABRX (0x3F7)
1315: #define SPR_40x_DAC2 (0x3F7)
1316: #define SPR_MMUCFG (0x3F7)
1317: #define SPR_LDSTCR (0x3F8)
1318: #define SPR_L2PMCR (0x3F8)
1319: #define SPR_750FX_HID2 (0x3F8)
1320: #define SPR_620_BUSCSR (0x3F8)
1321: #define SPR_Exxx_L1FINV0 (0x3F8)
1322: #define SPR_L2CR (0x3F9)
1323: #define SPR_620_L2CR (0x3F9)
1324: #define SPR_L3CR (0x3FA)
1325: #define SPR_750_TDCH (0x3FA)
1326: #define SPR_IABR2 (0x3FA)
1327: #define SPR_40x_DCCR (0x3FA)
1328: #define SPR_620_L2SR (0x3FA)
1329: #define SPR_ICTC (0x3FB)
1330: #define SPR_40x_ICCR (0x3FB)
1331: #define SPR_THRM1 (0x3FC)
1332: #define SPR_403_PBL1 (0x3FC)
1333: #define SPR_SP (0x3FD)
1334: #define SPR_THRM2 (0x3FD)
1335: #define SPR_403_PBU1 (0x3FD)
1336: #define SPR_604_HID13 (0x3FD)
1337: #define SPR_LT (0x3FE)
1338: #define SPR_THRM3 (0x3FE)
1339: #define SPR_RCPU_FPECR (0x3FE)
1340: #define SPR_403_PBL2 (0x3FE)
1341: #define SPR_PIR (0x3FF)
1342: #define SPR_403_PBU2 (0x3FF)
1343: #define SPR_601_HID15 (0x3FF)
1344: #define SPR_604_HID15 (0x3FF)
1345: #define SPR_E500_SVR (0x3FF)
1.1 root 1346:
1.1.1.4 root 1347: /*****************************************************************************/
1.1.1.6 root 1348: /* PowerPC Instructions types definitions */
1349: enum {
1350: PPC_NONE = 0x0000000000000000ULL,
1351: /* PowerPC base instructions set */
1352: PPC_INSNS_BASE = 0x0000000000000001ULL,
1353: /* integer operations instructions */
1354: #define PPC_INTEGER PPC_INSNS_BASE
1355: /* flow control instructions */
1356: #define PPC_FLOW PPC_INSNS_BASE
1357: /* virtual memory instructions */
1358: #define PPC_MEM PPC_INSNS_BASE
1359: /* ld/st with reservation instructions */
1360: #define PPC_RES PPC_INSNS_BASE
1361: /* spr/msr access instructions */
1362: #define PPC_MISC PPC_INSNS_BASE
1363: /* Deprecated instruction sets */
1364: /* Original POWER instruction set */
1365: PPC_POWER = 0x0000000000000002ULL,
1366: /* POWER2 instruction set extension */
1367: PPC_POWER2 = 0x0000000000000004ULL,
1368: /* Power RTC support */
1369: PPC_POWER_RTC = 0x0000000000000008ULL,
1370: /* Power-to-PowerPC bridge (601) */
1371: PPC_POWER_BR = 0x0000000000000010ULL,
1372: /* 64 bits PowerPC instruction set */
1373: PPC_64B = 0x0000000000000020ULL,
1374: /* New 64 bits extensions (PowerPC 2.0x) */
1375: PPC_64BX = 0x0000000000000040ULL,
1376: /* 64 bits hypervisor extensions */
1377: PPC_64H = 0x0000000000000080ULL,
1378: /* New wait instruction (PowerPC 2.0x) */
1379: PPC_WAIT = 0x0000000000000100ULL,
1380: /* Time base mftb instruction */
1381: PPC_MFTB = 0x0000000000000200ULL,
1382:
1383: /* Fixed-point unit extensions */
1384: /* PowerPC 602 specific */
1385: PPC_602_SPEC = 0x0000000000000400ULL,
1386: /* isel instruction */
1387: PPC_ISEL = 0x0000000000000800ULL,
1388: /* popcntb instruction */
1389: PPC_POPCNTB = 0x0000000000001000ULL,
1390: /* string load / store */
1391: PPC_STRING = 0x0000000000002000ULL,
1392:
1393: /* Floating-point unit extensions */
1394: /* Optional floating point instructions */
1395: PPC_FLOAT = 0x0000000000010000ULL,
1396: /* New floating-point extensions (PowerPC 2.0x) */
1397: PPC_FLOAT_EXT = 0x0000000000020000ULL,
1398: PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1399: PPC_FLOAT_FRES = 0x0000000000080000ULL,
1400: PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1401: PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1402: PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1403: PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1404:
1405: /* Vector/SIMD extensions */
1406: /* Altivec support */
1407: PPC_ALTIVEC = 0x0000000001000000ULL,
1408: /* PowerPC 2.03 SPE extension */
1409: PPC_SPE = 0x0000000002000000ULL,
1410: /* PowerPC 2.03 SPE single-precision floating-point extension */
1411: PPC_SPE_SINGLE = 0x0000000004000000ULL,
1412: /* PowerPC 2.03 SPE double-precision floating-point extension */
1413: PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1414:
1415: /* Optional memory control instructions */
1416: PPC_MEM_TLBIA = 0x0000000010000000ULL,
1417: PPC_MEM_TLBIE = 0x0000000020000000ULL,
1418: PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1419: /* sync instruction */
1420: PPC_MEM_SYNC = 0x0000000080000000ULL,
1421: /* eieio instruction */
1422: PPC_MEM_EIEIO = 0x0000000100000000ULL,
1423:
1424: /* Cache control instructions */
1425: PPC_CACHE = 0x0000000200000000ULL,
1426: /* icbi instruction */
1427: PPC_CACHE_ICBI = 0x0000000400000000ULL,
1428: /* dcbz instruction with fixed cache line size */
1429: PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1430: /* dcbz instruction with tunable cache line size */
1431: PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1432: /* dcba instruction */
1433: PPC_CACHE_DCBA = 0x0000002000000000ULL,
1434: /* Freescale cache locking instructions */
1435: PPC_CACHE_LOCK = 0x0000004000000000ULL,
1436:
1437: /* MMU related extensions */
1438: /* external control instructions */
1439: PPC_EXTERN = 0x0000010000000000ULL,
1440: /* segment register access instructions */
1441: PPC_SEGMENT = 0x0000020000000000ULL,
1442: /* PowerPC 6xx TLB management instructions */
1443: PPC_6xx_TLB = 0x0000040000000000ULL,
1444: /* PowerPC 74xx TLB management instructions */
1445: PPC_74xx_TLB = 0x0000080000000000ULL,
1446: /* PowerPC 40x TLB management instructions */
1447: PPC_40x_TLB = 0x0000100000000000ULL,
1448: /* segment register access instructions for PowerPC 64 "bridge" */
1449: PPC_SEGMENT_64B = 0x0000200000000000ULL,
1450: /* SLB management */
1451: PPC_SLBI = 0x0000400000000000ULL,
1452:
1453: /* Embedded PowerPC dedicated instructions */
1454: PPC_WRTEE = 0x0001000000000000ULL,
1455: /* PowerPC 40x exception model */
1456: PPC_40x_EXCP = 0x0002000000000000ULL,
1457: /* PowerPC 405 Mac instructions */
1458: PPC_405_MAC = 0x0004000000000000ULL,
1459: /* PowerPC 440 specific instructions */
1460: PPC_440_SPEC = 0x0008000000000000ULL,
1461: /* BookE (embedded) PowerPC specification */
1462: PPC_BOOKE = 0x0010000000000000ULL,
1463: /* mfapidi instruction */
1464: PPC_MFAPIDI = 0x0020000000000000ULL,
1465: /* tlbiva instruction */
1466: PPC_TLBIVA = 0x0040000000000000ULL,
1467: /* tlbivax instruction */
1468: PPC_TLBIVAX = 0x0080000000000000ULL,
1469: /* PowerPC 4xx dedicated instructions */
1470: PPC_4xx_COMMON = 0x0100000000000000ULL,
1471: /* PowerPC 40x ibct instructions */
1472: PPC_40x_ICBT = 0x0200000000000000ULL,
1473: /* rfmci is not implemented in all BookE PowerPC */
1474: PPC_RFMCI = 0x0400000000000000ULL,
1475: /* rfdi instruction */
1476: PPC_RFDI = 0x0800000000000000ULL,
1477: /* DCR accesses */
1478: PPC_DCR = 0x1000000000000000ULL,
1479: /* DCR extended accesse */
1480: PPC_DCRX = 0x2000000000000000ULL,
1481: /* user-mode DCR access, implemented in PowerPC 460 */
1482: PPC_DCRUX = 0x4000000000000000ULL,
1483: };
1484:
1485: /*****************************************************************************/
1.1 root 1486: /* Memory access type :
1487: * may be needed for precise access rights control and precise exceptions.
1488: */
1489: enum {
1490: /* 1 bit to define user level / supervisor access */
1491: ACCESS_USER = 0x00,
1492: ACCESS_SUPER = 0x01,
1493: /* Type of instruction that generated the access */
1494: ACCESS_CODE = 0x10, /* Code fetch access */
1495: ACCESS_INT = 0x20, /* Integer load/store access */
1496: ACCESS_FLOAT = 0x30, /* floating point load/store access */
1497: ACCESS_RES = 0x40, /* load/store with reservation */
1498: ACCESS_EXT = 0x50, /* external access */
1499: ACCESS_CACHE = 0x60, /* Cache manipulation */
1500: };
1501:
1.1.1.4 root 1502: /* Hardware interruption sources:
1503: * all those exception can be raised simulteaneously
1504: */
1505: /* Input pins definitions */
1506: enum {
1507: /* 6xx bus input pins */
1508: PPC6xx_INPUT_HRESET = 0,
1509: PPC6xx_INPUT_SRESET = 1,
1510: PPC6xx_INPUT_CKSTP_IN = 2,
1511: PPC6xx_INPUT_MCP = 3,
1512: PPC6xx_INPUT_SMI = 4,
1513: PPC6xx_INPUT_INT = 5,
1514: PPC6xx_INPUT_TBEN = 6,
1515: PPC6xx_INPUT_WAKEUP = 7,
1516: PPC6xx_INPUT_NB,
1517: };
1518:
1519: enum {
1520: /* Embedded PowerPC input pins */
1521: PPCBookE_INPUT_HRESET = 0,
1522: PPCBookE_INPUT_SRESET = 1,
1523: PPCBookE_INPUT_CKSTP_IN = 2,
1524: PPCBookE_INPUT_MCP = 3,
1525: PPCBookE_INPUT_SMI = 4,
1526: PPCBookE_INPUT_INT = 5,
1527: PPCBookE_INPUT_CINT = 6,
1528: PPCBookE_INPUT_NB,
1529: };
1530:
1531: enum {
1.1.1.5 root 1532: /* PowerPC E500 input pins */
1533: PPCE500_INPUT_RESET_CORE = 0,
1534: PPCE500_INPUT_MCK = 1,
1535: PPCE500_INPUT_CINT = 3,
1536: PPCE500_INPUT_INT = 4,
1537: PPCE500_INPUT_DEBUG = 6,
1538: PPCE500_INPUT_NB,
1539: };
1540:
1541: enum {
1.1.1.4 root 1542: /* PowerPC 40x input pins */
1543: PPC40x_INPUT_RESET_CORE = 0,
1544: PPC40x_INPUT_RESET_CHIP = 1,
1545: PPC40x_INPUT_RESET_SYS = 2,
1546: PPC40x_INPUT_CINT = 3,
1547: PPC40x_INPUT_INT = 4,
1548: PPC40x_INPUT_HALT = 5,
1549: PPC40x_INPUT_DEBUG = 6,
1550: PPC40x_INPUT_NB,
1551: };
1552:
1553: enum {
1554: /* RCPU input pins */
1555: PPCRCPU_INPUT_PORESET = 0,
1556: PPCRCPU_INPUT_HRESET = 1,
1557: PPCRCPU_INPUT_SRESET = 2,
1558: PPCRCPU_INPUT_IRQ0 = 3,
1559: PPCRCPU_INPUT_IRQ1 = 4,
1560: PPCRCPU_INPUT_IRQ2 = 5,
1561: PPCRCPU_INPUT_IRQ3 = 6,
1562: PPCRCPU_INPUT_IRQ4 = 7,
1563: PPCRCPU_INPUT_IRQ5 = 8,
1564: PPCRCPU_INPUT_IRQ6 = 9,
1565: PPCRCPU_INPUT_IRQ7 = 10,
1566: PPCRCPU_INPUT_NB,
1567: };
1568:
1569: #if defined(TARGET_PPC64)
1570: enum {
1571: /* PowerPC 970 input pins */
1572: PPC970_INPUT_HRESET = 0,
1573: PPC970_INPUT_SRESET = 1,
1574: PPC970_INPUT_CKSTP = 2,
1575: PPC970_INPUT_TBEN = 3,
1576: PPC970_INPUT_MCP = 4,
1577: PPC970_INPUT_INT = 5,
1578: PPC970_INPUT_THINT = 6,
1579: PPC970_INPUT_NB,
1580: };
1581: #endif
1.1 root 1582:
1.1.1.4 root 1583: /* Hardware exceptions definitions */
1.1 root 1584: enum {
1.1.1.4 root 1585: /* External hardware exception sources */
1586: PPC_INTERRUPT_RESET = 0, /* Reset exception */
1587: PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
1588: PPC_INTERRUPT_MCK, /* Machine check exception */
1589: PPC_INTERRUPT_EXT, /* External interrupt */
1590: PPC_INTERRUPT_SMI, /* System management interrupt */
1591: PPC_INTERRUPT_CEXT, /* Critical external interrupt */
1592: PPC_INTERRUPT_DEBUG, /* External debug exception */
1593: PPC_INTERRUPT_THERM, /* Thermal exception */
1594: /* Internal hardware exception sources */
1595: PPC_INTERRUPT_DECR, /* Decrementer exception */
1596: PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
1597: PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
1598: PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
1599: PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
1600: PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
1601: PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
1602: PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
1.1 root 1603: };
1604:
1605: /*****************************************************************************/
1606:
1.1.1.5 root 1607: static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
1608: target_ulong *cs_base, int *flags)
1609: {
1610: *pc = env->nip;
1611: *cs_base = 0;
1612: *flags = env->hflags;
1613: }
1614:
1.1.1.7 root 1615: static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
1616: {
1617: #if defined(TARGET_PPC64)
1618: /* The kernel checks TIF_32BIT here; we don't support loading 32-bit
1619: binaries on PPC64 yet. */
1620: env->gpr[13] = newtls;
1621: #else
1622: env->gpr[2] = newtls;
1623: #endif
1624: }
1625:
1.1 root 1626: #endif /* !defined (__CPU_PPC_H__) */
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