File:  [Qemu by Fabrice Bellard] / qemu / target-ppc / cpu.h
Revision 1.1.1.7 (vendor branch): download - view: text, annotated - select for diffs
Tue Apr 24 17:40:54 2018 UTC (3 years, 5 months ago) by root
Branches: qemu, MAIN
CVS tags: qemu0125, qemu0124, qemu0123, qemu0122, qemu0121, qemu0120, HEAD
qemu 0.12.0

    1: /*
    2:  *  PowerPC emulation cpu definitions for qemu.
    3:  *
    4:  *  Copyright (c) 2003-2007 Jocelyn Mayer
    5:  *
    6:  * This library is free software; you can redistribute it and/or
    7:  * modify it under the terms of the GNU Lesser General Public
    8:  * License as published by the Free Software Foundation; either
    9:  * version 2 of the License, or (at your option) any later version.
   10:  *
   11:  * This library is distributed in the hope that it will be useful,
   12:  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   13:  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   14:  * Lesser General Public License for more details.
   15:  *
   16:  * You should have received a copy of the GNU Lesser General Public
   17:  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
   18:  */
   19: #if !defined (__CPU_PPC_H__)
   20: #define __CPU_PPC_H__
   21: 
   22: #include "config.h"
   23: #include <inttypes.h>
   24: 
   25: //#define PPC_EMULATE_32BITS_HYPV
   26: 
   27: #if defined (TARGET_PPC64)
   28: /* PowerPC 64 definitions */
   29: #define TARGET_LONG_BITS 64
   30: #define TARGET_PAGE_BITS 12
   31: 
   32: #else /* defined (TARGET_PPC64) */
   33: /* PowerPC 32 definitions */
   34: #define TARGET_LONG_BITS 32
   35: 
   36: #if defined(TARGET_PPCEMB)
   37: /* Specific definitions for PowerPC embedded */
   38: /* BookE have 36 bits physical address space */
   39: #if defined(CONFIG_USER_ONLY)
   40: /* It looks like a lot of Linux programs assume page size
   41:  * is 4kB long. This is evil, but we have to deal with it...
   42:  */
   43: #define TARGET_PAGE_BITS 12
   44: #else /* defined(CONFIG_USER_ONLY) */
   45: /* Pages can be 1 kB small */
   46: #define TARGET_PAGE_BITS 10
   47: #endif /* defined(CONFIG_USER_ONLY) */
   48: #else /* defined(TARGET_PPCEMB) */
   49: /* "standard" PowerPC 32 definitions */
   50: #define TARGET_PAGE_BITS 12
   51: #endif /* defined(TARGET_PPCEMB) */
   52: 
   53: #endif /* defined (TARGET_PPC64) */
   54: 
   55: #define CPUState struct CPUPPCState
   56: 
   57: #include "cpu-defs.h"
   58: 
   59: #include <setjmp.h>
   60: 
   61: #include "softfloat.h"
   62: 
   63: #define TARGET_HAS_ICE 1
   64: 
   65: #if defined (TARGET_PPC64)
   66: #define ELF_MACHINE     EM_PPC64
   67: #else
   68: #define ELF_MACHINE     EM_PPC
   69: #endif
   70: 
   71: /*****************************************************************************/
   72: /* MMU model                                                                 */
   73: typedef enum powerpc_mmu_t powerpc_mmu_t;
   74: enum powerpc_mmu_t {
   75:     POWERPC_MMU_UNKNOWN    = 0x00000000,
   76:     /* Standard 32 bits PowerPC MMU                            */
   77:     POWERPC_MMU_32B        = 0x00000001,
   78:     /* PowerPC 6xx MMU with software TLB                       */
   79:     POWERPC_MMU_SOFT_6xx   = 0x00000002,
   80:     /* PowerPC 74xx MMU with software TLB                      */
   81:     POWERPC_MMU_SOFT_74xx  = 0x00000003,
   82:     /* PowerPC 4xx MMU with software TLB                       */
   83:     POWERPC_MMU_SOFT_4xx   = 0x00000004,
   84:     /* PowerPC 4xx MMU with software TLB and zones protections */
   85:     POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
   86:     /* PowerPC MMU in real mode only                           */
   87:     POWERPC_MMU_REAL       = 0x00000006,
   88:     /* Freescale MPC8xx MMU model                              */
   89:     POWERPC_MMU_MPC8xx     = 0x00000007,
   90:     /* BookE MMU model                                         */
   91:     POWERPC_MMU_BOOKE      = 0x00000008,
   92:     /* BookE FSL MMU model                                     */
   93:     POWERPC_MMU_BOOKE_FSL  = 0x00000009,
   94:     /* PowerPC 601 MMU model (specific BATs format)            */
   95:     POWERPC_MMU_601        = 0x0000000A,
   96: #if defined(TARGET_PPC64)
   97: #define POWERPC_MMU_64       0x00010000
   98:     /* 64 bits PowerPC MMU                                     */
   99:     POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,
  100:     /* 620 variant (no segment exceptions)                     */
  101:     POWERPC_MMU_620        = POWERPC_MMU_64 | 0x00000002,
  102: #endif /* defined(TARGET_PPC64) */
  103: };
  104: 
  105: /*****************************************************************************/
  106: /* Exception model                                                           */
  107: typedef enum powerpc_excp_t powerpc_excp_t;
  108: enum powerpc_excp_t {
  109:     POWERPC_EXCP_UNKNOWN   = 0,
  110:     /* Standard PowerPC exception model */
  111:     POWERPC_EXCP_STD,
  112:     /* PowerPC 40x exception model      */
  113:     POWERPC_EXCP_40x,
  114:     /* PowerPC 601 exception model      */
  115:     POWERPC_EXCP_601,
  116:     /* PowerPC 602 exception model      */
  117:     POWERPC_EXCP_602,
  118:     /* PowerPC 603 exception model      */
  119:     POWERPC_EXCP_603,
  120:     /* PowerPC 603e exception model     */
  121:     POWERPC_EXCP_603E,
  122:     /* PowerPC G2 exception model       */
  123:     POWERPC_EXCP_G2,
  124:     /* PowerPC 604 exception model      */
  125:     POWERPC_EXCP_604,
  126:     /* PowerPC 7x0 exception model      */
  127:     POWERPC_EXCP_7x0,
  128:     /* PowerPC 7x5 exception model      */
  129:     POWERPC_EXCP_7x5,
  130:     /* PowerPC 74xx exception model     */
  131:     POWERPC_EXCP_74xx,
  132:     /* BookE exception model            */
  133:     POWERPC_EXCP_BOOKE,
  134: #if defined(TARGET_PPC64)
  135:     /* PowerPC 970 exception model      */
  136:     POWERPC_EXCP_970,
  137: #endif /* defined(TARGET_PPC64) */
  138: };
  139: 
  140: /*****************************************************************************/
  141: /* Exception vectors definitions                                             */
  142: enum {
  143:     POWERPC_EXCP_NONE    = -1,
  144:     /* The 64 first entries are used by the PowerPC embedded specification   */
  145:     POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
  146:     POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
  147:     POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
  148:     POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
  149:     POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
  150:     POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
  151:     POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
  152:     POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
  153:     POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
  154:     POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
  155:     POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
  156:     POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
  157:     POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
  158:     POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
  159:     POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
  160:     POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
  161:     /* Vectors 16 to 31 are reserved                                         */
  162:     POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
  163:     POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
  164:     POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
  165:     POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
  166:     POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
  167:     POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
  168:     /* Vectors 38 to 63 are reserved                                         */
  169:     /* Exceptions defined in the PowerPC server specification                */
  170:     POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
  171:     POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
  172:     POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
  173:     POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
  174:     POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
  175:     POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
  176:     POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
  177:     POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
  178:     POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
  179:     POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
  180:     /* 40x specific exceptions                                               */
  181:     POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
  182:     /* 601 specific exceptions                                               */
  183:     POWERPC_EXCP_IO       = 75, /* IO error exception                        */
  184:     POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
  185:     /* 602 specific exceptions                                               */
  186:     POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
  187:     /* 602/603 specific exceptions                                           */
  188:     POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
  189:     POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
  190:     POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
  191:     /* Exceptions available on most PowerPC                                  */
  192:     POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
  193:     POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
  194:     POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
  195:     POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
  196:     POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
  197:     /* 7xx/74xx specific exceptions                                          */
  198:     POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
  199:     /* 74xx specific exceptions                                              */
  200:     POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
  201:     /* 970FX specific exceptions                                             */
  202:     POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
  203:     POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
  204:     /* Freescale embeded cores specific exceptions                           */
  205:     POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
  206:     POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
  207:     POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
  208:     POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
  209:     /* EOL                                                                   */
  210:     POWERPC_EXCP_NB       = 96,
  211:     /* Qemu exceptions: used internally during code translation              */
  212:     POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
  213:     POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
  214:     /* Qemu exceptions: special cases we want to stop translation            */
  215:     POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */
  216:     POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
  217:     POWERPC_EXCP_STCX         = 0x204 /* Conditional stores in user mode     */
  218: };
  219: 
  220: /* Exceptions error codes                                                    */
  221: enum {
  222:     /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
  223:     POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
  224:     POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
  225:     POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
  226:     POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
  227:     POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
  228:     POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
  229:     /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
  230:     /* FP exceptions                                                         */
  231:     POWERPC_EXCP_FP            = 0x10,
  232:     POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
  233:     POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
  234:     POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
  235:     POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
  236:     POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
  237:     POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
  238:     POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
  239:     POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
  240:     POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
  241:     POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
  242:     POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
  243:     POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
  244:     POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
  245:     /* Invalid instruction                                                   */
  246:     POWERPC_EXCP_INVAL         = 0x20,
  247:     POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
  248:     POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
  249:     POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
  250:     POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
  251:     /* Privileged instruction                                                */
  252:     POWERPC_EXCP_PRIV          = 0x30,
  253:     POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
  254:     POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
  255:     /* Trap                                                                  */
  256:     POWERPC_EXCP_TRAP          = 0x40,
  257: };
  258: 
  259: /*****************************************************************************/
  260: /* Input pins model                                                          */
  261: typedef enum powerpc_input_t powerpc_input_t;
  262: enum powerpc_input_t {
  263:     PPC_FLAGS_INPUT_UNKNOWN = 0,
  264:     /* PowerPC 6xx bus                  */
  265:     PPC_FLAGS_INPUT_6xx,
  266:     /* BookE bus                        */
  267:     PPC_FLAGS_INPUT_BookE,
  268:     /* PowerPC 405 bus                  */
  269:     PPC_FLAGS_INPUT_405,
  270:     /* PowerPC 970 bus                  */
  271:     PPC_FLAGS_INPUT_970,
  272:     /* PowerPC 401 bus                  */
  273:     PPC_FLAGS_INPUT_401,
  274:     /* Freescale RCPU bus               */
  275:     PPC_FLAGS_INPUT_RCPU,
  276: };
  277: 
  278: #define PPC_INPUT(env) (env->bus_model)
  279: 
  280: /*****************************************************************************/
  281: typedef struct ppc_def_t ppc_def_t;
  282: typedef struct opc_handler_t opc_handler_t;
  283: 
  284: /*****************************************************************************/
  285: /* Types used to describe some PowerPC registers */
  286: typedef struct CPUPPCState CPUPPCState;
  287: typedef struct ppc_tb_t ppc_tb_t;
  288: typedef struct ppc_spr_t ppc_spr_t;
  289: typedef struct ppc_dcr_t ppc_dcr_t;
  290: typedef union ppc_avr_t ppc_avr_t;
  291: typedef union ppc_tlb_t ppc_tlb_t;
  292: 
  293: /* SPR access micro-ops generations callbacks */
  294: struct ppc_spr_t {
  295:     void (*uea_read)(void *opaque, int gpr_num, int spr_num);
  296:     void (*uea_write)(void *opaque, int spr_num, int gpr_num);
  297: #if !defined(CONFIG_USER_ONLY)
  298:     void (*oea_read)(void *opaque, int gpr_num, int spr_num);
  299:     void (*oea_write)(void *opaque, int spr_num, int gpr_num);
  300:     void (*hea_read)(void *opaque, int gpr_num, int spr_num);
  301:     void (*hea_write)(void *opaque, int spr_num, int gpr_num);
  302: #endif
  303:     const char *name;
  304: };
  305: 
  306: /* Altivec registers (128 bits) */
  307: union ppc_avr_t {
  308:     float32 f[4];
  309:     uint8_t u8[16];
  310:     uint16_t u16[8];
  311:     uint32_t u32[4];
  312:     int8_t s8[16];
  313:     int16_t s16[8];
  314:     int32_t s32[4];
  315:     uint64_t u64[2];
  316: };
  317: 
  318: /* Software TLB cache */
  319: typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
  320: struct ppc6xx_tlb_t {
  321:     target_ulong pte0;
  322:     target_ulong pte1;
  323:     target_ulong EPN;
  324: };
  325: 
  326: typedef struct ppcemb_tlb_t ppcemb_tlb_t;
  327: struct ppcemb_tlb_t {
  328:     target_phys_addr_t RPN;
  329:     target_ulong EPN;
  330:     target_ulong PID;
  331:     target_ulong size;
  332:     uint32_t prot;
  333:     uint32_t attr; /* Storage attributes */
  334: };
  335: 
  336: union ppc_tlb_t {
  337:     ppc6xx_tlb_t tlb6;
  338:     ppcemb_tlb_t tlbe;
  339: };
  340: 
  341: typedef struct ppc_slb_t ppc_slb_t;
  342: struct ppc_slb_t {
  343:     uint64_t tmp64;
  344:     uint32_t tmp;
  345: };
  346: 
  347: /*****************************************************************************/
  348: /* Machine state register bits definition                                    */
  349: #define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
  350: #define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */
  351: #define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
  352: #define MSR_SHV  60 /* hypervisor state                               hflags */
  353: #define MSR_CM   31 /* Computation mode for BookE                     hflags */
  354: #define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
  355: #define MSR_THV  29 /* hypervisor state for 32 bits PowerPC           hflags */
  356: #define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
  357: #define MSR_VR   25 /* altivec available                            x hflags */
  358: #define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
  359: #define MSR_AP   23 /* Access privilege state on 602                  hflags */
  360: #define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
  361: #define MSR_KEY  19 /* key bit on 603e                                       */
  362: #define MSR_POW  18 /* Power management                                      */
  363: #define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
  364: #define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
  365: #define MSR_ILE  16 /* Interrupt little-endian mode                          */
  366: #define MSR_EE   15 /* External interrupt enable                             */
  367: #define MSR_PR   14 /* Problem state                                  hflags */
  368: #define MSR_FP   13 /* Floating point available                       hflags */
  369: #define MSR_ME   12 /* Machine check interrupt enable                        */
  370: #define MSR_FE0  11 /* Floating point exception mode 0                hflags */
  371: #define MSR_SE   10 /* Single-step trace enable                     x hflags */
  372: #define MSR_DWE  10 /* Debug wait enable on 405                     x        */
  373: #define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
  374: #define MSR_BE   9  /* Branch trace enable                          x hflags */
  375: #define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
  376: #define MSR_FE1  8  /* Floating point exception mode 1                hflags */
  377: #define MSR_AL   7  /* AL bit on POWER                                       */
  378: #define MSR_EP   6  /* Exception prefix on 601                               */
  379: #define MSR_IR   5  /* Instruction relocate                                  */
  380: #define MSR_DR   4  /* Data relocate                                         */
  381: #define MSR_PE   3  /* Protection enable on 403                              */
  382: #define MSR_PX   2  /* Protection exclusive on 403                  x        */
  383: #define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
  384: #define MSR_RI   1  /* Recoverable interrupt                        1        */
  385: #define MSR_LE   0  /* Little-endian mode                           1 hflags */
  386: 
  387: #define msr_sf   ((env->msr >> MSR_SF)   & 1)
  388: #define msr_isf  ((env->msr >> MSR_ISF)  & 1)
  389: #define msr_shv  ((env->msr >> MSR_SHV)  & 1)
  390: #define msr_cm   ((env->msr >> MSR_CM)   & 1)
  391: #define msr_icm  ((env->msr >> MSR_ICM)  & 1)
  392: #define msr_thv  ((env->msr >> MSR_THV)  & 1)
  393: #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
  394: #define msr_vr   ((env->msr >> MSR_VR)   & 1)
  395: #define msr_spe  ((env->msr >> MSR_SPE)  & 1)
  396: #define msr_ap   ((env->msr >> MSR_AP)   & 1)
  397: #define msr_sa   ((env->msr >> MSR_SA)   & 1)
  398: #define msr_key  ((env->msr >> MSR_KEY)  & 1)
  399: #define msr_pow  ((env->msr >> MSR_POW)  & 1)
  400: #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
  401: #define msr_ce   ((env->msr >> MSR_CE)   & 1)
  402: #define msr_ile  ((env->msr >> MSR_ILE)  & 1)
  403: #define msr_ee   ((env->msr >> MSR_EE)   & 1)
  404: #define msr_pr   ((env->msr >> MSR_PR)   & 1)
  405: #define msr_fp   ((env->msr >> MSR_FP)   & 1)
  406: #define msr_me   ((env->msr >> MSR_ME)   & 1)
  407: #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
  408: #define msr_se   ((env->msr >> MSR_SE)   & 1)
  409: #define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
  410: #define msr_uble ((env->msr >> MSR_UBLE) & 1)
  411: #define msr_be   ((env->msr >> MSR_BE)   & 1)
  412: #define msr_de   ((env->msr >> MSR_DE)   & 1)
  413: #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
  414: #define msr_al   ((env->msr >> MSR_AL)   & 1)
  415: #define msr_ep   ((env->msr >> MSR_EP)   & 1)
  416: #define msr_ir   ((env->msr >> MSR_IR)   & 1)
  417: #define msr_dr   ((env->msr >> MSR_DR)   & 1)
  418: #define msr_pe   ((env->msr >> MSR_PE)   & 1)
  419: #define msr_px   ((env->msr >> MSR_PX)   & 1)
  420: #define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
  421: #define msr_ri   ((env->msr >> MSR_RI)   & 1)
  422: #define msr_le   ((env->msr >> MSR_LE)   & 1)
  423: /* Hypervisor bit is more specific */
  424: #if defined(TARGET_PPC64)
  425: #define MSR_HVB (1ULL << MSR_SHV)
  426: #define msr_hv  msr_shv
  427: #else
  428: #if defined(PPC_EMULATE_32BITS_HYPV)
  429: #define MSR_HVB (1ULL << MSR_THV)
  430: #define msr_hv  msr_thv
  431: #else
  432: #define MSR_HVB (0ULL)
  433: #define msr_hv  (0)
  434: #endif
  435: #endif
  436: 
  437: enum {
  438:     POWERPC_FLAG_NONE     = 0x00000000,
  439:     /* Flag for MSR bit 25 signification (VRE/SPE)                           */
  440:     POWERPC_FLAG_SPE      = 0x00000001,
  441:     POWERPC_FLAG_VRE      = 0x00000002,
  442:     /* Flag for MSR bit 17 signification (TGPR/CE)                           */
  443:     POWERPC_FLAG_TGPR     = 0x00000004,
  444:     POWERPC_FLAG_CE       = 0x00000008,
  445:     /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
  446:     POWERPC_FLAG_SE       = 0x00000010,
  447:     POWERPC_FLAG_DWE      = 0x00000020,
  448:     POWERPC_FLAG_UBLE     = 0x00000040,
  449:     /* Flag for MSR bit 9 signification (BE/DE)                              */
  450:     POWERPC_FLAG_BE       = 0x00000080,
  451:     POWERPC_FLAG_DE       = 0x00000100,
  452:     /* Flag for MSR bit 2 signification (PX/PMM)                             */
  453:     POWERPC_FLAG_PX       = 0x00000200,
  454:     POWERPC_FLAG_PMM      = 0x00000400,
  455:     /* Flag for special features                                             */
  456:     /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */
  457:     POWERPC_FLAG_RTC_CLK  = 0x00010000,
  458:     POWERPC_FLAG_BUS_CLK  = 0x00020000,
  459: };
  460: 
  461: /*****************************************************************************/
  462: /* Floating point status and control register                                */
  463: #define FPSCR_FX     31 /* Floating-point exception summary                  */
  464: #define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
  465: #define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
  466: #define FPSCR_OX     28 /* Floating-point overflow exception                 */
  467: #define FPSCR_UX     27 /* Floating-point underflow exception                */
  468: #define FPSCR_ZX     26 /* Floating-point zero divide exception              */
  469: #define FPSCR_XX     25 /* Floating-point inexact exception                  */
  470: #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
  471: #define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
  472: #define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
  473: #define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
  474: #define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
  475: #define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
  476: #define FPSCR_FR     18 /* Floating-point fraction rounded                   */
  477: #define FPSCR_FI     17 /* Floating-point fraction inexact                   */
  478: #define FPSCR_C      16 /* Floating-point result class descriptor            */
  479: #define FPSCR_FL     15 /* Floating-point less than or negative              */
  480: #define FPSCR_FG     14 /* Floating-point greater than or negative           */
  481: #define FPSCR_FE     13 /* Floating-point equal or zero                      */
  482: #define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
  483: #define FPSCR_FPCC   12 /* Floating-point condition code                     */
  484: #define FPSCR_FPRF   12 /* Floating-point result flags                       */
  485: #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
  486: #define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
  487: #define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
  488: #define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
  489: #define FPSCR_OE     6  /* Floating-point overflow exception enable          */
  490: #define FPSCR_UE     5  /* Floating-point undeflow exception enable          */
  491: #define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
  492: #define FPSCR_XE     3  /* Floating-point inexact exception enable           */
  493: #define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
  494: #define FPSCR_RN1    1
  495: #define FPSCR_RN     0  /* Floating-point rounding control                   */
  496: #define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
  497: #define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
  498: #define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
  499: #define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
  500: #define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
  501: #define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
  502: #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
  503: #define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
  504: #define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
  505: #define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
  506: #define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
  507: #define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
  508: #define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
  509: #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
  510: #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
  511: #define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
  512: #define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
  513: #define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
  514: #define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
  515: #define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
  516: #define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
  517: #define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
  518: #define fpscr_rn     (((env->fpscr) >> FPSCR_RN)     & 0x3)
  519: /* Invalid operation exception summary */
  520: #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
  521:                                   (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
  522:                                   (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
  523:                                   (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
  524:                                   (1 << FPSCR_VXCVI)))
  525: /* exception summary */
  526: #define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
  527: /* enabled exception summary */
  528: #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
  529:                    0x1F)
  530: 
  531: /*****************************************************************************/
  532: /* Vector status and control register */
  533: #define VSCR_NJ		16 /* Vector non-java */
  534: #define VSCR_SAT	0 /* Vector saturation */
  535: #define vscr_nj		(((env->vscr) >> VSCR_NJ)	& 0x1)
  536: #define vscr_sat	(((env->vscr) >> VSCR_SAT)	& 0x1)
  537: 
  538: /*****************************************************************************/
  539: /* The whole PowerPC CPU context */
  540: #define NB_MMU_MODES 3
  541: 
  542: struct CPUPPCState {
  543:     /* First are the most commonly used resources
  544:      * during translated code execution
  545:      */
  546:     /* general purpose registers */
  547:     target_ulong gpr[32];
  548: #if !defined(TARGET_PPC64)
  549:     /* Storage for GPR MSB, used by the SPE extension */
  550:     target_ulong gprh[32];
  551: #endif
  552:     /* LR */
  553:     target_ulong lr;
  554:     /* CTR */
  555:     target_ulong ctr;
  556:     /* condition register */
  557:     uint32_t crf[8];
  558:     /* XER */
  559:     target_ulong xer;
  560:     /* Reservation address */
  561:     target_ulong reserve_addr;
  562:     /* Reservation value */
  563:     target_ulong reserve_val;
  564:     /* Reservation store address */
  565:     target_ulong reserve_ea;
  566:     /* Reserved store source register and size */
  567:     target_ulong reserve_info;
  568: 
  569:     /* Those ones are used in supervisor mode only */
  570:     /* machine state register */
  571:     target_ulong msr;
  572:     /* temporary general purpose registers */
  573:     target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
  574: 
  575:     /* Floating point execution context */
  576:     float_status fp_status;
  577:     /* floating point registers */
  578:     float64 fpr[32];
  579:     /* floating point status and control register */
  580:     uint32_t fpscr;
  581: 
  582:     /* Next instruction pointer */
  583:     target_ulong nip;
  584: 
  585:     int access_type; /* when a memory exception occurs, the access
  586:                         type is stored here */
  587: 
  588:     CPU_COMMON
  589: 
  590:     /* MMU context - only relevant for full system emulation */
  591: #if !defined(CONFIG_USER_ONLY)
  592: #if defined(TARGET_PPC64)
  593:     /* Address space register */
  594:     target_ulong asr;
  595:     /* PowerPC 64 SLB area */
  596:     ppc_slb_t slb[64];
  597:     int slb_nr;
  598: #endif
  599:     /* segment registers */
  600:     target_ulong sdr1;
  601:     target_ulong sr[32];
  602:     /* BATs */
  603:     int nb_BATs;
  604:     target_ulong DBAT[2][8];
  605:     target_ulong IBAT[2][8];
  606:     /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
  607:     int nb_tlb;      /* Total number of TLB                                  */
  608:     int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
  609:     int nb_ways;     /* Number of ways in the TLB set                        */
  610:     int last_way;    /* Last used way used to allocate TLB in a LRU way      */
  611:     int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
  612:     int nb_pids;     /* Number of available PID registers                    */
  613:     ppc_tlb_t *tlb;  /* TLB is optional. Allocate them only if needed        */
  614:     /* 403 dedicated access protection registers */
  615:     target_ulong pb[4];
  616: #endif
  617: 
  618:     /* Other registers */
  619:     /* Special purpose registers */
  620:     target_ulong spr[1024];
  621:     ppc_spr_t spr_cb[1024];
  622:     /* Altivec registers */
  623:     ppc_avr_t avr[32];
  624:     uint32_t vscr;
  625:     /* SPE registers */
  626:     uint64_t spe_acc;
  627:     uint32_t spe_fscr;
  628:     /* SPE and Altivec can share a status since they will never be used
  629:      * simultaneously */
  630:     float_status vec_status;
  631: 
  632:     /* Internal devices resources */
  633:     /* Time base and decrementer */
  634:     ppc_tb_t *tb_env;
  635:     /* Device control registers */
  636:     ppc_dcr_t *dcr_env;
  637: 
  638:     int dcache_line_size;
  639:     int icache_line_size;
  640: 
  641:     /* Those resources are used during exception processing */
  642:     /* CPU model definition */
  643:     target_ulong msr_mask;
  644:     powerpc_mmu_t mmu_model;
  645:     powerpc_excp_t excp_model;
  646:     powerpc_input_t bus_model;
  647:     int bfd_mach;
  648:     uint32_t flags;
  649:     uint64_t insns_flags;
  650: 
  651:     int error_code;
  652:     uint32_t pending_interrupts;
  653: #if !defined(CONFIG_USER_ONLY)
  654:     /* This is the IRQ controller, which is implementation dependant
  655:      * and only relevant when emulating a complete machine.
  656:      */
  657:     uint32_t irq_input_state;
  658:     void **irq_inputs;
  659:     /* Exception vectors */
  660:     target_ulong excp_vectors[POWERPC_EXCP_NB];
  661:     target_ulong excp_prefix;
  662:     target_ulong hreset_excp_prefix;
  663:     target_ulong ivor_mask;
  664:     target_ulong ivpr_mask;
  665:     target_ulong hreset_vector;
  666: #endif
  667: 
  668:     /* Those resources are used only during code translation */
  669:     /* opcode handlers */
  670:     opc_handler_t *opcodes[0x40];
  671: 
  672:     /* Those resources are used only in Qemu core */
  673:     target_ulong hflags;      /* hflags is a MSR & HFLAGS_MASK         */
  674:     target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
  675:     int mmu_idx;         /* precomputed MMU index to speed up mem accesses */
  676: 
  677:     /* Power management */
  678:     int power_mode;
  679:     int (*check_pow)(CPUPPCState *env);
  680: 
  681:     /* temporary hack to handle OSI calls (only used if non NULL) */
  682:     int (*osi_call)(struct CPUPPCState *env);
  683: };
  684: 
  685: /* Context used internally during MMU translations */
  686: typedef struct mmu_ctx_t mmu_ctx_t;
  687: struct mmu_ctx_t {
  688:     target_phys_addr_t raddr;      /* Real address              */
  689:     target_phys_addr_t eaddr;      /* Effective address         */
  690:     int prot;                      /* Protection bits           */
  691:     target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
  692:     target_ulong ptem;             /* Virtual segment ID | API  */
  693:     int key;                       /* Access key                */
  694:     int nx;                        /* Non-execute area          */
  695: };
  696: 
  697: /*****************************************************************************/
  698: CPUPPCState *cpu_ppc_init (const char *cpu_model);
  699: void ppc_translate_init(void);
  700: int cpu_ppc_exec (CPUPPCState *s);
  701: void cpu_ppc_close (CPUPPCState *s);
  702: /* you can call this signal handler from your SIGBUS and SIGSEGV
  703:    signal handlers to inform the virtual CPU of exceptions. non zero
  704:    is returned if the signal was handled by the virtual CPU.  */
  705: int cpu_ppc_signal_handler (int host_signum, void *pinfo,
  706:                             void *puc);
  707: int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
  708:                               int mmu_idx, int is_softmmu);
  709: #define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
  710: int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,
  711:                           int rw, int access_type);
  712: void do_interrupt (CPUPPCState *env);
  713: void ppc_hw_interrupt (CPUPPCState *env);
  714: 
  715: void cpu_dump_rfi (target_ulong RA, target_ulong msr);
  716: 
  717: #if !defined(CONFIG_USER_ONLY)
  718: void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code,
  719:                        target_ulong pte0, target_ulong pte1);
  720: void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
  721: void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
  722: void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
  723: void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
  724: void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);
  725: void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);
  726: void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
  727: #if defined(TARGET_PPC64)
  728: void ppc_store_asr (CPUPPCState *env, target_ulong value);
  729: target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
  730: target_ulong ppc_load_sr (CPUPPCState *env, int sr_nr);
  731: void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
  732: #endif /* defined(TARGET_PPC64) */
  733: void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value);
  734: #endif /* !defined(CONFIG_USER_ONLY) */
  735: void ppc_store_msr (CPUPPCState *env, target_ulong value);
  736: 
  737: void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
  738: 
  739: const ppc_def_t *cpu_ppc_find_by_name (const char *name);
  740: int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
  741: 
  742: /* Time-base and decrementer management */
  743: #ifndef NO_CPU_IO_DEFS
  744: uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
  745: uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
  746: void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
  747: void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
  748: uint32_t cpu_ppc_load_atbl (CPUPPCState *env);
  749: uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
  750: void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
  751: void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
  752: uint32_t cpu_ppc_load_decr (CPUPPCState *env);
  753: void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
  754: uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
  755: void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
  756: uint64_t cpu_ppc_load_purr (CPUPPCState *env);
  757: void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
  758: uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
  759: uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
  760: #if !defined(CONFIG_USER_ONLY)
  761: void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
  762: void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
  763: target_ulong load_40x_pit (CPUPPCState *env);
  764: void store_40x_pit (CPUPPCState *env, target_ulong val);
  765: void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
  766: void store_40x_sler (CPUPPCState *env, uint32_t val);
  767: void store_booke_tcr (CPUPPCState *env, target_ulong val);
  768: void store_booke_tsr (CPUPPCState *env, target_ulong val);
  769: void ppc_tlb_invalidate_all (CPUPPCState *env);
  770: void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
  771: #if defined(TARGET_PPC64)
  772: void ppc_slb_invalidate_all (CPUPPCState *env);
  773: void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
  774: #endif
  775: int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
  776: #endif
  777: #endif
  778: 
  779: static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
  780: {
  781:     uint64_t gprv;
  782: 
  783:     gprv = env->gpr[gprn];
  784: #if !defined(TARGET_PPC64)
  785:     if (env->flags & POWERPC_FLAG_SPE) {
  786:         /* If the CPU implements the SPE extension, we have to get the
  787:          * high bits of the GPR from the gprh storage area
  788:          */
  789:         gprv &= 0xFFFFFFFFULL;
  790:         gprv |= (uint64_t)env->gprh[gprn] << 32;
  791:     }
  792: #endif
  793: 
  794:     return gprv;
  795: }
  796: 
  797: /* Device control registers */
  798: int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
  799: int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
  800: 
  801: #define cpu_init cpu_ppc_init
  802: #define cpu_exec cpu_ppc_exec
  803: #define cpu_gen_code cpu_ppc_gen_code
  804: #define cpu_signal_handler cpu_ppc_signal_handler
  805: #define cpu_list ppc_cpu_list
  806: 
  807: #define CPU_SAVE_VERSION 4
  808: 
  809: /* MMU modes definitions */
  810: #define MMU_MODE0_SUFFIX _user
  811: #define MMU_MODE1_SUFFIX _kernel
  812: #define MMU_MODE2_SUFFIX _hypv
  813: #define MMU_USER_IDX 0
  814: static inline int cpu_mmu_index (CPUState *env)
  815: {
  816:     return env->mmu_idx;
  817: }
  818: 
  819: #if defined(CONFIG_USER_ONLY)
  820: static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
  821: {
  822:     if (newsp)
  823:         env->gpr[1] = newsp;
  824:     env->gpr[3] = 0;
  825: }
  826: #endif
  827: 
  828: #include "cpu-all.h"
  829: #include "exec-all.h"
  830: 
  831: /*****************************************************************************/
  832: /* CRF definitions */
  833: #define CRF_LT        3
  834: #define CRF_GT        2
  835: #define CRF_EQ        1
  836: #define CRF_SO        0
  837: #define CRF_CH        (1 << 4)
  838: #define CRF_CL        (1 << 3)
  839: #define CRF_CH_OR_CL  (1 << 2)
  840: #define CRF_CH_AND_CL (1 << 1)
  841: 
  842: /* XER definitions */
  843: #define XER_SO  31
  844: #define XER_OV  30
  845: #define XER_CA  29
  846: #define XER_CMP  8
  847: #define XER_BC   0
  848: #define xer_so  ((env->xer >> XER_SO)  &    1)
  849: #define xer_ov  ((env->xer >> XER_OV)  &    1)
  850: #define xer_ca  ((env->xer >> XER_CA)  &    1)
  851: #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
  852: #define xer_bc  ((env->xer >> XER_BC)  & 0x7F)
  853: 
  854: /* SPR definitions */
  855: #define SPR_MQ                (0x000)
  856: #define SPR_XER               (0x001)
  857: #define SPR_601_VRTCU         (0x004)
  858: #define SPR_601_VRTCL         (0x005)
  859: #define SPR_601_UDECR         (0x006)
  860: #define SPR_LR                (0x008)
  861: #define SPR_CTR               (0x009)
  862: #define SPR_DSISR             (0x012)
  863: #define SPR_DAR               (0x013) /* DAE for PowerPC 601 */
  864: #define SPR_601_RTCU          (0x014)
  865: #define SPR_601_RTCL          (0x015)
  866: #define SPR_DECR              (0x016)
  867: #define SPR_SDR1              (0x019)
  868: #define SPR_SRR0              (0x01A)
  869: #define SPR_SRR1              (0x01B)
  870: #define SPR_AMR               (0x01D)
  871: #define SPR_BOOKE_PID         (0x030)
  872: #define SPR_BOOKE_DECAR       (0x036)
  873: #define SPR_BOOKE_CSRR0       (0x03A)
  874: #define SPR_BOOKE_CSRR1       (0x03B)
  875: #define SPR_BOOKE_DEAR        (0x03D)
  876: #define SPR_BOOKE_ESR         (0x03E)
  877: #define SPR_BOOKE_IVPR        (0x03F)
  878: #define SPR_MPC_EIE           (0x050)
  879: #define SPR_MPC_EID           (0x051)
  880: #define SPR_MPC_NRI           (0x052)
  881: #define SPR_CTRL              (0x088)
  882: #define SPR_MPC_CMPA          (0x090)
  883: #define SPR_MPC_CMPB          (0x091)
  884: #define SPR_MPC_CMPC          (0x092)
  885: #define SPR_MPC_CMPD          (0x093)
  886: #define SPR_MPC_ECR           (0x094)
  887: #define SPR_MPC_DER           (0x095)
  888: #define SPR_MPC_COUNTA        (0x096)
  889: #define SPR_MPC_COUNTB        (0x097)
  890: #define SPR_UCTRL             (0x098)
  891: #define SPR_MPC_CMPE          (0x098)
  892: #define SPR_MPC_CMPF          (0x099)
  893: #define SPR_MPC_CMPG          (0x09A)
  894: #define SPR_MPC_CMPH          (0x09B)
  895: #define SPR_MPC_LCTRL1        (0x09C)
  896: #define SPR_MPC_LCTRL2        (0x09D)
  897: #define SPR_MPC_ICTRL         (0x09E)
  898: #define SPR_MPC_BAR           (0x09F)
  899: #define SPR_VRSAVE            (0x100)
  900: #define SPR_USPRG0            (0x100)
  901: #define SPR_USPRG1            (0x101)
  902: #define SPR_USPRG2            (0x102)
  903: #define SPR_USPRG3            (0x103)
  904: #define SPR_USPRG4            (0x104)
  905: #define SPR_USPRG5            (0x105)
  906: #define SPR_USPRG6            (0x106)
  907: #define SPR_USPRG7            (0x107)
  908: #define SPR_VTBL              (0x10C)
  909: #define SPR_VTBU              (0x10D)
  910: #define SPR_SPRG0             (0x110)
  911: #define SPR_SPRG1             (0x111)
  912: #define SPR_SPRG2             (0x112)
  913: #define SPR_SPRG3             (0x113)
  914: #define SPR_SPRG4             (0x114)
  915: #define SPR_SCOMC             (0x114)
  916: #define SPR_SPRG5             (0x115)
  917: #define SPR_SCOMD             (0x115)
  918: #define SPR_SPRG6             (0x116)
  919: #define SPR_SPRG7             (0x117)
  920: #define SPR_ASR               (0x118)
  921: #define SPR_EAR               (0x11A)
  922: #define SPR_TBL               (0x11C)
  923: #define SPR_TBU               (0x11D)
  924: #define SPR_TBU40             (0x11E)
  925: #define SPR_SVR               (0x11E)
  926: #define SPR_BOOKE_PIR         (0x11E)
  927: #define SPR_PVR               (0x11F)
  928: #define SPR_HSPRG0            (0x130)
  929: #define SPR_BOOKE_DBSR        (0x130)
  930: #define SPR_HSPRG1            (0x131)
  931: #define SPR_HDSISR            (0x132)
  932: #define SPR_HDAR              (0x133)
  933: #define SPR_BOOKE_DBCR0       (0x134)
  934: #define SPR_IBCR              (0x135)
  935: #define SPR_PURR              (0x135)
  936: #define SPR_BOOKE_DBCR1       (0x135)
  937: #define SPR_DBCR              (0x136)
  938: #define SPR_HDEC              (0x136)
  939: #define SPR_BOOKE_DBCR2       (0x136)
  940: #define SPR_HIOR              (0x137)
  941: #define SPR_MBAR              (0x137)
  942: #define SPR_RMOR              (0x138)
  943: #define SPR_BOOKE_IAC1        (0x138)
  944: #define SPR_HRMOR             (0x139)
  945: #define SPR_BOOKE_IAC2        (0x139)
  946: #define SPR_HSRR0             (0x13A)
  947: #define SPR_BOOKE_IAC3        (0x13A)
  948: #define SPR_HSRR1             (0x13B)
  949: #define SPR_BOOKE_IAC4        (0x13B)
  950: #define SPR_LPCR              (0x13C)
  951: #define SPR_BOOKE_DAC1        (0x13C)
  952: #define SPR_LPIDR             (0x13D)
  953: #define SPR_DABR2             (0x13D)
  954: #define SPR_BOOKE_DAC2        (0x13D)
  955: #define SPR_BOOKE_DVC1        (0x13E)
  956: #define SPR_BOOKE_DVC2        (0x13F)
  957: #define SPR_BOOKE_TSR         (0x150)
  958: #define SPR_BOOKE_TCR         (0x154)
  959: #define SPR_BOOKE_IVOR0       (0x190)
  960: #define SPR_BOOKE_IVOR1       (0x191)
  961: #define SPR_BOOKE_IVOR2       (0x192)
  962: #define SPR_BOOKE_IVOR3       (0x193)
  963: #define SPR_BOOKE_IVOR4       (0x194)
  964: #define SPR_BOOKE_IVOR5       (0x195)
  965: #define SPR_BOOKE_IVOR6       (0x196)
  966: #define SPR_BOOKE_IVOR7       (0x197)
  967: #define SPR_BOOKE_IVOR8       (0x198)
  968: #define SPR_BOOKE_IVOR9       (0x199)
  969: #define SPR_BOOKE_IVOR10      (0x19A)
  970: #define SPR_BOOKE_IVOR11      (0x19B)
  971: #define SPR_BOOKE_IVOR12      (0x19C)
  972: #define SPR_BOOKE_IVOR13      (0x19D)
  973: #define SPR_BOOKE_IVOR14      (0x19E)
  974: #define SPR_BOOKE_IVOR15      (0x19F)
  975: #define SPR_BOOKE_SPEFSCR     (0x200)
  976: #define SPR_Exxx_BBEAR        (0x201)
  977: #define SPR_Exxx_BBTAR        (0x202)
  978: #define SPR_Exxx_L1CFG0       (0x203)
  979: #define SPR_Exxx_NPIDR        (0x205)
  980: #define SPR_ATBL              (0x20E)
  981: #define SPR_ATBU              (0x20F)
  982: #define SPR_IBAT0U            (0x210)
  983: #define SPR_BOOKE_IVOR32      (0x210)
  984: #define SPR_RCPU_MI_GRA       (0x210)
  985: #define SPR_IBAT0L            (0x211)
  986: #define SPR_BOOKE_IVOR33      (0x211)
  987: #define SPR_IBAT1U            (0x212)
  988: #define SPR_BOOKE_IVOR34      (0x212)
  989: #define SPR_IBAT1L            (0x213)
  990: #define SPR_BOOKE_IVOR35      (0x213)
  991: #define SPR_IBAT2U            (0x214)
  992: #define SPR_BOOKE_IVOR36      (0x214)
  993: #define SPR_IBAT2L            (0x215)
  994: #define SPR_BOOKE_IVOR37      (0x215)
  995: #define SPR_IBAT3U            (0x216)
  996: #define SPR_IBAT3L            (0x217)
  997: #define SPR_DBAT0U            (0x218)
  998: #define SPR_RCPU_L2U_GRA      (0x218)
  999: #define SPR_DBAT0L            (0x219)
 1000: #define SPR_DBAT1U            (0x21A)
 1001: #define SPR_DBAT1L            (0x21B)
 1002: #define SPR_DBAT2U            (0x21C)
 1003: #define SPR_DBAT2L            (0x21D)
 1004: #define SPR_DBAT3U            (0x21E)
 1005: #define SPR_DBAT3L            (0x21F)
 1006: #define SPR_IBAT4U            (0x230)
 1007: #define SPR_RPCU_BBCMCR       (0x230)
 1008: #define SPR_MPC_IC_CST        (0x230)
 1009: #define SPR_Exxx_CTXCR        (0x230)
 1010: #define SPR_IBAT4L            (0x231)
 1011: #define SPR_MPC_IC_ADR        (0x231)
 1012: #define SPR_Exxx_DBCR3        (0x231)
 1013: #define SPR_IBAT5U            (0x232)
 1014: #define SPR_MPC_IC_DAT        (0x232)
 1015: #define SPR_Exxx_DBCNT        (0x232)
 1016: #define SPR_IBAT5L            (0x233)
 1017: #define SPR_IBAT6U            (0x234)
 1018: #define SPR_IBAT6L            (0x235)
 1019: #define SPR_IBAT7U            (0x236)
 1020: #define SPR_IBAT7L            (0x237)
 1021: #define SPR_DBAT4U            (0x238)
 1022: #define SPR_RCPU_L2U_MCR      (0x238)
 1023: #define SPR_MPC_DC_CST        (0x238)
 1024: #define SPR_Exxx_ALTCTXCR     (0x238)
 1025: #define SPR_DBAT4L            (0x239)
 1026: #define SPR_MPC_DC_ADR        (0x239)
 1027: #define SPR_DBAT5U            (0x23A)
 1028: #define SPR_BOOKE_MCSRR0      (0x23A)
 1029: #define SPR_MPC_DC_DAT        (0x23A)
 1030: #define SPR_DBAT5L            (0x23B)
 1031: #define SPR_BOOKE_MCSRR1      (0x23B)
 1032: #define SPR_DBAT6U            (0x23C)
 1033: #define SPR_BOOKE_MCSR        (0x23C)
 1034: #define SPR_DBAT6L            (0x23D)
 1035: #define SPR_Exxx_MCAR         (0x23D)
 1036: #define SPR_DBAT7U            (0x23E)
 1037: #define SPR_BOOKE_DSRR0       (0x23E)
 1038: #define SPR_DBAT7L            (0x23F)
 1039: #define SPR_BOOKE_DSRR1       (0x23F)
 1040: #define SPR_BOOKE_SPRG8       (0x25C)
 1041: #define SPR_BOOKE_SPRG9       (0x25D)
 1042: #define SPR_BOOKE_MAS0        (0x270)
 1043: #define SPR_BOOKE_MAS1        (0x271)
 1044: #define SPR_BOOKE_MAS2        (0x272)
 1045: #define SPR_BOOKE_MAS3        (0x273)
 1046: #define SPR_BOOKE_MAS4        (0x274)
 1047: #define SPR_BOOKE_MAS5        (0x275)
 1048: #define SPR_BOOKE_MAS6        (0x276)
 1049: #define SPR_BOOKE_PID1        (0x279)
 1050: #define SPR_BOOKE_PID2        (0x27A)
 1051: #define SPR_MPC_DPDR          (0x280)
 1052: #define SPR_MPC_IMMR          (0x288)
 1053: #define SPR_BOOKE_TLB0CFG     (0x2B0)
 1054: #define SPR_BOOKE_TLB1CFG     (0x2B1)
 1055: #define SPR_BOOKE_TLB2CFG     (0x2B2)
 1056: #define SPR_BOOKE_TLB3CFG     (0x2B3)
 1057: #define SPR_BOOKE_EPR         (0x2BE)
 1058: #define SPR_PERF0             (0x300)
 1059: #define SPR_RCPU_MI_RBA0      (0x300)
 1060: #define SPR_MPC_MI_CTR        (0x300)
 1061: #define SPR_PERF1             (0x301)
 1062: #define SPR_RCPU_MI_RBA1      (0x301)
 1063: #define SPR_PERF2             (0x302)
 1064: #define SPR_RCPU_MI_RBA2      (0x302)
 1065: #define SPR_MPC_MI_AP         (0x302)
 1066: #define SPR_PERF3             (0x303)
 1067: #define SPR_620_PMC1R         (0x303)
 1068: #define SPR_RCPU_MI_RBA3      (0x303)
 1069: #define SPR_MPC_MI_EPN        (0x303)
 1070: #define SPR_PERF4             (0x304)
 1071: #define SPR_620_PMC2R         (0x304)
 1072: #define SPR_PERF5             (0x305)
 1073: #define SPR_MPC_MI_TWC        (0x305)
 1074: #define SPR_PERF6             (0x306)
 1075: #define SPR_MPC_MI_RPN        (0x306)
 1076: #define SPR_PERF7             (0x307)
 1077: #define SPR_PERF8             (0x308)
 1078: #define SPR_RCPU_L2U_RBA0     (0x308)
 1079: #define SPR_MPC_MD_CTR        (0x308)
 1080: #define SPR_PERF9             (0x309)
 1081: #define SPR_RCPU_L2U_RBA1     (0x309)
 1082: #define SPR_MPC_MD_CASID      (0x309)
 1083: #define SPR_PERFA             (0x30A)
 1084: #define SPR_RCPU_L2U_RBA2     (0x30A)
 1085: #define SPR_MPC_MD_AP         (0x30A)
 1086: #define SPR_PERFB             (0x30B)
 1087: #define SPR_620_MMCR0R        (0x30B)
 1088: #define SPR_RCPU_L2U_RBA3     (0x30B)
 1089: #define SPR_MPC_MD_EPN        (0x30B)
 1090: #define SPR_PERFC             (0x30C)
 1091: #define SPR_MPC_MD_TWB        (0x30C)
 1092: #define SPR_PERFD             (0x30D)
 1093: #define SPR_MPC_MD_TWC        (0x30D)
 1094: #define SPR_PERFE             (0x30E)
 1095: #define SPR_MPC_MD_RPN        (0x30E)
 1096: #define SPR_PERFF             (0x30F)
 1097: #define SPR_MPC_MD_TW         (0x30F)
 1098: #define SPR_UPERF0            (0x310)
 1099: #define SPR_UPERF1            (0x311)
 1100: #define SPR_UPERF2            (0x312)
 1101: #define SPR_UPERF3            (0x313)
 1102: #define SPR_620_PMC1W         (0x313)
 1103: #define SPR_UPERF4            (0x314)
 1104: #define SPR_620_PMC2W         (0x314)
 1105: #define SPR_UPERF5            (0x315)
 1106: #define SPR_UPERF6            (0x316)
 1107: #define SPR_UPERF7            (0x317)
 1108: #define SPR_UPERF8            (0x318)
 1109: #define SPR_UPERF9            (0x319)
 1110: #define SPR_UPERFA            (0x31A)
 1111: #define SPR_UPERFB            (0x31B)
 1112: #define SPR_620_MMCR0W        (0x31B)
 1113: #define SPR_UPERFC            (0x31C)
 1114: #define SPR_UPERFD            (0x31D)
 1115: #define SPR_UPERFE            (0x31E)
 1116: #define SPR_UPERFF            (0x31F)
 1117: #define SPR_RCPU_MI_RA0       (0x320)
 1118: #define SPR_MPC_MI_DBCAM      (0x320)
 1119: #define SPR_RCPU_MI_RA1       (0x321)
 1120: #define SPR_MPC_MI_DBRAM0     (0x321)
 1121: #define SPR_RCPU_MI_RA2       (0x322)
 1122: #define SPR_MPC_MI_DBRAM1     (0x322)
 1123: #define SPR_RCPU_MI_RA3       (0x323)
 1124: #define SPR_RCPU_L2U_RA0      (0x328)
 1125: #define SPR_MPC_MD_DBCAM      (0x328)
 1126: #define SPR_RCPU_L2U_RA1      (0x329)
 1127: #define SPR_MPC_MD_DBRAM0     (0x329)
 1128: #define SPR_RCPU_L2U_RA2      (0x32A)
 1129: #define SPR_MPC_MD_DBRAM1     (0x32A)
 1130: #define SPR_RCPU_L2U_RA3      (0x32B)
 1131: #define SPR_440_INV0          (0x370)
 1132: #define SPR_440_INV1          (0x371)
 1133: #define SPR_440_INV2          (0x372)
 1134: #define SPR_440_INV3          (0x373)
 1135: #define SPR_440_ITV0          (0x374)
 1136: #define SPR_440_ITV1          (0x375)
 1137: #define SPR_440_ITV2          (0x376)
 1138: #define SPR_440_ITV3          (0x377)
 1139: #define SPR_440_CCR1          (0x378)
 1140: #define SPR_DCRIPR            (0x37B)
 1141: #define SPR_PPR               (0x380)
 1142: #define SPR_750_GQR0          (0x390)
 1143: #define SPR_440_DNV0          (0x390)
 1144: #define SPR_750_GQR1          (0x391)
 1145: #define SPR_440_DNV1          (0x391)
 1146: #define SPR_750_GQR2          (0x392)
 1147: #define SPR_440_DNV2          (0x392)
 1148: #define SPR_750_GQR3          (0x393)
 1149: #define SPR_440_DNV3          (0x393)
 1150: #define SPR_750_GQR4          (0x394)
 1151: #define SPR_440_DTV0          (0x394)
 1152: #define SPR_750_GQR5          (0x395)
 1153: #define SPR_440_DTV1          (0x395)
 1154: #define SPR_750_GQR6          (0x396)
 1155: #define SPR_440_DTV2          (0x396)
 1156: #define SPR_750_GQR7          (0x397)
 1157: #define SPR_440_DTV3          (0x397)
 1158: #define SPR_750_THRM4         (0x398)
 1159: #define SPR_750CL_HID2        (0x398)
 1160: #define SPR_440_DVLIM         (0x398)
 1161: #define SPR_750_WPAR          (0x399)
 1162: #define SPR_440_IVLIM         (0x399)
 1163: #define SPR_750_DMAU          (0x39A)
 1164: #define SPR_750_DMAL          (0x39B)
 1165: #define SPR_440_RSTCFG        (0x39B)
 1166: #define SPR_BOOKE_DCDBTRL     (0x39C)
 1167: #define SPR_BOOKE_DCDBTRH     (0x39D)
 1168: #define SPR_BOOKE_ICDBTRL     (0x39E)
 1169: #define SPR_BOOKE_ICDBTRH     (0x39F)
 1170: #define SPR_UMMCR2            (0x3A0)
 1171: #define SPR_UPMC5             (0x3A1)
 1172: #define SPR_UPMC6             (0x3A2)
 1173: #define SPR_UBAMR             (0x3A7)
 1174: #define SPR_UMMCR0            (0x3A8)
 1175: #define SPR_UPMC1             (0x3A9)
 1176: #define SPR_UPMC2             (0x3AA)
 1177: #define SPR_USIAR             (0x3AB)
 1178: #define SPR_UMMCR1            (0x3AC)
 1179: #define SPR_UPMC3             (0x3AD)
 1180: #define SPR_UPMC4             (0x3AE)
 1181: #define SPR_USDA              (0x3AF)
 1182: #define SPR_40x_ZPR           (0x3B0)
 1183: #define SPR_BOOKE_MAS7        (0x3B0)
 1184: #define SPR_620_PMR0          (0x3B0)
 1185: #define SPR_MMCR2             (0x3B0)
 1186: #define SPR_PMC5              (0x3B1)
 1187: #define SPR_40x_PID           (0x3B1)
 1188: #define SPR_620_PMR1          (0x3B1)
 1189: #define SPR_PMC6              (0x3B2)
 1190: #define SPR_440_MMUCR         (0x3B2)
 1191: #define SPR_620_PMR2          (0x3B2)
 1192: #define SPR_4xx_CCR0          (0x3B3)
 1193: #define SPR_BOOKE_EPLC        (0x3B3)
 1194: #define SPR_620_PMR3          (0x3B3)
 1195: #define SPR_405_IAC3          (0x3B4)
 1196: #define SPR_BOOKE_EPSC        (0x3B4)
 1197: #define SPR_620_PMR4          (0x3B4)
 1198: #define SPR_405_IAC4          (0x3B5)
 1199: #define SPR_620_PMR5          (0x3B5)
 1200: #define SPR_405_DVC1          (0x3B6)
 1201: #define SPR_620_PMR6          (0x3B6)
 1202: #define SPR_405_DVC2          (0x3B7)
 1203: #define SPR_620_PMR7          (0x3B7)
 1204: #define SPR_BAMR              (0x3B7)
 1205: #define SPR_MMCR0             (0x3B8)
 1206: #define SPR_620_PMR8          (0x3B8)
 1207: #define SPR_PMC1              (0x3B9)
 1208: #define SPR_40x_SGR           (0x3B9)
 1209: #define SPR_620_PMR9          (0x3B9)
 1210: #define SPR_PMC2              (0x3BA)
 1211: #define SPR_40x_DCWR          (0x3BA)
 1212: #define SPR_620_PMRA          (0x3BA)
 1213: #define SPR_SIAR              (0x3BB)
 1214: #define SPR_405_SLER          (0x3BB)
 1215: #define SPR_620_PMRB          (0x3BB)
 1216: #define SPR_MMCR1             (0x3BC)
 1217: #define SPR_405_SU0R          (0x3BC)
 1218: #define SPR_620_PMRC          (0x3BC)
 1219: #define SPR_401_SKR           (0x3BC)
 1220: #define SPR_PMC3              (0x3BD)
 1221: #define SPR_405_DBCR1         (0x3BD)
 1222: #define SPR_620_PMRD          (0x3BD)
 1223: #define SPR_PMC4              (0x3BE)
 1224: #define SPR_620_PMRE          (0x3BE)
 1225: #define SPR_SDA               (0x3BF)
 1226: #define SPR_620_PMRF          (0x3BF)
 1227: #define SPR_403_VTBL          (0x3CC)
 1228: #define SPR_403_VTBU          (0x3CD)
 1229: #define SPR_DMISS             (0x3D0)
 1230: #define SPR_DCMP              (0x3D1)
 1231: #define SPR_HASH1             (0x3D2)
 1232: #define SPR_HASH2             (0x3D3)
 1233: #define SPR_BOOKE_ICDBDR      (0x3D3)
 1234: #define SPR_TLBMISS           (0x3D4)
 1235: #define SPR_IMISS             (0x3D4)
 1236: #define SPR_40x_ESR           (0x3D4)
 1237: #define SPR_PTEHI             (0x3D5)
 1238: #define SPR_ICMP              (0x3D5)
 1239: #define SPR_40x_DEAR          (0x3D5)
 1240: #define SPR_PTELO             (0x3D6)
 1241: #define SPR_RPA               (0x3D6)
 1242: #define SPR_40x_EVPR          (0x3D6)
 1243: #define SPR_L3PM              (0x3D7)
 1244: #define SPR_403_CDBCR         (0x3D7)
 1245: #define SPR_L3ITCR0           (0x3D8)
 1246: #define SPR_TCR               (0x3D8)
 1247: #define SPR_40x_TSR           (0x3D8)
 1248: #define SPR_IBR               (0x3DA)
 1249: #define SPR_40x_TCR           (0x3DA)
 1250: #define SPR_ESASRR            (0x3DB)
 1251: #define SPR_40x_PIT           (0x3DB)
 1252: #define SPR_403_TBL           (0x3DC)
 1253: #define SPR_403_TBU           (0x3DD)
 1254: #define SPR_SEBR              (0x3DE)
 1255: #define SPR_40x_SRR2          (0x3DE)
 1256: #define SPR_SER               (0x3DF)
 1257: #define SPR_40x_SRR3          (0x3DF)
 1258: #define SPR_L3OHCR            (0x3E8)
 1259: #define SPR_L3ITCR1           (0x3E9)
 1260: #define SPR_L3ITCR2           (0x3EA)
 1261: #define SPR_L3ITCR3           (0x3EB)
 1262: #define SPR_HID0              (0x3F0)
 1263: #define SPR_40x_DBSR          (0x3F0)
 1264: #define SPR_HID1              (0x3F1)
 1265: #define SPR_IABR              (0x3F2)
 1266: #define SPR_40x_DBCR0         (0x3F2)
 1267: #define SPR_601_HID2          (0x3F2)
 1268: #define SPR_Exxx_L1CSR0       (0x3F2)
 1269: #define SPR_ICTRL             (0x3F3)
 1270: #define SPR_HID2              (0x3F3)
 1271: #define SPR_750CL_HID4        (0x3F3)
 1272: #define SPR_Exxx_L1CSR1       (0x3F3)
 1273: #define SPR_440_DBDR          (0x3F3)
 1274: #define SPR_LDSTDB            (0x3F4)
 1275: #define SPR_750_TDCL          (0x3F4)
 1276: #define SPR_40x_IAC1          (0x3F4)
 1277: #define SPR_MMUCSR0           (0x3F4)
 1278: #define SPR_DABR              (0x3F5)
 1279: #define DABR_MASK (~(target_ulong)0x7)
 1280: #define SPR_Exxx_BUCSR        (0x3F5)
 1281: #define SPR_40x_IAC2          (0x3F5)
 1282: #define SPR_601_HID5          (0x3F5)
 1283: #define SPR_40x_DAC1          (0x3F6)
 1284: #define SPR_MSSCR0            (0x3F6)
 1285: #define SPR_970_HID5          (0x3F6)
 1286: #define SPR_MSSSR0            (0x3F7)
 1287: #define SPR_MSSCR1            (0x3F7)
 1288: #define SPR_DABRX             (0x3F7)
 1289: #define SPR_40x_DAC2          (0x3F7)
 1290: #define SPR_MMUCFG            (0x3F7)
 1291: #define SPR_LDSTCR            (0x3F8)
 1292: #define SPR_L2PMCR            (0x3F8)
 1293: #define SPR_750FX_HID2        (0x3F8)
 1294: #define SPR_620_BUSCSR        (0x3F8)
 1295: #define SPR_Exxx_L1FINV0      (0x3F8)
 1296: #define SPR_L2CR              (0x3F9)
 1297: #define SPR_620_L2CR          (0x3F9)
 1298: #define SPR_L3CR              (0x3FA)
 1299: #define SPR_750_TDCH          (0x3FA)
 1300: #define SPR_IABR2             (0x3FA)
 1301: #define SPR_40x_DCCR          (0x3FA)
 1302: #define SPR_620_L2SR          (0x3FA)
 1303: #define SPR_ICTC              (0x3FB)
 1304: #define SPR_40x_ICCR          (0x3FB)
 1305: #define SPR_THRM1             (0x3FC)
 1306: #define SPR_403_PBL1          (0x3FC)
 1307: #define SPR_SP                (0x3FD)
 1308: #define SPR_THRM2             (0x3FD)
 1309: #define SPR_403_PBU1          (0x3FD)
 1310: #define SPR_604_HID13         (0x3FD)
 1311: #define SPR_LT                (0x3FE)
 1312: #define SPR_THRM3             (0x3FE)
 1313: #define SPR_RCPU_FPECR        (0x3FE)
 1314: #define SPR_403_PBL2          (0x3FE)
 1315: #define SPR_PIR               (0x3FF)
 1316: #define SPR_403_PBU2          (0x3FF)
 1317: #define SPR_601_HID15         (0x3FF)
 1318: #define SPR_604_HID15         (0x3FF)
 1319: #define SPR_E500_SVR          (0x3FF)
 1320: 
 1321: /*****************************************************************************/
 1322: /* PowerPC Instructions types definitions                                    */
 1323: enum {
 1324:     PPC_NONE           = 0x0000000000000000ULL,
 1325:     /* PowerPC base instructions set                                         */
 1326:     PPC_INSNS_BASE     = 0x0000000000000001ULL,
 1327:     /*   integer operations instructions                                     */
 1328: #define PPC_INTEGER PPC_INSNS_BASE
 1329:     /*   flow control instructions                                           */
 1330: #define PPC_FLOW    PPC_INSNS_BASE
 1331:     /*   virtual memory instructions                                         */
 1332: #define PPC_MEM     PPC_INSNS_BASE
 1333:     /*   ld/st with reservation instructions                                 */
 1334: #define PPC_RES     PPC_INSNS_BASE
 1335:     /*   spr/msr access instructions                                         */
 1336: #define PPC_MISC    PPC_INSNS_BASE
 1337:     /* Deprecated instruction sets                                           */
 1338:     /*   Original POWER instruction set                                      */
 1339:     PPC_POWER          = 0x0000000000000002ULL,
 1340:     /*   POWER2 instruction set extension                                    */
 1341:     PPC_POWER2         = 0x0000000000000004ULL,
 1342:     /*   Power RTC support                                                   */
 1343:     PPC_POWER_RTC      = 0x0000000000000008ULL,
 1344:     /*   Power-to-PowerPC bridge (601)                                       */
 1345:     PPC_POWER_BR       = 0x0000000000000010ULL,
 1346:     /* 64 bits PowerPC instruction set                                       */
 1347:     PPC_64B            = 0x0000000000000020ULL,
 1348:     /*   New 64 bits extensions (PowerPC 2.0x)                               */
 1349:     PPC_64BX           = 0x0000000000000040ULL,
 1350:     /*   64 bits hypervisor extensions                                       */
 1351:     PPC_64H            = 0x0000000000000080ULL,
 1352:     /*   New wait instruction (PowerPC 2.0x)                                 */
 1353:     PPC_WAIT           = 0x0000000000000100ULL,
 1354:     /*   Time base mftb instruction                                          */
 1355:     PPC_MFTB           = 0x0000000000000200ULL,
 1356: 
 1357:     /* Fixed-point unit extensions                                           */
 1358:     /*   PowerPC 602 specific                                                */
 1359:     PPC_602_SPEC       = 0x0000000000000400ULL,
 1360:     /*   isel instruction                                                    */
 1361:     PPC_ISEL           = 0x0000000000000800ULL,
 1362:     /*   popcntb instruction                                                 */
 1363:     PPC_POPCNTB        = 0x0000000000001000ULL,
 1364:     /*   string load / store                                                 */
 1365:     PPC_STRING         = 0x0000000000002000ULL,
 1366: 
 1367:     /* Floating-point unit extensions                                        */
 1368:     /*   Optional floating point instructions                                */
 1369:     PPC_FLOAT          = 0x0000000000010000ULL,
 1370:     /* New floating-point extensions (PowerPC 2.0x)                          */
 1371:     PPC_FLOAT_EXT      = 0x0000000000020000ULL,
 1372:     PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
 1373:     PPC_FLOAT_FRES     = 0x0000000000080000ULL,
 1374:     PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
 1375:     PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
 1376:     PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
 1377:     PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
 1378: 
 1379:     /* Vector/SIMD extensions                                                */
 1380:     /*   Altivec support                                                     */
 1381:     PPC_ALTIVEC        = 0x0000000001000000ULL,
 1382:     /*   PowerPC 2.03 SPE extension                                          */
 1383:     PPC_SPE            = 0x0000000002000000ULL,
 1384:     /*   PowerPC 2.03 SPE single-precision floating-point extension          */
 1385:     PPC_SPE_SINGLE     = 0x0000000004000000ULL,
 1386:     /*   PowerPC 2.03 SPE double-precision floating-point extension          */
 1387:     PPC_SPE_DOUBLE     = 0x0000000008000000ULL,
 1388: 
 1389:     /* Optional memory control instructions                                  */
 1390:     PPC_MEM_TLBIA      = 0x0000000010000000ULL,
 1391:     PPC_MEM_TLBIE      = 0x0000000020000000ULL,
 1392:     PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
 1393:     /*   sync instruction                                                    */
 1394:     PPC_MEM_SYNC       = 0x0000000080000000ULL,
 1395:     /*   eieio instruction                                                   */
 1396:     PPC_MEM_EIEIO      = 0x0000000100000000ULL,
 1397: 
 1398:     /* Cache control instructions                                            */
 1399:     PPC_CACHE          = 0x0000000200000000ULL,
 1400:     /*   icbi instruction                                                    */
 1401:     PPC_CACHE_ICBI     = 0x0000000400000000ULL,
 1402:     /*   dcbz instruction with fixed cache line size                         */
 1403:     PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
 1404:     /*   dcbz instruction with tunable cache line size                       */
 1405:     PPC_CACHE_DCBZT    = 0x0000001000000000ULL,
 1406:     /*   dcba instruction                                                    */
 1407:     PPC_CACHE_DCBA     = 0x0000002000000000ULL,
 1408:     /*   Freescale cache locking instructions                                */
 1409:     PPC_CACHE_LOCK     = 0x0000004000000000ULL,
 1410: 
 1411:     /* MMU related extensions                                                */
 1412:     /*   external control instructions                                       */
 1413:     PPC_EXTERN         = 0x0000010000000000ULL,
 1414:     /*   segment register access instructions                                */
 1415:     PPC_SEGMENT        = 0x0000020000000000ULL,
 1416:     /*   PowerPC 6xx TLB management instructions                             */
 1417:     PPC_6xx_TLB        = 0x0000040000000000ULL,
 1418:     /* PowerPC 74xx TLB management instructions                              */
 1419:     PPC_74xx_TLB       = 0x0000080000000000ULL,
 1420:     /*   PowerPC 40x TLB management instructions                             */
 1421:     PPC_40x_TLB        = 0x0000100000000000ULL,
 1422:     /*   segment register access instructions for PowerPC 64 "bridge"        */
 1423:     PPC_SEGMENT_64B    = 0x0000200000000000ULL,
 1424:     /*   SLB management                                                      */
 1425:     PPC_SLBI           = 0x0000400000000000ULL,
 1426: 
 1427:     /* Embedded PowerPC dedicated instructions                               */
 1428:     PPC_WRTEE          = 0x0001000000000000ULL,
 1429:     /* PowerPC 40x exception model                                           */
 1430:     PPC_40x_EXCP       = 0x0002000000000000ULL,
 1431:     /* PowerPC 405 Mac instructions                                          */
 1432:     PPC_405_MAC        = 0x0004000000000000ULL,
 1433:     /* PowerPC 440 specific instructions                                     */
 1434:     PPC_440_SPEC       = 0x0008000000000000ULL,
 1435:     /* BookE (embedded) PowerPC specification                                */
 1436:     PPC_BOOKE          = 0x0010000000000000ULL,
 1437:     /* mfapidi instruction                                                   */
 1438:     PPC_MFAPIDI        = 0x0020000000000000ULL,
 1439:     /* tlbiva instruction                                                    */
 1440:     PPC_TLBIVA         = 0x0040000000000000ULL,
 1441:     /* tlbivax instruction                                                   */
 1442:     PPC_TLBIVAX        = 0x0080000000000000ULL,
 1443:     /* PowerPC 4xx dedicated instructions                                    */
 1444:     PPC_4xx_COMMON     = 0x0100000000000000ULL,
 1445:     /* PowerPC 40x ibct instructions                                         */
 1446:     PPC_40x_ICBT       = 0x0200000000000000ULL,
 1447:     /* rfmci is not implemented in all BookE PowerPC                         */
 1448:     PPC_RFMCI          = 0x0400000000000000ULL,
 1449:     /* rfdi instruction                                                      */
 1450:     PPC_RFDI           = 0x0800000000000000ULL,
 1451:     /* DCR accesses                                                          */
 1452:     PPC_DCR            = 0x1000000000000000ULL,
 1453:     /* DCR extended accesse                                                  */
 1454:     PPC_DCRX           = 0x2000000000000000ULL,
 1455:     /* user-mode DCR access, implemented in PowerPC 460                      */
 1456:     PPC_DCRUX          = 0x4000000000000000ULL,
 1457: };
 1458: 
 1459: /*****************************************************************************/
 1460: /* Memory access type :
 1461:  * may be needed for precise access rights control and precise exceptions.
 1462:  */
 1463: enum {
 1464:     /* 1 bit to define user level / supervisor access */
 1465:     ACCESS_USER  = 0x00,
 1466:     ACCESS_SUPER = 0x01,
 1467:     /* Type of instruction that generated the access */
 1468:     ACCESS_CODE  = 0x10, /* Code fetch access                */
 1469:     ACCESS_INT   = 0x20, /* Integer load/store access        */
 1470:     ACCESS_FLOAT = 0x30, /* floating point load/store access */
 1471:     ACCESS_RES   = 0x40, /* load/store with reservation      */
 1472:     ACCESS_EXT   = 0x50, /* external access                  */
 1473:     ACCESS_CACHE = 0x60, /* Cache manipulation               */
 1474: };
 1475: 
 1476: /* Hardware interruption sources:
 1477:  * all those exception can be raised simulteaneously
 1478:  */
 1479: /* Input pins definitions */
 1480: enum {
 1481:     /* 6xx bus input pins */
 1482:     PPC6xx_INPUT_HRESET     = 0,
 1483:     PPC6xx_INPUT_SRESET     = 1,
 1484:     PPC6xx_INPUT_CKSTP_IN   = 2,
 1485:     PPC6xx_INPUT_MCP        = 3,
 1486:     PPC6xx_INPUT_SMI        = 4,
 1487:     PPC6xx_INPUT_INT        = 5,
 1488:     PPC6xx_INPUT_TBEN       = 6,
 1489:     PPC6xx_INPUT_WAKEUP     = 7,
 1490:     PPC6xx_INPUT_NB,
 1491: };
 1492: 
 1493: enum {
 1494:     /* Embedded PowerPC input pins */
 1495:     PPCBookE_INPUT_HRESET     = 0,
 1496:     PPCBookE_INPUT_SRESET     = 1,
 1497:     PPCBookE_INPUT_CKSTP_IN   = 2,
 1498:     PPCBookE_INPUT_MCP        = 3,
 1499:     PPCBookE_INPUT_SMI        = 4,
 1500:     PPCBookE_INPUT_INT        = 5,
 1501:     PPCBookE_INPUT_CINT       = 6,
 1502:     PPCBookE_INPUT_NB,
 1503: };
 1504: 
 1505: enum {
 1506:     /* PowerPC E500 input pins */
 1507:     PPCE500_INPUT_RESET_CORE = 0,
 1508:     PPCE500_INPUT_MCK        = 1,
 1509:     PPCE500_INPUT_CINT       = 3,
 1510:     PPCE500_INPUT_INT        = 4,
 1511:     PPCE500_INPUT_DEBUG      = 6,
 1512:     PPCE500_INPUT_NB,
 1513: };
 1514: 
 1515: enum {
 1516:     /* PowerPC 40x input pins */
 1517:     PPC40x_INPUT_RESET_CORE = 0,
 1518:     PPC40x_INPUT_RESET_CHIP = 1,
 1519:     PPC40x_INPUT_RESET_SYS  = 2,
 1520:     PPC40x_INPUT_CINT       = 3,
 1521:     PPC40x_INPUT_INT        = 4,
 1522:     PPC40x_INPUT_HALT       = 5,
 1523:     PPC40x_INPUT_DEBUG      = 6,
 1524:     PPC40x_INPUT_NB,
 1525: };
 1526: 
 1527: enum {
 1528:     /* RCPU input pins */
 1529:     PPCRCPU_INPUT_PORESET   = 0,
 1530:     PPCRCPU_INPUT_HRESET    = 1,
 1531:     PPCRCPU_INPUT_SRESET    = 2,
 1532:     PPCRCPU_INPUT_IRQ0      = 3,
 1533:     PPCRCPU_INPUT_IRQ1      = 4,
 1534:     PPCRCPU_INPUT_IRQ2      = 5,
 1535:     PPCRCPU_INPUT_IRQ3      = 6,
 1536:     PPCRCPU_INPUT_IRQ4      = 7,
 1537:     PPCRCPU_INPUT_IRQ5      = 8,
 1538:     PPCRCPU_INPUT_IRQ6      = 9,
 1539:     PPCRCPU_INPUT_IRQ7      = 10,
 1540:     PPCRCPU_INPUT_NB,
 1541: };
 1542: 
 1543: #if defined(TARGET_PPC64)
 1544: enum {
 1545:     /* PowerPC 970 input pins */
 1546:     PPC970_INPUT_HRESET     = 0,
 1547:     PPC970_INPUT_SRESET     = 1,
 1548:     PPC970_INPUT_CKSTP      = 2,
 1549:     PPC970_INPUT_TBEN       = 3,
 1550:     PPC970_INPUT_MCP        = 4,
 1551:     PPC970_INPUT_INT        = 5,
 1552:     PPC970_INPUT_THINT      = 6,
 1553:     PPC970_INPUT_NB,
 1554: };
 1555: #endif
 1556: 
 1557: /* Hardware exceptions definitions */
 1558: enum {
 1559:     /* External hardware exception sources */
 1560:     PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
 1561:     PPC_INTERRUPT_WAKEUP,         /* Wakeup exception                     */
 1562:     PPC_INTERRUPT_MCK,            /* Machine check exception              */
 1563:     PPC_INTERRUPT_EXT,            /* External interrupt                   */
 1564:     PPC_INTERRUPT_SMI,            /* System management interrupt          */
 1565:     PPC_INTERRUPT_CEXT,           /* Critical external interrupt          */
 1566:     PPC_INTERRUPT_DEBUG,          /* External debug exception             */
 1567:     PPC_INTERRUPT_THERM,          /* Thermal exception                    */
 1568:     /* Internal hardware exception sources */
 1569:     PPC_INTERRUPT_DECR,           /* Decrementer exception                */
 1570:     PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
 1571:     PPC_INTERRUPT_PIT,            /* Programmable inteval timer interrupt */
 1572:     PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
 1573:     PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
 1574:     PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
 1575:     PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
 1576:     PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
 1577: };
 1578: 
 1579: /*****************************************************************************/
 1580: 
 1581: static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 1582: {
 1583:     env->nip = tb->pc;
 1584: }
 1585: 
 1586: static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 1587:                                         target_ulong *cs_base, int *flags)
 1588: {
 1589:     *pc = env->nip;
 1590:     *cs_base = 0;
 1591:     *flags = env->hflags;
 1592: }
 1593: 
 1594: static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
 1595: {
 1596: #if defined(TARGET_PPC64)
 1597:     /* The kernel checks TIF_32BIT here; we don't support loading 32-bit
 1598:        binaries on PPC64 yet. */
 1599:     env->gpr[13] = newtls;
 1600: #else
 1601:     env->gpr[2] = newtls;
 1602: #endif
 1603: }
 1604: 
 1605: #endif /* !defined (__CPU_PPC_H__) */

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