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1.1 root 1: /*
2: * PowerPC emulation helpers for qemu.
3: *
4: * Copyright (c) 2003-2005 Jocelyn Mayer
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
17: * License along with this library; if not, write to the Free Software
18: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19: */
20: #include <stdarg.h>
21: #include <stdlib.h>
22: #include <stdio.h>
23: #include <string.h>
24: #include <inttypes.h>
25: #include <signal.h>
26: #include <assert.h>
27:
28: #include "cpu.h"
29: #include "exec-all.h"
30:
31: //#define DEBUG_MMU
32: //#define DEBUG_BATS
33: //#define DEBUG_EXCEPTIONS
34: //#define FLUSH_ALL_TLBS
35:
36: /*****************************************************************************/
37: /* PowerPC MMU emulation */
38:
39: /* Perform BAT hit & translation */
40: static int get_bat (CPUState *env, uint32_t *real, int *prot,
41: uint32_t virtual, int rw, int type)
42: {
43: uint32_t *BATlt, *BATut, *BATu, *BATl;
44: uint32_t base, BEPIl, BEPIu, bl;
45: int i;
46: int ret = -1;
47:
48: #if defined (DEBUG_BATS)
49: if (loglevel > 0) {
50: fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
51: type == ACCESS_CODE ? 'I' : 'D', virtual);
52: }
53: #endif
54: switch (type) {
55: case ACCESS_CODE:
56: BATlt = env->IBAT[1];
57: BATut = env->IBAT[0];
58: break;
59: default:
60: BATlt = env->DBAT[1];
61: BATut = env->DBAT[0];
62: break;
63: }
64: #if defined (DEBUG_BATS)
65: if (loglevel > 0) {
66: fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
67: type == ACCESS_CODE ? 'I' : 'D', virtual);
68: }
69: #endif
70: base = virtual & 0xFFFC0000;
71: for (i = 0; i < 4; i++) {
72: BATu = &BATut[i];
73: BATl = &BATlt[i];
74: BEPIu = *BATu & 0xF0000000;
75: BEPIl = *BATu & 0x0FFE0000;
76: bl = (*BATu & 0x00001FFC) << 15;
77: #if defined (DEBUG_BATS)
78: if (loglevel > 0) {
79: fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
80: __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
81: *BATu, *BATl);
82: }
83: #endif
84: if ((virtual & 0xF0000000) == BEPIu &&
85: ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
86: /* BAT matches */
87: if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
88: (msr_pr == 1 && (*BATu & 0x00000001))) {
89: /* Get physical address */
90: *real = (*BATl & 0xF0000000) |
91: ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
92: (virtual & 0x0001F000);
93: if (*BATl & 0x00000001)
94: *prot = PAGE_READ;
95: if (*BATl & 0x00000002)
96: *prot = PAGE_WRITE | PAGE_READ;
97: #if defined (DEBUG_BATS)
98: if (loglevel > 0) {
99: fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
100: i, *real, *prot & PAGE_READ ? 'R' : '-',
101: *prot & PAGE_WRITE ? 'W' : '-');
102: }
103: #endif
104: ret = 0;
105: break;
106: }
107: }
108: }
109: if (ret < 0) {
110: #if defined (DEBUG_BATS)
111: printf("no BAT match for 0x%08x:\n", virtual);
112: for (i = 0; i < 4; i++) {
113: BATu = &BATut[i];
114: BATl = &BATlt[i];
115: BEPIu = *BATu & 0xF0000000;
116: BEPIl = *BATu & 0x0FFE0000;
117: bl = (*BATu & 0x00001FFC) << 15;
118: printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
119: "0x%08x 0x%08x 0x%08x\n",
120: __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
121: *BATu, *BATl, BEPIu, BEPIl, bl);
122: }
123: #endif
124: }
125: /* No hit */
126: return ret;
127: }
128:
129: /* PTE table lookup */
130: static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
131: int h, int key, int rw)
132: {
133: uint32_t pte0, pte1, keep = 0, access = 0;
134: int i, good = -1, store = 0;
135: int ret = -1; /* No entry found */
136:
137: for (i = 0; i < 8; i++) {
138: pte0 = ldl_phys(base + (i * 8));
139: pte1 = ldl_phys(base + (i * 8) + 4);
140: #if defined (DEBUG_MMU)
141: if (loglevel > 0) {
142: fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
143: "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1,
144: pte0 >> 31, h, (pte0 >> 6) & 1, va);
145: }
146: #endif
147: /* Check validity and table match */
148: if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
149: /* Check vsid & api */
150: if ((pte0 & 0x7FFFFFBF) == va) {
151: if (good == -1) {
152: good = i;
153: keep = pte1;
154: } else {
155: /* All matches should have equal RPN, WIMG & PP */
156: if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
157: if (loglevel > 0)
158: fprintf(logfile, "Bad RPN/WIMG/PP\n");
159: return -1;
160: }
161: }
162: /* Check access rights */
163: if (key == 0) {
164: access = PAGE_READ;
165: if ((pte1 & 0x00000003) != 0x3)
166: access |= PAGE_WRITE;
167: } else {
168: switch (pte1 & 0x00000003) {
169: case 0x0:
170: access = 0;
171: break;
172: case 0x1:
173: case 0x3:
174: access = PAGE_READ;
175: break;
176: case 0x2:
177: access = PAGE_READ | PAGE_WRITE;
178: break;
179: }
180: }
181: if (ret < 0) {
182: if ((rw == 0 && (access & PAGE_READ)) ||
183: (rw == 1 && (access & PAGE_WRITE))) {
184: #if defined (DEBUG_MMU)
185: if (loglevel > 0)
186: fprintf(logfile, "PTE access granted !\n");
187: #endif
188: good = i;
189: keep = pte1;
190: ret = 0;
191: } else {
192: /* Access right violation */
193: ret = -2;
194: #if defined (DEBUG_MMU)
195: if (loglevel > 0)
196: fprintf(logfile, "PTE access rejected\n");
197: #endif
198: }
199: *prot = access;
200: }
201: }
202: }
203: }
204: if (good != -1) {
205: *RPN = keep & 0xFFFFF000;
206: #if defined (DEBUG_MMU)
207: if (loglevel > 0) {
208: fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
209: *RPN, *prot, ret);
210: }
211: #endif
212: /* Update page flags */
213: if (!(keep & 0x00000100)) {
214: /* Access flag */
215: keep |= 0x00000100;
216: store = 1;
217: }
218: if (!(keep & 0x00000080)) {
219: if (rw && ret == 0) {
220: /* Change flag */
221: keep |= 0x00000080;
222: store = 1;
223: } else {
224: /* Force page fault for first write access */
225: *prot &= ~PAGE_WRITE;
226: }
227: }
228: if (store) {
229: stl_phys_notdirty(base + (good * 8) + 4, keep);
230: }
231: }
232:
233: return ret;
234: }
235:
236: static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
237: {
238: return (sdr1 & 0xFFFF0000) | (hash & mask);
239: }
240:
241: /* Perform segment based translation */
242: static int get_segment (CPUState *env, uint32_t *real, int *prot,
243: uint32_t virtual, int rw, int type)
244: {
245: uint32_t pg_addr, sdr, ptem, vsid, pgidx;
246: uint32_t hash, mask;
247: uint32_t sr;
248: int key;
249: int ret = -1, ret2;
250:
251: sr = env->sr[virtual >> 28];
252: #if defined (DEBUG_MMU)
253: if (loglevel > 0) {
254: fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
255: "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
256: virtual, virtual >> 28, sr, env->nip,
257: env->lr, msr_ir, msr_dr, msr_pr, rw, type);
258: }
259: #endif
260: key = (((sr & 0x20000000) && msr_pr == 1) ||
261: ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
262: if ((sr & 0x80000000) == 0) {
263: #if defined (DEBUG_MMU)
264: if (loglevel > 0)
265: fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
266: key, sr & 0x10000000);
267: #endif
268: /* Check if instruction fetch is allowed, if needed */
269: if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
270: /* Page address translation */
271: vsid = sr & 0x00FFFFFF;
272: pgidx = (virtual >> 12) & 0xFFFF;
273: sdr = env->sdr1;
274: hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
275: mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
276: pg_addr = get_pgaddr(sdr, hash, mask);
277: ptem = (vsid << 7) | (pgidx >> 10);
278: #if defined (DEBUG_MMU)
279: if (loglevel > 0) {
280: fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
281: "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
282: pg_addr);
283: }
284: #endif
285: /* Primary table lookup */
286: ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
287: if (ret < 0) {
288: /* Secondary table lookup */
289: hash = (~hash) & 0x01FFFFC0;
290: pg_addr = get_pgaddr(sdr, hash, mask);
291: #if defined (DEBUG_MMU)
292: if (virtual != 0xEFFFFFFF && loglevel > 0) {
293: fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
294: "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
295: hash, pg_addr);
296: }
297: #endif
298: ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
299: if (ret2 != -1)
300: ret = ret2;
301: }
302: } else {
303: #if defined (DEBUG_MMU)
304: if (loglevel > 0)
305: fprintf(logfile, "No access allowed\n");
306: #endif
307: ret = -3;
308: }
309: } else {
310: #if defined (DEBUG_MMU)
311: if (loglevel > 0)
312: fprintf(logfile, "direct store...\n");
313: #endif
314: /* Direct-store segment : absolutely *BUGGY* for now */
315: switch (type) {
316: case ACCESS_INT:
317: /* Integer load/store : only access allowed */
318: break;
319: case ACCESS_CODE:
320: /* No code fetch is allowed in direct-store areas */
321: return -4;
322: case ACCESS_FLOAT:
323: /* Floating point load/store */
324: return -4;
325: case ACCESS_RES:
326: /* lwarx, ldarx or srwcx. */
327: return -4;
328: case ACCESS_CACHE:
329: /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
330: /* Should make the instruction do no-op.
331: * As it already do no-op, it's quite easy :-)
332: */
333: *real = virtual;
334: return 0;
335: case ACCESS_EXT:
336: /* eciwx or ecowx */
337: return -4;
338: default:
339: if (logfile) {
340: fprintf(logfile, "ERROR: instruction should not need "
341: "address translation\n");
342: }
343: printf("ERROR: instruction should not need "
344: "address translation\n");
345: return -4;
346: }
347: if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
348: *real = virtual;
349: ret = 2;
350: } else {
351: ret = -2;
352: }
353: }
354:
355: return ret;
356: }
357:
358: int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
359: uint32_t address, int rw, int access_type)
360: {
361: int ret;
362: #if 0
363: if (loglevel > 0) {
364: fprintf(logfile, "%s\n", __func__);
365: }
366: #endif
367: if ((access_type == ACCESS_CODE && msr_ir == 0) ||
368: (access_type != ACCESS_CODE && msr_dr == 0)) {
369: /* No address translation */
370: *physical = address & ~0xFFF;
371: *prot = PAGE_READ | PAGE_WRITE;
372: ret = 0;
373: } else {
374: /* Try to find a BAT */
375: ret = get_bat(env, physical, prot, address, rw, access_type);
376: if (ret < 0) {
377: /* We didn't match any BAT entry */
378: ret = get_segment(env, physical, prot, address, rw, access_type);
379: }
380: }
381: #if 0
382: if (loglevel > 0) {
383: fprintf(logfile, "%s address %08x => %08x\n",
384: __func__, address, *physical);
385: }
386: #endif
387: return ret;
388: }
389:
390: #if defined(CONFIG_USER_ONLY)
391: target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
392: {
393: return addr;
394: }
395: #else
396: target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
397: {
398: uint32_t phys_addr;
399: int prot;
400:
401: if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
402: return -1;
403: return phys_addr;
404: }
405: #endif
406:
407: /* Perform address translation */
408: int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
409: int is_user, int is_softmmu)
410: {
411: uint32_t physical;
412: int prot;
413: int exception = 0, error_code = 0;
414: int access_type;
415: int ret = 0;
416:
417: if (rw == 2) {
418: /* code access */
419: rw = 0;
420: access_type = ACCESS_CODE;
421: } else {
422: /* data access */
423: /* XXX: put correct access by using cpu_restore_state()
424: correctly */
425: access_type = ACCESS_INT;
426: // access_type = env->access_type;
427: }
428: if (env->user_mode_only) {
429: /* user mode only emulation */
430: ret = -2;
431: goto do_fault;
432: }
433: ret = get_physical_address(env, &physical, &prot,
434: address, rw, access_type);
435: if (ret == 0) {
436: ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
437: is_user, is_softmmu);
438: } else if (ret < 0) {
439: do_fault:
440: #if defined (DEBUG_MMU)
441: if (loglevel > 0)
442: cpu_dump_state(env, logfile, fprintf, 0);
443: #endif
444: if (access_type == ACCESS_CODE) {
445: exception = EXCP_ISI;
446: switch (ret) {
447: case -1:
448: /* No matches in page tables */
449: error_code = 0x40000000;
450: break;
451: case -2:
452: /* Access rights violation */
453: error_code = 0x08000000;
454: break;
455: case -3:
456: /* No execute protection violation */
457: error_code = 0x10000000;
458: break;
459: case -4:
460: /* Direct store exception */
461: /* No code fetch is allowed in direct-store areas */
462: error_code = 0x10000000;
463: break;
464: case -5:
465: /* No match in segment table */
466: exception = EXCP_ISEG;
467: error_code = 0;
468: break;
469: }
470: } else {
471: exception = EXCP_DSI;
472: switch (ret) {
473: case -1:
474: /* No matches in page tables */
475: error_code = 0x40000000;
476: break;
477: case -2:
478: /* Access rights violation */
479: error_code = 0x08000000;
480: break;
481: case -4:
482: /* Direct store exception */
483: switch (access_type) {
484: case ACCESS_FLOAT:
485: /* Floating point load/store */
486: exception = EXCP_ALIGN;
487: error_code = EXCP_ALIGN_FP;
488: break;
489: case ACCESS_RES:
490: /* lwarx, ldarx or srwcx. */
491: error_code = 0x04000000;
492: break;
493: case ACCESS_EXT:
494: /* eciwx or ecowx */
495: error_code = 0x04100000;
496: break;
497: default:
498: printf("DSI: invalid exception (%d)\n", ret);
499: exception = EXCP_PROGRAM;
500: error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
501: break;
502: }
503: break;
504: case -5:
505: /* No match in segment table */
506: exception = EXCP_DSEG;
507: error_code = 0;
508: break;
509: }
510: if (exception == EXCP_DSI && rw == 1)
511: error_code |= 0x02000000;
512: /* Store fault address */
513: env->spr[SPR_DAR] = address;
514: env->spr[SPR_DSISR] = error_code;
515: }
516: #if 0
517: printf("%s: set exception to %d %02x\n",
518: __func__, exception, error_code);
519: #endif
520: env->exception_index = exception;
521: env->error_code = error_code;
522: ret = 1;
523: }
524: return ret;
525: }
526:
527: /*****************************************************************************/
528: /* BATs management */
529: #if !defined(FLUSH_ALL_TLBS)
530: static inline void do_invalidate_BAT (CPUPPCState *env,
531: target_ulong BATu, target_ulong mask)
532: {
533: target_ulong base, end, page;
534: base = BATu & ~0x0001FFFF;
535: end = base + mask + 0x00020000;
536: #if defined (DEBUG_BATS)
537: if (loglevel != 0)
538: fprintf(logfile, "Flush BAT from %08x to %08x (%08x)\n", base, end, mask);
539: #endif
540: for (page = base; page != end; page += TARGET_PAGE_SIZE)
541: tlb_flush_page(env, page);
542: #if defined (DEBUG_BATS)
543: if (loglevel != 0)
544: fprintf(logfile, "Flush done\n");
545: #endif
546: }
547: #endif
548:
549: static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr,
550: target_ulong value)
551: {
552: #if defined (DEBUG_BATS)
553: if (loglevel != 0) {
554: fprintf(logfile, "Set %cBAT%d%c to 0x%08lx (0x%08lx)\n",
555: ID, nr, ul == 0 ? 'u' : 'l', (unsigned long)value,
556: (unsigned long)env->nip);
557: }
558: #endif
559: }
560:
561: target_ulong do_load_ibatu (CPUPPCState *env, int nr)
562: {
563: return env->IBAT[0][nr];
564: }
565:
566: target_ulong do_load_ibatl (CPUPPCState *env, int nr)
567: {
568: return env->IBAT[1][nr];
569: }
570:
571: void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
572: {
573: target_ulong mask;
574:
575: dump_store_bat(env, 'I', 0, nr, value);
576: if (env->IBAT[0][nr] != value) {
577: mask = (value << 15) & 0x0FFE0000UL;
578: #if !defined(FLUSH_ALL_TLBS)
579: do_invalidate_BAT(env, env->IBAT[0][nr], mask);
580: #endif
581: /* When storing valid upper BAT, mask BEPI and BRPN
582: * and invalidate all TLBs covered by this BAT
583: */
584: mask = (value << 15) & 0x0FFE0000UL;
585: env->IBAT[0][nr] = (value & 0x00001FFFUL) |
586: (value & ~0x0001FFFFUL & ~mask);
587: env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
588: (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
589: #if !defined(FLUSH_ALL_TLBS)
590: do_invalidate_BAT(env, env->IBAT[0][nr], mask);
591: #endif
592: #if defined(FLUSH_ALL_TLBS)
593: tlb_flush(env, 1);
594: #endif
595: }
596: }
597:
598: void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
599: {
600: dump_store_bat(env, 'I', 1, nr, value);
601: env->IBAT[1][nr] = value;
602: }
603:
604: target_ulong do_load_dbatu (CPUPPCState *env, int nr)
605: {
606: return env->DBAT[0][nr];
607: }
608:
609: target_ulong do_load_dbatl (CPUPPCState *env, int nr)
610: {
611: return env->DBAT[1][nr];
612: }
613:
614: void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
615: {
616: target_ulong mask;
617:
618: dump_store_bat(env, 'D', 0, nr, value);
619: if (env->DBAT[0][nr] != value) {
620: /* When storing valid upper BAT, mask BEPI and BRPN
621: * and invalidate all TLBs covered by this BAT
622: */
623: mask = (value << 15) & 0x0FFE0000UL;
624: #if !defined(FLUSH_ALL_TLBS)
625: do_invalidate_BAT(env, env->DBAT[0][nr], mask);
626: #endif
627: mask = (value << 15) & 0x0FFE0000UL;
628: env->DBAT[0][nr] = (value & 0x00001FFFUL) |
629: (value & ~0x0001FFFFUL & ~mask);
630: env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
631: (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
632: #if !defined(FLUSH_ALL_TLBS)
633: do_invalidate_BAT(env, env->DBAT[0][nr], mask);
634: #else
635: tlb_flush(env, 1);
636: #endif
637: }
638: }
639:
640: void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
641: {
642: dump_store_bat(env, 'D', 1, nr, value);
643: env->DBAT[1][nr] = value;
644: }
645:
646: static inline void invalidate_all_tlbs (CPUPPCState *env)
647: {
648: /* XXX: this needs to be completed for sotware driven TLB support */
649: tlb_flush(env, 1);
650: }
651:
652: /*****************************************************************************/
653: /* Special registers manipulation */
654: target_ulong do_load_nip (CPUPPCState *env)
655: {
656: return env->nip;
657: }
658:
659: void do_store_nip (CPUPPCState *env, target_ulong value)
660: {
661: env->nip = value;
662: }
663:
664: target_ulong do_load_sdr1 (CPUPPCState *env)
665: {
666: return env->sdr1;
667: }
668:
669: void do_store_sdr1 (CPUPPCState *env, target_ulong value)
670: {
671: #if defined (DEBUG_MMU)
672: if (loglevel != 0) {
673: fprintf(logfile, "%s: 0x%08lx\n", __func__, (unsigned long)value);
674: }
675: #endif
676: if (env->sdr1 != value) {
677: env->sdr1 = value;
678: invalidate_all_tlbs(env);
679: }
680: }
681:
682: target_ulong do_load_sr (CPUPPCState *env, int srnum)
683: {
684: return env->sr[srnum];
685: }
686:
687: void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
688: {
689: #if defined (DEBUG_MMU)
690: if (loglevel != 0) {
691: fprintf(logfile, "%s: reg=%d 0x%08lx %08lx\n",
692: __func__, srnum, (unsigned long)value, env->sr[srnum]);
693: }
694: #endif
695: if (env->sr[srnum] != value) {
696: env->sr[srnum] = value;
697: #if !defined(FLUSH_ALL_TLBS) && 0
698: {
699: target_ulong page, end;
700: /* Invalidate 256 MB of virtual memory */
701: page = (16 << 20) * srnum;
702: end = page + (16 << 20);
703: for (; page != end; page += TARGET_PAGE_SIZE)
704: tlb_flush_page(env, page);
705: }
706: #else
707: invalidate_all_tlbs(env);
708: #endif
709: }
710: }
711:
712: uint32_t do_load_cr (CPUPPCState *env)
713: {
714: return (env->crf[0] << 28) |
715: (env->crf[1] << 24) |
716: (env->crf[2] << 20) |
717: (env->crf[3] << 16) |
718: (env->crf[4] << 12) |
719: (env->crf[5] << 8) |
720: (env->crf[6] << 4) |
721: (env->crf[7] << 0);
722: }
723:
724: void do_store_cr (CPUPPCState *env, uint32_t value, uint32_t mask)
725: {
726: int i, sh;
727:
728: for (i = 0, sh = 7; i < 8; i++, sh --) {
729: if (mask & (1 << sh))
730: env->crf[i] = (value >> (sh * 4)) & 0xFUL;
731: }
732: }
733:
734: uint32_t do_load_xer (CPUPPCState *env)
735: {
736: return (xer_so << XER_SO) |
737: (xer_ov << XER_OV) |
738: (xer_ca << XER_CA) |
739: (xer_bc << XER_BC) |
740: (xer_cmp << XER_CMP);
741: }
742:
743: void do_store_xer (CPUPPCState *env, uint32_t value)
744: {
745: xer_so = (value >> XER_SO) & 0x01;
746: xer_ov = (value >> XER_OV) & 0x01;
747: xer_ca = (value >> XER_CA) & 0x01;
748: xer_cmp = (value >> XER_CMP) & 0xFF;
749: xer_bc = (value >> XER_BC) & 0x3F;
750: }
751:
752: target_ulong do_load_msr (CPUPPCState *env)
753: {
754: return (msr_vr << MSR_VR) |
755: (msr_ap << MSR_AP) |
756: (msr_sa << MSR_SA) |
757: (msr_key << MSR_KEY) |
758: (msr_pow << MSR_POW) |
759: (msr_tlb << MSR_TLB) |
760: (msr_ile << MSR_ILE) |
761: (msr_ee << MSR_EE) |
762: (msr_pr << MSR_PR) |
763: (msr_fp << MSR_FP) |
764: (msr_me << MSR_ME) |
765: (msr_fe0 << MSR_FE0) |
766: (msr_se << MSR_SE) |
767: (msr_be << MSR_BE) |
768: (msr_fe1 << MSR_FE1) |
769: (msr_al << MSR_AL) |
770: (msr_ip << MSR_IP) |
771: (msr_ir << MSR_IR) |
772: (msr_dr << MSR_DR) |
773: (msr_pe << MSR_PE) |
774: (msr_px << MSR_PX) |
775: (msr_ri << MSR_RI) |
776: (msr_le << MSR_LE);
777: }
778:
779: void do_compute_hflags (CPUPPCState *env)
780: {
781: /* Compute current hflags */
782: env->hflags = (msr_pr << MSR_PR) | (msr_le << MSR_LE) |
783: (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_fe1 << MSR_FE1) |
784: (msr_vr << MSR_VR) | (msr_ap << MSR_AP) | (msr_sa << MSR_SA) |
785: (msr_se << MSR_SE) | (msr_be << MSR_BE);
786: }
787:
788: void do_store_msr (CPUPPCState *env, target_ulong value)
789: {
790: value &= env->msr_mask;
791: if (((value >> MSR_IR) & 1) != msr_ir ||
792: ((value >> MSR_DR) & 1) != msr_dr) {
793: /* Flush all tlb when changing translation mode
794: * When using software driven TLB, we may also need to reload
795: * all defined TLBs
796: */
797: tlb_flush(env, 1);
798: env->interrupt_request |= CPU_INTERRUPT_EXITTB;
799: }
800: #if 0
801: if (loglevel != 0) {
802: fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
803: }
804: #endif
805: msr_vr = (value >> MSR_VR) & 1;
806: msr_ap = (value >> MSR_AP) & 1;
807: msr_sa = (value >> MSR_SA) & 1;
808: msr_key = (value >> MSR_KEY) & 1;
809: msr_pow = (value >> MSR_POW) & 1;
810: msr_tlb = (value >> MSR_TLB) & 1;
811: msr_ile = (value >> MSR_ILE) & 1;
812: msr_ee = (value >> MSR_EE) & 1;
813: msr_pr = (value >> MSR_PR) & 1;
814: msr_fp = (value >> MSR_FP) & 1;
815: msr_me = (value >> MSR_ME) & 1;
816: msr_fe0 = (value >> MSR_FE0) & 1;
817: msr_se = (value >> MSR_SE) & 1;
818: msr_be = (value >> MSR_BE) & 1;
819: msr_fe1 = (value >> MSR_FE1) & 1;
820: msr_al = (value >> MSR_AL) & 1;
821: msr_ip = (value >> MSR_IP) & 1;
822: msr_ir = (value >> MSR_IR) & 1;
823: msr_dr = (value >> MSR_DR) & 1;
824: msr_pe = (value >> MSR_PE) & 1;
825: msr_px = (value >> MSR_PX) & 1;
826: msr_ri = (value >> MSR_RI) & 1;
827: msr_le = (value >> MSR_LE) & 1;
828: do_compute_hflags(env);
829: }
830:
831: float64 do_load_fpscr (CPUPPCState *env)
832: {
833: /* The 32 MSB of the target fpr are undefined.
834: * They'll be zero...
835: */
836: union {
837: float64 d;
838: struct {
839: uint32_t u[2];
840: } s;
841: } u;
842: int i;
843:
844: #ifdef WORDS_BIGENDIAN
845: #define WORD0 0
846: #define WORD1 1
847: #else
848: #define WORD0 1
849: #define WORD1 0
850: #endif
851: u.s.u[WORD0] = 0;
852: u.s.u[WORD1] = 0;
853: for (i = 0; i < 8; i++)
854: u.s.u[WORD1] |= env->fpscr[i] << (4 * i);
855: return u.d;
856: }
857:
858: void do_store_fpscr (CPUPPCState *env, float64 f, uint32_t mask)
859: {
860: /*
861: * We use only the 32 LSB of the incoming fpr
862: */
863: union {
864: double d;
865: struct {
866: uint32_t u[2];
867: } s;
868: } u;
869: int i, rnd_type;
870:
871: u.d = f;
872: if (mask & 0x80)
873: env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9);
874: for (i = 1; i < 7; i++) {
875: if (mask & (1 << (7 - i)))
876: env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF;
877: }
878: /* TODO: update FEX & VX */
879: /* Set rounding mode */
880: switch (env->fpscr[0] & 0x3) {
881: case 0:
882: /* Best approximation (round to nearest) */
883: rnd_type = float_round_nearest_even;
884: break;
885: case 1:
886: /* Smaller magnitude (round toward zero) */
887: rnd_type = float_round_to_zero;
888: break;
889: case 2:
890: /* Round toward +infinite */
891: rnd_type = float_round_up;
892: break;
893: default:
894: case 3:
895: /* Round toward -infinite */
896: rnd_type = float_round_down;
897: break;
898: }
899: set_float_rounding_mode(rnd_type, &env->fp_status);
900: }
901:
902: /*****************************************************************************/
903: /* Exception processing */
904: #if defined (CONFIG_USER_ONLY)
905: void do_interrupt (CPUState *env)
906: {
907: env->exception_index = -1;
908: }
909: #else
910: static void dump_syscall(CPUState *env)
911: {
912: fprintf(logfile, "syscall r0=0x%08x r3=0x%08x r4=0x%08x r5=0x%08x r6=0x%08x nip=0x%08x\n",
913: env->gpr[0], env->gpr[3], env->gpr[4],
914: env->gpr[5], env->gpr[6], env->nip);
915: }
916:
917: void do_interrupt (CPUState *env)
918: {
919: target_ulong msr, *srr_0, *srr_1, tmp;
920: int excp;
921:
922: excp = env->exception_index;
923: msr = do_load_msr(env);
924: /* The default is to use SRR0 & SRR1 to save the exception context */
925: srr_0 = &env->spr[SPR_SRR0];
926: srr_1 = &env->spr[SPR_SRR1];
927: #if defined (DEBUG_EXCEPTIONS)
928: if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) {
929: if (loglevel != 0) {
930: fprintf(logfile, "Raise exception at 0x%08lx => 0x%08x (%02x)\n",
931: (unsigned long)env->nip, excp, env->error_code);
932: cpu_dump_state(env, logfile, fprintf, 0);
933: }
934: }
935: #endif
936: if (loglevel & CPU_LOG_INT) {
937: fprintf(logfile, "Raise exception at 0x%08lx => 0x%08x (%02x)\n",
938: (unsigned long)env->nip, excp, env->error_code);
939: }
940: msr_pow = 0;
941: /* Generate informations in save/restore registers */
942: switch (excp) {
943: /* Generic PowerPC exceptions */
944: case EXCP_RESET: /* 0x0100 */
945: if (PPC_EXCP(env) != PPC_FLAGS_EXCP_40x) {
946: if (msr_ip)
947: excp += 0xFFC00;
948: excp |= 0xFFC00000;
949: } else {
950: srr_0 = &env->spr[SPR_40x_SRR2];
951: srr_1 = &env->spr[SPR_40x_SRR3];
952: }
953: goto store_next;
954: case EXCP_MACHINE_CHECK: /* 0x0200 */
955: if (msr_me == 0) {
956: cpu_abort(env, "Machine check exception while not allowed\n");
957: }
958: if (PPC_EXCP(env) == PPC_FLAGS_EXCP_40x) {
959: srr_0 = &env->spr[SPR_40x_SRR2];
960: srr_1 = &env->spr[SPR_40x_SRR3];
961: }
962: msr_me = 0;
963: break;
964: case EXCP_DSI: /* 0x0300 */
965: /* Store exception cause */
966: /* data location address has been stored
967: * when the fault has been detected
968: */
969: msr &= ~0xFFFF0000;
970: #if defined (DEBUG_EXCEPTIONS)
971: if (loglevel) {
972: fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
973: env->spr[SPR_DSISR], env->spr[SPR_DAR]);
974: } else {
975: printf("DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
976: env->spr[SPR_DSISR], env->spr[SPR_DAR]);
977: }
978: #endif
979: goto store_next;
980: case EXCP_ISI: /* 0x0400 */
981: /* Store exception cause */
982: msr &= ~0xFFFF0000;
983: msr |= env->error_code;
984: #if defined (DEBUG_EXCEPTIONS)
985: if (loglevel != 0) {
986: fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
987: msr, env->nip);
988: }
989: #endif
990: goto store_next;
991: case EXCP_EXTERNAL: /* 0x0500 */
992: if (msr_ee == 0) {
993: #if defined (DEBUG_EXCEPTIONS)
994: if (loglevel > 0) {
995: fprintf(logfile, "Skipping hardware interrupt\n");
996: }
997: #endif
998: /* Requeue it */
999: env->interrupt_request |= CPU_INTERRUPT_HARD;
1000: return;
1001: }
1002: goto store_next;
1003: case EXCP_ALIGN: /* 0x0600 */
1004: if (PPC_EXCP(env) != PPC_FLAGS_EXCP_601) {
1005: /* Store exception cause */
1006: /* Get rS/rD and rA from faulting opcode */
1007: env->spr[SPR_DSISR] |=
1008: (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
1009: /* data location address has been stored
1010: * when the fault has been detected
1011: */
1012: } else {
1013: /* IO error exception on PowerPC 601 */
1014: /* XXX: TODO */
1015: cpu_abort(env,
1016: "601 IO error exception is not implemented yet !\n");
1017: }
1018: goto store_current;
1019: case EXCP_PROGRAM: /* 0x0700 */
1020: msr &= ~0xFFFF0000;
1021: switch (env->error_code & ~0xF) {
1022: case EXCP_FP:
1023: if (msr_fe0 == 0 && msr_fe1 == 0) {
1024: #if defined (DEBUG_EXCEPTIONS)
1025: printf("Ignore floating point exception\n");
1026: #endif
1027: return;
1028: }
1029: msr |= 0x00100000;
1030: /* Set FX */
1031: env->fpscr[7] |= 0x8;
1032: /* Finally, update FEX */
1033: if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
1034: ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
1035: env->fpscr[7] |= 0x4;
1036: break;
1037: case EXCP_INVAL:
1038: // printf("Invalid instruction at 0x%08x\n", env->nip);
1039: msr |= 0x00080000;
1040: break;
1041: case EXCP_PRIV:
1042: msr |= 0x00040000;
1043: break;
1044: case EXCP_TRAP:
1045: msr |= 0x00020000;
1046: break;
1047: default:
1048: /* Should never occur */
1049: break;
1050: }
1051: msr |= 0x00010000;
1052: goto store_current;
1053: case EXCP_NO_FP: /* 0x0800 */
1054: msr &= ~0xFFFF0000;
1055: goto store_current;
1056: case EXCP_DECR:
1057: if (msr_ee == 0) {
1058: #if 1
1059: /* Requeue it */
1060: env->interrupt_request |= CPU_INTERRUPT_TIMER;
1061: #endif
1062: return;
1063: }
1064: goto store_next;
1065: case EXCP_SYSCALL: /* 0x0C00 */
1066: /* NOTE: this is a temporary hack to support graphics OSI
1067: calls from the MOL driver */
1068: if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
1069: env->osi_call) {
1070: if (env->osi_call(env) != 0)
1071: return;
1072: }
1073: if (loglevel & CPU_LOG_INT) {
1074: dump_syscall(env);
1075: }
1076: goto store_next;
1077: case EXCP_TRACE: /* 0x0D00 */
1078: /* XXX: TODO */
1079: cpu_abort(env, "Trace exception is not implemented yet !\n");
1080: goto store_next;
1081: case EXCP_PERF: /* 0x0F00 */
1082: /* XXX: TODO */
1083: cpu_abort(env,
1084: "Performance counter exception is not implemented yet !\n");
1085: goto store_next;
1086: /* 32 bits PowerPC specific exceptions */
1087: case EXCP_FP_ASSIST: /* 0x0E00 */
1088: /* XXX: TODO */
1089: cpu_abort(env, "Floating point assist exception "
1090: "is not implemented yet !\n");
1091: goto store_next;
1092: /* 64 bits PowerPC exceptions */
1093: case EXCP_DSEG: /* 0x0380 */
1094: /* XXX: TODO */
1095: cpu_abort(env, "Data segment exception is not implemented yet !\n");
1096: goto store_next;
1097: case EXCP_ISEG: /* 0x0480 */
1098: /* XXX: TODO */
1099: cpu_abort(env,
1100: "Instruction segment exception is not implemented yet !\n");
1101: goto store_next;
1102: case EXCP_HDECR: /* 0x0980 */
1103: if (msr_ee == 0) {
1104: #if 1
1105: /* Requeue it */
1106: env->interrupt_request |= CPU_INTERRUPT_TIMER;
1107: #endif
1108: return;
1109: }
1110: cpu_abort(env,
1111: "Hypervisor decrementer exception is not implemented yet !\n");
1112: goto store_next;
1113: /* Implementation specific exceptions */
1114: case 0x0A00:
1115: if (PPC_EXCP(env) != PPC_FLAGS_EXCP_602) {
1116: /* Critical interrupt on G2 */
1117: /* XXX: TODO */
1118: cpu_abort(env, "G2 critical interrupt is not implemented yet !\n");
1119: goto store_next;
1120: } else {
1121: cpu_abort(env, "Invalid exception 0x0A00 !\n");
1122: }
1123: return;
1124: case 0x0F20:
1125: switch (PPC_EXCP(env)) {
1126: case PPC_FLAGS_EXCP_40x:
1127: /* APU unavailable on 405 */
1128: /* XXX: TODO */
1129: cpu_abort(env,
1130: "APU unavailable exception is not implemented yet !\n");
1131: goto store_next;
1132: case PPC_FLAGS_EXCP_74xx:
1133: /* Altivec unavailable */
1134: /* XXX: TODO */
1135: cpu_abort(env, "Altivec unavailable exception "
1136: "is not implemented yet !\n");
1137: goto store_next;
1138: default:
1139: cpu_abort(env, "Invalid exception 0x0F20 !\n");
1140: break;
1141: }
1142: return;
1143: case 0x1000:
1144: switch (PPC_EXCP(env)) {
1145: case PPC_FLAGS_EXCP_40x:
1146: /* PIT on 4xx */
1147: /* XXX: TODO */
1148: cpu_abort(env, "40x PIT exception is not implemented yet !\n");
1149: goto store_next;
1150: case PPC_FLAGS_EXCP_602:
1151: case PPC_FLAGS_EXCP_603:
1152: /* ITLBMISS on 602/603 */
1153: msr &= ~0xF00F0000;
1154: msr_tgpr = 1;
1155: goto store_gprs;
1156: default:
1157: cpu_abort(env, "Invalid exception 0x1000 !\n");
1158: break;
1159: }
1160: return;
1161: case 0x1010:
1162: switch (PPC_EXCP(env)) {
1163: case PPC_FLAGS_EXCP_40x:
1164: /* FIT on 4xx */
1165: cpu_abort(env, "40x FIT exception is not implemented yet !\n");
1166: /* XXX: TODO */
1167: goto store_next;
1168: default:
1169: cpu_abort(env, "Invalid exception 0x1010 !\n");
1170: break;
1171: }
1172: return;
1173: case 0x1020:
1174: switch (PPC_EXCP(env)) {
1175: case PPC_FLAGS_EXCP_40x:
1176: /* Watchdog on 4xx */
1177: /* XXX: TODO */
1178: cpu_abort(env,
1179: "40x watchdog exception is not implemented yet !\n");
1180: goto store_next;
1181: default:
1182: cpu_abort(env, "Invalid exception 0x1020 !\n");
1183: break;
1184: }
1185: return;
1186: case 0x1100:
1187: switch (PPC_EXCP(env)) {
1188: case PPC_FLAGS_EXCP_40x:
1189: /* DTLBMISS on 4xx */
1190: /* XXX: TODO */
1191: cpu_abort(env,
1192: "40x DTLBMISS exception is not implemented yet !\n");
1193: goto store_next;
1194: case PPC_FLAGS_EXCP_602:
1195: case PPC_FLAGS_EXCP_603:
1196: /* DLTLBMISS on 602/603 */
1197: msr &= ~0xF00F0000;
1198: msr_tgpr = 1;
1199: goto store_gprs;
1200: default:
1201: cpu_abort(env, "Invalid exception 0x1100 !\n");
1202: break;
1203: }
1204: return;
1205: case 0x1200:
1206: switch (PPC_EXCP(env)) {
1207: case PPC_FLAGS_EXCP_40x:
1208: /* ITLBMISS on 4xx */
1209: /* XXX: TODO */
1210: cpu_abort(env,
1211: "40x ITLBMISS exception is not implemented yet !\n");
1212: goto store_next;
1213: case PPC_FLAGS_EXCP_602:
1214: case PPC_FLAGS_EXCP_603:
1215: /* DSTLBMISS on 602/603 */
1216: msr &= ~0xF00F0000;
1217: msr_tgpr = 1;
1218: store_gprs:
1219: #if defined (DEBUG_SOFTWARE_TLB)
1220: if (loglevel != 0) {
1221: fprintf(logfile, "6xx %sTLB miss: IM %08x DM %08x IC %08x "
1222: "DC %08x H1 %08x H2 %08x %08x\n",
1223: excp == 0x1000 ? "I" : excp == 0x1100 ? "DL" : "DS",
1224: env->spr[SPR_IMISS], env->spr[SPR_DMISS],
1225: env->spr[SPR_ICMP], env->spr[SPR_DCMP],
1226: env->spr[SPR_DHASH1], env->spr[SPR_DHASH2],
1227: env->error_code);
1228: }
1229: #endif
1230: /* Swap temporary saved registers with GPRs */
1231: tmp = env->gpr[0];
1232: env->gpr[0] = env->tgpr[0];
1233: env->tgpr[0] = tmp;
1234: tmp = env->gpr[1];
1235: env->gpr[1] = env->tgpr[1];
1236: env->tgpr[1] = tmp;
1237: tmp = env->gpr[2];
1238: env->gpr[2] = env->tgpr[2];
1239: env->tgpr[2] = tmp;
1240: tmp = env->gpr[3];
1241: env->gpr[3] = env->tgpr[3];
1242: env->tgpr[3] = tmp;
1243: msr |= env->crf[0] << 28;
1244: msr |= env->error_code; /* key, D/I, S/L bits */
1245: /* Set way using a LRU mechanism */
1246: msr |= (env->last_way ^ 1) << 17;
1247: goto store_next;
1248: default:
1249: cpu_abort(env, "Invalid exception 0x1200 !\n");
1250: break;
1251: }
1252: return;
1253: case 0x1300:
1254: switch (PPC_EXCP(env)) {
1255: case PPC_FLAGS_EXCP_601:
1256: case PPC_FLAGS_EXCP_602:
1257: case PPC_FLAGS_EXCP_603:
1258: case PPC_FLAGS_EXCP_604:
1259: case PPC_FLAGS_EXCP_7x0:
1260: case PPC_FLAGS_EXCP_7x5:
1261: /* IABR on 6xx/7xx */
1262: /* XXX: TODO */
1263: cpu_abort(env, "IABR exception is not implemented yet !\n");
1264: goto store_next;
1265: default:
1266: cpu_abort(env, "Invalid exception 0x1300 !\n");
1267: break;
1268: }
1269: return;
1270: case 0x1400:
1271: switch (PPC_EXCP(env)) {
1272: case PPC_FLAGS_EXCP_601:
1273: case PPC_FLAGS_EXCP_602:
1274: case PPC_FLAGS_EXCP_603:
1275: case PPC_FLAGS_EXCP_604:
1276: case PPC_FLAGS_EXCP_7x0:
1277: case PPC_FLAGS_EXCP_7x5:
1278: /* SMI on 6xx/7xx */
1279: /* XXX: TODO */
1280: cpu_abort(env, "SMI exception is not implemented yet !\n");
1281: goto store_next;
1282: default:
1283: cpu_abort(env, "Invalid exception 0x1400 !\n");
1284: break;
1285: }
1286: return;
1287: case 0x1500:
1288: switch (PPC_EXCP(env)) {
1289: case PPC_FLAGS_EXCP_602:
1290: /* Watchdog on 602 */
1291: cpu_abort(env,
1292: "602 watchdog exception is not implemented yet !\n");
1293: goto store_next;
1294: case PPC_FLAGS_EXCP_970:
1295: /* Soft patch exception on 970 */
1296: /* XXX: TODO */
1297: cpu_abort(env,
1298: "970 soft-patch exception is not implemented yet !\n");
1299: goto store_next;
1300: case PPC_FLAGS_EXCP_74xx:
1301: /* VPU assist on 74xx */
1302: /* XXX: TODO */
1303: cpu_abort(env, "VPU assist exception is not implemented yet !\n");
1304: goto store_next;
1305: default:
1306: cpu_abort(env, "Invalid exception 0x1500 !\n");
1307: break;
1308: }
1309: return;
1310: case 0x1600:
1311: switch (PPC_EXCP(env)) {
1312: case PPC_FLAGS_EXCP_602:
1313: /* Emulation trap on 602 */
1314: /* XXX: TODO */
1315: cpu_abort(env, "602 emulation trap exception "
1316: "is not implemented yet !\n");
1317: goto store_next;
1318: case PPC_FLAGS_EXCP_970:
1319: /* Maintenance exception on 970 */
1320: /* XXX: TODO */
1321: cpu_abort(env,
1322: "970 maintenance exception is not implemented yet !\n");
1323: goto store_next;
1324: default:
1325: cpu_abort(env, "Invalid exception 0x1600 !\n");
1326: break;
1327: }
1328: return;
1329: case 0x1700:
1330: switch (PPC_EXCP(env)) {
1331: case PPC_FLAGS_EXCP_7x0:
1332: case PPC_FLAGS_EXCP_7x5:
1333: /* Thermal management interrupt on G3 */
1334: /* XXX: TODO */
1335: cpu_abort(env, "G3 thermal management exception "
1336: "is not implemented yet !\n");
1337: goto store_next;
1338: case PPC_FLAGS_EXCP_970:
1339: /* VPU assist on 970 */
1340: /* XXX: TODO */
1341: cpu_abort(env,
1342: "970 VPU assist exception is not implemented yet !\n");
1343: goto store_next;
1344: default:
1345: cpu_abort(env, "Invalid exception 0x1700 !\n");
1346: break;
1347: }
1348: return;
1349: case 0x1800:
1350: switch (PPC_EXCP(env)) {
1351: case PPC_FLAGS_EXCP_970:
1352: /* Thermal exception on 970 */
1353: /* XXX: TODO */
1354: cpu_abort(env, "970 thermal management exception "
1355: "is not implemented yet !\n");
1356: goto store_next;
1357: default:
1358: cpu_abort(env, "Invalid exception 0x1800 !\n");
1359: break;
1360: }
1361: return;
1362: case 0x2000:
1363: switch (PPC_EXCP(env)) {
1364: case PPC_FLAGS_EXCP_40x:
1365: /* DEBUG on 4xx */
1366: /* XXX: TODO */
1367: cpu_abort(env, "40x debug exception is not implemented yet !\n");
1368: goto store_next;
1369: case PPC_FLAGS_EXCP_601:
1370: /* Run mode exception on 601 */
1371: /* XXX: TODO */
1372: cpu_abort(env,
1373: "601 run mode exception is not implemented yet !\n");
1374: goto store_next;
1375: default:
1376: cpu_abort(env, "Invalid exception 0x1800 !\n");
1377: break;
1378: }
1379: return;
1380: /* Other exceptions */
1381: /* Qemu internal exceptions:
1382: * we should never come here with those values: abort execution
1383: */
1384: default:
1385: cpu_abort(env, "Invalid exception: code %d (%04x)\n", excp, excp);
1386: return;
1387: store_current:
1388: /* save current instruction location */
1389: *srr_0 = (env->nip - 4) & 0xFFFFFFFFULL;
1390: break;
1391: store_next:
1392: /* save next instruction location */
1393: *srr_0 = env->nip & 0xFFFFFFFFULL;
1394: break;
1395: }
1396: /* Save msr */
1397: *srr_1 = msr;
1398: /* If we disactivated any translation, flush TLBs */
1399: if (msr_ir || msr_dr) {
1400: tlb_flush(env, 1);
1401: }
1402: /* reload MSR with correct bits */
1403: msr_ee = 0;
1404: msr_pr = 0;
1405: msr_fp = 0;
1406: msr_fe0 = 0;
1407: msr_se = 0;
1408: msr_be = 0;
1409: msr_fe1 = 0;
1410: msr_ir = 0;
1411: msr_dr = 0;
1412: msr_ri = 0;
1413: msr_le = msr_ile;
1414: msr_sf = msr_isf;
1415: do_compute_hflags(env);
1416: /* Jump to handler */
1417: env->nip = excp;
1418: env->exception_index = EXCP_NONE;
1419: #if 0
1420: /* ensure that no TB jump will be modified as
1421: the program flow was changed */
1422: #ifdef __sparc__
1423: tmp_T0 = 0;
1424: #else
1425: T0 = 0;
1426: #endif
1427: #endif
1428: env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1429: }
1430: #endif /* !CONFIG_USER_ONLY */
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