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1.1 root 1: /*
2: * PowerPC emulation helpers for qemu.
3: *
4: * Copyright (c) 2003-2005 Jocelyn Mayer
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
17: * License along with this library; if not, write to the Free Software
18: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19: */
20: #include <stdarg.h>
21: #include <stdlib.h>
22: #include <stdio.h>
23: #include <string.h>
24: #include <inttypes.h>
25: #include <signal.h>
26: #include <assert.h>
27:
28: #include "cpu.h"
29: #include "exec-all.h"
30:
31: //#define DEBUG_MMU
32: //#define DEBUG_BATS
33: //#define DEBUG_EXCEPTIONS
34: //#define FLUSH_ALL_TLBS
35:
36: /*****************************************************************************/
37: /* PowerPC MMU emulation */
38:
1.1.1.2 ! root 39: #if defined(CONFIG_USER_ONLY)
! 40: int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
! 41: int is_user, int is_softmmu)
! 42: {
! 43: int exception, error_code;
! 44:
! 45: if (rw == 2) {
! 46: exception = EXCP_ISI;
! 47: error_code = 0;
! 48: } else {
! 49: exception = EXCP_DSI;
! 50: error_code = 0;
! 51: if (rw)
! 52: error_code |= 0x02000000;
! 53: env->spr[SPR_DAR] = address;
! 54: env->spr[SPR_DSISR] = error_code;
! 55: }
! 56: env->exception_index = exception;
! 57: env->error_code = error_code;
! 58: return 1;
! 59: }
! 60: target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
! 61: {
! 62: return addr;
! 63: }
! 64: #else
1.1 root 65: /* Perform BAT hit & translation */
66: static int get_bat (CPUState *env, uint32_t *real, int *prot,
67: uint32_t virtual, int rw, int type)
68: {
69: uint32_t *BATlt, *BATut, *BATu, *BATl;
70: uint32_t base, BEPIl, BEPIu, bl;
71: int i;
72: int ret = -1;
73:
74: #if defined (DEBUG_BATS)
75: if (loglevel > 0) {
76: fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
77: type == ACCESS_CODE ? 'I' : 'D', virtual);
78: }
79: #endif
80: switch (type) {
81: case ACCESS_CODE:
82: BATlt = env->IBAT[1];
83: BATut = env->IBAT[0];
84: break;
85: default:
86: BATlt = env->DBAT[1];
87: BATut = env->DBAT[0];
88: break;
89: }
90: #if defined (DEBUG_BATS)
91: if (loglevel > 0) {
92: fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
93: type == ACCESS_CODE ? 'I' : 'D', virtual);
94: }
95: #endif
96: base = virtual & 0xFFFC0000;
97: for (i = 0; i < 4; i++) {
98: BATu = &BATut[i];
99: BATl = &BATlt[i];
100: BEPIu = *BATu & 0xF0000000;
101: BEPIl = *BATu & 0x0FFE0000;
102: bl = (*BATu & 0x00001FFC) << 15;
103: #if defined (DEBUG_BATS)
104: if (loglevel > 0) {
105: fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
106: __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
107: *BATu, *BATl);
108: }
109: #endif
110: if ((virtual & 0xF0000000) == BEPIu &&
111: ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
112: /* BAT matches */
113: if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
114: (msr_pr == 1 && (*BATu & 0x00000001))) {
115: /* Get physical address */
116: *real = (*BATl & 0xF0000000) |
117: ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
118: (virtual & 0x0001F000);
119: if (*BATl & 0x00000001)
120: *prot = PAGE_READ;
121: if (*BATl & 0x00000002)
122: *prot = PAGE_WRITE | PAGE_READ;
123: #if defined (DEBUG_BATS)
124: if (loglevel > 0) {
125: fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
126: i, *real, *prot & PAGE_READ ? 'R' : '-',
127: *prot & PAGE_WRITE ? 'W' : '-');
128: }
129: #endif
130: ret = 0;
131: break;
132: }
133: }
134: }
135: if (ret < 0) {
136: #if defined (DEBUG_BATS)
137: printf("no BAT match for 0x%08x:\n", virtual);
138: for (i = 0; i < 4; i++) {
139: BATu = &BATut[i];
140: BATl = &BATlt[i];
141: BEPIu = *BATu & 0xF0000000;
142: BEPIl = *BATu & 0x0FFE0000;
143: bl = (*BATu & 0x00001FFC) << 15;
144: printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
145: "0x%08x 0x%08x 0x%08x\n",
146: __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
147: *BATu, *BATl, BEPIu, BEPIl, bl);
148: }
149: #endif
150: }
151: /* No hit */
152: return ret;
153: }
154:
155: /* PTE table lookup */
156: static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
157: int h, int key, int rw)
158: {
159: uint32_t pte0, pte1, keep = 0, access = 0;
160: int i, good = -1, store = 0;
161: int ret = -1; /* No entry found */
162:
163: for (i = 0; i < 8; i++) {
164: pte0 = ldl_phys(base + (i * 8));
165: pte1 = ldl_phys(base + (i * 8) + 4);
166: #if defined (DEBUG_MMU)
167: if (loglevel > 0) {
168: fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
169: "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1,
170: pte0 >> 31, h, (pte0 >> 6) & 1, va);
171: }
172: #endif
173: /* Check validity and table match */
174: if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
175: /* Check vsid & api */
176: if ((pte0 & 0x7FFFFFBF) == va) {
177: if (good == -1) {
178: good = i;
179: keep = pte1;
180: } else {
181: /* All matches should have equal RPN, WIMG & PP */
182: if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
183: if (loglevel > 0)
184: fprintf(logfile, "Bad RPN/WIMG/PP\n");
185: return -1;
186: }
187: }
188: /* Check access rights */
189: if (key == 0) {
190: access = PAGE_READ;
191: if ((pte1 & 0x00000003) != 0x3)
192: access |= PAGE_WRITE;
193: } else {
194: switch (pte1 & 0x00000003) {
195: case 0x0:
196: access = 0;
197: break;
198: case 0x1:
199: case 0x3:
200: access = PAGE_READ;
201: break;
202: case 0x2:
203: access = PAGE_READ | PAGE_WRITE;
204: break;
205: }
206: }
207: if (ret < 0) {
208: if ((rw == 0 && (access & PAGE_READ)) ||
209: (rw == 1 && (access & PAGE_WRITE))) {
210: #if defined (DEBUG_MMU)
211: if (loglevel > 0)
212: fprintf(logfile, "PTE access granted !\n");
213: #endif
214: good = i;
215: keep = pte1;
216: ret = 0;
217: } else {
218: /* Access right violation */
219: ret = -2;
220: #if defined (DEBUG_MMU)
221: if (loglevel > 0)
222: fprintf(logfile, "PTE access rejected\n");
223: #endif
224: }
225: *prot = access;
226: }
227: }
228: }
229: }
230: if (good != -1) {
231: *RPN = keep & 0xFFFFF000;
232: #if defined (DEBUG_MMU)
233: if (loglevel > 0) {
234: fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
235: *RPN, *prot, ret);
236: }
237: #endif
238: /* Update page flags */
239: if (!(keep & 0x00000100)) {
240: /* Access flag */
241: keep |= 0x00000100;
242: store = 1;
243: }
244: if (!(keep & 0x00000080)) {
245: if (rw && ret == 0) {
246: /* Change flag */
247: keep |= 0x00000080;
248: store = 1;
249: } else {
250: /* Force page fault for first write access */
251: *prot &= ~PAGE_WRITE;
252: }
253: }
254: if (store) {
255: stl_phys_notdirty(base + (good * 8) + 4, keep);
256: }
257: }
258:
259: return ret;
260: }
261:
262: static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
263: {
264: return (sdr1 & 0xFFFF0000) | (hash & mask);
265: }
266:
267: /* Perform segment based translation */
268: static int get_segment (CPUState *env, uint32_t *real, int *prot,
269: uint32_t virtual, int rw, int type)
270: {
271: uint32_t pg_addr, sdr, ptem, vsid, pgidx;
272: uint32_t hash, mask;
273: uint32_t sr;
274: int key;
275: int ret = -1, ret2;
276:
277: sr = env->sr[virtual >> 28];
278: #if defined (DEBUG_MMU)
279: if (loglevel > 0) {
280: fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
281: "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
282: virtual, virtual >> 28, sr, env->nip,
283: env->lr, msr_ir, msr_dr, msr_pr, rw, type);
284: }
285: #endif
286: key = (((sr & 0x20000000) && msr_pr == 1) ||
287: ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
288: if ((sr & 0x80000000) == 0) {
289: #if defined (DEBUG_MMU)
290: if (loglevel > 0)
291: fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
292: key, sr & 0x10000000);
293: #endif
294: /* Check if instruction fetch is allowed, if needed */
295: if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
296: /* Page address translation */
297: vsid = sr & 0x00FFFFFF;
298: pgidx = (virtual >> 12) & 0xFFFF;
299: sdr = env->sdr1;
300: hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
301: mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
302: pg_addr = get_pgaddr(sdr, hash, mask);
303: ptem = (vsid << 7) | (pgidx >> 10);
304: #if defined (DEBUG_MMU)
305: if (loglevel > 0) {
306: fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
307: "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
308: pg_addr);
309: }
310: #endif
311: /* Primary table lookup */
312: ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
313: if (ret < 0) {
314: /* Secondary table lookup */
315: hash = (~hash) & 0x01FFFFC0;
316: pg_addr = get_pgaddr(sdr, hash, mask);
317: #if defined (DEBUG_MMU)
318: if (virtual != 0xEFFFFFFF && loglevel > 0) {
319: fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
320: "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
321: hash, pg_addr);
322: }
323: #endif
324: ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
325: if (ret2 != -1)
326: ret = ret2;
327: }
328: } else {
329: #if defined (DEBUG_MMU)
330: if (loglevel > 0)
331: fprintf(logfile, "No access allowed\n");
332: #endif
333: ret = -3;
334: }
335: } else {
336: #if defined (DEBUG_MMU)
337: if (loglevel > 0)
338: fprintf(logfile, "direct store...\n");
339: #endif
340: /* Direct-store segment : absolutely *BUGGY* for now */
341: switch (type) {
342: case ACCESS_INT:
343: /* Integer load/store : only access allowed */
344: break;
345: case ACCESS_CODE:
346: /* No code fetch is allowed in direct-store areas */
347: return -4;
348: case ACCESS_FLOAT:
349: /* Floating point load/store */
350: return -4;
351: case ACCESS_RES:
352: /* lwarx, ldarx or srwcx. */
353: return -4;
354: case ACCESS_CACHE:
355: /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
356: /* Should make the instruction do no-op.
357: * As it already do no-op, it's quite easy :-)
358: */
359: *real = virtual;
360: return 0;
361: case ACCESS_EXT:
362: /* eciwx or ecowx */
363: return -4;
364: default:
365: if (logfile) {
366: fprintf(logfile, "ERROR: instruction should not need "
367: "address translation\n");
368: }
369: printf("ERROR: instruction should not need "
370: "address translation\n");
371: return -4;
372: }
373: if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
374: *real = virtual;
375: ret = 2;
376: } else {
377: ret = -2;
378: }
379: }
380:
381: return ret;
382: }
383:
1.1.1.2 ! root 384: static int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
! 385: uint32_t address, int rw, int access_type)
1.1 root 386: {
387: int ret;
388: #if 0
389: if (loglevel > 0) {
390: fprintf(logfile, "%s\n", __func__);
391: }
392: #endif
393: if ((access_type == ACCESS_CODE && msr_ir == 0) ||
394: (access_type != ACCESS_CODE && msr_dr == 0)) {
395: /* No address translation */
396: *physical = address & ~0xFFF;
397: *prot = PAGE_READ | PAGE_WRITE;
398: ret = 0;
399: } else {
400: /* Try to find a BAT */
401: ret = get_bat(env, physical, prot, address, rw, access_type);
402: if (ret < 0) {
403: /* We didn't match any BAT entry */
404: ret = get_segment(env, physical, prot, address, rw, access_type);
405: }
406: }
407: #if 0
408: if (loglevel > 0) {
409: fprintf(logfile, "%s address %08x => %08x\n",
410: __func__, address, *physical);
411: }
412: #endif
413: return ret;
414: }
415:
416: target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
417: {
418: uint32_t phys_addr;
419: int prot;
420:
421: if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
422: return -1;
423: return phys_addr;
424: }
425:
426: /* Perform address translation */
427: int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
428: int is_user, int is_softmmu)
429: {
430: uint32_t physical;
431: int prot;
432: int exception = 0, error_code = 0;
433: int access_type;
434: int ret = 0;
435:
436: if (rw == 2) {
437: /* code access */
438: rw = 0;
439: access_type = ACCESS_CODE;
440: } else {
441: /* data access */
442: /* XXX: put correct access by using cpu_restore_state()
443: correctly */
444: access_type = ACCESS_INT;
445: // access_type = env->access_type;
446: }
447: if (env->user_mode_only) {
448: /* user mode only emulation */
449: ret = -2;
450: goto do_fault;
451: }
452: ret = get_physical_address(env, &physical, &prot,
453: address, rw, access_type);
454: if (ret == 0) {
455: ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
456: is_user, is_softmmu);
457: } else if (ret < 0) {
458: do_fault:
459: #if defined (DEBUG_MMU)
460: if (loglevel > 0)
461: cpu_dump_state(env, logfile, fprintf, 0);
462: #endif
463: if (access_type == ACCESS_CODE) {
464: exception = EXCP_ISI;
465: switch (ret) {
466: case -1:
467: /* No matches in page tables */
468: error_code = 0x40000000;
469: break;
470: case -2:
471: /* Access rights violation */
472: error_code = 0x08000000;
473: break;
474: case -3:
475: /* No execute protection violation */
476: error_code = 0x10000000;
477: break;
478: case -4:
479: /* Direct store exception */
480: /* No code fetch is allowed in direct-store areas */
481: error_code = 0x10000000;
482: break;
483: case -5:
484: /* No match in segment table */
485: exception = EXCP_ISEG;
486: error_code = 0;
487: break;
488: }
489: } else {
490: exception = EXCP_DSI;
491: switch (ret) {
492: case -1:
493: /* No matches in page tables */
494: error_code = 0x40000000;
495: break;
496: case -2:
497: /* Access rights violation */
498: error_code = 0x08000000;
499: break;
500: case -4:
501: /* Direct store exception */
502: switch (access_type) {
503: case ACCESS_FLOAT:
504: /* Floating point load/store */
505: exception = EXCP_ALIGN;
506: error_code = EXCP_ALIGN_FP;
507: break;
508: case ACCESS_RES:
509: /* lwarx, ldarx or srwcx. */
510: error_code = 0x04000000;
511: break;
512: case ACCESS_EXT:
513: /* eciwx or ecowx */
514: error_code = 0x04100000;
515: break;
516: default:
517: printf("DSI: invalid exception (%d)\n", ret);
518: exception = EXCP_PROGRAM;
519: error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
520: break;
521: }
522: break;
523: case -5:
524: /* No match in segment table */
525: exception = EXCP_DSEG;
526: error_code = 0;
527: break;
528: }
529: if (exception == EXCP_DSI && rw == 1)
530: error_code |= 0x02000000;
531: /* Store fault address */
532: env->spr[SPR_DAR] = address;
533: env->spr[SPR_DSISR] = error_code;
534: }
535: #if 0
536: printf("%s: set exception to %d %02x\n",
537: __func__, exception, error_code);
538: #endif
539: env->exception_index = exception;
540: env->error_code = error_code;
541: ret = 1;
542: }
543: return ret;
544: }
1.1.1.2 ! root 545: #endif
1.1 root 546:
547: /*****************************************************************************/
548: /* BATs management */
549: #if !defined(FLUSH_ALL_TLBS)
550: static inline void do_invalidate_BAT (CPUPPCState *env,
551: target_ulong BATu, target_ulong mask)
552: {
553: target_ulong base, end, page;
554: base = BATu & ~0x0001FFFF;
555: end = base + mask + 0x00020000;
556: #if defined (DEBUG_BATS)
557: if (loglevel != 0)
558: fprintf(logfile, "Flush BAT from %08x to %08x (%08x)\n", base, end, mask);
559: #endif
560: for (page = base; page != end; page += TARGET_PAGE_SIZE)
561: tlb_flush_page(env, page);
562: #if defined (DEBUG_BATS)
563: if (loglevel != 0)
564: fprintf(logfile, "Flush done\n");
565: #endif
566: }
567: #endif
568:
569: static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr,
570: target_ulong value)
571: {
572: #if defined (DEBUG_BATS)
573: if (loglevel != 0) {
574: fprintf(logfile, "Set %cBAT%d%c to 0x%08lx (0x%08lx)\n",
575: ID, nr, ul == 0 ? 'u' : 'l', (unsigned long)value,
576: (unsigned long)env->nip);
577: }
578: #endif
579: }
580:
581: target_ulong do_load_ibatu (CPUPPCState *env, int nr)
582: {
583: return env->IBAT[0][nr];
584: }
585:
586: target_ulong do_load_ibatl (CPUPPCState *env, int nr)
587: {
588: return env->IBAT[1][nr];
589: }
590:
591: void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
592: {
593: target_ulong mask;
594:
595: dump_store_bat(env, 'I', 0, nr, value);
596: if (env->IBAT[0][nr] != value) {
597: mask = (value << 15) & 0x0FFE0000UL;
598: #if !defined(FLUSH_ALL_TLBS)
599: do_invalidate_BAT(env, env->IBAT[0][nr], mask);
600: #endif
601: /* When storing valid upper BAT, mask BEPI and BRPN
602: * and invalidate all TLBs covered by this BAT
603: */
604: mask = (value << 15) & 0x0FFE0000UL;
605: env->IBAT[0][nr] = (value & 0x00001FFFUL) |
606: (value & ~0x0001FFFFUL & ~mask);
607: env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
608: (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
609: #if !defined(FLUSH_ALL_TLBS)
610: do_invalidate_BAT(env, env->IBAT[0][nr], mask);
611: #endif
612: #if defined(FLUSH_ALL_TLBS)
613: tlb_flush(env, 1);
614: #endif
615: }
616: }
617:
618: void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
619: {
620: dump_store_bat(env, 'I', 1, nr, value);
621: env->IBAT[1][nr] = value;
622: }
623:
624: target_ulong do_load_dbatu (CPUPPCState *env, int nr)
625: {
626: return env->DBAT[0][nr];
627: }
628:
629: target_ulong do_load_dbatl (CPUPPCState *env, int nr)
630: {
631: return env->DBAT[1][nr];
632: }
633:
634: void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
635: {
636: target_ulong mask;
637:
638: dump_store_bat(env, 'D', 0, nr, value);
639: if (env->DBAT[0][nr] != value) {
640: /* When storing valid upper BAT, mask BEPI and BRPN
641: * and invalidate all TLBs covered by this BAT
642: */
643: mask = (value << 15) & 0x0FFE0000UL;
644: #if !defined(FLUSH_ALL_TLBS)
645: do_invalidate_BAT(env, env->DBAT[0][nr], mask);
646: #endif
647: mask = (value << 15) & 0x0FFE0000UL;
648: env->DBAT[0][nr] = (value & 0x00001FFFUL) |
649: (value & ~0x0001FFFFUL & ~mask);
650: env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
651: (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
652: #if !defined(FLUSH_ALL_TLBS)
653: do_invalidate_BAT(env, env->DBAT[0][nr], mask);
654: #else
655: tlb_flush(env, 1);
656: #endif
657: }
658: }
659:
660: void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
661: {
662: dump_store_bat(env, 'D', 1, nr, value);
663: env->DBAT[1][nr] = value;
664: }
665:
666: static inline void invalidate_all_tlbs (CPUPPCState *env)
667: {
668: /* XXX: this needs to be completed for sotware driven TLB support */
669: tlb_flush(env, 1);
670: }
671:
672: /*****************************************************************************/
673: /* Special registers manipulation */
674: target_ulong do_load_nip (CPUPPCState *env)
675: {
676: return env->nip;
677: }
678:
679: void do_store_nip (CPUPPCState *env, target_ulong value)
680: {
681: env->nip = value;
682: }
683:
684: target_ulong do_load_sdr1 (CPUPPCState *env)
685: {
686: return env->sdr1;
687: }
688:
689: void do_store_sdr1 (CPUPPCState *env, target_ulong value)
690: {
691: #if defined (DEBUG_MMU)
692: if (loglevel != 0) {
693: fprintf(logfile, "%s: 0x%08lx\n", __func__, (unsigned long)value);
694: }
695: #endif
696: if (env->sdr1 != value) {
697: env->sdr1 = value;
698: invalidate_all_tlbs(env);
699: }
700: }
701:
702: target_ulong do_load_sr (CPUPPCState *env, int srnum)
703: {
704: return env->sr[srnum];
705: }
706:
707: void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
708: {
709: #if defined (DEBUG_MMU)
710: if (loglevel != 0) {
711: fprintf(logfile, "%s: reg=%d 0x%08lx %08lx\n",
712: __func__, srnum, (unsigned long)value, env->sr[srnum]);
713: }
714: #endif
715: if (env->sr[srnum] != value) {
716: env->sr[srnum] = value;
717: #if !defined(FLUSH_ALL_TLBS) && 0
718: {
719: target_ulong page, end;
720: /* Invalidate 256 MB of virtual memory */
721: page = (16 << 20) * srnum;
722: end = page + (16 << 20);
723: for (; page != end; page += TARGET_PAGE_SIZE)
724: tlb_flush_page(env, page);
725: }
726: #else
727: invalidate_all_tlbs(env);
728: #endif
729: }
730: }
731:
732: uint32_t do_load_cr (CPUPPCState *env)
733: {
734: return (env->crf[0] << 28) |
735: (env->crf[1] << 24) |
736: (env->crf[2] << 20) |
737: (env->crf[3] << 16) |
738: (env->crf[4] << 12) |
739: (env->crf[5] << 8) |
740: (env->crf[6] << 4) |
741: (env->crf[7] << 0);
742: }
743:
744: void do_store_cr (CPUPPCState *env, uint32_t value, uint32_t mask)
745: {
746: int i, sh;
747:
748: for (i = 0, sh = 7; i < 8; i++, sh --) {
749: if (mask & (1 << sh))
750: env->crf[i] = (value >> (sh * 4)) & 0xFUL;
751: }
752: }
753:
754: uint32_t do_load_xer (CPUPPCState *env)
755: {
756: return (xer_so << XER_SO) |
757: (xer_ov << XER_OV) |
758: (xer_ca << XER_CA) |
759: (xer_bc << XER_BC) |
760: (xer_cmp << XER_CMP);
761: }
762:
763: void do_store_xer (CPUPPCState *env, uint32_t value)
764: {
765: xer_so = (value >> XER_SO) & 0x01;
766: xer_ov = (value >> XER_OV) & 0x01;
767: xer_ca = (value >> XER_CA) & 0x01;
768: xer_cmp = (value >> XER_CMP) & 0xFF;
769: xer_bc = (value >> XER_BC) & 0x3F;
770: }
771:
772: target_ulong do_load_msr (CPUPPCState *env)
773: {
774: return (msr_vr << MSR_VR) |
775: (msr_ap << MSR_AP) |
776: (msr_sa << MSR_SA) |
777: (msr_key << MSR_KEY) |
778: (msr_pow << MSR_POW) |
779: (msr_tlb << MSR_TLB) |
780: (msr_ile << MSR_ILE) |
781: (msr_ee << MSR_EE) |
782: (msr_pr << MSR_PR) |
783: (msr_fp << MSR_FP) |
784: (msr_me << MSR_ME) |
785: (msr_fe0 << MSR_FE0) |
786: (msr_se << MSR_SE) |
787: (msr_be << MSR_BE) |
788: (msr_fe1 << MSR_FE1) |
789: (msr_al << MSR_AL) |
790: (msr_ip << MSR_IP) |
791: (msr_ir << MSR_IR) |
792: (msr_dr << MSR_DR) |
793: (msr_pe << MSR_PE) |
794: (msr_px << MSR_PX) |
795: (msr_ri << MSR_RI) |
796: (msr_le << MSR_LE);
797: }
798:
799: void do_compute_hflags (CPUPPCState *env)
800: {
801: /* Compute current hflags */
802: env->hflags = (msr_pr << MSR_PR) | (msr_le << MSR_LE) |
803: (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_fe1 << MSR_FE1) |
804: (msr_vr << MSR_VR) | (msr_ap << MSR_AP) | (msr_sa << MSR_SA) |
805: (msr_se << MSR_SE) | (msr_be << MSR_BE);
806: }
807:
808: void do_store_msr (CPUPPCState *env, target_ulong value)
1.1.1.2 ! root 809: {
! 810: int enter_pm;
! 811:
1.1 root 812: value &= env->msr_mask;
813: if (((value >> MSR_IR) & 1) != msr_ir ||
814: ((value >> MSR_DR) & 1) != msr_dr) {
815: /* Flush all tlb when changing translation mode
816: * When using software driven TLB, we may also need to reload
817: * all defined TLBs
818: */
819: tlb_flush(env, 1);
820: env->interrupt_request |= CPU_INTERRUPT_EXITTB;
821: }
822: #if 0
823: if (loglevel != 0) {
824: fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
825: }
826: #endif
827: msr_vr = (value >> MSR_VR) & 1;
828: msr_ap = (value >> MSR_AP) & 1;
829: msr_sa = (value >> MSR_SA) & 1;
830: msr_key = (value >> MSR_KEY) & 1;
831: msr_pow = (value >> MSR_POW) & 1;
832: msr_tlb = (value >> MSR_TLB) & 1;
833: msr_ile = (value >> MSR_ILE) & 1;
834: msr_ee = (value >> MSR_EE) & 1;
835: msr_pr = (value >> MSR_PR) & 1;
836: msr_fp = (value >> MSR_FP) & 1;
837: msr_me = (value >> MSR_ME) & 1;
838: msr_fe0 = (value >> MSR_FE0) & 1;
839: msr_se = (value >> MSR_SE) & 1;
840: msr_be = (value >> MSR_BE) & 1;
841: msr_fe1 = (value >> MSR_FE1) & 1;
842: msr_al = (value >> MSR_AL) & 1;
843: msr_ip = (value >> MSR_IP) & 1;
844: msr_ir = (value >> MSR_IR) & 1;
845: msr_dr = (value >> MSR_DR) & 1;
846: msr_pe = (value >> MSR_PE) & 1;
847: msr_px = (value >> MSR_PX) & 1;
848: msr_ri = (value >> MSR_RI) & 1;
849: msr_le = (value >> MSR_LE) & 1;
850: do_compute_hflags(env);
1.1.1.2 ! root 851:
! 852: enter_pm = 0;
! 853: switch (PPC_EXCP(env)) {
! 854: case PPC_FLAGS_EXCP_7x0:
! 855: if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0)
! 856: enter_pm = 1;
! 857: break;
! 858: default:
! 859: break;
! 860: }
! 861: if (enter_pm) {
! 862: /* power save: exit cpu loop */
! 863: env->halted = 1;
! 864: env->exception_index = EXCP_HLT;
! 865: cpu_loop_exit();
! 866: }
1.1 root 867: }
868:
869: float64 do_load_fpscr (CPUPPCState *env)
870: {
871: /* The 32 MSB of the target fpr are undefined.
872: * They'll be zero...
873: */
874: union {
875: float64 d;
876: struct {
877: uint32_t u[2];
878: } s;
879: } u;
880: int i;
881:
882: #ifdef WORDS_BIGENDIAN
883: #define WORD0 0
884: #define WORD1 1
885: #else
886: #define WORD0 1
887: #define WORD1 0
888: #endif
889: u.s.u[WORD0] = 0;
890: u.s.u[WORD1] = 0;
891: for (i = 0; i < 8; i++)
892: u.s.u[WORD1] |= env->fpscr[i] << (4 * i);
893: return u.d;
894: }
895:
896: void do_store_fpscr (CPUPPCState *env, float64 f, uint32_t mask)
897: {
898: /*
899: * We use only the 32 LSB of the incoming fpr
900: */
901: union {
902: double d;
903: struct {
904: uint32_t u[2];
905: } s;
906: } u;
907: int i, rnd_type;
908:
909: u.d = f;
910: if (mask & 0x80)
911: env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9);
912: for (i = 1; i < 7; i++) {
913: if (mask & (1 << (7 - i)))
914: env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF;
915: }
916: /* TODO: update FEX & VX */
917: /* Set rounding mode */
918: switch (env->fpscr[0] & 0x3) {
919: case 0:
920: /* Best approximation (round to nearest) */
921: rnd_type = float_round_nearest_even;
922: break;
923: case 1:
924: /* Smaller magnitude (round toward zero) */
925: rnd_type = float_round_to_zero;
926: break;
927: case 2:
928: /* Round toward +infinite */
929: rnd_type = float_round_up;
930: break;
931: default:
932: case 3:
933: /* Round toward -infinite */
934: rnd_type = float_round_down;
935: break;
936: }
937: set_float_rounding_mode(rnd_type, &env->fp_status);
938: }
939:
940: /*****************************************************************************/
941: /* Exception processing */
942: #if defined (CONFIG_USER_ONLY)
943: void do_interrupt (CPUState *env)
944: {
945: env->exception_index = -1;
946: }
947: #else
948: static void dump_syscall(CPUState *env)
949: {
950: fprintf(logfile, "syscall r0=0x%08x r3=0x%08x r4=0x%08x r5=0x%08x r6=0x%08x nip=0x%08x\n",
951: env->gpr[0], env->gpr[3], env->gpr[4],
952: env->gpr[5], env->gpr[6], env->nip);
953: }
954:
955: void do_interrupt (CPUState *env)
956: {
957: target_ulong msr, *srr_0, *srr_1, tmp;
958: int excp;
959:
960: excp = env->exception_index;
961: msr = do_load_msr(env);
962: /* The default is to use SRR0 & SRR1 to save the exception context */
963: srr_0 = &env->spr[SPR_SRR0];
964: srr_1 = &env->spr[SPR_SRR1];
965: #if defined (DEBUG_EXCEPTIONS)
966: if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) {
967: if (loglevel != 0) {
968: fprintf(logfile, "Raise exception at 0x%08lx => 0x%08x (%02x)\n",
969: (unsigned long)env->nip, excp, env->error_code);
970: cpu_dump_state(env, logfile, fprintf, 0);
971: }
972: }
973: #endif
974: if (loglevel & CPU_LOG_INT) {
975: fprintf(logfile, "Raise exception at 0x%08lx => 0x%08x (%02x)\n",
976: (unsigned long)env->nip, excp, env->error_code);
977: }
978: msr_pow = 0;
979: /* Generate informations in save/restore registers */
980: switch (excp) {
981: /* Generic PowerPC exceptions */
982: case EXCP_RESET: /* 0x0100 */
983: if (PPC_EXCP(env) != PPC_FLAGS_EXCP_40x) {
984: if (msr_ip)
985: excp += 0xFFC00;
986: excp |= 0xFFC00000;
987: } else {
988: srr_0 = &env->spr[SPR_40x_SRR2];
989: srr_1 = &env->spr[SPR_40x_SRR3];
990: }
991: goto store_next;
992: case EXCP_MACHINE_CHECK: /* 0x0200 */
993: if (msr_me == 0) {
994: cpu_abort(env, "Machine check exception while not allowed\n");
995: }
996: if (PPC_EXCP(env) == PPC_FLAGS_EXCP_40x) {
997: srr_0 = &env->spr[SPR_40x_SRR2];
998: srr_1 = &env->spr[SPR_40x_SRR3];
999: }
1000: msr_me = 0;
1001: break;
1002: case EXCP_DSI: /* 0x0300 */
1003: /* Store exception cause */
1004: /* data location address has been stored
1005: * when the fault has been detected
1006: */
1007: msr &= ~0xFFFF0000;
1008: #if defined (DEBUG_EXCEPTIONS)
1009: if (loglevel) {
1010: fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
1011: env->spr[SPR_DSISR], env->spr[SPR_DAR]);
1012: } else {
1013: printf("DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
1014: env->spr[SPR_DSISR], env->spr[SPR_DAR]);
1015: }
1016: #endif
1017: goto store_next;
1018: case EXCP_ISI: /* 0x0400 */
1019: /* Store exception cause */
1020: msr &= ~0xFFFF0000;
1021: msr |= env->error_code;
1022: #if defined (DEBUG_EXCEPTIONS)
1023: if (loglevel != 0) {
1024: fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
1025: msr, env->nip);
1026: }
1027: #endif
1028: goto store_next;
1029: case EXCP_EXTERNAL: /* 0x0500 */
1030: if (msr_ee == 0) {
1031: #if defined (DEBUG_EXCEPTIONS)
1032: if (loglevel > 0) {
1033: fprintf(logfile, "Skipping hardware interrupt\n");
1034: }
1035: #endif
1036: /* Requeue it */
1037: env->interrupt_request |= CPU_INTERRUPT_HARD;
1038: return;
1039: }
1040: goto store_next;
1041: case EXCP_ALIGN: /* 0x0600 */
1042: if (PPC_EXCP(env) != PPC_FLAGS_EXCP_601) {
1043: /* Store exception cause */
1044: /* Get rS/rD and rA from faulting opcode */
1045: env->spr[SPR_DSISR] |=
1046: (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
1047: /* data location address has been stored
1048: * when the fault has been detected
1049: */
1050: } else {
1051: /* IO error exception on PowerPC 601 */
1052: /* XXX: TODO */
1053: cpu_abort(env,
1054: "601 IO error exception is not implemented yet !\n");
1055: }
1056: goto store_current;
1057: case EXCP_PROGRAM: /* 0x0700 */
1058: msr &= ~0xFFFF0000;
1059: switch (env->error_code & ~0xF) {
1060: case EXCP_FP:
1061: if (msr_fe0 == 0 && msr_fe1 == 0) {
1062: #if defined (DEBUG_EXCEPTIONS)
1063: printf("Ignore floating point exception\n");
1064: #endif
1065: return;
1066: }
1067: msr |= 0x00100000;
1068: /* Set FX */
1069: env->fpscr[7] |= 0x8;
1070: /* Finally, update FEX */
1071: if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
1072: ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
1073: env->fpscr[7] |= 0x4;
1074: break;
1075: case EXCP_INVAL:
1076: // printf("Invalid instruction at 0x%08x\n", env->nip);
1077: msr |= 0x00080000;
1078: break;
1079: case EXCP_PRIV:
1080: msr |= 0x00040000;
1081: break;
1082: case EXCP_TRAP:
1083: msr |= 0x00020000;
1084: break;
1085: default:
1086: /* Should never occur */
1087: break;
1088: }
1089: msr |= 0x00010000;
1090: goto store_current;
1091: case EXCP_NO_FP: /* 0x0800 */
1092: msr &= ~0xFFFF0000;
1093: goto store_current;
1094: case EXCP_DECR:
1095: if (msr_ee == 0) {
1096: #if 1
1097: /* Requeue it */
1098: env->interrupt_request |= CPU_INTERRUPT_TIMER;
1099: #endif
1100: return;
1101: }
1102: goto store_next;
1103: case EXCP_SYSCALL: /* 0x0C00 */
1104: /* NOTE: this is a temporary hack to support graphics OSI
1105: calls from the MOL driver */
1106: if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
1107: env->osi_call) {
1108: if (env->osi_call(env) != 0)
1109: return;
1110: }
1111: if (loglevel & CPU_LOG_INT) {
1112: dump_syscall(env);
1113: }
1114: goto store_next;
1115: case EXCP_TRACE: /* 0x0D00 */
1116: /* XXX: TODO */
1117: cpu_abort(env, "Trace exception is not implemented yet !\n");
1118: goto store_next;
1119: case EXCP_PERF: /* 0x0F00 */
1120: /* XXX: TODO */
1121: cpu_abort(env,
1122: "Performance counter exception is not implemented yet !\n");
1123: goto store_next;
1124: /* 32 bits PowerPC specific exceptions */
1125: case EXCP_FP_ASSIST: /* 0x0E00 */
1126: /* XXX: TODO */
1127: cpu_abort(env, "Floating point assist exception "
1128: "is not implemented yet !\n");
1129: goto store_next;
1130: /* 64 bits PowerPC exceptions */
1131: case EXCP_DSEG: /* 0x0380 */
1132: /* XXX: TODO */
1133: cpu_abort(env, "Data segment exception is not implemented yet !\n");
1134: goto store_next;
1135: case EXCP_ISEG: /* 0x0480 */
1136: /* XXX: TODO */
1137: cpu_abort(env,
1138: "Instruction segment exception is not implemented yet !\n");
1139: goto store_next;
1140: case EXCP_HDECR: /* 0x0980 */
1141: if (msr_ee == 0) {
1142: #if 1
1143: /* Requeue it */
1144: env->interrupt_request |= CPU_INTERRUPT_TIMER;
1145: #endif
1146: return;
1147: }
1148: cpu_abort(env,
1149: "Hypervisor decrementer exception is not implemented yet !\n");
1150: goto store_next;
1151: /* Implementation specific exceptions */
1152: case 0x0A00:
1153: if (PPC_EXCP(env) != PPC_FLAGS_EXCP_602) {
1154: /* Critical interrupt on G2 */
1155: /* XXX: TODO */
1156: cpu_abort(env, "G2 critical interrupt is not implemented yet !\n");
1157: goto store_next;
1158: } else {
1159: cpu_abort(env, "Invalid exception 0x0A00 !\n");
1160: }
1161: return;
1162: case 0x0F20:
1163: switch (PPC_EXCP(env)) {
1164: case PPC_FLAGS_EXCP_40x:
1165: /* APU unavailable on 405 */
1166: /* XXX: TODO */
1167: cpu_abort(env,
1168: "APU unavailable exception is not implemented yet !\n");
1169: goto store_next;
1170: case PPC_FLAGS_EXCP_74xx:
1171: /* Altivec unavailable */
1172: /* XXX: TODO */
1173: cpu_abort(env, "Altivec unavailable exception "
1174: "is not implemented yet !\n");
1175: goto store_next;
1176: default:
1177: cpu_abort(env, "Invalid exception 0x0F20 !\n");
1178: break;
1179: }
1180: return;
1181: case 0x1000:
1182: switch (PPC_EXCP(env)) {
1183: case PPC_FLAGS_EXCP_40x:
1184: /* PIT on 4xx */
1185: /* XXX: TODO */
1186: cpu_abort(env, "40x PIT exception is not implemented yet !\n");
1187: goto store_next;
1188: case PPC_FLAGS_EXCP_602:
1189: case PPC_FLAGS_EXCP_603:
1190: /* ITLBMISS on 602/603 */
1191: msr &= ~0xF00F0000;
1192: msr_tgpr = 1;
1193: goto store_gprs;
1194: default:
1195: cpu_abort(env, "Invalid exception 0x1000 !\n");
1196: break;
1197: }
1198: return;
1199: case 0x1010:
1200: switch (PPC_EXCP(env)) {
1201: case PPC_FLAGS_EXCP_40x:
1202: /* FIT on 4xx */
1203: cpu_abort(env, "40x FIT exception is not implemented yet !\n");
1204: /* XXX: TODO */
1205: goto store_next;
1206: default:
1207: cpu_abort(env, "Invalid exception 0x1010 !\n");
1208: break;
1209: }
1210: return;
1211: case 0x1020:
1212: switch (PPC_EXCP(env)) {
1213: case PPC_FLAGS_EXCP_40x:
1214: /* Watchdog on 4xx */
1215: /* XXX: TODO */
1216: cpu_abort(env,
1217: "40x watchdog exception is not implemented yet !\n");
1218: goto store_next;
1219: default:
1220: cpu_abort(env, "Invalid exception 0x1020 !\n");
1221: break;
1222: }
1223: return;
1224: case 0x1100:
1225: switch (PPC_EXCP(env)) {
1226: case PPC_FLAGS_EXCP_40x:
1227: /* DTLBMISS on 4xx */
1228: /* XXX: TODO */
1229: cpu_abort(env,
1230: "40x DTLBMISS exception is not implemented yet !\n");
1231: goto store_next;
1232: case PPC_FLAGS_EXCP_602:
1233: case PPC_FLAGS_EXCP_603:
1234: /* DLTLBMISS on 602/603 */
1235: msr &= ~0xF00F0000;
1236: msr_tgpr = 1;
1237: goto store_gprs;
1238: default:
1239: cpu_abort(env, "Invalid exception 0x1100 !\n");
1240: break;
1241: }
1242: return;
1243: case 0x1200:
1244: switch (PPC_EXCP(env)) {
1245: case PPC_FLAGS_EXCP_40x:
1246: /* ITLBMISS on 4xx */
1247: /* XXX: TODO */
1248: cpu_abort(env,
1249: "40x ITLBMISS exception is not implemented yet !\n");
1250: goto store_next;
1251: case PPC_FLAGS_EXCP_602:
1252: case PPC_FLAGS_EXCP_603:
1253: /* DSTLBMISS on 602/603 */
1254: msr &= ~0xF00F0000;
1255: msr_tgpr = 1;
1256: store_gprs:
1257: #if defined (DEBUG_SOFTWARE_TLB)
1258: if (loglevel != 0) {
1259: fprintf(logfile, "6xx %sTLB miss: IM %08x DM %08x IC %08x "
1260: "DC %08x H1 %08x H2 %08x %08x\n",
1261: excp == 0x1000 ? "I" : excp == 0x1100 ? "DL" : "DS",
1262: env->spr[SPR_IMISS], env->spr[SPR_DMISS],
1263: env->spr[SPR_ICMP], env->spr[SPR_DCMP],
1264: env->spr[SPR_DHASH1], env->spr[SPR_DHASH2],
1265: env->error_code);
1266: }
1267: #endif
1268: /* Swap temporary saved registers with GPRs */
1269: tmp = env->gpr[0];
1270: env->gpr[0] = env->tgpr[0];
1271: env->tgpr[0] = tmp;
1272: tmp = env->gpr[1];
1273: env->gpr[1] = env->tgpr[1];
1274: env->tgpr[1] = tmp;
1275: tmp = env->gpr[2];
1276: env->gpr[2] = env->tgpr[2];
1277: env->tgpr[2] = tmp;
1278: tmp = env->gpr[3];
1279: env->gpr[3] = env->tgpr[3];
1280: env->tgpr[3] = tmp;
1281: msr |= env->crf[0] << 28;
1282: msr |= env->error_code; /* key, D/I, S/L bits */
1283: /* Set way using a LRU mechanism */
1284: msr |= (env->last_way ^ 1) << 17;
1285: goto store_next;
1286: default:
1287: cpu_abort(env, "Invalid exception 0x1200 !\n");
1288: break;
1289: }
1290: return;
1291: case 0x1300:
1292: switch (PPC_EXCP(env)) {
1293: case PPC_FLAGS_EXCP_601:
1294: case PPC_FLAGS_EXCP_602:
1295: case PPC_FLAGS_EXCP_603:
1296: case PPC_FLAGS_EXCP_604:
1297: case PPC_FLAGS_EXCP_7x0:
1298: case PPC_FLAGS_EXCP_7x5:
1299: /* IABR on 6xx/7xx */
1300: /* XXX: TODO */
1301: cpu_abort(env, "IABR exception is not implemented yet !\n");
1302: goto store_next;
1303: default:
1304: cpu_abort(env, "Invalid exception 0x1300 !\n");
1305: break;
1306: }
1307: return;
1308: case 0x1400:
1309: switch (PPC_EXCP(env)) {
1310: case PPC_FLAGS_EXCP_601:
1311: case PPC_FLAGS_EXCP_602:
1312: case PPC_FLAGS_EXCP_603:
1313: case PPC_FLAGS_EXCP_604:
1314: case PPC_FLAGS_EXCP_7x0:
1315: case PPC_FLAGS_EXCP_7x5:
1316: /* SMI on 6xx/7xx */
1317: /* XXX: TODO */
1318: cpu_abort(env, "SMI exception is not implemented yet !\n");
1319: goto store_next;
1320: default:
1321: cpu_abort(env, "Invalid exception 0x1400 !\n");
1322: break;
1323: }
1324: return;
1325: case 0x1500:
1326: switch (PPC_EXCP(env)) {
1327: case PPC_FLAGS_EXCP_602:
1328: /* Watchdog on 602 */
1329: cpu_abort(env,
1330: "602 watchdog exception is not implemented yet !\n");
1331: goto store_next;
1332: case PPC_FLAGS_EXCP_970:
1333: /* Soft patch exception on 970 */
1334: /* XXX: TODO */
1335: cpu_abort(env,
1336: "970 soft-patch exception is not implemented yet !\n");
1337: goto store_next;
1338: case PPC_FLAGS_EXCP_74xx:
1339: /* VPU assist on 74xx */
1340: /* XXX: TODO */
1341: cpu_abort(env, "VPU assist exception is not implemented yet !\n");
1342: goto store_next;
1343: default:
1344: cpu_abort(env, "Invalid exception 0x1500 !\n");
1345: break;
1346: }
1347: return;
1348: case 0x1600:
1349: switch (PPC_EXCP(env)) {
1350: case PPC_FLAGS_EXCP_602:
1351: /* Emulation trap on 602 */
1352: /* XXX: TODO */
1353: cpu_abort(env, "602 emulation trap exception "
1354: "is not implemented yet !\n");
1355: goto store_next;
1356: case PPC_FLAGS_EXCP_970:
1357: /* Maintenance exception on 970 */
1358: /* XXX: TODO */
1359: cpu_abort(env,
1360: "970 maintenance exception is not implemented yet !\n");
1361: goto store_next;
1362: default:
1363: cpu_abort(env, "Invalid exception 0x1600 !\n");
1364: break;
1365: }
1366: return;
1367: case 0x1700:
1368: switch (PPC_EXCP(env)) {
1369: case PPC_FLAGS_EXCP_7x0:
1370: case PPC_FLAGS_EXCP_7x5:
1371: /* Thermal management interrupt on G3 */
1372: /* XXX: TODO */
1373: cpu_abort(env, "G3 thermal management exception "
1374: "is not implemented yet !\n");
1375: goto store_next;
1376: case PPC_FLAGS_EXCP_970:
1377: /* VPU assist on 970 */
1378: /* XXX: TODO */
1379: cpu_abort(env,
1380: "970 VPU assist exception is not implemented yet !\n");
1381: goto store_next;
1382: default:
1383: cpu_abort(env, "Invalid exception 0x1700 !\n");
1384: break;
1385: }
1386: return;
1387: case 0x1800:
1388: switch (PPC_EXCP(env)) {
1389: case PPC_FLAGS_EXCP_970:
1390: /* Thermal exception on 970 */
1391: /* XXX: TODO */
1392: cpu_abort(env, "970 thermal management exception "
1393: "is not implemented yet !\n");
1394: goto store_next;
1395: default:
1396: cpu_abort(env, "Invalid exception 0x1800 !\n");
1397: break;
1398: }
1399: return;
1400: case 0x2000:
1401: switch (PPC_EXCP(env)) {
1402: case PPC_FLAGS_EXCP_40x:
1403: /* DEBUG on 4xx */
1404: /* XXX: TODO */
1405: cpu_abort(env, "40x debug exception is not implemented yet !\n");
1406: goto store_next;
1407: case PPC_FLAGS_EXCP_601:
1408: /* Run mode exception on 601 */
1409: /* XXX: TODO */
1410: cpu_abort(env,
1411: "601 run mode exception is not implemented yet !\n");
1412: goto store_next;
1413: default:
1414: cpu_abort(env, "Invalid exception 0x1800 !\n");
1415: break;
1416: }
1417: return;
1418: /* Other exceptions */
1419: /* Qemu internal exceptions:
1420: * we should never come here with those values: abort execution
1421: */
1422: default:
1423: cpu_abort(env, "Invalid exception: code %d (%04x)\n", excp, excp);
1424: return;
1425: store_current:
1426: /* save current instruction location */
1427: *srr_0 = (env->nip - 4) & 0xFFFFFFFFULL;
1428: break;
1429: store_next:
1430: /* save next instruction location */
1431: *srr_0 = env->nip & 0xFFFFFFFFULL;
1432: break;
1433: }
1434: /* Save msr */
1435: *srr_1 = msr;
1436: /* If we disactivated any translation, flush TLBs */
1437: if (msr_ir || msr_dr) {
1438: tlb_flush(env, 1);
1439: }
1440: /* reload MSR with correct bits */
1441: msr_ee = 0;
1442: msr_pr = 0;
1443: msr_fp = 0;
1444: msr_fe0 = 0;
1445: msr_se = 0;
1446: msr_be = 0;
1447: msr_fe1 = 0;
1448: msr_ir = 0;
1449: msr_dr = 0;
1450: msr_ri = 0;
1451: msr_le = msr_ile;
1452: msr_sf = msr_isf;
1453: do_compute_hflags(env);
1454: /* Jump to handler */
1455: env->nip = excp;
1456: env->exception_index = EXCP_NONE;
1457: }
1458: #endif /* !CONFIG_USER_ONLY */
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