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1.1 root 1: #include "hw/hw.h"
2: #include "hw/boards.h"
1.1.1.2 ! root 3: #include "kvm.h"
1.1 root 4:
5: void cpu_save(QEMUFile *f, void *opaque)
6: {
7: CPUState *env = (CPUState *)opaque;
8: unsigned int i, j;
9:
1.1.1.2 ! root 10: cpu_synchronize_state(env, 0);
! 11:
1.1 root 12: for (i = 0; i < 32; i++)
13: qemu_put_betls(f, &env->gpr[i]);
14: #if !defined(TARGET_PPC64)
15: for (i = 0; i < 32; i++)
16: qemu_put_betls(f, &env->gprh[i]);
17: #endif
18: qemu_put_betls(f, &env->lr);
19: qemu_put_betls(f, &env->ctr);
20: for (i = 0; i < 8; i++)
21: qemu_put_be32s(f, &env->crf[i]);
22: qemu_put_betls(f, &env->xer);
23: qemu_put_betls(f, &env->reserve);
24: qemu_put_betls(f, &env->msr);
25: for (i = 0; i < 4; i++)
26: qemu_put_betls(f, &env->tgpr[i]);
27: for (i = 0; i < 32; i++) {
28: union {
29: float64 d;
30: uint64_t l;
31: } u;
32: u.d = env->fpr[i];
33: qemu_put_be64(f, u.l);
34: }
35: qemu_put_be32s(f, &env->fpscr);
36: qemu_put_sbe32s(f, &env->access_type);
37: #if !defined(CONFIG_USER_ONLY)
38: #if defined(TARGET_PPC64)
39: qemu_put_betls(f, &env->asr);
40: qemu_put_sbe32s(f, &env->slb_nr);
41: #endif
42: qemu_put_betls(f, &env->sdr1);
43: for (i = 0; i < 32; i++)
44: qemu_put_betls(f, &env->sr[i]);
45: for (i = 0; i < 2; i++)
46: for (j = 0; j < 8; j++)
47: qemu_put_betls(f, &env->DBAT[i][j]);
48: for (i = 0; i < 2; i++)
49: for (j = 0; j < 8; j++)
50: qemu_put_betls(f, &env->IBAT[i][j]);
51: qemu_put_sbe32s(f, &env->nb_tlb);
52: qemu_put_sbe32s(f, &env->tlb_per_way);
53: qemu_put_sbe32s(f, &env->nb_ways);
54: qemu_put_sbe32s(f, &env->last_way);
55: qemu_put_sbe32s(f, &env->id_tlbs);
56: qemu_put_sbe32s(f, &env->nb_pids);
57: if (env->tlb) {
58: // XXX assumes 6xx
59: for (i = 0; i < env->nb_tlb; i++) {
60: qemu_put_betls(f, &env->tlb[i].tlb6.pte0);
61: qemu_put_betls(f, &env->tlb[i].tlb6.pte1);
62: qemu_put_betls(f, &env->tlb[i].tlb6.EPN);
63: }
64: }
65: for (i = 0; i < 4; i++)
66: qemu_put_betls(f, &env->pb[i]);
67: #endif
68: for (i = 0; i < 1024; i++)
69: qemu_put_betls(f, &env->spr[i]);
70: qemu_put_be32s(f, &env->vscr);
71: qemu_put_be64s(f, &env->spe_acc);
72: qemu_put_be32s(f, &env->spe_fscr);
73: qemu_put_betls(f, &env->msr_mask);
74: qemu_put_be32s(f, &env->flags);
75: qemu_put_sbe32s(f, &env->error_code);
76: qemu_put_be32s(f, &env->pending_interrupts);
77: #if !defined(CONFIG_USER_ONLY)
78: qemu_put_be32s(f, &env->irq_input_state);
79: for (i = 0; i < POWERPC_EXCP_NB; i++)
80: qemu_put_betls(f, &env->excp_vectors[i]);
81: qemu_put_betls(f, &env->excp_prefix);
1.1.1.2 ! root 82: qemu_put_betls(f, &env->hreset_excp_prefix);
1.1 root 83: qemu_put_betls(f, &env->ivor_mask);
84: qemu_put_betls(f, &env->ivpr_mask);
85: qemu_put_betls(f, &env->hreset_vector);
86: #endif
87: qemu_put_betls(f, &env->nip);
88: qemu_put_betls(f, &env->hflags);
89: qemu_put_betls(f, &env->hflags_nmsr);
90: qemu_put_sbe32s(f, &env->mmu_idx);
91: qemu_put_sbe32s(f, &env->power_mode);
92: }
93:
94: int cpu_load(QEMUFile *f, void *opaque, int version_id)
95: {
96: CPUState *env = (CPUState *)opaque;
97: unsigned int i, j;
98:
99: for (i = 0; i < 32; i++)
100: qemu_get_betls(f, &env->gpr[i]);
101: #if !defined(TARGET_PPC64)
102: for (i = 0; i < 32; i++)
103: qemu_get_betls(f, &env->gprh[i]);
104: #endif
105: qemu_get_betls(f, &env->lr);
106: qemu_get_betls(f, &env->ctr);
107: for (i = 0; i < 8; i++)
108: qemu_get_be32s(f, &env->crf[i]);
109: qemu_get_betls(f, &env->xer);
110: qemu_get_betls(f, &env->reserve);
111: qemu_get_betls(f, &env->msr);
112: for (i = 0; i < 4; i++)
113: qemu_get_betls(f, &env->tgpr[i]);
114: for (i = 0; i < 32; i++) {
115: union {
116: float64 d;
117: uint64_t l;
118: } u;
119: u.l = qemu_get_be64(f);
120: env->fpr[i] = u.d;
121: }
122: qemu_get_be32s(f, &env->fpscr);
123: qemu_get_sbe32s(f, &env->access_type);
124: #if !defined(CONFIG_USER_ONLY)
125: #if defined(TARGET_PPC64)
126: qemu_get_betls(f, &env->asr);
127: qemu_get_sbe32s(f, &env->slb_nr);
128: #endif
129: qemu_get_betls(f, &env->sdr1);
130: for (i = 0; i < 32; i++)
131: qemu_get_betls(f, &env->sr[i]);
132: for (i = 0; i < 2; i++)
133: for (j = 0; j < 8; j++)
134: qemu_get_betls(f, &env->DBAT[i][j]);
135: for (i = 0; i < 2; i++)
136: for (j = 0; j < 8; j++)
137: qemu_get_betls(f, &env->IBAT[i][j]);
138: qemu_get_sbe32s(f, &env->nb_tlb);
139: qemu_get_sbe32s(f, &env->tlb_per_way);
140: qemu_get_sbe32s(f, &env->nb_ways);
141: qemu_get_sbe32s(f, &env->last_way);
142: qemu_get_sbe32s(f, &env->id_tlbs);
143: qemu_get_sbe32s(f, &env->nb_pids);
144: if (env->tlb) {
145: // XXX assumes 6xx
146: for (i = 0; i < env->nb_tlb; i++) {
147: qemu_get_betls(f, &env->tlb[i].tlb6.pte0);
148: qemu_get_betls(f, &env->tlb[i].tlb6.pte1);
149: qemu_get_betls(f, &env->tlb[i].tlb6.EPN);
150: }
151: }
152: for (i = 0; i < 4; i++)
153: qemu_get_betls(f, &env->pb[i]);
154: #endif
155: for (i = 0; i < 1024; i++)
156: qemu_get_betls(f, &env->spr[i]);
157: qemu_get_be32s(f, &env->vscr);
158: qemu_get_be64s(f, &env->spe_acc);
159: qemu_get_be32s(f, &env->spe_fscr);
160: qemu_get_betls(f, &env->msr_mask);
161: qemu_get_be32s(f, &env->flags);
162: qemu_get_sbe32s(f, &env->error_code);
163: qemu_get_be32s(f, &env->pending_interrupts);
164: #if !defined(CONFIG_USER_ONLY)
165: qemu_get_be32s(f, &env->irq_input_state);
166: for (i = 0; i < POWERPC_EXCP_NB; i++)
167: qemu_get_betls(f, &env->excp_vectors[i]);
168: qemu_get_betls(f, &env->excp_prefix);
1.1.1.2 ! root 169: qemu_get_betls(f, &env->hreset_excp_prefix);
1.1 root 170: qemu_get_betls(f, &env->ivor_mask);
171: qemu_get_betls(f, &env->ivpr_mask);
172: qemu_get_betls(f, &env->hreset_vector);
173: #endif
174: qemu_get_betls(f, &env->nip);
175: qemu_get_betls(f, &env->hflags);
176: qemu_get_betls(f, &env->hflags_nmsr);
177: qemu_get_sbe32s(f, &env->mmu_idx);
178: qemu_get_sbe32s(f, &env->power_mode);
179:
1.1.1.2 ! root 180: cpu_synchronize_state(env, 1);
! 181:
1.1 root 182: return 0;
183: }
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