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1.1 root 1: /*
2: * PowerPC emulation for qemu: main translation routines.
3: *
4: * Copyright (c) 2003-2005 Jocelyn Mayer
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
17: * License along with this library; if not, write to the Free Software
18: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19: */
20: #include <stdarg.h>
21: #include <stdlib.h>
22: #include <stdio.h>
23: #include <string.h>
24: #include <inttypes.h>
25:
26: #include "cpu.h"
27: #include "exec-all.h"
28: #include "disas.h"
29:
30: //#define DO_SINGLE_STEP
31: //#define PPC_DEBUG_DISAS
32:
1.1.1.2 root 33: #ifdef USE_DIRECT_JUMP
34: #define TBPARAM(x)
35: #else
36: #define TBPARAM(x) (long)(x)
37: #endif
38:
1.1 root 39: enum {
40: #define DEF(s, n, copy_size) INDEX_op_ ## s,
41: #include "opc.h"
42: #undef DEF
43: NB_OPS,
44: };
45:
46: static uint16_t *gen_opc_ptr;
47: static uint32_t *gen_opparam_ptr;
48:
49: #include "gen-op.h"
50:
51: #define GEN8(func, NAME) \
52: static GenOpFunc *NAME ## _table [8] = { \
53: NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
54: NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
55: }; \
56: static inline void func(int n) \
57: { \
58: NAME ## _table[n](); \
59: }
60:
61: #define GEN16(func, NAME) \
62: static GenOpFunc *NAME ## _table [16] = { \
63: NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
64: NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
65: NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
66: NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
67: }; \
68: static inline void func(int n) \
69: { \
70: NAME ## _table[n](); \
71: }
72:
73: #define GEN32(func, NAME) \
74: static GenOpFunc *NAME ## _table [32] = { \
75: NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
76: NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
77: NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
78: NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
79: NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
80: NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
81: NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
82: NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
83: }; \
84: static inline void func(int n) \
85: { \
86: NAME ## _table[n](); \
87: }
88:
89: /* Condition register moves */
90: GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
91: GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
92: GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
93: GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
94:
95: /* Floating point condition and status register moves */
96: GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
97: GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
98: GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
99: static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = {
100: &gen_op_store_T0_fpscri_fpscr0,
101: &gen_op_store_T0_fpscri_fpscr1,
102: &gen_op_store_T0_fpscri_fpscr2,
103: &gen_op_store_T0_fpscri_fpscr3,
104: &gen_op_store_T0_fpscri_fpscr4,
105: &gen_op_store_T0_fpscri_fpscr5,
106: &gen_op_store_T0_fpscri_fpscr6,
107: &gen_op_store_T0_fpscri_fpscr7,
108: };
109: static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
110: {
111: (*gen_op_store_T0_fpscri_fpscr_table[n])(param);
112: }
113:
114: /* Segment register moves */
115: GEN16(gen_op_load_sr, gen_op_load_sr);
116: GEN16(gen_op_store_sr, gen_op_store_sr);
117:
118: /* General purpose registers moves */
119: GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
120: GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
121: GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
122:
123: GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
124: GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
125: GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
126:
127: /* floating point registers moves */
128: GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
129: GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
130: GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
131: GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
132: GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
133: GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
134:
135: static uint8_t spr_access[1024 / 2];
136:
137: /* internal defines */
138: typedef struct DisasContext {
139: struct TranslationBlock *tb;
140: target_ulong nip;
141: uint32_t opcode;
142: uint32_t exception;
143: /* Routine used to access memory */
144: int mem_idx;
145: /* Translation flags */
146: #if !defined(CONFIG_USER_ONLY)
147: int supervisor;
148: #endif
149: int fpu_enabled;
150: ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
1.1.1.3 root 151: int singlestep_enabled;
1.1 root 152: } DisasContext;
153:
154: struct opc_handler_t {
155: /* invalid bits */
156: uint32_t inval;
157: /* instruction type */
158: uint32_t type;
159: /* handler */
160: void (*handler)(DisasContext *ctx);
161: };
162:
163: #define RET_EXCP(ctx, excp, error) \
164: do { \
165: if ((ctx)->exception == EXCP_NONE) { \
166: gen_op_update_nip((ctx)->nip); \
167: } \
168: gen_op_raise_exception_err((excp), (error)); \
169: ctx->exception = (excp); \
170: } while (0)
171:
172: #define RET_INVAL(ctx) \
173: RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)
174:
175: #define RET_PRIVOPC(ctx) \
176: RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)
177:
178: #define RET_PRIVREG(ctx) \
179: RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)
180:
1.1.1.2 root 181: /* Stop translation */
1.1 root 182: static inline void RET_STOP (DisasContext *ctx)
183: {
1.1.1.2 root 184: gen_op_update_nip((ctx)->nip);
185: ctx->exception = EXCP_MTMSR;
1.1 root 186: }
187:
1.1.1.2 root 188: /* No need to update nip here, as execution flow will change */
1.1 root 189: static inline void RET_CHG_FLOW (DisasContext *ctx)
190: {
191: ctx->exception = EXCP_MTMSR;
192: }
193:
194: #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
195: static void gen_##name (DisasContext *ctx); \
196: GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
197: static void gen_##name (DisasContext *ctx)
198:
199: typedef struct opcode_t {
200: unsigned char opc1, opc2, opc3;
201: #if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
202: unsigned char pad[5];
203: #else
204: unsigned char pad[1];
205: #endif
206: opc_handler_t handler;
207: const unsigned char *oname;
208: } opcode_t;
209:
210: /*** Instruction decoding ***/
211: #define EXTRACT_HELPER(name, shift, nb) \
212: static inline uint32_t name (uint32_t opcode) \
213: { \
214: return (opcode >> (shift)) & ((1 << (nb)) - 1); \
215: }
216:
217: #define EXTRACT_SHELPER(name, shift, nb) \
218: static inline int32_t name (uint32_t opcode) \
219: { \
220: return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
221: }
222:
223: /* Opcode part 1 */
224: EXTRACT_HELPER(opc1, 26, 6);
225: /* Opcode part 2 */
226: EXTRACT_HELPER(opc2, 1, 5);
227: /* Opcode part 3 */
228: EXTRACT_HELPER(opc3, 6, 5);
229: /* Update Cr0 flags */
230: EXTRACT_HELPER(Rc, 0, 1);
231: /* Destination */
232: EXTRACT_HELPER(rD, 21, 5);
233: /* Source */
234: EXTRACT_HELPER(rS, 21, 5);
235: /* First operand */
236: EXTRACT_HELPER(rA, 16, 5);
237: /* Second operand */
238: EXTRACT_HELPER(rB, 11, 5);
239: /* Third operand */
240: EXTRACT_HELPER(rC, 6, 5);
241: /*** Get CRn ***/
242: EXTRACT_HELPER(crfD, 23, 3);
243: EXTRACT_HELPER(crfS, 18, 3);
244: EXTRACT_HELPER(crbD, 21, 5);
245: EXTRACT_HELPER(crbA, 16, 5);
246: EXTRACT_HELPER(crbB, 11, 5);
247: /* SPR / TBL */
248: EXTRACT_HELPER(_SPR, 11, 10);
249: static inline uint32_t SPR (uint32_t opcode)
250: {
251: uint32_t sprn = _SPR(opcode);
252:
253: return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
254: }
255: /*** Get constants ***/
256: EXTRACT_HELPER(IMM, 12, 8);
257: /* 16 bits signed immediate value */
258: EXTRACT_SHELPER(SIMM, 0, 16);
259: /* 16 bits unsigned immediate value */
260: EXTRACT_HELPER(UIMM, 0, 16);
261: /* Bit count */
262: EXTRACT_HELPER(NB, 11, 5);
263: /* Shift count */
264: EXTRACT_HELPER(SH, 11, 5);
265: /* Mask start */
266: EXTRACT_HELPER(MB, 6, 5);
267: /* Mask end */
268: EXTRACT_HELPER(ME, 1, 5);
269: /* Trap operand */
270: EXTRACT_HELPER(TO, 21, 5);
271:
272: EXTRACT_HELPER(CRM, 12, 8);
273: EXTRACT_HELPER(FM, 17, 8);
274: EXTRACT_HELPER(SR, 16, 4);
275: EXTRACT_HELPER(FPIMM, 20, 4);
276:
277: /*** Jump target decoding ***/
278: /* Displacement */
279: EXTRACT_SHELPER(d, 0, 16);
280: /* Immediate address */
281: static inline uint32_t LI (uint32_t opcode)
282: {
283: return (opcode >> 0) & 0x03FFFFFC;
284: }
285:
286: static inline uint32_t BD (uint32_t opcode)
287: {
288: return (opcode >> 0) & 0xFFFC;
289: }
290:
291: EXTRACT_HELPER(BO, 21, 5);
292: EXTRACT_HELPER(BI, 16, 5);
293: /* Absolute/relative address */
294: EXTRACT_HELPER(AA, 1, 1);
295: /* Link */
296: EXTRACT_HELPER(LK, 0, 1);
297:
298: /* Create a mask between <start> and <end> bits */
299: static inline uint32_t MASK (uint32_t start, uint32_t end)
300: {
301: uint32_t ret;
302:
303: ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1);
304: if (start > end)
305: return ~ret;
306:
307: return ret;
308: }
309:
310: #if HOST_LONG_BITS == 64
311: #define OPC_ALIGN 8
312: #else
313: #define OPC_ALIGN 4
314: #endif
315: #if defined(__APPLE__)
316: #define OPCODES_SECTION \
317: __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
318: #else
319: #define OPCODES_SECTION \
320: __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
321: #endif
322:
323: #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
324: OPCODES_SECTION opcode_t opc_##name = { \
325: .opc1 = op1, \
326: .opc2 = op2, \
327: .opc3 = op3, \
328: .pad = { 0, }, \
329: .handler = { \
330: .inval = invl, \
331: .type = _typ, \
332: .handler = &gen_##name, \
333: }, \
334: .oname = stringify(name), \
335: }
336:
337: #define GEN_OPCODE_MARK(name) \
338: OPCODES_SECTION opcode_t opc_##name = { \
339: .opc1 = 0xFF, \
340: .opc2 = 0xFF, \
341: .opc3 = 0xFF, \
342: .pad = { 0, }, \
343: .handler = { \
344: .inval = 0x00000000, \
345: .type = 0x00, \
346: .handler = NULL, \
347: }, \
348: .oname = stringify(name), \
349: }
350:
351: /* Start opcode list */
352: GEN_OPCODE_MARK(start);
353:
354: /* Invalid instruction */
355: GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
356: {
357: RET_INVAL(ctx);
358: }
359:
360: static opc_handler_t invalid_handler = {
361: .inval = 0xFFFFFFFF,
362: .type = PPC_NONE,
363: .handler = gen_invalid,
364: };
365:
366: /*** Integer arithmetic ***/
367: #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval) \
368: GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
369: { \
370: gen_op_load_gpr_T0(rA(ctx->opcode)); \
371: gen_op_load_gpr_T1(rB(ctx->opcode)); \
372: gen_op_##name(); \
373: if (Rc(ctx->opcode) != 0) \
374: gen_op_set_Rc0(); \
375: gen_op_store_T0_gpr(rD(ctx->opcode)); \
376: }
377:
378: #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval) \
379: GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
380: { \
381: gen_op_load_gpr_T0(rA(ctx->opcode)); \
382: gen_op_load_gpr_T1(rB(ctx->opcode)); \
383: gen_op_##name(); \
384: if (Rc(ctx->opcode) != 0) \
385: gen_op_set_Rc0(); \
386: gen_op_store_T0_gpr(rD(ctx->opcode)); \
387: }
388:
389: #define __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
390: GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
391: { \
392: gen_op_load_gpr_T0(rA(ctx->opcode)); \
393: gen_op_##name(); \
394: if (Rc(ctx->opcode) != 0) \
395: gen_op_set_Rc0(); \
396: gen_op_store_T0_gpr(rD(ctx->opcode)); \
397: }
398: #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3) \
399: GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
400: { \
401: gen_op_load_gpr_T0(rA(ctx->opcode)); \
402: gen_op_##name(); \
403: if (Rc(ctx->opcode) != 0) \
404: gen_op_set_Rc0(); \
405: gen_op_store_T0_gpr(rD(ctx->opcode)); \
406: }
407:
408: /* Two operands arithmetic functions */
409: #define GEN_INT_ARITH2(name, opc1, opc2, opc3) \
410: __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000) \
411: __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000)
412:
413: /* Two operands arithmetic functions with no overflow allowed */
414: #define GEN_INT_ARITHN(name, opc1, opc2, opc3) \
415: __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
416:
417: /* One operand arithmetic functions */
418: #define GEN_INT_ARITH1(name, opc1, opc2, opc3) \
419: __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
420: __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10)
421:
422: /* add add. addo addo. */
423: GEN_INT_ARITH2 (add, 0x1F, 0x0A, 0x08);
424: /* addc addc. addco addco. */
425: GEN_INT_ARITH2 (addc, 0x1F, 0x0A, 0x00);
426: /* adde adde. addeo addeo. */
427: GEN_INT_ARITH2 (adde, 0x1F, 0x0A, 0x04);
428: /* addme addme. addmeo addmeo. */
429: GEN_INT_ARITH1 (addme, 0x1F, 0x0A, 0x07);
430: /* addze addze. addzeo addzeo. */
431: GEN_INT_ARITH1 (addze, 0x1F, 0x0A, 0x06);
432: /* divw divw. divwo divwo. */
433: GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F);
434: /* divwu divwu. divwuo divwuo. */
435: GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E);
436: /* mulhw mulhw. */
437: GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02);
438: /* mulhwu mulhwu. */
439: GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00);
440: /* mullw mullw. mullwo mullwo. */
441: GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07);
442: /* neg neg. nego nego. */
443: GEN_INT_ARITH1 (neg, 0x1F, 0x08, 0x03);
444: /* subf subf. subfo subfo. */
445: GEN_INT_ARITH2 (subf, 0x1F, 0x08, 0x01);
446: /* subfc subfc. subfco subfco. */
447: GEN_INT_ARITH2 (subfc, 0x1F, 0x08, 0x00);
448: /* subfe subfe. subfeo subfeo. */
449: GEN_INT_ARITH2 (subfe, 0x1F, 0x08, 0x04);
450: /* subfme subfme. subfmeo subfmeo. */
451: GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07);
452: /* subfze subfze. subfzeo subfzeo. */
453: GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06);
454: /* addi */
455: GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
456: {
457: int32_t simm = SIMM(ctx->opcode);
458:
459: if (rA(ctx->opcode) == 0) {
460: gen_op_set_T0(simm);
461: } else {
462: gen_op_load_gpr_T0(rA(ctx->opcode));
463: gen_op_addi(simm);
464: }
465: gen_op_store_T0_gpr(rD(ctx->opcode));
466: }
467: /* addic */
468: GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
469: {
470: gen_op_load_gpr_T0(rA(ctx->opcode));
471: gen_op_addic(SIMM(ctx->opcode));
472: gen_op_store_T0_gpr(rD(ctx->opcode));
473: }
474: /* addic. */
475: GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
476: {
477: gen_op_load_gpr_T0(rA(ctx->opcode));
478: gen_op_addic(SIMM(ctx->opcode));
479: gen_op_set_Rc0();
480: gen_op_store_T0_gpr(rD(ctx->opcode));
481: }
482: /* addis */
483: GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
484: {
485: int32_t simm = SIMM(ctx->opcode);
486:
487: if (rA(ctx->opcode) == 0) {
488: gen_op_set_T0(simm << 16);
489: } else {
490: gen_op_load_gpr_T0(rA(ctx->opcode));
491: gen_op_addi(simm << 16);
492: }
493: gen_op_store_T0_gpr(rD(ctx->opcode));
494: }
495: /* mulli */
496: GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
497: {
498: gen_op_load_gpr_T0(rA(ctx->opcode));
499: gen_op_mulli(SIMM(ctx->opcode));
500: gen_op_store_T0_gpr(rD(ctx->opcode));
501: }
502: /* subfic */
503: GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
504: {
505: gen_op_load_gpr_T0(rA(ctx->opcode));
506: gen_op_subfic(SIMM(ctx->opcode));
507: gen_op_store_T0_gpr(rD(ctx->opcode));
508: }
509:
510: /*** Integer comparison ***/
511: #define GEN_CMP(name, opc) \
512: GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER) \
513: { \
514: gen_op_load_gpr_T0(rA(ctx->opcode)); \
515: gen_op_load_gpr_T1(rB(ctx->opcode)); \
516: gen_op_##name(); \
517: gen_op_store_T0_crf(crfD(ctx->opcode)); \
518: }
519:
520: /* cmp */
521: GEN_CMP(cmp, 0x00);
522: /* cmpi */
523: GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
524: {
525: gen_op_load_gpr_T0(rA(ctx->opcode));
526: gen_op_cmpi(SIMM(ctx->opcode));
527: gen_op_store_T0_crf(crfD(ctx->opcode));
528: }
529: /* cmpl */
530: GEN_CMP(cmpl, 0x01);
531: /* cmpli */
532: GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
533: {
534: gen_op_load_gpr_T0(rA(ctx->opcode));
535: gen_op_cmpli(UIMM(ctx->opcode));
536: gen_op_store_T0_crf(crfD(ctx->opcode));
537: }
538:
539: /*** Integer logical ***/
540: #define __GEN_LOGICAL2(name, opc2, opc3) \
541: GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER) \
542: { \
543: gen_op_load_gpr_T0(rS(ctx->opcode)); \
544: gen_op_load_gpr_T1(rB(ctx->opcode)); \
545: gen_op_##name(); \
546: if (Rc(ctx->opcode) != 0) \
547: gen_op_set_Rc0(); \
548: gen_op_store_T0_gpr(rA(ctx->opcode)); \
549: }
550: #define GEN_LOGICAL2(name, opc) \
551: __GEN_LOGICAL2(name, 0x1C, opc)
552:
553: #define GEN_LOGICAL1(name, opc) \
554: GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER) \
555: { \
556: gen_op_load_gpr_T0(rS(ctx->opcode)); \
557: gen_op_##name(); \
558: if (Rc(ctx->opcode) != 0) \
559: gen_op_set_Rc0(); \
560: gen_op_store_T0_gpr(rA(ctx->opcode)); \
561: }
562:
563: /* and & and. */
564: GEN_LOGICAL2(and, 0x00);
565: /* andc & andc. */
566: GEN_LOGICAL2(andc, 0x01);
567: /* andi. */
568: GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
569: {
570: gen_op_load_gpr_T0(rS(ctx->opcode));
571: gen_op_andi_(UIMM(ctx->opcode));
572: gen_op_set_Rc0();
573: gen_op_store_T0_gpr(rA(ctx->opcode));
574: }
575: /* andis. */
576: GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
577: {
578: gen_op_load_gpr_T0(rS(ctx->opcode));
579: gen_op_andi_(UIMM(ctx->opcode) << 16);
580: gen_op_set_Rc0();
581: gen_op_store_T0_gpr(rA(ctx->opcode));
582: }
583:
584: /* cntlzw */
585: GEN_LOGICAL1(cntlzw, 0x00);
586: /* eqv & eqv. */
587: GEN_LOGICAL2(eqv, 0x08);
588: /* extsb & extsb. */
589: GEN_LOGICAL1(extsb, 0x1D);
590: /* extsh & extsh. */
591: GEN_LOGICAL1(extsh, 0x1C);
592: /* nand & nand. */
593: GEN_LOGICAL2(nand, 0x0E);
594: /* nor & nor. */
595: GEN_LOGICAL2(nor, 0x03);
596:
597: /* or & or. */
598: GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
599: {
600: gen_op_load_gpr_T0(rS(ctx->opcode));
601: /* Optimisation for mr case */
602: if (rS(ctx->opcode) != rB(ctx->opcode)) {
603: gen_op_load_gpr_T1(rB(ctx->opcode));
604: gen_op_or();
605: }
606: if (Rc(ctx->opcode) != 0)
607: gen_op_set_Rc0();
608: gen_op_store_T0_gpr(rA(ctx->opcode));
609: }
610:
611: /* orc & orc. */
612: GEN_LOGICAL2(orc, 0x0C);
613: /* xor & xor. */
614: GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
615: {
616: gen_op_load_gpr_T0(rS(ctx->opcode));
617: /* Optimisation for "set to zero" case */
618: if (rS(ctx->opcode) != rB(ctx->opcode)) {
619: gen_op_load_gpr_T1(rB(ctx->opcode));
620: gen_op_xor();
621: } else {
622: gen_op_set_T0(0);
623: }
624: if (Rc(ctx->opcode) != 0)
625: gen_op_set_Rc0();
626: gen_op_store_T0_gpr(rA(ctx->opcode));
627: }
628: /* ori */
629: GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
630: {
631: uint32_t uimm = UIMM(ctx->opcode);
632:
633: if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
634: /* NOP */
635: return;
636: }
637: gen_op_load_gpr_T0(rS(ctx->opcode));
638: if (uimm != 0)
639: gen_op_ori(uimm);
640: gen_op_store_T0_gpr(rA(ctx->opcode));
641: }
642: /* oris */
643: GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
644: {
645: uint32_t uimm = UIMM(ctx->opcode);
646:
647: if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
648: /* NOP */
649: return;
650: }
651: gen_op_load_gpr_T0(rS(ctx->opcode));
652: if (uimm != 0)
653: gen_op_ori(uimm << 16);
654: gen_op_store_T0_gpr(rA(ctx->opcode));
655: }
656: /* xori */
657: GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
658: {
659: uint32_t uimm = UIMM(ctx->opcode);
660:
661: if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
662: /* NOP */
663: return;
664: }
665: gen_op_load_gpr_T0(rS(ctx->opcode));
666: if (uimm != 0)
667: gen_op_xori(uimm);
668: gen_op_store_T0_gpr(rA(ctx->opcode));
669: }
670:
671: /* xoris */
672: GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
673: {
674: uint32_t uimm = UIMM(ctx->opcode);
675:
676: if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
677: /* NOP */
678: return;
679: }
680: gen_op_load_gpr_T0(rS(ctx->opcode));
681: if (uimm != 0)
682: gen_op_xori(uimm << 16);
683: gen_op_store_T0_gpr(rA(ctx->opcode));
684: }
685:
686: /*** Integer rotate ***/
687: /* rlwimi & rlwimi. */
688: GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
689: {
690: uint32_t mb, me;
691:
692: mb = MB(ctx->opcode);
693: me = ME(ctx->opcode);
694: gen_op_load_gpr_T0(rS(ctx->opcode));
695: gen_op_load_gpr_T1(rA(ctx->opcode));
696: gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me));
697: if (Rc(ctx->opcode) != 0)
698: gen_op_set_Rc0();
699: gen_op_store_T0_gpr(rA(ctx->opcode));
700: }
701: /* rlwinm & rlwinm. */
702: GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
703: {
704: uint32_t mb, me, sh;
705:
706: sh = SH(ctx->opcode);
707: mb = MB(ctx->opcode);
708: me = ME(ctx->opcode);
709: gen_op_load_gpr_T0(rS(ctx->opcode));
710: #if 1 // TRY
711: if (sh == 0) {
712: gen_op_andi_(MASK(mb, me));
713: goto store;
714: }
715: #endif
716: if (mb == 0) {
717: if (me == 31) {
718: gen_op_rotlwi(sh);
719: goto store;
720: #if 0
721: } else if (me == (31 - sh)) {
722: gen_op_slwi(sh);
723: goto store;
724: #endif
725: }
726: } else if (me == 31) {
727: #if 0
728: if (sh == (32 - mb)) {
729: gen_op_srwi(mb);
730: goto store;
731: }
732: #endif
733: }
734: gen_op_rlwinm(sh, MASK(mb, me));
735: store:
736: if (Rc(ctx->opcode) != 0)
737: gen_op_set_Rc0();
738: gen_op_store_T0_gpr(rA(ctx->opcode));
739: }
740: /* rlwnm & rlwnm. */
741: GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
742: {
743: uint32_t mb, me;
744:
745: mb = MB(ctx->opcode);
746: me = ME(ctx->opcode);
747: gen_op_load_gpr_T0(rS(ctx->opcode));
748: gen_op_load_gpr_T1(rB(ctx->opcode));
749: if (mb == 0 && me == 31) {
750: gen_op_rotl();
751: } else
752: {
753: gen_op_rlwnm(MASK(mb, me));
754: }
755: if (Rc(ctx->opcode) != 0)
756: gen_op_set_Rc0();
757: gen_op_store_T0_gpr(rA(ctx->opcode));
758: }
759:
760: /*** Integer shift ***/
761: /* slw & slw. */
762: __GEN_LOGICAL2(slw, 0x18, 0x00);
763: /* sraw & sraw. */
764: __GEN_LOGICAL2(sraw, 0x18, 0x18);
765: /* srawi & srawi. */
766: GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
767: {
768: gen_op_load_gpr_T0(rS(ctx->opcode));
769: if (SH(ctx->opcode) != 0)
770: gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31));
771: if (Rc(ctx->opcode) != 0)
772: gen_op_set_Rc0();
773: gen_op_store_T0_gpr(rA(ctx->opcode));
774: }
775: /* srw & srw. */
776: __GEN_LOGICAL2(srw, 0x18, 0x10);
777:
778: /*** Floating-Point arithmetic ***/
779: #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat) \
780: GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \
781: { \
782: if (!ctx->fpu_enabled) { \
783: RET_EXCP(ctx, EXCP_NO_FP, 0); \
784: return; \
785: } \
786: gen_op_reset_scrfx(); \
787: gen_op_load_fpr_FT0(rA(ctx->opcode)); \
788: gen_op_load_fpr_FT1(rC(ctx->opcode)); \
789: gen_op_load_fpr_FT2(rB(ctx->opcode)); \
790: gen_op_f##op(); \
791: if (isfloat) { \
792: gen_op_frsp(); \
793: } \
794: gen_op_store_FT0_fpr(rD(ctx->opcode)); \
795: if (Rc(ctx->opcode)) \
796: gen_op_set_Rc1(); \
797: }
798:
799: #define GEN_FLOAT_ACB(name, op2) \
800: _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0); \
801: _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1);
802:
803: #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat) \
804: GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
805: { \
806: if (!ctx->fpu_enabled) { \
807: RET_EXCP(ctx, EXCP_NO_FP, 0); \
808: return; \
809: } \
810: gen_op_reset_scrfx(); \
811: gen_op_load_fpr_FT0(rA(ctx->opcode)); \
812: gen_op_load_fpr_FT1(rB(ctx->opcode)); \
813: gen_op_f##op(); \
814: if (isfloat) { \
815: gen_op_frsp(); \
816: } \
817: gen_op_store_FT0_fpr(rD(ctx->opcode)); \
818: if (Rc(ctx->opcode)) \
819: gen_op_set_Rc1(); \
820: }
821: #define GEN_FLOAT_AB(name, op2, inval) \
822: _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0); \
823: _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1);
824:
825: #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat) \
826: GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
827: { \
828: if (!ctx->fpu_enabled) { \
829: RET_EXCP(ctx, EXCP_NO_FP, 0); \
830: return; \
831: } \
832: gen_op_reset_scrfx(); \
833: gen_op_load_fpr_FT0(rA(ctx->opcode)); \
834: gen_op_load_fpr_FT1(rC(ctx->opcode)); \
835: gen_op_f##op(); \
836: if (isfloat) { \
837: gen_op_frsp(); \
838: } \
839: gen_op_store_FT0_fpr(rD(ctx->opcode)); \
840: if (Rc(ctx->opcode)) \
841: gen_op_set_Rc1(); \
842: }
843: #define GEN_FLOAT_AC(name, op2, inval) \
844: _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0); \
845: _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1);
846:
847: #define GEN_FLOAT_B(name, op2, op3) \
848: GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \
849: { \
850: if (!ctx->fpu_enabled) { \
851: RET_EXCP(ctx, EXCP_NO_FP, 0); \
852: return; \
853: } \
854: gen_op_reset_scrfx(); \
855: gen_op_load_fpr_FT0(rB(ctx->opcode)); \
856: gen_op_f##name(); \
857: gen_op_store_FT0_fpr(rD(ctx->opcode)); \
858: if (Rc(ctx->opcode)) \
859: gen_op_set_Rc1(); \
860: }
861:
862: #define GEN_FLOAT_BS(name, op1, op2) \
863: GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \
864: { \
865: if (!ctx->fpu_enabled) { \
866: RET_EXCP(ctx, EXCP_NO_FP, 0); \
867: return; \
868: } \
869: gen_op_reset_scrfx(); \
870: gen_op_load_fpr_FT0(rB(ctx->opcode)); \
871: gen_op_f##name(); \
872: gen_op_store_FT0_fpr(rD(ctx->opcode)); \
873: if (Rc(ctx->opcode)) \
874: gen_op_set_Rc1(); \
875: }
876:
877: /* fadd - fadds */
878: GEN_FLOAT_AB(add, 0x15, 0x000007C0);
879: /* fdiv - fdivs */
880: GEN_FLOAT_AB(div, 0x12, 0x000007C0);
881: /* fmul - fmuls */
882: GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
883:
884: /* fres */
885: GEN_FLOAT_BS(res, 0x3B, 0x18);
886:
887: /* frsqrte */
888: GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A);
889:
890: /* fsel */
891: _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0);
892: /* fsub - fsubs */
893: GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
894: /* Optional: */
895: /* fsqrt */
896: GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
897: {
898: if (!ctx->fpu_enabled) {
899: RET_EXCP(ctx, EXCP_NO_FP, 0);
900: return;
901: }
902: gen_op_reset_scrfx();
903: gen_op_load_fpr_FT0(rB(ctx->opcode));
904: gen_op_fsqrt();
905: gen_op_store_FT0_fpr(rD(ctx->opcode));
906: if (Rc(ctx->opcode))
907: gen_op_set_Rc1();
908: }
909:
910: GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
911: {
912: if (!ctx->fpu_enabled) {
913: RET_EXCP(ctx, EXCP_NO_FP, 0);
914: return;
915: }
916: gen_op_reset_scrfx();
917: gen_op_load_fpr_FT0(rB(ctx->opcode));
918: gen_op_fsqrt();
919: gen_op_frsp();
920: gen_op_store_FT0_fpr(rD(ctx->opcode));
921: if (Rc(ctx->opcode))
922: gen_op_set_Rc1();
923: }
924:
925: /*** Floating-Point multiply-and-add ***/
926: /* fmadd - fmadds */
927: GEN_FLOAT_ACB(madd, 0x1D);
928: /* fmsub - fmsubs */
929: GEN_FLOAT_ACB(msub, 0x1C);
930: /* fnmadd - fnmadds */
931: GEN_FLOAT_ACB(nmadd, 0x1F);
932: /* fnmsub - fnmsubs */
933: GEN_FLOAT_ACB(nmsub, 0x1E);
934:
935: /*** Floating-Point round & convert ***/
936: /* fctiw */
937: GEN_FLOAT_B(ctiw, 0x0E, 0x00);
938: /* fctiwz */
939: GEN_FLOAT_B(ctiwz, 0x0F, 0x00);
940: /* frsp */
941: GEN_FLOAT_B(rsp, 0x0C, 0x00);
942:
943: /*** Floating-Point compare ***/
944: /* fcmpo */
945: GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
946: {
947: if (!ctx->fpu_enabled) {
948: RET_EXCP(ctx, EXCP_NO_FP, 0);
949: return;
950: }
951: gen_op_reset_scrfx();
952: gen_op_load_fpr_FT0(rA(ctx->opcode));
953: gen_op_load_fpr_FT1(rB(ctx->opcode));
954: gen_op_fcmpo();
955: gen_op_store_T0_crf(crfD(ctx->opcode));
956: }
957:
958: /* fcmpu */
959: GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
960: {
961: if (!ctx->fpu_enabled) {
962: RET_EXCP(ctx, EXCP_NO_FP, 0);
963: return;
964: }
965: gen_op_reset_scrfx();
966: gen_op_load_fpr_FT0(rA(ctx->opcode));
967: gen_op_load_fpr_FT1(rB(ctx->opcode));
968: gen_op_fcmpu();
969: gen_op_store_T0_crf(crfD(ctx->opcode));
970: }
971:
972: /*** Floating-point move ***/
973: /* fabs */
974: GEN_FLOAT_B(abs, 0x08, 0x08);
975:
976: /* fmr - fmr. */
977: GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
978: {
979: if (!ctx->fpu_enabled) {
980: RET_EXCP(ctx, EXCP_NO_FP, 0);
981: return;
982: }
983: gen_op_reset_scrfx();
984: gen_op_load_fpr_FT0(rB(ctx->opcode));
985: gen_op_store_FT0_fpr(rD(ctx->opcode));
986: if (Rc(ctx->opcode))
987: gen_op_set_Rc1();
988: }
989:
990: /* fnabs */
991: GEN_FLOAT_B(nabs, 0x08, 0x04);
992: /* fneg */
993: GEN_FLOAT_B(neg, 0x08, 0x01);
994:
995: /*** Floating-Point status & ctrl register ***/
996: /* mcrfs */
997: GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
998: {
999: if (!ctx->fpu_enabled) {
1000: RET_EXCP(ctx, EXCP_NO_FP, 0);
1001: return;
1002: }
1003: gen_op_load_fpscr_T0(crfS(ctx->opcode));
1004: gen_op_store_T0_crf(crfD(ctx->opcode));
1005: gen_op_clear_fpscr(crfS(ctx->opcode));
1006: }
1007:
1008: /* mffs */
1009: GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
1010: {
1011: if (!ctx->fpu_enabled) {
1012: RET_EXCP(ctx, EXCP_NO_FP, 0);
1013: return;
1014: }
1015: gen_op_load_fpscr();
1016: gen_op_store_FT0_fpr(rD(ctx->opcode));
1017: if (Rc(ctx->opcode))
1018: gen_op_set_Rc1();
1019: }
1020:
1021: /* mtfsb0 */
1022: GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
1023: {
1024: uint8_t crb;
1025:
1026: if (!ctx->fpu_enabled) {
1027: RET_EXCP(ctx, EXCP_NO_FP, 0);
1028: return;
1029: }
1030: crb = crbD(ctx->opcode) >> 2;
1031: gen_op_load_fpscr_T0(crb);
1032: gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03)));
1033: gen_op_store_T0_fpscr(crb);
1034: if (Rc(ctx->opcode))
1035: gen_op_set_Rc1();
1036: }
1037:
1038: /* mtfsb1 */
1039: GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
1040: {
1041: uint8_t crb;
1042:
1043: if (!ctx->fpu_enabled) {
1044: RET_EXCP(ctx, EXCP_NO_FP, 0);
1045: return;
1046: }
1047: crb = crbD(ctx->opcode) >> 2;
1048: gen_op_load_fpscr_T0(crb);
1049: gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
1050: gen_op_store_T0_fpscr(crb);
1051: if (Rc(ctx->opcode))
1052: gen_op_set_Rc1();
1053: }
1054:
1055: /* mtfsf */
1056: GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
1057: {
1058: if (!ctx->fpu_enabled) {
1059: RET_EXCP(ctx, EXCP_NO_FP, 0);
1060: return;
1061: }
1062: gen_op_load_fpr_FT0(rB(ctx->opcode));
1063: gen_op_store_fpscr(FM(ctx->opcode));
1064: if (Rc(ctx->opcode))
1065: gen_op_set_Rc1();
1066: }
1067:
1068: /* mtfsfi */
1069: GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
1070: {
1071: if (!ctx->fpu_enabled) {
1072: RET_EXCP(ctx, EXCP_NO_FP, 0);
1073: return;
1074: }
1075: gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
1076: if (Rc(ctx->opcode))
1077: gen_op_set_Rc1();
1078: }
1079:
1080: /*** Integer load ***/
1081: #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
1082: #if defined(CONFIG_USER_ONLY)
1083: #define OP_LD_TABLE(width) \
1084: static GenOpFunc *gen_op_l##width[] = { \
1085: &gen_op_l##width##_raw, \
1086: &gen_op_l##width##_le_raw, \
1087: };
1088: #define OP_ST_TABLE(width) \
1089: static GenOpFunc *gen_op_st##width[] = { \
1090: &gen_op_st##width##_raw, \
1091: &gen_op_st##width##_le_raw, \
1092: };
1093: /* Byte access routine are endian safe */
1094: #define gen_op_stb_le_raw gen_op_stb_raw
1095: #define gen_op_lbz_le_raw gen_op_lbz_raw
1096: #else
1097: #define OP_LD_TABLE(width) \
1098: static GenOpFunc *gen_op_l##width[] = { \
1099: &gen_op_l##width##_user, \
1100: &gen_op_l##width##_le_user, \
1101: &gen_op_l##width##_kernel, \
1102: &gen_op_l##width##_le_kernel, \
1103: };
1104: #define OP_ST_TABLE(width) \
1105: static GenOpFunc *gen_op_st##width[] = { \
1106: &gen_op_st##width##_user, \
1107: &gen_op_st##width##_le_user, \
1108: &gen_op_st##width##_kernel, \
1109: &gen_op_st##width##_le_kernel, \
1110: };
1111: /* Byte access routine are endian safe */
1112: #define gen_op_stb_le_user gen_op_stb_user
1113: #define gen_op_lbz_le_user gen_op_lbz_user
1114: #define gen_op_stb_le_kernel gen_op_stb_kernel
1115: #define gen_op_lbz_le_kernel gen_op_lbz_kernel
1116: #endif
1117:
1118: #define GEN_LD(width, opc) \
1119: GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1120: { \
1121: uint32_t simm = SIMM(ctx->opcode); \
1122: if (rA(ctx->opcode) == 0) { \
1123: gen_op_set_T0(simm); \
1124: } else { \
1125: gen_op_load_gpr_T0(rA(ctx->opcode)); \
1126: if (simm != 0) \
1127: gen_op_addi(simm); \
1128: } \
1129: op_ldst(l##width); \
1130: gen_op_store_T1_gpr(rD(ctx->opcode)); \
1131: }
1132:
1133: #define GEN_LDU(width, opc) \
1134: GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1135: { \
1136: uint32_t simm = SIMM(ctx->opcode); \
1137: if (rA(ctx->opcode) == 0 || \
1138: rA(ctx->opcode) == rD(ctx->opcode)) { \
1139: RET_INVAL(ctx); \
1140: return; \
1141: } \
1142: gen_op_load_gpr_T0(rA(ctx->opcode)); \
1143: if (simm != 0) \
1144: gen_op_addi(simm); \
1145: op_ldst(l##width); \
1146: gen_op_store_T1_gpr(rD(ctx->opcode)); \
1147: gen_op_store_T0_gpr(rA(ctx->opcode)); \
1148: }
1149:
1150: #define GEN_LDUX(width, opc) \
1151: GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1152: { \
1153: if (rA(ctx->opcode) == 0 || \
1154: rA(ctx->opcode) == rD(ctx->opcode)) { \
1155: RET_INVAL(ctx); \
1156: return; \
1157: } \
1158: gen_op_load_gpr_T0(rA(ctx->opcode)); \
1159: gen_op_load_gpr_T1(rB(ctx->opcode)); \
1160: gen_op_add(); \
1161: op_ldst(l##width); \
1162: gen_op_store_T1_gpr(rD(ctx->opcode)); \
1163: gen_op_store_T0_gpr(rA(ctx->opcode)); \
1164: }
1165:
1166: #define GEN_LDX(width, opc2, opc3) \
1167: GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1168: { \
1169: if (rA(ctx->opcode) == 0) { \
1170: gen_op_load_gpr_T0(rB(ctx->opcode)); \
1171: } else { \
1172: gen_op_load_gpr_T0(rA(ctx->opcode)); \
1173: gen_op_load_gpr_T1(rB(ctx->opcode)); \
1174: gen_op_add(); \
1175: } \
1176: op_ldst(l##width); \
1177: gen_op_store_T1_gpr(rD(ctx->opcode)); \
1178: }
1179:
1180: #define GEN_LDS(width, op) \
1181: OP_LD_TABLE(width); \
1182: GEN_LD(width, op | 0x20); \
1183: GEN_LDU(width, op | 0x21); \
1184: GEN_LDUX(width, op | 0x01); \
1185: GEN_LDX(width, 0x17, op | 0x00)
1186:
1187: /* lbz lbzu lbzux lbzx */
1188: GEN_LDS(bz, 0x02);
1189: /* lha lhau lhaux lhax */
1190: GEN_LDS(ha, 0x0A);
1191: /* lhz lhzu lhzux lhzx */
1192: GEN_LDS(hz, 0x08);
1193: /* lwz lwzu lwzux lwzx */
1194: GEN_LDS(wz, 0x00);
1195:
1196: /*** Integer store ***/
1197: #define GEN_ST(width, opc) \
1198: GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1199: { \
1200: uint32_t simm = SIMM(ctx->opcode); \
1201: if (rA(ctx->opcode) == 0) { \
1202: gen_op_set_T0(simm); \
1203: } else { \
1204: gen_op_load_gpr_T0(rA(ctx->opcode)); \
1205: if (simm != 0) \
1206: gen_op_addi(simm); \
1207: } \
1208: gen_op_load_gpr_T1(rS(ctx->opcode)); \
1209: op_ldst(st##width); \
1210: }
1211:
1212: #define GEN_STU(width, opc) \
1213: GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1214: { \
1215: uint32_t simm = SIMM(ctx->opcode); \
1216: if (rA(ctx->opcode) == 0) { \
1217: RET_INVAL(ctx); \
1218: return; \
1219: } \
1220: gen_op_load_gpr_T0(rA(ctx->opcode)); \
1221: if (simm != 0) \
1222: gen_op_addi(simm); \
1223: gen_op_load_gpr_T1(rS(ctx->opcode)); \
1224: op_ldst(st##width); \
1225: gen_op_store_T0_gpr(rA(ctx->opcode)); \
1226: }
1227:
1228: #define GEN_STUX(width, opc) \
1229: GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1230: { \
1231: if (rA(ctx->opcode) == 0) { \
1232: RET_INVAL(ctx); \
1233: return; \
1234: } \
1235: gen_op_load_gpr_T0(rA(ctx->opcode)); \
1236: gen_op_load_gpr_T1(rB(ctx->opcode)); \
1237: gen_op_add(); \
1238: gen_op_load_gpr_T1(rS(ctx->opcode)); \
1239: op_ldst(st##width); \
1240: gen_op_store_T0_gpr(rA(ctx->opcode)); \
1241: }
1242:
1243: #define GEN_STX(width, opc2, opc3) \
1244: GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1245: { \
1246: if (rA(ctx->opcode) == 0) { \
1247: gen_op_load_gpr_T0(rB(ctx->opcode)); \
1248: } else { \
1249: gen_op_load_gpr_T0(rA(ctx->opcode)); \
1250: gen_op_load_gpr_T1(rB(ctx->opcode)); \
1251: gen_op_add(); \
1252: } \
1253: gen_op_load_gpr_T1(rS(ctx->opcode)); \
1254: op_ldst(st##width); \
1255: }
1256:
1257: #define GEN_STS(width, op) \
1258: OP_ST_TABLE(width); \
1259: GEN_ST(width, op | 0x20); \
1260: GEN_STU(width, op | 0x21); \
1261: GEN_STUX(width, op | 0x01); \
1262: GEN_STX(width, 0x17, op | 0x00)
1263:
1264: /* stb stbu stbux stbx */
1265: GEN_STS(b, 0x06);
1266: /* sth sthu sthux sthx */
1267: GEN_STS(h, 0x0C);
1268: /* stw stwu stwux stwx */
1269: GEN_STS(w, 0x04);
1270:
1271: /*** Integer load and store with byte reverse ***/
1272: /* lhbrx */
1273: OP_LD_TABLE(hbr);
1274: GEN_LDX(hbr, 0x16, 0x18);
1275: /* lwbrx */
1276: OP_LD_TABLE(wbr);
1277: GEN_LDX(wbr, 0x16, 0x10);
1278: /* sthbrx */
1279: OP_ST_TABLE(hbr);
1280: GEN_STX(hbr, 0x16, 0x1C);
1281: /* stwbrx */
1282: OP_ST_TABLE(wbr);
1283: GEN_STX(wbr, 0x16, 0x14);
1284:
1285: /*** Integer load and store multiple ***/
1286: #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
1287: #if defined(CONFIG_USER_ONLY)
1288: static GenOpFunc1 *gen_op_lmw[] = {
1289: &gen_op_lmw_raw,
1290: &gen_op_lmw_le_raw,
1291: };
1292: static GenOpFunc1 *gen_op_stmw[] = {
1293: &gen_op_stmw_raw,
1294: &gen_op_stmw_le_raw,
1295: };
1296: #else
1297: static GenOpFunc1 *gen_op_lmw[] = {
1298: &gen_op_lmw_user,
1299: &gen_op_lmw_le_user,
1300: &gen_op_lmw_kernel,
1301: &gen_op_lmw_le_kernel,
1302: };
1303: static GenOpFunc1 *gen_op_stmw[] = {
1304: &gen_op_stmw_user,
1305: &gen_op_stmw_le_user,
1306: &gen_op_stmw_kernel,
1307: &gen_op_stmw_le_kernel,
1308: };
1309: #endif
1310:
1311: /* lmw */
1312: GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1313: {
1314: int simm = SIMM(ctx->opcode);
1315:
1316: if (rA(ctx->opcode) == 0) {
1317: gen_op_set_T0(simm);
1318: } else {
1319: gen_op_load_gpr_T0(rA(ctx->opcode));
1320: if (simm != 0)
1321: gen_op_addi(simm);
1322: }
1323: op_ldstm(lmw, rD(ctx->opcode));
1324: }
1325:
1326: /* stmw */
1327: GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1328: {
1329: int simm = SIMM(ctx->opcode);
1330:
1331: if (rA(ctx->opcode) == 0) {
1332: gen_op_set_T0(simm);
1333: } else {
1334: gen_op_load_gpr_T0(rA(ctx->opcode));
1335: if (simm != 0)
1336: gen_op_addi(simm);
1337: }
1338: op_ldstm(stmw, rS(ctx->opcode));
1339: }
1340:
1341: /*** Integer load and store strings ***/
1342: #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
1343: #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
1344: #if defined(CONFIG_USER_ONLY)
1345: static GenOpFunc1 *gen_op_lswi[] = {
1346: &gen_op_lswi_raw,
1347: &gen_op_lswi_le_raw,
1348: };
1349: static GenOpFunc3 *gen_op_lswx[] = {
1350: &gen_op_lswx_raw,
1351: &gen_op_lswx_le_raw,
1352: };
1353: static GenOpFunc1 *gen_op_stsw[] = {
1354: &gen_op_stsw_raw,
1355: &gen_op_stsw_le_raw,
1356: };
1357: #else
1358: static GenOpFunc1 *gen_op_lswi[] = {
1359: &gen_op_lswi_user,
1360: &gen_op_lswi_le_user,
1361: &gen_op_lswi_kernel,
1362: &gen_op_lswi_le_kernel,
1363: };
1364: static GenOpFunc3 *gen_op_lswx[] = {
1365: &gen_op_lswx_user,
1366: &gen_op_lswx_le_user,
1367: &gen_op_lswx_kernel,
1368: &gen_op_lswx_le_kernel,
1369: };
1370: static GenOpFunc1 *gen_op_stsw[] = {
1371: &gen_op_stsw_user,
1372: &gen_op_stsw_le_user,
1373: &gen_op_stsw_kernel,
1374: &gen_op_stsw_le_kernel,
1375: };
1376: #endif
1377:
1378: /* lswi */
1379: /* PowerPC32 specification says we must generate an exception if
1380: * rA is in the range of registers to be loaded.
1381: * In an other hand, IBM says this is valid, but rA won't be loaded.
1382: * For now, I'll follow the spec...
1383: */
1384: GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
1385: {
1386: int nb = NB(ctx->opcode);
1387: int start = rD(ctx->opcode);
1388: int ra = rA(ctx->opcode);
1389: int nr;
1390:
1391: if (nb == 0)
1392: nb = 32;
1393: nr = nb / 4;
1394: if (((start + nr) > 32 && start <= ra && (start + nr - 32) > ra) ||
1395: ((start + nr) <= 32 && start <= ra && (start + nr) > ra)) {
1396: RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
1397: return;
1398: }
1399: if (ra == 0) {
1400: gen_op_set_T0(0);
1401: } else {
1402: gen_op_load_gpr_T0(ra);
1403: }
1404: gen_op_set_T1(nb);
1405: /* NIP cannot be restored if the memory exception comes from an helper */
1406: gen_op_update_nip((ctx)->nip - 4);
1407: op_ldsts(lswi, start);
1408: }
1409:
1410: /* lswx */
1411: GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
1412: {
1413: int ra = rA(ctx->opcode);
1414: int rb = rB(ctx->opcode);
1415:
1416: if (ra == 0) {
1417: gen_op_load_gpr_T0(rb);
1418: ra = rb;
1419: } else {
1420: gen_op_load_gpr_T0(ra);
1421: gen_op_load_gpr_T1(rb);
1422: gen_op_add();
1423: }
1424: gen_op_load_xer_bc();
1425: /* NIP cannot be restored if the memory exception comes from an helper */
1426: gen_op_update_nip((ctx)->nip - 4);
1427: op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
1428: }
1429:
1430: /* stswi */
1431: GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
1432: {
1433: int nb = NB(ctx->opcode);
1434:
1435: if (rA(ctx->opcode) == 0) {
1436: gen_op_set_T0(0);
1437: } else {
1438: gen_op_load_gpr_T0(rA(ctx->opcode));
1439: }
1440: if (nb == 0)
1441: nb = 32;
1442: gen_op_set_T1(nb);
1443: /* NIP cannot be restored if the memory exception comes from an helper */
1444: gen_op_update_nip((ctx)->nip - 4);
1445: op_ldsts(stsw, rS(ctx->opcode));
1446: }
1447:
1448: /* stswx */
1449: GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
1450: {
1451: int ra = rA(ctx->opcode);
1452:
1453: if (ra == 0) {
1454: gen_op_load_gpr_T0(rB(ctx->opcode));
1455: ra = rB(ctx->opcode);
1456: } else {
1457: gen_op_load_gpr_T0(ra);
1458: gen_op_load_gpr_T1(rB(ctx->opcode));
1459: gen_op_add();
1460: }
1461: gen_op_load_xer_bc();
1462: /* NIP cannot be restored if the memory exception comes from an helper */
1463: gen_op_update_nip((ctx)->nip - 4);
1464: op_ldsts(stsw, rS(ctx->opcode));
1465: }
1466:
1467: /*** Memory synchronisation ***/
1468: /* eieio */
1469: GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM)
1470: {
1471: }
1472:
1473: /* isync */
1474: GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM)
1475: {
1476: }
1477:
1478: #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
1479: #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
1480: #if defined(CONFIG_USER_ONLY)
1481: static GenOpFunc *gen_op_lwarx[] = {
1482: &gen_op_lwarx_raw,
1483: &gen_op_lwarx_le_raw,
1484: };
1485: static GenOpFunc *gen_op_stwcx[] = {
1486: &gen_op_stwcx_raw,
1487: &gen_op_stwcx_le_raw,
1488: };
1489: #else
1490: static GenOpFunc *gen_op_lwarx[] = {
1491: &gen_op_lwarx_user,
1492: &gen_op_lwarx_le_user,
1493: &gen_op_lwarx_kernel,
1494: &gen_op_lwarx_le_kernel,
1495: };
1496: static GenOpFunc *gen_op_stwcx[] = {
1497: &gen_op_stwcx_user,
1498: &gen_op_stwcx_le_user,
1499: &gen_op_stwcx_kernel,
1500: &gen_op_stwcx_le_kernel,
1501: };
1502: #endif
1503:
1504: /* lwarx */
1505: GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES)
1506: {
1507: if (rA(ctx->opcode) == 0) {
1508: gen_op_load_gpr_T0(rB(ctx->opcode));
1509: } else {
1510: gen_op_load_gpr_T0(rA(ctx->opcode));
1511: gen_op_load_gpr_T1(rB(ctx->opcode));
1512: gen_op_add();
1513: }
1514: op_lwarx();
1515: gen_op_store_T1_gpr(rD(ctx->opcode));
1516: }
1517:
1518: /* stwcx. */
1519: GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
1520: {
1521: if (rA(ctx->opcode) == 0) {
1522: gen_op_load_gpr_T0(rB(ctx->opcode));
1523: } else {
1524: gen_op_load_gpr_T0(rA(ctx->opcode));
1525: gen_op_load_gpr_T1(rB(ctx->opcode));
1526: gen_op_add();
1527: }
1528: gen_op_load_gpr_T1(rS(ctx->opcode));
1529: op_stwcx();
1530: }
1531:
1532: /* sync */
1533: GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM)
1534: {
1535: }
1536:
1537: /*** Floating-point load ***/
1538: #define GEN_LDF(width, opc) \
1539: GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
1540: { \
1541: uint32_t simm = SIMM(ctx->opcode); \
1542: if (!ctx->fpu_enabled) { \
1543: RET_EXCP(ctx, EXCP_NO_FP, 0); \
1544: return; \
1545: } \
1546: if (rA(ctx->opcode) == 0) { \
1547: gen_op_set_T0(simm); \
1548: } else { \
1549: gen_op_load_gpr_T0(rA(ctx->opcode)); \
1550: if (simm != 0) \
1551: gen_op_addi(simm); \
1552: } \
1553: op_ldst(l##width); \
1554: gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1555: }
1556:
1557: #define GEN_LDUF(width, opc) \
1558: GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
1559: { \
1560: uint32_t simm = SIMM(ctx->opcode); \
1561: if (!ctx->fpu_enabled) { \
1562: RET_EXCP(ctx, EXCP_NO_FP, 0); \
1563: return; \
1564: } \
1565: if (rA(ctx->opcode) == 0 || \
1566: rA(ctx->opcode) == rD(ctx->opcode)) { \
1567: RET_INVAL(ctx); \
1568: return; \
1569: } \
1570: gen_op_load_gpr_T0(rA(ctx->opcode)); \
1571: if (simm != 0) \
1572: gen_op_addi(simm); \
1573: op_ldst(l##width); \
1574: gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1575: gen_op_store_T0_gpr(rA(ctx->opcode)); \
1576: }
1577:
1578: #define GEN_LDUXF(width, opc) \
1579: GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT) \
1580: { \
1581: if (!ctx->fpu_enabled) { \
1582: RET_EXCP(ctx, EXCP_NO_FP, 0); \
1583: return; \
1584: } \
1585: if (rA(ctx->opcode) == 0 || \
1586: rA(ctx->opcode) == rD(ctx->opcode)) { \
1587: RET_INVAL(ctx); \
1588: return; \
1589: } \
1590: gen_op_load_gpr_T0(rA(ctx->opcode)); \
1591: gen_op_load_gpr_T1(rB(ctx->opcode)); \
1592: gen_op_add(); \
1593: op_ldst(l##width); \
1594: gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1595: gen_op_store_T0_gpr(rA(ctx->opcode)); \
1596: }
1597:
1598: #define GEN_LDXF(width, opc2, opc3) \
1599: GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT) \
1600: { \
1601: if (!ctx->fpu_enabled) { \
1602: RET_EXCP(ctx, EXCP_NO_FP, 0); \
1603: return; \
1604: } \
1605: if (rA(ctx->opcode) == 0) { \
1606: gen_op_load_gpr_T0(rB(ctx->opcode)); \
1607: } else { \
1608: gen_op_load_gpr_T0(rA(ctx->opcode)); \
1609: gen_op_load_gpr_T1(rB(ctx->opcode)); \
1610: gen_op_add(); \
1611: } \
1612: op_ldst(l##width); \
1613: gen_op_store_FT1_fpr(rD(ctx->opcode)); \
1614: }
1615:
1616: #define GEN_LDFS(width, op) \
1617: OP_LD_TABLE(width); \
1618: GEN_LDF(width, op | 0x20); \
1619: GEN_LDUF(width, op | 0x21); \
1620: GEN_LDUXF(width, op | 0x01); \
1621: GEN_LDXF(width, 0x17, op | 0x00)
1622:
1623: /* lfd lfdu lfdux lfdx */
1624: GEN_LDFS(fd, 0x12);
1625: /* lfs lfsu lfsux lfsx */
1626: GEN_LDFS(fs, 0x10);
1627:
1628: /*** Floating-point store ***/
1629: #define GEN_STF(width, opc) \
1630: GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
1631: { \
1632: uint32_t simm = SIMM(ctx->opcode); \
1633: if (!ctx->fpu_enabled) { \
1634: RET_EXCP(ctx, EXCP_NO_FP, 0); \
1635: return; \
1636: } \
1637: if (rA(ctx->opcode) == 0) { \
1638: gen_op_set_T0(simm); \
1639: } else { \
1640: gen_op_load_gpr_T0(rA(ctx->opcode)); \
1641: if (simm != 0) \
1642: gen_op_addi(simm); \
1643: } \
1644: gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1645: op_ldst(st##width); \
1646: }
1647:
1648: #define GEN_STUF(width, opc) \
1649: GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
1650: { \
1651: uint32_t simm = SIMM(ctx->opcode); \
1652: if (!ctx->fpu_enabled) { \
1653: RET_EXCP(ctx, EXCP_NO_FP, 0); \
1654: return; \
1655: } \
1656: if (rA(ctx->opcode) == 0) { \
1657: RET_INVAL(ctx); \
1658: return; \
1659: } \
1660: gen_op_load_gpr_T0(rA(ctx->opcode)); \
1661: if (simm != 0) \
1662: gen_op_addi(simm); \
1663: gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1664: op_ldst(st##width); \
1665: gen_op_store_T0_gpr(rA(ctx->opcode)); \
1666: }
1667:
1668: #define GEN_STUXF(width, opc) \
1669: GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT) \
1670: { \
1671: if (!ctx->fpu_enabled) { \
1672: RET_EXCP(ctx, EXCP_NO_FP, 0); \
1673: return; \
1674: } \
1675: if (rA(ctx->opcode) == 0) { \
1676: RET_INVAL(ctx); \
1677: return; \
1678: } \
1679: gen_op_load_gpr_T0(rA(ctx->opcode)); \
1680: gen_op_load_gpr_T1(rB(ctx->opcode)); \
1681: gen_op_add(); \
1682: gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1683: op_ldst(st##width); \
1684: gen_op_store_T0_gpr(rA(ctx->opcode)); \
1685: }
1686:
1687: #define GEN_STXF(width, opc2, opc3) \
1688: GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT) \
1689: { \
1690: if (!ctx->fpu_enabled) { \
1691: RET_EXCP(ctx, EXCP_NO_FP, 0); \
1692: return; \
1693: } \
1694: if (rA(ctx->opcode) == 0) { \
1695: gen_op_load_gpr_T0(rB(ctx->opcode)); \
1696: } else { \
1697: gen_op_load_gpr_T0(rA(ctx->opcode)); \
1698: gen_op_load_gpr_T1(rB(ctx->opcode)); \
1699: gen_op_add(); \
1700: } \
1701: gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1702: op_ldst(st##width); \
1703: }
1704:
1705: #define GEN_STFS(width, op) \
1706: OP_ST_TABLE(width); \
1707: GEN_STF(width, op | 0x20); \
1708: GEN_STUF(width, op | 0x21); \
1709: GEN_STUXF(width, op | 0x01); \
1710: GEN_STXF(width, 0x17, op | 0x00)
1711:
1712: /* stfd stfdu stfdux stfdx */
1713: GEN_STFS(fd, 0x16);
1714: /* stfs stfsu stfsux stfsx */
1715: GEN_STFS(fs, 0x14);
1716:
1717: /* Optional: */
1718: /* stfiwx */
1719: GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
1720: {
1721: if (!ctx->fpu_enabled) {
1722: RET_EXCP(ctx, EXCP_NO_FP, 0);
1723: return;
1724: }
1725: RET_INVAL(ctx);
1726: }
1727:
1728: /*** Branch ***/
1729:
1.1.1.2 root 1730: static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
1731: {
1732: TranslationBlock *tb;
1733: tb = ctx->tb;
1734: if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
1735: if (n == 0)
1736: gen_op_goto_tb0(TBPARAM(tb));
1737: else
1738: gen_op_goto_tb1(TBPARAM(tb));
1739: gen_op_set_T1(dest);
1740: gen_op_b_T1();
1741: gen_op_set_T0((long)tb + n);
1.1.1.3 root 1742: if (ctx->singlestep_enabled)
1743: gen_op_debug();
1.1.1.2 root 1744: gen_op_exit_tb();
1745: } else {
1746: gen_op_set_T1(dest);
1747: gen_op_b_T1();
1.1.1.3 root 1748: if (ctx->singlestep_enabled)
1749: gen_op_debug();
1.1.1.2 root 1750: gen_op_set_T0(0);
1751: gen_op_exit_tb();
1752: }
1753: }
1754:
1.1 root 1755: /* b ba bl bla */
1756: GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1757: {
1758: uint32_t li, target;
1759:
1760: /* sign extend LI */
1761: li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
1762:
1763: if (AA(ctx->opcode) == 0)
1764: target = ctx->nip + li - 4;
1765: else
1766: target = li;
1767: if (LK(ctx->opcode)) {
1768: gen_op_setlr(ctx->nip);
1769: }
1.1.1.2 root 1770: gen_goto_tb(ctx, 0, target);
1.1 root 1771: ctx->exception = EXCP_BRANCH;
1772: }
1773:
1774: #define BCOND_IM 0
1775: #define BCOND_LR 1
1776: #define BCOND_CTR 2
1777:
1778: static inline void gen_bcond(DisasContext *ctx, int type)
1779: {
1780: uint32_t target = 0;
1781: uint32_t bo = BO(ctx->opcode);
1782: uint32_t bi = BI(ctx->opcode);
1783: uint32_t mask;
1784: uint32_t li;
1785:
1786: if ((bo & 0x4) == 0)
1787: gen_op_dec_ctr();
1788: switch(type) {
1789: case BCOND_IM:
1790: li = (int32_t)((int16_t)(BD(ctx->opcode)));
1791: if (AA(ctx->opcode) == 0) {
1792: target = ctx->nip + li - 4;
1793: } else {
1794: target = li;
1795: }
1796: break;
1797: case BCOND_CTR:
1798: gen_op_movl_T1_ctr();
1799: break;
1800: default:
1801: case BCOND_LR:
1802: gen_op_movl_T1_lr();
1803: break;
1804: }
1805: if (LK(ctx->opcode)) {
1806: gen_op_setlr(ctx->nip);
1807: }
1808: if (bo & 0x10) {
1809: /* No CR condition */
1810: switch (bo & 0x6) {
1811: case 0:
1812: gen_op_test_ctr();
1813: break;
1814: case 2:
1815: gen_op_test_ctrz();
1816: break;
1817: default:
1818: case 4:
1819: case 6:
1820: if (type == BCOND_IM) {
1.1.1.2 root 1821: gen_goto_tb(ctx, 0, target);
1.1 root 1822: } else {
1823: gen_op_b_T1();
1824: }
1825: goto no_test;
1826: }
1827: } else {
1828: mask = 1 << (3 - (bi & 0x03));
1829: gen_op_load_crf_T0(bi >> 2);
1830: if (bo & 0x8) {
1831: switch (bo & 0x6) {
1832: case 0:
1833: gen_op_test_ctr_true(mask);
1834: break;
1835: case 2:
1836: gen_op_test_ctrz_true(mask);
1837: break;
1838: default:
1839: case 4:
1840: case 6:
1841: gen_op_test_true(mask);
1842: break;
1843: }
1844: } else {
1845: switch (bo & 0x6) {
1846: case 0:
1847: gen_op_test_ctr_false(mask);
1848: break;
1849: case 2:
1850: gen_op_test_ctrz_false(mask);
1851: break;
1852: default:
1853: case 4:
1854: case 6:
1855: gen_op_test_false(mask);
1856: break;
1857: }
1858: }
1859: }
1860: if (type == BCOND_IM) {
1.1.1.2 root 1861: int l1 = gen_new_label();
1862: gen_op_jz_T0(l1);
1863: gen_goto_tb(ctx, 0, target);
1864: gen_set_label(l1);
1865: gen_goto_tb(ctx, 1, ctx->nip);
1.1 root 1866: } else {
1867: gen_op_btest_T1(ctx->nip);
1868: }
1869: no_test:
1870: ctx->exception = EXCP_BRANCH;
1871: }
1872:
1873: GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1874: {
1875: gen_bcond(ctx, BCOND_IM);
1876: }
1877:
1878: GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
1879: {
1880: gen_bcond(ctx, BCOND_CTR);
1881: }
1882:
1883: GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
1884: {
1885: gen_bcond(ctx, BCOND_LR);
1886: }
1887:
1888: /*** Condition register logical ***/
1889: #define GEN_CRLOGIC(op, opc) \
1890: GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
1891: { \
1892: gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
1893: gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
1894: gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
1895: gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
1896: gen_op_##op(); \
1897: gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
1898: gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
1899: 3 - (crbD(ctx->opcode) & 0x03)); \
1900: gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
1901: }
1902:
1903: /* crand */
1904: GEN_CRLOGIC(and, 0x08)
1905: /* crandc */
1906: GEN_CRLOGIC(andc, 0x04)
1907: /* creqv */
1908: GEN_CRLOGIC(eqv, 0x09)
1909: /* crnand */
1910: GEN_CRLOGIC(nand, 0x07)
1911: /* crnor */
1912: GEN_CRLOGIC(nor, 0x01)
1913: /* cror */
1914: GEN_CRLOGIC(or, 0x0E)
1915: /* crorc */
1916: GEN_CRLOGIC(orc, 0x0D)
1917: /* crxor */
1918: GEN_CRLOGIC(xor, 0x06)
1919: /* mcrf */
1920: GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
1921: {
1922: gen_op_load_crf_T0(crfS(ctx->opcode));
1923: gen_op_store_T0_crf(crfD(ctx->opcode));
1924: }
1925:
1926: /*** System linkage ***/
1927: /* rfi (supervisor only) */
1928: GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW)
1929: {
1930: #if defined(CONFIG_USER_ONLY)
1931: RET_PRIVOPC(ctx);
1932: #else
1933: /* Restore CPU state */
1934: if (!ctx->supervisor) {
1935: RET_PRIVOPC(ctx);
1936: return;
1937: }
1938: gen_op_rfi();
1939: RET_CHG_FLOW(ctx);
1940: #endif
1941: }
1942:
1943: /* sc */
1944: GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW)
1945: {
1946: #if defined(CONFIG_USER_ONLY)
1947: RET_EXCP(ctx, EXCP_SYSCALL_USER, 0);
1948: #else
1949: RET_EXCP(ctx, EXCP_SYSCALL, 0);
1950: #endif
1951: }
1952:
1953: /*** Trap ***/
1954: /* tw */
1955: GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW)
1956: {
1957: gen_op_load_gpr_T0(rA(ctx->opcode));
1958: gen_op_load_gpr_T1(rB(ctx->opcode));
1.1.1.4 ! root 1959: /* Update the nip since this might generate a trap exception */
! 1960: gen_op_update_nip(ctx->nip);
1.1 root 1961: gen_op_tw(TO(ctx->opcode));
1962: }
1963:
1964: /* twi */
1965: GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1966: {
1967: gen_op_load_gpr_T0(rA(ctx->opcode));
1968: #if 0
1969: printf("%s: param=0x%04x T0=0x%04x\n", __func__,
1970: SIMM(ctx->opcode), TO(ctx->opcode));
1971: #endif
1972: gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode));
1973: }
1974:
1975: /*** Processor control ***/
1976: static inline int check_spr_access (int spr, int rw, int supervisor)
1977: {
1978: uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1));
1979:
1980: #if 0
1981: if (spr != LR && spr != CTR) {
1982: if (loglevel > 0) {
1983: fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1984: SPR_ENCODE(spr), supervisor, rw, rights,
1985: (rights >> ((2 * supervisor) + rw)) & 1);
1986: } else {
1987: printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1988: SPR_ENCODE(spr), supervisor, rw, rights,
1989: (rights >> ((2 * supervisor) + rw)) & 1);
1990: }
1991: }
1992: #endif
1993: if (rights == 0)
1994: return -1;
1995: rights = rights >> (2 * supervisor);
1996: rights = rights >> rw;
1997:
1998: return rights & 1;
1999: }
2000:
2001: /* mcrxr */
2002: GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
2003: {
2004: gen_op_load_xer_cr();
2005: gen_op_store_T0_crf(crfD(ctx->opcode));
2006: gen_op_clear_xer_cr();
2007: }
2008:
2009: /* mfcr */
2010: GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC)
2011: {
2012: gen_op_load_cr();
2013: gen_op_store_T0_gpr(rD(ctx->opcode));
2014: }
2015:
2016: /* mfmsr */
2017: GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
2018: {
2019: #if defined(CONFIG_USER_ONLY)
2020: RET_PRIVREG(ctx);
2021: #else
2022: if (!ctx->supervisor) {
2023: RET_PRIVREG(ctx);
2024: return;
2025: }
2026: gen_op_load_msr();
2027: gen_op_store_T0_gpr(rD(ctx->opcode));
2028: #endif
2029: }
2030:
2031: #if 0
2032: #define SPR_NOACCESS ((void *)(-1))
2033: #else
2034: static void spr_noaccess (void *opaque, int sprn)
2035: {
2036: sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
2037: printf("ERROR: try to access SPR %d !\n", sprn);
2038: }
2039: #define SPR_NOACCESS (&spr_noaccess)
2040: #endif
2041:
2042: /* mfspr */
2043: static inline void gen_op_mfspr (DisasContext *ctx)
2044: {
2045: void (*read_cb)(void *opaque, int sprn);
2046: uint32_t sprn = SPR(ctx->opcode);
2047:
2048: #if !defined(CONFIG_USER_ONLY)
2049: if (ctx->supervisor)
2050: read_cb = ctx->spr_cb[sprn].oea_read;
2051: else
2052: #endif
2053: read_cb = ctx->spr_cb[sprn].uea_read;
2054: if (read_cb != NULL) {
2055: if (read_cb != SPR_NOACCESS) {
2056: (*read_cb)(ctx, sprn);
2057: gen_op_store_T0_gpr(rD(ctx->opcode));
2058: } else {
2059: /* Privilege exception */
1.1.1.2 root 2060: if (loglevel) {
2061: fprintf(logfile, "Trying to read priviledged spr %d %03x\n",
2062: sprn, sprn);
2063: }
1.1 root 2064: printf("Trying to read priviledged spr %d %03x\n", sprn, sprn);
2065: RET_PRIVREG(ctx);
2066: }
2067: } else {
2068: /* Not defined */
1.1.1.2 root 2069: if (loglevel) {
2070: fprintf(logfile, "Trying to read invalid spr %d %03x\n",
2071: sprn, sprn);
2072: }
1.1 root 2073: printf("Trying to read invalid spr %d %03x\n", sprn, sprn);
2074: RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
2075: }
2076: }
2077:
2078: GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
2079: {
2080: gen_op_mfspr(ctx);
2081: }
2082:
2083: /* mftb */
2084: GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_TB)
2085: {
2086: gen_op_mfspr(ctx);
2087: }
2088:
2089: /* mtcrf */
2090: /* The mask should be 0x00100801, but Mac OS X 10.4 use an alternate form */
2091: GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
2092: {
2093: gen_op_load_gpr_T0(rS(ctx->opcode));
2094: gen_op_store_cr(CRM(ctx->opcode));
2095: }
2096:
2097: /* mtmsr */
2098: GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
2099: {
2100: #if defined(CONFIG_USER_ONLY)
2101: RET_PRIVREG(ctx);
2102: #else
2103: if (!ctx->supervisor) {
2104: RET_PRIVREG(ctx);
2105: return;
2106: }
1.1.1.2 root 2107: gen_op_update_nip((ctx)->nip);
1.1 root 2108: gen_op_load_gpr_T0(rS(ctx->opcode));
2109: gen_op_store_msr();
2110: /* Must stop the translation as machine state (may have) changed */
1.1.1.2 root 2111: RET_CHG_FLOW(ctx);
1.1 root 2112: #endif
2113: }
2114:
2115: /* mtspr */
2116: GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
2117: {
2118: void (*write_cb)(void *opaque, int sprn);
2119: uint32_t sprn = SPR(ctx->opcode);
2120:
2121: #if !defined(CONFIG_USER_ONLY)
2122: if (ctx->supervisor)
2123: write_cb = ctx->spr_cb[sprn].oea_write;
2124: else
2125: #endif
2126: write_cb = ctx->spr_cb[sprn].uea_write;
2127: if (write_cb != NULL) {
2128: if (write_cb != SPR_NOACCESS) {
2129: gen_op_load_gpr_T0(rS(ctx->opcode));
2130: (*write_cb)(ctx, sprn);
2131: } else {
2132: /* Privilege exception */
1.1.1.2 root 2133: if (loglevel) {
2134: fprintf(logfile, "Trying to write priviledged spr %d %03x\n",
2135: sprn, sprn);
2136: }
1.1 root 2137: printf("Trying to write priviledged spr %d %03x\n", sprn, sprn);
2138: RET_PRIVREG(ctx);
2139: }
2140: } else {
2141: /* Not defined */
1.1.1.2 root 2142: if (loglevel) {
2143: fprintf(logfile, "Trying to write invalid spr %d %03x\n",
2144: sprn, sprn);
2145: }
1.1 root 2146: printf("Trying to write invalid spr %d %03x\n", sprn, sprn);
2147: RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
2148: }
2149: }
2150:
2151: /*** Cache management ***/
2152: /* For now, all those will be implemented as nop:
2153: * this is valid, regarding the PowerPC specs...
2154: * We just have to flush tb while invalidating instruction cache lines...
2155: */
2156: /* dcbf */
2157: GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE)
2158: {
2159: if (rA(ctx->opcode) == 0) {
2160: gen_op_load_gpr_T0(rB(ctx->opcode));
2161: } else {
2162: gen_op_load_gpr_T0(rA(ctx->opcode));
2163: gen_op_load_gpr_T1(rB(ctx->opcode));
2164: gen_op_add();
2165: }
2166: op_ldst(lbz);
2167: }
2168:
2169: /* dcbi (Supervisor only) */
2170: GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
2171: {
2172: #if defined(CONFIG_USER_ONLY)
2173: RET_PRIVOPC(ctx);
2174: #else
2175: if (!ctx->supervisor) {
2176: RET_PRIVOPC(ctx);
2177: return;
2178: }
2179: if (rA(ctx->opcode) == 0) {
2180: gen_op_load_gpr_T0(rB(ctx->opcode));
2181: } else {
2182: gen_op_load_gpr_T0(rA(ctx->opcode));
2183: gen_op_load_gpr_T1(rB(ctx->opcode));
2184: gen_op_add();
2185: }
2186: op_ldst(lbz);
2187: op_ldst(stb);
2188: #endif
2189: }
2190:
2191: /* dcdst */
2192: GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
2193: {
2194: if (rA(ctx->opcode) == 0) {
2195: gen_op_load_gpr_T0(rB(ctx->opcode));
2196: } else {
2197: gen_op_load_gpr_T0(rA(ctx->opcode));
2198: gen_op_load_gpr_T1(rB(ctx->opcode));
2199: gen_op_add();
2200: }
2201: op_ldst(lbz);
2202: }
2203:
2204: /* dcbt */
2205: GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE)
2206: {
2207: }
2208:
2209: /* dcbtst */
2210: GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE)
2211: {
2212: }
2213:
2214: /* dcbz */
2215: #if defined(CONFIG_USER_ONLY)
2216: #define op_dcbz() gen_op_dcbz_raw()
2217: #else
2218: #define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
2219: static GenOpFunc *gen_op_dcbz[] = {
2220: &gen_op_dcbz_user,
2221: &gen_op_dcbz_user,
2222: &gen_op_dcbz_kernel,
2223: &gen_op_dcbz_kernel,
2224: };
2225: #endif
2226:
2227: GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE)
2228: {
2229: if (rA(ctx->opcode) == 0) {
2230: gen_op_load_gpr_T0(rB(ctx->opcode));
2231: } else {
2232: gen_op_load_gpr_T0(rA(ctx->opcode));
2233: gen_op_load_gpr_T1(rB(ctx->opcode));
2234: gen_op_add();
2235: }
2236: op_dcbz();
2237: gen_op_check_reservation();
2238: }
2239:
2240: /* icbi */
2241: GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
2242: {
2243: if (rA(ctx->opcode) == 0) {
2244: gen_op_load_gpr_T0(rB(ctx->opcode));
2245: } else {
2246: gen_op_load_gpr_T0(rA(ctx->opcode));
2247: gen_op_load_gpr_T1(rB(ctx->opcode));
2248: gen_op_add();
2249: }
2250: gen_op_icbi();
2251: }
2252:
2253: /* Optional: */
2254: /* dcba */
2255: GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_OPT)
2256: {
2257: }
2258:
2259: /*** Segment register manipulation ***/
2260: /* Supervisor only: */
2261: /* mfsr */
2262: GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
2263: {
2264: #if defined(CONFIG_USER_ONLY)
2265: RET_PRIVREG(ctx);
2266: #else
2267: if (!ctx->supervisor) {
2268: RET_PRIVREG(ctx);
2269: return;
2270: }
2271: gen_op_load_sr(SR(ctx->opcode));
2272: gen_op_store_T0_gpr(rD(ctx->opcode));
2273: #endif
2274: }
2275:
2276: /* mfsrin */
2277: GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
2278: {
2279: #if defined(CONFIG_USER_ONLY)
2280: RET_PRIVREG(ctx);
2281: #else
2282: if (!ctx->supervisor) {
2283: RET_PRIVREG(ctx);
2284: return;
2285: }
2286: gen_op_load_gpr_T1(rB(ctx->opcode));
2287: gen_op_load_srin();
2288: gen_op_store_T0_gpr(rD(ctx->opcode));
2289: #endif
2290: }
2291:
2292: /* mtsr */
2293: GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
2294: {
2295: #if defined(CONFIG_USER_ONLY)
2296: RET_PRIVREG(ctx);
2297: #else
2298: if (!ctx->supervisor) {
2299: RET_PRIVREG(ctx);
2300: return;
2301: }
2302: gen_op_load_gpr_T0(rS(ctx->opcode));
2303: gen_op_store_sr(SR(ctx->opcode));
1.1.1.2 root 2304: RET_STOP(ctx);
1.1 root 2305: #endif
2306: }
2307:
2308: /* mtsrin */
2309: GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
2310: {
2311: #if defined(CONFIG_USER_ONLY)
2312: RET_PRIVREG(ctx);
2313: #else
2314: if (!ctx->supervisor) {
2315: RET_PRIVREG(ctx);
2316: return;
2317: }
2318: gen_op_load_gpr_T0(rS(ctx->opcode));
2319: gen_op_load_gpr_T1(rB(ctx->opcode));
2320: gen_op_store_srin();
1.1.1.2 root 2321: RET_STOP(ctx);
1.1 root 2322: #endif
2323: }
2324:
2325: /*** Lookaside buffer management ***/
2326: /* Optional & supervisor only: */
2327: /* tlbia */
2328: GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
2329: {
2330: #if defined(CONFIG_USER_ONLY)
2331: RET_PRIVOPC(ctx);
2332: #else
2333: if (!ctx->supervisor) {
2334: if (loglevel)
2335: fprintf(logfile, "%s: ! supervisor\n", __func__);
2336: RET_PRIVOPC(ctx);
2337: return;
2338: }
2339: gen_op_tlbia();
1.1.1.2 root 2340: RET_STOP(ctx);
1.1 root 2341: #endif
2342: }
2343:
2344: /* tlbie */
2345: GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM)
2346: {
2347: #if defined(CONFIG_USER_ONLY)
2348: RET_PRIVOPC(ctx);
2349: #else
2350: if (!ctx->supervisor) {
2351: RET_PRIVOPC(ctx);
2352: return;
2353: }
2354: gen_op_load_gpr_T0(rB(ctx->opcode));
2355: gen_op_tlbie();
1.1.1.2 root 2356: RET_STOP(ctx);
1.1 root 2357: #endif
2358: }
2359:
2360: /* tlbsync */
2361: GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM)
2362: {
2363: #if defined(CONFIG_USER_ONLY)
2364: RET_PRIVOPC(ctx);
2365: #else
2366: if (!ctx->supervisor) {
2367: RET_PRIVOPC(ctx);
2368: return;
2369: }
2370: /* This has no effect: it should ensure that all previous
2371: * tlbie have completed
2372: */
1.1.1.2 root 2373: RET_STOP(ctx);
1.1 root 2374: #endif
2375: }
2376:
2377: /*** External control ***/
2378: /* Optional: */
2379: #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
2380: #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
2381: #if defined(CONFIG_USER_ONLY)
2382: static GenOpFunc *gen_op_eciwx[] = {
2383: &gen_op_eciwx_raw,
2384: &gen_op_eciwx_le_raw,
2385: };
2386: static GenOpFunc *gen_op_ecowx[] = {
2387: &gen_op_ecowx_raw,
2388: &gen_op_ecowx_le_raw,
2389: };
2390: #else
2391: static GenOpFunc *gen_op_eciwx[] = {
2392: &gen_op_eciwx_user,
2393: &gen_op_eciwx_le_user,
2394: &gen_op_eciwx_kernel,
2395: &gen_op_eciwx_le_kernel,
2396: };
2397: static GenOpFunc *gen_op_ecowx[] = {
2398: &gen_op_ecowx_user,
2399: &gen_op_ecowx_le_user,
2400: &gen_op_ecowx_kernel,
2401: &gen_op_ecowx_le_kernel,
2402: };
2403: #endif
2404:
2405: /* eciwx */
2406: GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
2407: {
2408: /* Should check EAR[E] & alignment ! */
2409: if (rA(ctx->opcode) == 0) {
2410: gen_op_load_gpr_T0(rB(ctx->opcode));
2411: } else {
2412: gen_op_load_gpr_T0(rA(ctx->opcode));
2413: gen_op_load_gpr_T1(rB(ctx->opcode));
2414: gen_op_add();
2415: }
2416: op_eciwx();
2417: gen_op_store_T0_gpr(rD(ctx->opcode));
2418: }
2419:
2420: /* ecowx */
2421: GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
2422: {
2423: /* Should check EAR[E] & alignment ! */
2424: if (rA(ctx->opcode) == 0) {
2425: gen_op_load_gpr_T0(rB(ctx->opcode));
2426: } else {
2427: gen_op_load_gpr_T0(rA(ctx->opcode));
2428: gen_op_load_gpr_T1(rB(ctx->opcode));
2429: gen_op_add();
2430: }
2431: gen_op_load_gpr_T2(rS(ctx->opcode));
2432: op_ecowx();
2433: }
2434:
2435: /* End opcode list */
2436: GEN_OPCODE_MARK(end);
2437:
2438: #include "translate_init.c"
2439:
2440: /*****************************************************************************/
2441: /* Misc PowerPC helpers */
2442: void cpu_dump_state(CPUState *env, FILE *f,
2443: int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2444: int flags)
2445: {
2446: #if defined(TARGET_PPC64) || 1
2447: #define FILL ""
1.1.1.3 root 2448: #define REGX "%016" PRIx64
1.1 root 2449: #define RGPL 4
2450: #define RFPL 4
2451: #else
2452: #define FILL " "
1.1.1.3 root 2453: #define REGX "%08" PRIx64
1.1 root 2454: #define RGPL 8
2455: #define RFPL 4
2456: #endif
2457:
2458: int i;
2459:
2460: cpu_fprintf(f, "NIP " REGX " LR " REGX " CTR " REGX "\n",
2461: env->nip, env->lr, env->ctr);
2462: cpu_fprintf(f, "MSR " REGX FILL " XER %08x TB %08x %08x DECR %08x\n",
2463: do_load_msr(env), do_load_xer(env), cpu_ppc_load_tbu(env),
2464: cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env));
2465: for (i = 0; i < 32; i++) {
2466: if ((i & (RGPL - 1)) == 0)
2467: cpu_fprintf(f, "GPR%02d", i);
2468: cpu_fprintf(f, " " REGX, env->gpr[i]);
2469: if ((i & (RGPL - 1)) == (RGPL - 1))
2470: cpu_fprintf(f, "\n");
2471: }
2472: cpu_fprintf(f, "CR ");
2473: for (i = 0; i < 8; i++)
2474: cpu_fprintf(f, "%01x", env->crf[i]);
2475: cpu_fprintf(f, " [");
2476: for (i = 0; i < 8; i++) {
2477: char a = '-';
2478: if (env->crf[i] & 0x08)
2479: a = 'L';
2480: else if (env->crf[i] & 0x04)
2481: a = 'G';
2482: else if (env->crf[i] & 0x02)
2483: a = 'E';
2484: cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
2485: }
2486: cpu_fprintf(f, " ] " FILL "RES " REGX "\n", env->reserve);
2487: for (i = 0; i < 32; i++) {
2488: if ((i & (RFPL - 1)) == 0)
2489: cpu_fprintf(f, "FPR%02d", i);
1.1.1.3 root 2490: cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
1.1 root 2491: if ((i & (RFPL - 1)) == (RFPL - 1))
2492: cpu_fprintf(f, "\n");
2493: }
2494: cpu_fprintf(f, "SRR0 " REGX " SRR1 " REGX " " FILL FILL FILL
2495: "SDR1 " REGX "\n",
2496: env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
2497:
2498: #undef REGX
2499: #undef RGPL
2500: #undef RFPL
2501: #undef FILL
2502: }
2503:
2504: /*****************************************************************************/
2505: int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
2506: int search_pc)
2507: {
2508: DisasContext ctx, *ctxp = &ctx;
2509: opc_handler_t **table, *handler;
2510: target_ulong pc_start;
2511: uint16_t *gen_opc_end;
2512: int j, lj = -1;
2513:
2514: pc_start = tb->pc;
2515: gen_opc_ptr = gen_opc_buf;
2516: gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2517: gen_opparam_ptr = gen_opparam_buf;
1.1.1.2 root 2518: nb_gen_labels = 0;
1.1 root 2519: ctx.nip = pc_start;
2520: ctx.tb = tb;
2521: ctx.exception = EXCP_NONE;
2522: ctx.spr_cb = env->spr_cb;
2523: #if defined(CONFIG_USER_ONLY)
2524: ctx.mem_idx = msr_le;
2525: #else
2526: ctx.supervisor = 1 - msr_pr;
2527: ctx.mem_idx = ((1 - msr_pr) << 1) | msr_le;
2528: #endif
2529: ctx.fpu_enabled = msr_fp;
1.1.1.3 root 2530: ctx.singlestep_enabled = env->singlestep_enabled;
1.1 root 2531: #if defined (DO_SINGLE_STEP) && 0
2532: /* Single step trace mode */
2533: msr_se = 1;
2534: #endif
2535: /* Set env in case of segfault during code fetch */
2536: while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) {
1.1.1.3 root 2537: if (env->nb_breakpoints > 0) {
2538: for(j = 0; j < env->nb_breakpoints; j++) {
2539: if (env->breakpoints[j] == ctx.nip) {
2540: gen_op_update_nip(ctx.nip);
2541: gen_op_debug();
2542: break;
2543: }
2544: }
2545: }
1.1 root 2546: if (search_pc) {
2547: j = gen_opc_ptr - gen_opc_buf;
2548: if (lj < j) {
2549: lj++;
2550: while (lj < j)
2551: gen_opc_instr_start[lj++] = 0;
2552: gen_opc_pc[lj] = ctx.nip;
2553: gen_opc_instr_start[lj] = 1;
2554: }
2555: }
2556: #if defined PPC_DEBUG_DISAS
2557: if (loglevel & CPU_LOG_TB_IN_ASM) {
2558: fprintf(logfile, "----------------\n");
2559: fprintf(logfile, "nip=%08x super=%d ir=%d\n",
2560: ctx.nip, 1 - msr_pr, msr_ir);
2561: }
2562: #endif
2563: ctx.opcode = ldl_code(ctx.nip);
2564: if (msr_le) {
2565: ctx.opcode = ((ctx.opcode & 0xFF000000) >> 24) |
2566: ((ctx.opcode & 0x00FF0000) >> 8) |
2567: ((ctx.opcode & 0x0000FF00) << 8) |
2568: ((ctx.opcode & 0x000000FF) << 24);
2569: }
2570: #if defined PPC_DEBUG_DISAS
2571: if (loglevel & CPU_LOG_TB_IN_ASM) {
2572: fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
2573: ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
2574: opc3(ctx.opcode), msr_le ? "little" : "big");
2575: }
2576: #endif
2577: ctx.nip += 4;
2578: table = env->opcodes;
2579: handler = table[opc1(ctx.opcode)];
2580: if (is_indirect_opcode(handler)) {
2581: table = ind_table(handler);
2582: handler = table[opc2(ctx.opcode)];
2583: if (is_indirect_opcode(handler)) {
2584: table = ind_table(handler);
2585: handler = table[opc3(ctx.opcode)];
2586: }
2587: }
2588: /* Is opcode *REALLY* valid ? */
2589: if (handler->handler == &gen_invalid) {
2590: if (loglevel > 0) {
2591: fprintf(logfile, "invalid/unsupported opcode: "
2592: "%02x - %02x - %02x (%08x) 0x%08x %d\n",
2593: opc1(ctx.opcode), opc2(ctx.opcode),
2594: opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
2595: } else {
2596: printf("invalid/unsupported opcode: "
2597: "%02x - %02x - %02x (%08x) 0x%08x %d\n",
2598: opc1(ctx.opcode), opc2(ctx.opcode),
2599: opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
2600: }
2601: } else {
2602: if ((ctx.opcode & handler->inval) != 0) {
2603: if (loglevel > 0) {
2604: fprintf(logfile, "invalid bits: %08x for opcode: "
2605: "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
2606: ctx.opcode & handler->inval, opc1(ctx.opcode),
2607: opc2(ctx.opcode), opc3(ctx.opcode),
2608: ctx.opcode, ctx.nip - 4);
2609: } else {
2610: printf("invalid bits: %08x for opcode: "
2611: "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
2612: ctx.opcode & handler->inval, opc1(ctx.opcode),
2613: opc2(ctx.opcode), opc3(ctx.opcode),
2614: ctx.opcode, ctx.nip - 4);
2615: }
2616: RET_INVAL(ctxp);
2617: break;
2618: }
2619: }
2620: (*(handler->handler))(&ctx);
2621: /* Check trace mode exceptions */
2622: if ((msr_be && ctx.exception == EXCP_BRANCH) ||
2623: /* Check in single step trace mode
2624: * we need to stop except if:
2625: * - rfi, trap or syscall
2626: * - first instruction of an exception handler
2627: */
2628: (msr_se && (ctx.nip < 0x100 ||
2629: ctx.nip > 0xF00 ||
2630: (ctx.nip & 0xFC) != 0x04) &&
2631: ctx.exception != EXCP_SYSCALL &&
2632: ctx.exception != EXCP_SYSCALL_USER &&
2633: ctx.exception != EXCP_TRAP)) {
2634: RET_EXCP(ctxp, EXCP_TRACE, 0);
2635: }
1.1.1.3 root 2636:
2637: /* if we reach a page boundary or are single stepping, stop
2638: * generation
2639: */
2640: if (((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2641: (env->singlestep_enabled)) {
1.1 root 2642: break;
2643: }
2644: #if defined (DO_SINGLE_STEP)
2645: break;
2646: #endif
2647: }
2648: if (ctx.exception == EXCP_NONE) {
1.1.1.2 root 2649: gen_goto_tb(&ctx, 0, ctx.nip);
1.1 root 2650: } else if (ctx.exception != EXCP_BRANCH) {
2651: gen_op_set_T0(0);
2652: }
2653: #if 1
2654: /* TO BE FIXED: T0 hasn't got a proper value, which makes tb_add_jump
2655: * do bad business and then qemu crashes !
2656: */
2657: gen_op_set_T0(0);
2658: #endif
2659: /* Generate the return instruction */
2660: gen_op_exit_tb();
2661: *gen_opc_ptr = INDEX_op_end;
2662: if (search_pc) {
2663: j = gen_opc_ptr - gen_opc_buf;
2664: lj++;
2665: while (lj <= j)
2666: gen_opc_instr_start[lj++] = 0;
2667: tb->size = 0;
2668: #if 0
2669: if (loglevel > 0) {
2670: page_dump(logfile);
2671: }
2672: #endif
2673: } else {
2674: tb->size = ctx.nip - pc_start;
2675: }
2676: #ifdef DEBUG_DISAS
2677: if (loglevel & CPU_LOG_TB_CPU) {
2678: fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
2679: cpu_dump_state(env, logfile, fprintf, 0);
2680: }
2681: if (loglevel & CPU_LOG_TB_IN_ASM) {
2682: fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
1.1.1.2 root 2683: target_disas(logfile, pc_start, ctx.nip - pc_start, msr_le);
1.1 root 2684: fprintf(logfile, "\n");
2685: }
2686: if (loglevel & CPU_LOG_TB_OP) {
2687: fprintf(logfile, "OP:\n");
2688: dump_ops(gen_opc_buf, gen_opparam_buf);
2689: fprintf(logfile, "\n");
2690: }
2691: #endif
2692: return 0;
2693: }
2694:
2695: int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
2696: {
2697: return gen_intermediate_code_internal(env, tb, 0);
2698: }
2699:
2700: int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
2701: {
2702: return gen_intermediate_code_internal(env, tb, 1);
2703: }
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