File:  [Qemu by Fabrice Bellard] / qemu / target-ppc / translate_init.c
Revision 1.1.1.11 (vendor branch): download - view: text, annotated - select for diffs
Tue Apr 24 19:30:53 2018 UTC (3 years, 7 months ago) by root
Branches: qemu, MAIN
CVS tags: qemu1001, HEAD
qemu 1.0.1

    1: /*
    2:  *  PowerPC CPU initialization for qemu.
    3:  *
    4:  *  Copyright (c) 2003-2007 Jocelyn Mayer
    5:  *
    6:  * This library is free software; you can redistribute it and/or
    7:  * modify it under the terms of the GNU Lesser General Public
    8:  * License as published by the Free Software Foundation; either
    9:  * version 2 of the License, or (at your option) any later version.
   10:  *
   11:  * This library is distributed in the hope that it will be useful,
   12:  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   13:  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   14:  * Lesser General Public License for more details.
   15:  *
   16:  * You should have received a copy of the GNU Lesser General Public
   17:  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
   18:  */
   19: 
   20: /* A lot of PowerPC definition have been included here.
   21:  * Most of them are not usable for now but have been kept
   22:  * inside "#if defined(TODO) ... #endif" statements to make tests easier.
   23:  */
   24: 
   25: #include "dis-asm.h"
   26: #include "gdbstub.h"
   27: #include <kvm.h>
   28: #include "kvm_ppc.h"
   29: 
   30: //#define PPC_DUMP_CPU
   31: //#define PPC_DEBUG_SPR
   32: //#define PPC_DUMP_SPR_ACCESSES
   33: #if defined(CONFIG_USER_ONLY)
   34: #define TODO_USER_ONLY 1
   35: #endif
   36: 
   37: /* For user-mode emulation, we don't emulate any IRQ controller */
   38: #if defined(CONFIG_USER_ONLY)
   39: #define PPC_IRQ_INIT_FN(name)                                                 \
   40: static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env)         \
   41: {                                                                             \
   42: }
   43: #else
   44: #define PPC_IRQ_INIT_FN(name)                                                 \
   45: void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
   46: #endif
   47: 
   48: PPC_IRQ_INIT_FN(40x);
   49: PPC_IRQ_INIT_FN(6xx);
   50: PPC_IRQ_INIT_FN(970);
   51: PPC_IRQ_INIT_FN(POWER7);
   52: PPC_IRQ_INIT_FN(e500);
   53: 
   54: /* Generic callbacks:
   55:  * do nothing but store/retrieve spr value
   56:  */
   57: static void spr_read_generic (void *opaque, int gprn, int sprn)
   58: {
   59:     gen_load_spr(cpu_gpr[gprn], sprn);
   60: #ifdef PPC_DUMP_SPR_ACCESSES
   61:     {
   62:         TCGv_i32 t0 = tcg_const_i32(sprn);
   63:         gen_helper_load_dump_spr(t0);
   64:         tcg_temp_free_i32(t0);
   65:     }
   66: #endif
   67: }
   68: 
   69: static void spr_write_generic (void *opaque, int sprn, int gprn)
   70: {
   71:     gen_store_spr(sprn, cpu_gpr[gprn]);
   72: #ifdef PPC_DUMP_SPR_ACCESSES
   73:     {
   74:         TCGv_i32 t0 = tcg_const_i32(sprn);
   75:         gen_helper_store_dump_spr(t0);
   76:         tcg_temp_free_i32(t0);
   77:     }
   78: #endif
   79: }
   80: 
   81: #if !defined(CONFIG_USER_ONLY)
   82: static void spr_write_clear (void *opaque, int sprn, int gprn)
   83: {
   84:     TCGv t0 = tcg_temp_new();
   85:     TCGv t1 = tcg_temp_new();
   86:     gen_load_spr(t0, sprn);
   87:     tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
   88:     tcg_gen_and_tl(t0, t0, t1);
   89:     gen_store_spr(sprn, t0);
   90:     tcg_temp_free(t0);
   91:     tcg_temp_free(t1);
   92: }
   93: #endif
   94: 
   95: /* SPR common to all PowerPC */
   96: /* XER */
   97: static void spr_read_xer (void *opaque, int gprn, int sprn)
   98: {
   99:     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
  100: }
  101: 
  102: static void spr_write_xer (void *opaque, int sprn, int gprn)
  103: {
  104:     tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
  105: }
  106: 
  107: /* LR */
  108: static void spr_read_lr (void *opaque, int gprn, int sprn)
  109: {
  110:     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
  111: }
  112: 
  113: static void spr_write_lr (void *opaque, int sprn, int gprn)
  114: {
  115:     tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
  116: }
  117: 
  118: /* CFAR */
  119: #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
  120: static void spr_read_cfar (void *opaque, int gprn, int sprn)
  121: {
  122:     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
  123: }
  124: 
  125: static void spr_write_cfar (void *opaque, int sprn, int gprn)
  126: {
  127:     tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
  128: }
  129: #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
  130: 
  131: /* CTR */
  132: static void spr_read_ctr (void *opaque, int gprn, int sprn)
  133: {
  134:     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
  135: }
  136: 
  137: static void spr_write_ctr (void *opaque, int sprn, int gprn)
  138: {
  139:     tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
  140: }
  141: 
  142: /* User read access to SPR */
  143: /* USPRx */
  144: /* UMMCRx */
  145: /* UPMCx */
  146: /* USIA */
  147: /* UDECR */
  148: static void spr_read_ureg (void *opaque, int gprn, int sprn)
  149: {
  150:     gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
  151: }
  152: 
  153: /* SPR common to all non-embedded PowerPC */
  154: /* DECR */
  155: #if !defined(CONFIG_USER_ONLY)
  156: static void spr_read_decr (void *opaque, int gprn, int sprn)
  157: {
  158:     if (use_icount) {
  159:         gen_io_start();
  160:     }
  161:     gen_helper_load_decr(cpu_gpr[gprn]);
  162:     if (use_icount) {
  163:         gen_io_end();
  164:         gen_stop_exception(opaque);
  165:     }
  166: }
  167: 
  168: static void spr_write_decr (void *opaque, int sprn, int gprn)
  169: {
  170:     if (use_icount) {
  171:         gen_io_start();
  172:     }
  173:     gen_helper_store_decr(cpu_gpr[gprn]);
  174:     if (use_icount) {
  175:         gen_io_end();
  176:         gen_stop_exception(opaque);
  177:     }
  178: }
  179: #endif
  180: 
  181: /* SPR common to all non-embedded PowerPC, except 601 */
  182: /* Time base */
  183: static void spr_read_tbl (void *opaque, int gprn, int sprn)
  184: {
  185:     if (use_icount) {
  186:         gen_io_start();
  187:     }
  188:     gen_helper_load_tbl(cpu_gpr[gprn]);
  189:     if (use_icount) {
  190:         gen_io_end();
  191:         gen_stop_exception(opaque);
  192:     }
  193: }
  194: 
  195: static void spr_read_tbu (void *opaque, int gprn, int sprn)
  196: {
  197:     if (use_icount) {
  198:         gen_io_start();
  199:     }
  200:     gen_helper_load_tbu(cpu_gpr[gprn]);
  201:     if (use_icount) {
  202:         gen_io_end();
  203:         gen_stop_exception(opaque);
  204:     }
  205: }
  206: 
  207: __attribute__ (( unused ))
  208: static void spr_read_atbl (void *opaque, int gprn, int sprn)
  209: {
  210:     gen_helper_load_atbl(cpu_gpr[gprn]);
  211: }
  212: 
  213: __attribute__ (( unused ))
  214: static void spr_read_atbu (void *opaque, int gprn, int sprn)
  215: {
  216:     gen_helper_load_atbu(cpu_gpr[gprn]);
  217: }
  218: 
  219: #if !defined(CONFIG_USER_ONLY)
  220: static void spr_write_tbl (void *opaque, int sprn, int gprn)
  221: {
  222:     if (use_icount) {
  223:         gen_io_start();
  224:     }
  225:     gen_helper_store_tbl(cpu_gpr[gprn]);
  226:     if (use_icount) {
  227:         gen_io_end();
  228:         gen_stop_exception(opaque);
  229:     }
  230: }
  231: 
  232: static void spr_write_tbu (void *opaque, int sprn, int gprn)
  233: {
  234:     if (use_icount) {
  235:         gen_io_start();
  236:     }
  237:     gen_helper_store_tbu(cpu_gpr[gprn]);
  238:     if (use_icount) {
  239:         gen_io_end();
  240:         gen_stop_exception(opaque);
  241:     }
  242: }
  243: 
  244: __attribute__ (( unused ))
  245: static void spr_write_atbl (void *opaque, int sprn, int gprn)
  246: {
  247:     gen_helper_store_atbl(cpu_gpr[gprn]);
  248: }
  249: 
  250: __attribute__ (( unused ))
  251: static void spr_write_atbu (void *opaque, int sprn, int gprn)
  252: {
  253:     gen_helper_store_atbu(cpu_gpr[gprn]);
  254: }
  255: 
  256: #if defined(TARGET_PPC64)
  257: __attribute__ (( unused ))
  258: static void spr_read_purr (void *opaque, int gprn, int sprn)
  259: {
  260:     gen_helper_load_purr(cpu_gpr[gprn]);
  261: }
  262: #endif
  263: #endif
  264: 
  265: #if !defined(CONFIG_USER_ONLY)
  266: /* IBAT0U...IBAT0U */
  267: /* IBAT0L...IBAT7L */
  268: static void spr_read_ibat (void *opaque, int gprn, int sprn)
  269: {
  270:     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
  271: }
  272: 
  273: static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
  274: {
  275:     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
  276: }
  277: 
  278: static void spr_write_ibatu (void *opaque, int sprn, int gprn)
  279: {
  280:     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
  281:     gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
  282:     tcg_temp_free_i32(t0);
  283: }
  284: 
  285: static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
  286: {
  287:     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
  288:     gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
  289:     tcg_temp_free_i32(t0);
  290: }
  291: 
  292: static void spr_write_ibatl (void *opaque, int sprn, int gprn)
  293: {
  294:     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
  295:     gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
  296:     tcg_temp_free_i32(t0);
  297: }
  298: 
  299: static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
  300: {
  301:     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
  302:     gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
  303:     tcg_temp_free_i32(t0);
  304: }
  305: 
  306: /* DBAT0U...DBAT7U */
  307: /* DBAT0L...DBAT7L */
  308: static void spr_read_dbat (void *opaque, int gprn, int sprn)
  309: {
  310:     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
  311: }
  312: 
  313: static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
  314: {
  315:     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
  316: }
  317: 
  318: static void spr_write_dbatu (void *opaque, int sprn, int gprn)
  319: {
  320:     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
  321:     gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
  322:     tcg_temp_free_i32(t0);
  323: }
  324: 
  325: static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
  326: {
  327:     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
  328:     gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
  329:     tcg_temp_free_i32(t0);
  330: }
  331: 
  332: static void spr_write_dbatl (void *opaque, int sprn, int gprn)
  333: {
  334:     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
  335:     gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
  336:     tcg_temp_free_i32(t0);
  337: }
  338: 
  339: static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
  340: {
  341:     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
  342:     gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
  343:     tcg_temp_free_i32(t0);
  344: }
  345: 
  346: /* SDR1 */
  347: static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
  348: {
  349:     gen_helper_store_sdr1(cpu_gpr[gprn]);
  350: }
  351: 
  352: /* 64 bits PowerPC specific SPRs */
  353: /* ASR */
  354: #if defined(TARGET_PPC64)
  355: static void spr_read_hior (void *opaque, int gprn, int sprn)
  356: {
  357:     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
  358: }
  359: 
  360: static void spr_write_hior (void *opaque, int sprn, int gprn)
  361: {
  362:     TCGv t0 = tcg_temp_new();
  363:     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
  364:     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
  365:     tcg_temp_free(t0);
  366: }
  367: 
  368: static void spr_read_asr (void *opaque, int gprn, int sprn)
  369: {
  370:     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
  371: }
  372: 
  373: static void spr_write_asr (void *opaque, int sprn, int gprn)
  374: {
  375:     gen_helper_store_asr(cpu_gpr[gprn]);
  376: }
  377: #endif
  378: #endif
  379: 
  380: /* PowerPC 601 specific registers */
  381: /* RTC */
  382: static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
  383: {
  384:     gen_helper_load_601_rtcl(cpu_gpr[gprn]);
  385: }
  386: 
  387: static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
  388: {
  389:     gen_helper_load_601_rtcu(cpu_gpr[gprn]);
  390: }
  391: 
  392: #if !defined(CONFIG_USER_ONLY)
  393: static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
  394: {
  395:     gen_helper_store_601_rtcu(cpu_gpr[gprn]);
  396: }
  397: 
  398: static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
  399: {
  400:     gen_helper_store_601_rtcl(cpu_gpr[gprn]);
  401: }
  402: 
  403: static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
  404: {
  405:     DisasContext *ctx = opaque;
  406: 
  407:     gen_helper_store_hid0_601(cpu_gpr[gprn]);
  408:     /* Must stop the translation as endianness may have changed */
  409:     gen_stop_exception(ctx);
  410: }
  411: #endif
  412: 
  413: /* Unified bats */
  414: #if !defined(CONFIG_USER_ONLY)
  415: static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
  416: {
  417:     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
  418: }
  419: 
  420: static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
  421: {
  422:     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
  423:     gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
  424:     tcg_temp_free_i32(t0);
  425: }
  426: 
  427: static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
  428: {
  429:     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
  430:     gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
  431:     tcg_temp_free_i32(t0);
  432: }
  433: #endif
  434: 
  435: /* PowerPC 40x specific registers */
  436: #if !defined(CONFIG_USER_ONLY)
  437: static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
  438: {
  439:     gen_helper_load_40x_pit(cpu_gpr[gprn]);
  440: }
  441: 
  442: static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
  443: {
  444:     gen_helper_store_40x_pit(cpu_gpr[gprn]);
  445: }
  446: 
  447: static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
  448: {
  449:     DisasContext *ctx = opaque;
  450: 
  451:     gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
  452:     /* We must stop translation as we may have rebooted */
  453:     gen_stop_exception(ctx);
  454: }
  455: 
  456: static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
  457: {
  458:     gen_helper_store_40x_sler(cpu_gpr[gprn]);
  459: }
  460: 
  461: static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
  462: {
  463:     gen_helper_store_booke_tcr(cpu_gpr[gprn]);
  464: }
  465: 
  466: static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
  467: {
  468:     gen_helper_store_booke_tsr(cpu_gpr[gprn]);
  469: }
  470: #endif
  471: 
  472: /* PowerPC 403 specific registers */
  473: /* PBL1 / PBU1 / PBL2 / PBU2 */
  474: #if !defined(CONFIG_USER_ONLY)
  475: static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
  476: {
  477:     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
  478: }
  479: 
  480: static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
  481: {
  482:     TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
  483:     gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
  484:     tcg_temp_free_i32(t0);
  485: }
  486: 
  487: static void spr_write_pir (void *opaque, int sprn, int gprn)
  488: {
  489:     TCGv t0 = tcg_temp_new();
  490:     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
  491:     gen_store_spr(SPR_PIR, t0);
  492:     tcg_temp_free(t0);
  493: }
  494: #endif
  495: 
  496: /* SPE specific registers */
  497: static void spr_read_spefscr (void *opaque, int gprn, int sprn)
  498: {
  499:     TCGv_i32 t0 = tcg_temp_new_i32();
  500:     tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
  501:     tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
  502:     tcg_temp_free_i32(t0);
  503: }
  504: 
  505: static void spr_write_spefscr (void *opaque, int sprn, int gprn)
  506: {
  507:     TCGv_i32 t0 = tcg_temp_new_i32();
  508:     tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
  509:     tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
  510:     tcg_temp_free_i32(t0);
  511: }
  512: 
  513: #if !defined(CONFIG_USER_ONLY)
  514: /* Callback used to write the exception vector base */
  515: static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
  516: {
  517:     TCGv t0 = tcg_temp_new();
  518:     tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
  519:     tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
  520:     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
  521:     gen_store_spr(sprn, t0);
  522:     tcg_temp_free(t0);
  523: }
  524: 
  525: static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
  526: {
  527:     DisasContext *ctx = opaque;
  528: 
  529:     if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
  530:         TCGv t0 = tcg_temp_new();
  531:         tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
  532:         tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
  533:         tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
  534:         gen_store_spr(sprn, t0);
  535:         tcg_temp_free(t0);
  536:     } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
  537:         TCGv t0 = tcg_temp_new();
  538:         tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
  539:         tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
  540:         tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
  541:         gen_store_spr(sprn, t0);
  542:         tcg_temp_free(t0);
  543:     } else {
  544:         printf("Trying to write an unknown exception vector %d %03x\n",
  545:                sprn, sprn);
  546:         gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
  547:     }
  548: }
  549: #endif
  550: 
  551: static inline void vscr_init (CPUPPCState *env, uint32_t val)
  552: {
  553:     env->vscr = val;
  554:     /* Altivec always uses round-to-nearest */
  555:     set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
  556:     set_flush_to_zero(vscr_nj, &env->vec_status);
  557: }
  558: 
  559: #if defined(CONFIG_USER_ONLY)
  560: #define spr_register(env, num, name, uea_read, uea_write,                     \
  561:                      oea_read, oea_write, initial_value)                      \
  562: do {                                                                          \
  563:      _spr_register(env, num, name, uea_read, uea_write, initial_value);       \
  564: } while (0)
  565: static inline void _spr_register (CPUPPCState *env, int num,
  566:                                   const char *name,
  567:                                   void (*uea_read)(void *opaque, int gprn, int sprn),
  568:                                   void (*uea_write)(void *opaque, int sprn, int gprn),
  569:                                   target_ulong initial_value)
  570: #else
  571: static inline void spr_register (CPUPPCState *env, int num,
  572:                                  const char *name,
  573:                                  void (*uea_read)(void *opaque, int gprn, int sprn),
  574:                                  void (*uea_write)(void *opaque, int sprn, int gprn),
  575:                                  void (*oea_read)(void *opaque, int gprn, int sprn),
  576:                                  void (*oea_write)(void *opaque, int sprn, int gprn),
  577:                                  target_ulong initial_value)
  578: #endif
  579: {
  580:     ppc_spr_t *spr;
  581: 
  582:     spr = &env->spr_cb[num];
  583:     if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
  584: #if !defined(CONFIG_USER_ONLY)
  585:         spr->oea_read != NULL || spr->oea_write != NULL ||
  586: #endif
  587:         spr->uea_read != NULL || spr->uea_write != NULL) {
  588:         printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
  589:         exit(1);
  590:     }
  591: #if defined(PPC_DEBUG_SPR)
  592:     printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
  593:            name, initial_value);
  594: #endif
  595:     spr->name = name;
  596:     spr->uea_read = uea_read;
  597:     spr->uea_write = uea_write;
  598: #if !defined(CONFIG_USER_ONLY)
  599:     spr->oea_read = oea_read;
  600:     spr->oea_write = oea_write;
  601: #endif
  602:     env->spr[num] = initial_value;
  603: }
  604: 
  605: /* Generic PowerPC SPRs */
  606: static void gen_spr_generic (CPUPPCState *env)
  607: {
  608:     /* Integer processing */
  609:     spr_register(env, SPR_XER, "XER",
  610:                  &spr_read_xer, &spr_write_xer,
  611:                  &spr_read_xer, &spr_write_xer,
  612:                  0x00000000);
  613:     /* Branch contol */
  614:     spr_register(env, SPR_LR, "LR",
  615:                  &spr_read_lr, &spr_write_lr,
  616:                  &spr_read_lr, &spr_write_lr,
  617:                  0x00000000);
  618:     spr_register(env, SPR_CTR, "CTR",
  619:                  &spr_read_ctr, &spr_write_ctr,
  620:                  &spr_read_ctr, &spr_write_ctr,
  621:                  0x00000000);
  622:     /* Interrupt processing */
  623:     spr_register(env, SPR_SRR0, "SRR0",
  624:                  SPR_NOACCESS, SPR_NOACCESS,
  625:                  &spr_read_generic, &spr_write_generic,
  626:                  0x00000000);
  627:     spr_register(env, SPR_SRR1, "SRR1",
  628:                  SPR_NOACCESS, SPR_NOACCESS,
  629:                  &spr_read_generic, &spr_write_generic,
  630:                  0x00000000);
  631:     /* Processor control */
  632:     spr_register(env, SPR_SPRG0, "SPRG0",
  633:                  SPR_NOACCESS, SPR_NOACCESS,
  634:                  &spr_read_generic, &spr_write_generic,
  635:                  0x00000000);
  636:     spr_register(env, SPR_SPRG1, "SPRG1",
  637:                  SPR_NOACCESS, SPR_NOACCESS,
  638:                  &spr_read_generic, &spr_write_generic,
  639:                  0x00000000);
  640:     spr_register(env, SPR_SPRG2, "SPRG2",
  641:                  SPR_NOACCESS, SPR_NOACCESS,
  642:                  &spr_read_generic, &spr_write_generic,
  643:                  0x00000000);
  644:     spr_register(env, SPR_SPRG3, "SPRG3",
  645:                  SPR_NOACCESS, SPR_NOACCESS,
  646:                  &spr_read_generic, &spr_write_generic,
  647:                  0x00000000);
  648: }
  649: 
  650: /* SPR common to all non-embedded PowerPC, including 601 */
  651: static void gen_spr_ne_601 (CPUPPCState *env)
  652: {
  653:     /* Exception processing */
  654:     spr_register(env, SPR_DSISR, "DSISR",
  655:                  SPR_NOACCESS, SPR_NOACCESS,
  656:                  &spr_read_generic, &spr_write_generic,
  657:                  0x00000000);
  658:     spr_register(env, SPR_DAR, "DAR",
  659:                  SPR_NOACCESS, SPR_NOACCESS,
  660:                  &spr_read_generic, &spr_write_generic,
  661:                  0x00000000);
  662:     /* Timer */
  663:     spr_register(env, SPR_DECR, "DECR",
  664:                  SPR_NOACCESS, SPR_NOACCESS,
  665:                  &spr_read_decr, &spr_write_decr,
  666:                  0x00000000);
  667:     /* Memory management */
  668:     spr_register(env, SPR_SDR1, "SDR1",
  669:                  SPR_NOACCESS, SPR_NOACCESS,
  670:                  &spr_read_generic, &spr_write_sdr1,
  671:                  0x00000000);
  672: }
  673: 
  674: /* BATs 0-3 */
  675: static void gen_low_BATs (CPUPPCState *env)
  676: {
  677: #if !defined(CONFIG_USER_ONLY)
  678:     spr_register(env, SPR_IBAT0U, "IBAT0U",
  679:                  SPR_NOACCESS, SPR_NOACCESS,
  680:                  &spr_read_ibat, &spr_write_ibatu,
  681:                  0x00000000);
  682:     spr_register(env, SPR_IBAT0L, "IBAT0L",
  683:                  SPR_NOACCESS, SPR_NOACCESS,
  684:                  &spr_read_ibat, &spr_write_ibatl,
  685:                  0x00000000);
  686:     spr_register(env, SPR_IBAT1U, "IBAT1U",
  687:                  SPR_NOACCESS, SPR_NOACCESS,
  688:                  &spr_read_ibat, &spr_write_ibatu,
  689:                  0x00000000);
  690:     spr_register(env, SPR_IBAT1L, "IBAT1L",
  691:                  SPR_NOACCESS, SPR_NOACCESS,
  692:                  &spr_read_ibat, &spr_write_ibatl,
  693:                  0x00000000);
  694:     spr_register(env, SPR_IBAT2U, "IBAT2U",
  695:                  SPR_NOACCESS, SPR_NOACCESS,
  696:                  &spr_read_ibat, &spr_write_ibatu,
  697:                  0x00000000);
  698:     spr_register(env, SPR_IBAT2L, "IBAT2L",
  699:                  SPR_NOACCESS, SPR_NOACCESS,
  700:                  &spr_read_ibat, &spr_write_ibatl,
  701:                  0x00000000);
  702:     spr_register(env, SPR_IBAT3U, "IBAT3U",
  703:                  SPR_NOACCESS, SPR_NOACCESS,
  704:                  &spr_read_ibat, &spr_write_ibatu,
  705:                  0x00000000);
  706:     spr_register(env, SPR_IBAT3L, "IBAT3L",
  707:                  SPR_NOACCESS, SPR_NOACCESS,
  708:                  &spr_read_ibat, &spr_write_ibatl,
  709:                  0x00000000);
  710:     spr_register(env, SPR_DBAT0U, "DBAT0U",
  711:                  SPR_NOACCESS, SPR_NOACCESS,
  712:                  &spr_read_dbat, &spr_write_dbatu,
  713:                  0x00000000);
  714:     spr_register(env, SPR_DBAT0L, "DBAT0L",
  715:                  SPR_NOACCESS, SPR_NOACCESS,
  716:                  &spr_read_dbat, &spr_write_dbatl,
  717:                  0x00000000);
  718:     spr_register(env, SPR_DBAT1U, "DBAT1U",
  719:                  SPR_NOACCESS, SPR_NOACCESS,
  720:                  &spr_read_dbat, &spr_write_dbatu,
  721:                  0x00000000);
  722:     spr_register(env, SPR_DBAT1L, "DBAT1L",
  723:                  SPR_NOACCESS, SPR_NOACCESS,
  724:                  &spr_read_dbat, &spr_write_dbatl,
  725:                  0x00000000);
  726:     spr_register(env, SPR_DBAT2U, "DBAT2U",
  727:                  SPR_NOACCESS, SPR_NOACCESS,
  728:                  &spr_read_dbat, &spr_write_dbatu,
  729:                  0x00000000);
  730:     spr_register(env, SPR_DBAT2L, "DBAT2L",
  731:                  SPR_NOACCESS, SPR_NOACCESS,
  732:                  &spr_read_dbat, &spr_write_dbatl,
  733:                  0x00000000);
  734:     spr_register(env, SPR_DBAT3U, "DBAT3U",
  735:                  SPR_NOACCESS, SPR_NOACCESS,
  736:                  &spr_read_dbat, &spr_write_dbatu,
  737:                  0x00000000);
  738:     spr_register(env, SPR_DBAT3L, "DBAT3L",
  739:                  SPR_NOACCESS, SPR_NOACCESS,
  740:                  &spr_read_dbat, &spr_write_dbatl,
  741:                  0x00000000);
  742:     env->nb_BATs += 4;
  743: #endif
  744: }
  745: 
  746: /* BATs 4-7 */
  747: static void gen_high_BATs (CPUPPCState *env)
  748: {
  749: #if !defined(CONFIG_USER_ONLY)
  750:     spr_register(env, SPR_IBAT4U, "IBAT4U",
  751:                  SPR_NOACCESS, SPR_NOACCESS,
  752:                  &spr_read_ibat_h, &spr_write_ibatu_h,
  753:                  0x00000000);
  754:     spr_register(env, SPR_IBAT4L, "IBAT4L",
  755:                  SPR_NOACCESS, SPR_NOACCESS,
  756:                  &spr_read_ibat_h, &spr_write_ibatl_h,
  757:                  0x00000000);
  758:     spr_register(env, SPR_IBAT5U, "IBAT5U",
  759:                  SPR_NOACCESS, SPR_NOACCESS,
  760:                  &spr_read_ibat_h, &spr_write_ibatu_h,
  761:                  0x00000000);
  762:     spr_register(env, SPR_IBAT5L, "IBAT5L",
  763:                  SPR_NOACCESS, SPR_NOACCESS,
  764:                  &spr_read_ibat_h, &spr_write_ibatl_h,
  765:                  0x00000000);
  766:     spr_register(env, SPR_IBAT6U, "IBAT6U",
  767:                  SPR_NOACCESS, SPR_NOACCESS,
  768:                  &spr_read_ibat_h, &spr_write_ibatu_h,
  769:                  0x00000000);
  770:     spr_register(env, SPR_IBAT6L, "IBAT6L",
  771:                  SPR_NOACCESS, SPR_NOACCESS,
  772:                  &spr_read_ibat_h, &spr_write_ibatl_h,
  773:                  0x00000000);
  774:     spr_register(env, SPR_IBAT7U, "IBAT7U",
  775:                  SPR_NOACCESS, SPR_NOACCESS,
  776:                  &spr_read_ibat_h, &spr_write_ibatu_h,
  777:                  0x00000000);
  778:     spr_register(env, SPR_IBAT7L, "IBAT7L",
  779:                  SPR_NOACCESS, SPR_NOACCESS,
  780:                  &spr_read_ibat_h, &spr_write_ibatl_h,
  781:                  0x00000000);
  782:     spr_register(env, SPR_DBAT4U, "DBAT4U",
  783:                  SPR_NOACCESS, SPR_NOACCESS,
  784:                  &spr_read_dbat_h, &spr_write_dbatu_h,
  785:                  0x00000000);
  786:     spr_register(env, SPR_DBAT4L, "DBAT4L",
  787:                  SPR_NOACCESS, SPR_NOACCESS,
  788:                  &spr_read_dbat_h, &spr_write_dbatl_h,
  789:                  0x00000000);
  790:     spr_register(env, SPR_DBAT5U, "DBAT5U",
  791:                  SPR_NOACCESS, SPR_NOACCESS,
  792:                  &spr_read_dbat_h, &spr_write_dbatu_h,
  793:                  0x00000000);
  794:     spr_register(env, SPR_DBAT5L, "DBAT5L",
  795:                  SPR_NOACCESS, SPR_NOACCESS,
  796:                  &spr_read_dbat_h, &spr_write_dbatl_h,
  797:                  0x00000000);
  798:     spr_register(env, SPR_DBAT6U, "DBAT6U",
  799:                  SPR_NOACCESS, SPR_NOACCESS,
  800:                  &spr_read_dbat_h, &spr_write_dbatu_h,
  801:                  0x00000000);
  802:     spr_register(env, SPR_DBAT6L, "DBAT6L",
  803:                  SPR_NOACCESS, SPR_NOACCESS,
  804:                  &spr_read_dbat_h, &spr_write_dbatl_h,
  805:                  0x00000000);
  806:     spr_register(env, SPR_DBAT7U, "DBAT7U",
  807:                  SPR_NOACCESS, SPR_NOACCESS,
  808:                  &spr_read_dbat_h, &spr_write_dbatu_h,
  809:                  0x00000000);
  810:     spr_register(env, SPR_DBAT7L, "DBAT7L",
  811:                  SPR_NOACCESS, SPR_NOACCESS,
  812:                  &spr_read_dbat_h, &spr_write_dbatl_h,
  813:                  0x00000000);
  814:     env->nb_BATs += 4;
  815: #endif
  816: }
  817: 
  818: /* Generic PowerPC time base */
  819: static void gen_tbl (CPUPPCState *env)
  820: {
  821:     spr_register(env, SPR_VTBL,  "TBL",
  822:                  &spr_read_tbl, SPR_NOACCESS,
  823:                  &spr_read_tbl, SPR_NOACCESS,
  824:                  0x00000000);
  825:     spr_register(env, SPR_TBL,   "TBL",
  826:                  &spr_read_tbl, SPR_NOACCESS,
  827:                  &spr_read_tbl, &spr_write_tbl,
  828:                  0x00000000);
  829:     spr_register(env, SPR_VTBU,  "TBU",
  830:                  &spr_read_tbu, SPR_NOACCESS,
  831:                  &spr_read_tbu, SPR_NOACCESS,
  832:                  0x00000000);
  833:     spr_register(env, SPR_TBU,   "TBU",
  834:                  &spr_read_tbu, SPR_NOACCESS,
  835:                  &spr_read_tbu, &spr_write_tbu,
  836:                  0x00000000);
  837: }
  838: 
  839: /* Softare table search registers */
  840: static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
  841: {
  842: #if !defined(CONFIG_USER_ONLY)
  843:     env->nb_tlb = nb_tlbs;
  844:     env->nb_ways = nb_ways;
  845:     env->id_tlbs = 1;
  846:     env->tlb_type = TLB_6XX;
  847:     spr_register(env, SPR_DMISS, "DMISS",
  848:                  SPR_NOACCESS, SPR_NOACCESS,
  849:                  &spr_read_generic, SPR_NOACCESS,
  850:                  0x00000000);
  851:     spr_register(env, SPR_DCMP, "DCMP",
  852:                  SPR_NOACCESS, SPR_NOACCESS,
  853:                  &spr_read_generic, SPR_NOACCESS,
  854:                  0x00000000);
  855:     spr_register(env, SPR_HASH1, "HASH1",
  856:                  SPR_NOACCESS, SPR_NOACCESS,
  857:                  &spr_read_generic, SPR_NOACCESS,
  858:                  0x00000000);
  859:     spr_register(env, SPR_HASH2, "HASH2",
  860:                  SPR_NOACCESS, SPR_NOACCESS,
  861:                  &spr_read_generic, SPR_NOACCESS,
  862:                  0x00000000);
  863:     spr_register(env, SPR_IMISS, "IMISS",
  864:                  SPR_NOACCESS, SPR_NOACCESS,
  865:                  &spr_read_generic, SPR_NOACCESS,
  866:                  0x00000000);
  867:     spr_register(env, SPR_ICMP, "ICMP",
  868:                  SPR_NOACCESS, SPR_NOACCESS,
  869:                  &spr_read_generic, SPR_NOACCESS,
  870:                  0x00000000);
  871:     spr_register(env, SPR_RPA, "RPA",
  872:                  SPR_NOACCESS, SPR_NOACCESS,
  873:                  &spr_read_generic, &spr_write_generic,
  874:                  0x00000000);
  875: #endif
  876: }
  877: 
  878: /* SPR common to MPC755 and G2 */
  879: static void gen_spr_G2_755 (CPUPPCState *env)
  880: {
  881:     /* SGPRs */
  882:     spr_register(env, SPR_SPRG4, "SPRG4",
  883:                  SPR_NOACCESS, SPR_NOACCESS,
  884:                  &spr_read_generic, &spr_write_generic,
  885:                  0x00000000);
  886:     spr_register(env, SPR_SPRG5, "SPRG5",
  887:                  SPR_NOACCESS, SPR_NOACCESS,
  888:                  &spr_read_generic, &spr_write_generic,
  889:                  0x00000000);
  890:     spr_register(env, SPR_SPRG6, "SPRG6",
  891:                  SPR_NOACCESS, SPR_NOACCESS,
  892:                  &spr_read_generic, &spr_write_generic,
  893:                  0x00000000);
  894:     spr_register(env, SPR_SPRG7, "SPRG7",
  895:                  SPR_NOACCESS, SPR_NOACCESS,
  896:                  &spr_read_generic, &spr_write_generic,
  897:                  0x00000000);
  898: }
  899: 
  900: /* SPR common to all 7xx PowerPC implementations */
  901: static void gen_spr_7xx (CPUPPCState *env)
  902: {
  903:     /* Breakpoints */
  904:     /* XXX : not implemented */
  905:     spr_register(env, SPR_DABR, "DABR",
  906:                  SPR_NOACCESS, SPR_NOACCESS,
  907:                  &spr_read_generic, &spr_write_generic,
  908:                  0x00000000);
  909:     /* XXX : not implemented */
  910:     spr_register(env, SPR_IABR, "IABR",
  911:                  SPR_NOACCESS, SPR_NOACCESS,
  912:                  &spr_read_generic, &spr_write_generic,
  913:                  0x00000000);
  914:     /* Cache management */
  915:     /* XXX : not implemented */
  916:     spr_register(env, SPR_ICTC, "ICTC",
  917:                  SPR_NOACCESS, SPR_NOACCESS,
  918:                  &spr_read_generic, &spr_write_generic,
  919:                  0x00000000);
  920:     /* Performance monitors */
  921:     /* XXX : not implemented */
  922:     spr_register(env, SPR_MMCR0, "MMCR0",
  923:                  SPR_NOACCESS, SPR_NOACCESS,
  924:                  &spr_read_generic, &spr_write_generic,
  925:                  0x00000000);
  926:     /* XXX : not implemented */
  927:     spr_register(env, SPR_MMCR1, "MMCR1",
  928:                  SPR_NOACCESS, SPR_NOACCESS,
  929:                  &spr_read_generic, &spr_write_generic,
  930:                  0x00000000);
  931:     /* XXX : not implemented */
  932:     spr_register(env, SPR_PMC1, "PMC1",
  933:                  SPR_NOACCESS, SPR_NOACCESS,
  934:                  &spr_read_generic, &spr_write_generic,
  935:                  0x00000000);
  936:     /* XXX : not implemented */
  937:     spr_register(env, SPR_PMC2, "PMC2",
  938:                  SPR_NOACCESS, SPR_NOACCESS,
  939:                  &spr_read_generic, &spr_write_generic,
  940:                  0x00000000);
  941:     /* XXX : not implemented */
  942:     spr_register(env, SPR_PMC3, "PMC3",
  943:                  SPR_NOACCESS, SPR_NOACCESS,
  944:                  &spr_read_generic, &spr_write_generic,
  945:                  0x00000000);
  946:     /* XXX : not implemented */
  947:     spr_register(env, SPR_PMC4, "PMC4",
  948:                  SPR_NOACCESS, SPR_NOACCESS,
  949:                  &spr_read_generic, &spr_write_generic,
  950:                  0x00000000);
  951:     /* XXX : not implemented */
  952:     spr_register(env, SPR_SIAR, "SIAR",
  953:                  SPR_NOACCESS, SPR_NOACCESS,
  954:                  &spr_read_generic, SPR_NOACCESS,
  955:                  0x00000000);
  956:     /* XXX : not implemented */
  957:     spr_register(env, SPR_UMMCR0, "UMMCR0",
  958:                  &spr_read_ureg, SPR_NOACCESS,
  959:                  &spr_read_ureg, SPR_NOACCESS,
  960:                  0x00000000);
  961:     /* XXX : not implemented */
  962:     spr_register(env, SPR_UMMCR1, "UMMCR1",
  963:                  &spr_read_ureg, SPR_NOACCESS,
  964:                  &spr_read_ureg, SPR_NOACCESS,
  965:                  0x00000000);
  966:     /* XXX : not implemented */
  967:     spr_register(env, SPR_UPMC1, "UPMC1",
  968:                  &spr_read_ureg, SPR_NOACCESS,
  969:                  &spr_read_ureg, SPR_NOACCESS,
  970:                  0x00000000);
  971:     /* XXX : not implemented */
  972:     spr_register(env, SPR_UPMC2, "UPMC2",
  973:                  &spr_read_ureg, SPR_NOACCESS,
  974:                  &spr_read_ureg, SPR_NOACCESS,
  975:                  0x00000000);
  976:     /* XXX : not implemented */
  977:     spr_register(env, SPR_UPMC3, "UPMC3",
  978:                  &spr_read_ureg, SPR_NOACCESS,
  979:                  &spr_read_ureg, SPR_NOACCESS,
  980:                  0x00000000);
  981:     /* XXX : not implemented */
  982:     spr_register(env, SPR_UPMC4, "UPMC4",
  983:                  &spr_read_ureg, SPR_NOACCESS,
  984:                  &spr_read_ureg, SPR_NOACCESS,
  985:                  0x00000000);
  986:     /* XXX : not implemented */
  987:     spr_register(env, SPR_USIAR, "USIAR",
  988:                  &spr_read_ureg, SPR_NOACCESS,
  989:                  &spr_read_ureg, SPR_NOACCESS,
  990:                  0x00000000);
  991:     /* External access control */
  992:     /* XXX : not implemented */
  993:     spr_register(env, SPR_EAR, "EAR",
  994:                  SPR_NOACCESS, SPR_NOACCESS,
  995:                  &spr_read_generic, &spr_write_generic,
  996:                  0x00000000);
  997: }
  998: 
  999: static void gen_spr_thrm (CPUPPCState *env)
 1000: {
 1001:     /* Thermal management */
 1002:     /* XXX : not implemented */
 1003:     spr_register(env, SPR_THRM1, "THRM1",
 1004:                  SPR_NOACCESS, SPR_NOACCESS,
 1005:                  &spr_read_generic, &spr_write_generic,
 1006:                  0x00000000);
 1007:     /* XXX : not implemented */
 1008:     spr_register(env, SPR_THRM2, "THRM2",
 1009:                  SPR_NOACCESS, SPR_NOACCESS,
 1010:                  &spr_read_generic, &spr_write_generic,
 1011:                  0x00000000);
 1012:     /* XXX : not implemented */
 1013:     spr_register(env, SPR_THRM3, "THRM3",
 1014:                  SPR_NOACCESS, SPR_NOACCESS,
 1015:                  &spr_read_generic, &spr_write_generic,
 1016:                  0x00000000);
 1017: }
 1018: 
 1019: /* SPR specific to PowerPC 604 implementation */
 1020: static void gen_spr_604 (CPUPPCState *env)
 1021: {
 1022:     /* Processor identification */
 1023:     spr_register(env, SPR_PIR, "PIR",
 1024:                  SPR_NOACCESS, SPR_NOACCESS,
 1025:                  &spr_read_generic, &spr_write_pir,
 1026:                  0x00000000);
 1027:     /* Breakpoints */
 1028:     /* XXX : not implemented */
 1029:     spr_register(env, SPR_IABR, "IABR",
 1030:                  SPR_NOACCESS, SPR_NOACCESS,
 1031:                  &spr_read_generic, &spr_write_generic,
 1032:                  0x00000000);
 1033:     /* XXX : not implemented */
 1034:     spr_register(env, SPR_DABR, "DABR",
 1035:                  SPR_NOACCESS, SPR_NOACCESS,
 1036:                  &spr_read_generic, &spr_write_generic,
 1037:                  0x00000000);
 1038:     /* Performance counters */
 1039:     /* XXX : not implemented */
 1040:     spr_register(env, SPR_MMCR0, "MMCR0",
 1041:                  SPR_NOACCESS, SPR_NOACCESS,
 1042:                  &spr_read_generic, &spr_write_generic,
 1043:                  0x00000000);
 1044:     /* XXX : not implemented */
 1045:     spr_register(env, SPR_PMC1, "PMC1",
 1046:                  SPR_NOACCESS, SPR_NOACCESS,
 1047:                  &spr_read_generic, &spr_write_generic,
 1048:                  0x00000000);
 1049:     /* XXX : not implemented */
 1050:     spr_register(env, SPR_PMC2, "PMC2",
 1051:                  SPR_NOACCESS, SPR_NOACCESS,
 1052:                  &spr_read_generic, &spr_write_generic,
 1053:                  0x00000000);
 1054:     /* XXX : not implemented */
 1055:     spr_register(env, SPR_SIAR, "SIAR",
 1056:                  SPR_NOACCESS, SPR_NOACCESS,
 1057:                  &spr_read_generic, SPR_NOACCESS,
 1058:                  0x00000000);
 1059:     /* XXX : not implemented */
 1060:     spr_register(env, SPR_SDA, "SDA",
 1061:                  SPR_NOACCESS, SPR_NOACCESS,
 1062:                  &spr_read_generic, SPR_NOACCESS,
 1063:                  0x00000000);
 1064:     /* External access control */
 1065:     /* XXX : not implemented */
 1066:     spr_register(env, SPR_EAR, "EAR",
 1067:                  SPR_NOACCESS, SPR_NOACCESS,
 1068:                  &spr_read_generic, &spr_write_generic,
 1069:                  0x00000000);
 1070: }
 1071: 
 1072: /* SPR specific to PowerPC 603 implementation */
 1073: static void gen_spr_603 (CPUPPCState *env)
 1074: {
 1075:     /* External access control */
 1076:     /* XXX : not implemented */
 1077:     spr_register(env, SPR_EAR, "EAR",
 1078:                  SPR_NOACCESS, SPR_NOACCESS,
 1079:                  &spr_read_generic, &spr_write_generic,
 1080:                  0x00000000);
 1081: }
 1082: 
 1083: /* SPR specific to PowerPC G2 implementation */
 1084: static void gen_spr_G2 (CPUPPCState *env)
 1085: {
 1086:     /* Memory base address */
 1087:     /* MBAR */
 1088:     /* XXX : not implemented */
 1089:     spr_register(env, SPR_MBAR, "MBAR",
 1090:                  SPR_NOACCESS, SPR_NOACCESS,
 1091:                  &spr_read_generic, &spr_write_generic,
 1092:                  0x00000000);
 1093:     /* Exception processing */
 1094:     spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
 1095:                  SPR_NOACCESS, SPR_NOACCESS,
 1096:                  &spr_read_generic, &spr_write_generic,
 1097:                  0x00000000);
 1098:     spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
 1099:                  SPR_NOACCESS, SPR_NOACCESS,
 1100:                  &spr_read_generic, &spr_write_generic,
 1101:                  0x00000000);
 1102:     /* Breakpoints */
 1103:     /* XXX : not implemented */
 1104:     spr_register(env, SPR_DABR, "DABR",
 1105:                  SPR_NOACCESS, SPR_NOACCESS,
 1106:                  &spr_read_generic, &spr_write_generic,
 1107:                  0x00000000);
 1108:     /* XXX : not implemented */
 1109:     spr_register(env, SPR_DABR2, "DABR2",
 1110:                  SPR_NOACCESS, SPR_NOACCESS,
 1111:                  &spr_read_generic, &spr_write_generic,
 1112:                  0x00000000);
 1113:     /* XXX : not implemented */
 1114:     spr_register(env, SPR_IABR, "IABR",
 1115:                  SPR_NOACCESS, SPR_NOACCESS,
 1116:                  &spr_read_generic, &spr_write_generic,
 1117:                  0x00000000);
 1118:     /* XXX : not implemented */
 1119:     spr_register(env, SPR_IABR2, "IABR2",
 1120:                  SPR_NOACCESS, SPR_NOACCESS,
 1121:                  &spr_read_generic, &spr_write_generic,
 1122:                  0x00000000);
 1123:     /* XXX : not implemented */
 1124:     spr_register(env, SPR_IBCR, "IBCR",
 1125:                  SPR_NOACCESS, SPR_NOACCESS,
 1126:                  &spr_read_generic, &spr_write_generic,
 1127:                  0x00000000);
 1128:     /* XXX : not implemented */
 1129:     spr_register(env, SPR_DBCR, "DBCR",
 1130:                  SPR_NOACCESS, SPR_NOACCESS,
 1131:                  &spr_read_generic, &spr_write_generic,
 1132:                  0x00000000);
 1133: }
 1134: 
 1135: /* SPR specific to PowerPC 602 implementation */
 1136: static void gen_spr_602 (CPUPPCState *env)
 1137: {
 1138:     /* ESA registers */
 1139:     /* XXX : not implemented */
 1140:     spr_register(env, SPR_SER, "SER",
 1141:                  SPR_NOACCESS, SPR_NOACCESS,
 1142:                  &spr_read_generic, &spr_write_generic,
 1143:                  0x00000000);
 1144:     /* XXX : not implemented */
 1145:     spr_register(env, SPR_SEBR, "SEBR",
 1146:                  SPR_NOACCESS, SPR_NOACCESS,
 1147:                  &spr_read_generic, &spr_write_generic,
 1148:                  0x00000000);
 1149:     /* XXX : not implemented */
 1150:     spr_register(env, SPR_ESASRR, "ESASRR",
 1151:                  SPR_NOACCESS, SPR_NOACCESS,
 1152:                  &spr_read_generic, &spr_write_generic,
 1153:                  0x00000000);
 1154:     /* Floating point status */
 1155:     /* XXX : not implemented */
 1156:     spr_register(env, SPR_SP, "SP",
 1157:                  SPR_NOACCESS, SPR_NOACCESS,
 1158:                  &spr_read_generic, &spr_write_generic,
 1159:                  0x00000000);
 1160:     /* XXX : not implemented */
 1161:     spr_register(env, SPR_LT, "LT",
 1162:                  SPR_NOACCESS, SPR_NOACCESS,
 1163:                  &spr_read_generic, &spr_write_generic,
 1164:                  0x00000000);
 1165:     /* Watchdog timer */
 1166:     /* XXX : not implemented */
 1167:     spr_register(env, SPR_TCR, "TCR",
 1168:                  SPR_NOACCESS, SPR_NOACCESS,
 1169:                  &spr_read_generic, &spr_write_generic,
 1170:                  0x00000000);
 1171:     /* Interrupt base */
 1172:     spr_register(env, SPR_IBR, "IBR",
 1173:                  SPR_NOACCESS, SPR_NOACCESS,
 1174:                  &spr_read_generic, &spr_write_generic,
 1175:                  0x00000000);
 1176:     /* XXX : not implemented */
 1177:     spr_register(env, SPR_IABR, "IABR",
 1178:                  SPR_NOACCESS, SPR_NOACCESS,
 1179:                  &spr_read_generic, &spr_write_generic,
 1180:                  0x00000000);
 1181: }
 1182: 
 1183: /* SPR specific to PowerPC 601 implementation */
 1184: static void gen_spr_601 (CPUPPCState *env)
 1185: {
 1186:     /* Multiplication/division register */
 1187:     /* MQ */
 1188:     spr_register(env, SPR_MQ, "MQ",
 1189:                  &spr_read_generic, &spr_write_generic,
 1190:                  &spr_read_generic, &spr_write_generic,
 1191:                  0x00000000);
 1192:     /* RTC registers */
 1193:     spr_register(env, SPR_601_RTCU, "RTCU",
 1194:                  SPR_NOACCESS, SPR_NOACCESS,
 1195:                  SPR_NOACCESS, &spr_write_601_rtcu,
 1196:                  0x00000000);
 1197:     spr_register(env, SPR_601_VRTCU, "RTCU",
 1198:                  &spr_read_601_rtcu, SPR_NOACCESS,
 1199:                  &spr_read_601_rtcu, SPR_NOACCESS,
 1200:                  0x00000000);
 1201:     spr_register(env, SPR_601_RTCL, "RTCL",
 1202:                  SPR_NOACCESS, SPR_NOACCESS,
 1203:                  SPR_NOACCESS, &spr_write_601_rtcl,
 1204:                  0x00000000);
 1205:     spr_register(env, SPR_601_VRTCL, "RTCL",
 1206:                  &spr_read_601_rtcl, SPR_NOACCESS,
 1207:                  &spr_read_601_rtcl, SPR_NOACCESS,
 1208:                  0x00000000);
 1209:     /* Timer */
 1210: #if 0 /* ? */
 1211:     spr_register(env, SPR_601_UDECR, "UDECR",
 1212:                  &spr_read_decr, SPR_NOACCESS,
 1213:                  &spr_read_decr, SPR_NOACCESS,
 1214:                  0x00000000);
 1215: #endif
 1216:     /* External access control */
 1217:     /* XXX : not implemented */
 1218:     spr_register(env, SPR_EAR, "EAR",
 1219:                  SPR_NOACCESS, SPR_NOACCESS,
 1220:                  &spr_read_generic, &spr_write_generic,
 1221:                  0x00000000);
 1222:     /* Memory management */
 1223: #if !defined(CONFIG_USER_ONLY)
 1224:     spr_register(env, SPR_IBAT0U, "IBAT0U",
 1225:                  SPR_NOACCESS, SPR_NOACCESS,
 1226:                  &spr_read_601_ubat, &spr_write_601_ubatu,
 1227:                  0x00000000);
 1228:     spr_register(env, SPR_IBAT0L, "IBAT0L",
 1229:                  SPR_NOACCESS, SPR_NOACCESS,
 1230:                  &spr_read_601_ubat, &spr_write_601_ubatl,
 1231:                  0x00000000);
 1232:     spr_register(env, SPR_IBAT1U, "IBAT1U",
 1233:                  SPR_NOACCESS, SPR_NOACCESS,
 1234:                  &spr_read_601_ubat, &spr_write_601_ubatu,
 1235:                  0x00000000);
 1236:     spr_register(env, SPR_IBAT1L, "IBAT1L",
 1237:                  SPR_NOACCESS, SPR_NOACCESS,
 1238:                  &spr_read_601_ubat, &spr_write_601_ubatl,
 1239:                  0x00000000);
 1240:     spr_register(env, SPR_IBAT2U, "IBAT2U",
 1241:                  SPR_NOACCESS, SPR_NOACCESS,
 1242:                  &spr_read_601_ubat, &spr_write_601_ubatu,
 1243:                  0x00000000);
 1244:     spr_register(env, SPR_IBAT2L, "IBAT2L",
 1245:                  SPR_NOACCESS, SPR_NOACCESS,
 1246:                  &spr_read_601_ubat, &spr_write_601_ubatl,
 1247:                  0x00000000);
 1248:     spr_register(env, SPR_IBAT3U, "IBAT3U",
 1249:                  SPR_NOACCESS, SPR_NOACCESS,
 1250:                  &spr_read_601_ubat, &spr_write_601_ubatu,
 1251:                  0x00000000);
 1252:     spr_register(env, SPR_IBAT3L, "IBAT3L",
 1253:                  SPR_NOACCESS, SPR_NOACCESS,
 1254:                  &spr_read_601_ubat, &spr_write_601_ubatl,
 1255:                  0x00000000);
 1256:     env->nb_BATs = 4;
 1257: #endif
 1258: }
 1259: 
 1260: static void gen_spr_74xx (CPUPPCState *env)
 1261: {
 1262:     /* Processor identification */
 1263:     spr_register(env, SPR_PIR, "PIR",
 1264:                  SPR_NOACCESS, SPR_NOACCESS,
 1265:                  &spr_read_generic, &spr_write_pir,
 1266:                  0x00000000);
 1267:     /* XXX : not implemented */
 1268:     spr_register(env, SPR_MMCR2, "MMCR2",
 1269:                  SPR_NOACCESS, SPR_NOACCESS,
 1270:                  &spr_read_generic, &spr_write_generic,
 1271:                  0x00000000);
 1272:     /* XXX : not implemented */
 1273:     spr_register(env, SPR_UMMCR2, "UMMCR2",
 1274:                  &spr_read_ureg, SPR_NOACCESS,
 1275:                  &spr_read_ureg, SPR_NOACCESS,
 1276:                  0x00000000);
 1277:     /* XXX: not implemented */
 1278:     spr_register(env, SPR_BAMR, "BAMR",
 1279:                  SPR_NOACCESS, SPR_NOACCESS,
 1280:                  &spr_read_generic, &spr_write_generic,
 1281:                  0x00000000);
 1282:     /* XXX : not implemented */
 1283:     spr_register(env, SPR_MSSCR0, "MSSCR0",
 1284:                  SPR_NOACCESS, SPR_NOACCESS,
 1285:                  &spr_read_generic, &spr_write_generic,
 1286:                  0x00000000);
 1287:     /* Hardware implementation registers */
 1288:     /* XXX : not implemented */
 1289:     spr_register(env, SPR_HID0, "HID0",
 1290:                  SPR_NOACCESS, SPR_NOACCESS,
 1291:                  &spr_read_generic, &spr_write_generic,
 1292:                  0x00000000);
 1293:     /* XXX : not implemented */
 1294:     spr_register(env, SPR_HID1, "HID1",
 1295:                  SPR_NOACCESS, SPR_NOACCESS,
 1296:                  &spr_read_generic, &spr_write_generic,
 1297:                  0x00000000);
 1298:     /* Altivec */
 1299:     spr_register(env, SPR_VRSAVE, "VRSAVE",
 1300:                  &spr_read_generic, &spr_write_generic,
 1301:                  &spr_read_generic, &spr_write_generic,
 1302:                  0x00000000);
 1303:     /* XXX : not implemented */
 1304:     spr_register(env, SPR_L2CR, "L2CR",
 1305:                  SPR_NOACCESS, SPR_NOACCESS,
 1306:                  &spr_read_generic, &spr_write_generic,
 1307:                  0x00000000);
 1308:     /* Not strictly an SPR */
 1309:     vscr_init(env, 0x00010000);
 1310: }
 1311: 
 1312: static void gen_l3_ctrl (CPUPPCState *env)
 1313: {
 1314:     /* L3CR */
 1315:     /* XXX : not implemented */
 1316:     spr_register(env, SPR_L3CR, "L3CR",
 1317:                  SPR_NOACCESS, SPR_NOACCESS,
 1318:                  &spr_read_generic, &spr_write_generic,
 1319:                  0x00000000);
 1320:     /* L3ITCR0 */
 1321:     /* XXX : not implemented */
 1322:     spr_register(env, SPR_L3ITCR0, "L3ITCR0",
 1323:                  SPR_NOACCESS, SPR_NOACCESS,
 1324:                  &spr_read_generic, &spr_write_generic,
 1325:                  0x00000000);
 1326:     /* L3PM */
 1327:     /* XXX : not implemented */
 1328:     spr_register(env, SPR_L3PM, "L3PM",
 1329:                  SPR_NOACCESS, SPR_NOACCESS,
 1330:                  &spr_read_generic, &spr_write_generic,
 1331:                  0x00000000);
 1332: }
 1333: 
 1334: static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
 1335: {
 1336: #if !defined(CONFIG_USER_ONLY)
 1337:     env->nb_tlb = nb_tlbs;
 1338:     env->nb_ways = nb_ways;
 1339:     env->id_tlbs = 1;
 1340:     env->tlb_type = TLB_6XX;
 1341:     /* XXX : not implemented */
 1342:     spr_register(env, SPR_PTEHI, "PTEHI",
 1343:                  SPR_NOACCESS, SPR_NOACCESS,
 1344:                  &spr_read_generic, &spr_write_generic,
 1345:                  0x00000000);
 1346:     /* XXX : not implemented */
 1347:     spr_register(env, SPR_PTELO, "PTELO",
 1348:                  SPR_NOACCESS, SPR_NOACCESS,
 1349:                  &spr_read_generic, &spr_write_generic,
 1350:                  0x00000000);
 1351:     /* XXX : not implemented */
 1352:     spr_register(env, SPR_TLBMISS, "TLBMISS",
 1353:                  SPR_NOACCESS, SPR_NOACCESS,
 1354:                  &spr_read_generic, &spr_write_generic,
 1355:                  0x00000000);
 1356: #endif
 1357: }
 1358: 
 1359: #if !defined(CONFIG_USER_ONLY)
 1360: static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
 1361: {
 1362:     TCGv t0 = tcg_temp_new();
 1363: 
 1364:     tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
 1365:     gen_store_spr(sprn, t0);
 1366:     tcg_temp_free(t0);
 1367: }
 1368: 
 1369: static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
 1370: {
 1371:     TCGv_i32 t0 = tcg_const_i32(sprn);
 1372:     gen_helper_booke206_tlbflush(t0);
 1373:     tcg_temp_free_i32(t0);
 1374: }
 1375: 
 1376: static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
 1377: {
 1378:     TCGv_i32 t0 = tcg_const_i32(sprn);
 1379:     gen_helper_booke_setpid(t0, cpu_gpr[gprn]);
 1380:     tcg_temp_free_i32(t0);
 1381: }
 1382: #endif
 1383: 
 1384: static void gen_spr_usprgh (CPUPPCState *env)
 1385: {
 1386:     spr_register(env, SPR_USPRG4, "USPRG4",
 1387:                  &spr_read_ureg, SPR_NOACCESS,
 1388:                  &spr_read_ureg, SPR_NOACCESS,
 1389:                  0x00000000);
 1390:     spr_register(env, SPR_USPRG5, "USPRG5",
 1391:                  &spr_read_ureg, SPR_NOACCESS,
 1392:                  &spr_read_ureg, SPR_NOACCESS,
 1393:                  0x00000000);
 1394:     spr_register(env, SPR_USPRG6, "USPRG6",
 1395:                  &spr_read_ureg, SPR_NOACCESS,
 1396:                  &spr_read_ureg, SPR_NOACCESS,
 1397:                  0x00000000);
 1398:     spr_register(env, SPR_USPRG7, "USPRG7",
 1399:                  &spr_read_ureg, SPR_NOACCESS,
 1400:                  &spr_read_ureg, SPR_NOACCESS,
 1401:                  0x00000000);
 1402: }
 1403: 
 1404: /* PowerPC BookE SPR */
 1405: static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
 1406: {
 1407:     const char *ivor_names[64] = {
 1408:         "IVOR0",  "IVOR1",  "IVOR2",  "IVOR3",
 1409:         "IVOR4",  "IVOR5",  "IVOR6",  "IVOR7",
 1410:         "IVOR8",  "IVOR9",  "IVOR10", "IVOR11",
 1411:         "IVOR12", "IVOR13", "IVOR14", "IVOR15",
 1412:         "IVOR16", "IVOR17", "IVOR18", "IVOR19",
 1413:         "IVOR20", "IVOR21", "IVOR22", "IVOR23",
 1414:         "IVOR24", "IVOR25", "IVOR26", "IVOR27",
 1415:         "IVOR28", "IVOR29", "IVOR30", "IVOR31",
 1416:         "IVOR32", "IVOR33", "IVOR34", "IVOR35",
 1417:         "IVOR36", "IVOR37", "IVOR38", "IVOR39",
 1418:         "IVOR40", "IVOR41", "IVOR42", "IVOR43",
 1419:         "IVOR44", "IVOR45", "IVOR46", "IVOR47",
 1420:         "IVOR48", "IVOR49", "IVOR50", "IVOR51",
 1421:         "IVOR52", "IVOR53", "IVOR54", "IVOR55",
 1422:         "IVOR56", "IVOR57", "IVOR58", "IVOR59",
 1423:         "IVOR60", "IVOR61", "IVOR62", "IVOR63",
 1424:     };
 1425: #define SPR_BOOKE_IVORxx (-1)
 1426:     int ivor_sprn[64] = {
 1427:         SPR_BOOKE_IVOR0,  SPR_BOOKE_IVOR1,  SPR_BOOKE_IVOR2,  SPR_BOOKE_IVOR3,
 1428:         SPR_BOOKE_IVOR4,  SPR_BOOKE_IVOR5,  SPR_BOOKE_IVOR6,  SPR_BOOKE_IVOR7,
 1429:         SPR_BOOKE_IVOR8,  SPR_BOOKE_IVOR9,  SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
 1430:         SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
 1431:         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
 1432:         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
 1433:         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
 1434:         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
 1435:         SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
 1436:         SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
 1437:         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
 1438:         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
 1439:         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
 1440:         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
 1441:         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
 1442:         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
 1443:     };
 1444:     int i;
 1445: 
 1446:     /* Interrupt processing */
 1447:     spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
 1448:                  SPR_NOACCESS, SPR_NOACCESS,
 1449:                  &spr_read_generic, &spr_write_generic,
 1450:                  0x00000000);
 1451:     spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
 1452:                  SPR_NOACCESS, SPR_NOACCESS,
 1453:                  &spr_read_generic, &spr_write_generic,
 1454:                  0x00000000);
 1455:     /* Debug */
 1456:     /* XXX : not implemented */
 1457:     spr_register(env, SPR_BOOKE_IAC1, "IAC1",
 1458:                  SPR_NOACCESS, SPR_NOACCESS,
 1459:                  &spr_read_generic, &spr_write_generic,
 1460:                  0x00000000);
 1461:     /* XXX : not implemented */
 1462:     spr_register(env, SPR_BOOKE_IAC2, "IAC2",
 1463:                  SPR_NOACCESS, SPR_NOACCESS,
 1464:                  &spr_read_generic, &spr_write_generic,
 1465:                  0x00000000);
 1466:     /* XXX : not implemented */
 1467:     spr_register(env, SPR_BOOKE_DAC1, "DAC1",
 1468:                  SPR_NOACCESS, SPR_NOACCESS,
 1469:                  &spr_read_generic, &spr_write_generic,
 1470:                  0x00000000);
 1471:     /* XXX : not implemented */
 1472:     spr_register(env, SPR_BOOKE_DAC2, "DAC2",
 1473:                  SPR_NOACCESS, SPR_NOACCESS,
 1474:                  &spr_read_generic, &spr_write_generic,
 1475:                  0x00000000);
 1476:     /* XXX : not implemented */
 1477:     spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
 1478:                  SPR_NOACCESS, SPR_NOACCESS,
 1479:                  &spr_read_generic, &spr_write_generic,
 1480:                  0x00000000);
 1481:     /* XXX : not implemented */
 1482:     spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
 1483:                  SPR_NOACCESS, SPR_NOACCESS,
 1484:                  &spr_read_generic, &spr_write_generic,
 1485:                  0x00000000);
 1486:     /* XXX : not implemented */
 1487:     spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
 1488:                  SPR_NOACCESS, SPR_NOACCESS,
 1489:                  &spr_read_generic, &spr_write_generic,
 1490:                  0x00000000);
 1491:     /* XXX : not implemented */
 1492:     spr_register(env, SPR_BOOKE_DBSR, "DBSR",
 1493:                  SPR_NOACCESS, SPR_NOACCESS,
 1494:                  &spr_read_generic, &spr_write_clear,
 1495:                  0x00000000);
 1496:     spr_register(env, SPR_BOOKE_DEAR, "DEAR",
 1497:                  SPR_NOACCESS, SPR_NOACCESS,
 1498:                  &spr_read_generic, &spr_write_generic,
 1499:                  0x00000000);
 1500:     spr_register(env, SPR_BOOKE_ESR, "ESR",
 1501:                  SPR_NOACCESS, SPR_NOACCESS,
 1502:                  &spr_read_generic, &spr_write_generic,
 1503:                  0x00000000);
 1504:     spr_register(env, SPR_BOOKE_IVPR, "IVPR",
 1505:                  SPR_NOACCESS, SPR_NOACCESS,
 1506:                  &spr_read_generic, &spr_write_excp_prefix,
 1507:                  0x00000000);
 1508:     /* Exception vectors */
 1509:     for (i = 0; i < 64; i++) {
 1510:         if (ivor_mask & (1ULL << i)) {
 1511:             if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
 1512:                 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
 1513:                 exit(1);
 1514:             }
 1515:             spr_register(env, ivor_sprn[i], ivor_names[i],
 1516:                          SPR_NOACCESS, SPR_NOACCESS,
 1517:                          &spr_read_generic, &spr_write_excp_vector,
 1518:                          0x00000000);
 1519:         }
 1520:     }
 1521:     spr_register(env, SPR_BOOKE_PID, "PID",
 1522:                  SPR_NOACCESS, SPR_NOACCESS,
 1523:                  &spr_read_generic, &spr_write_booke_pid,
 1524:                  0x00000000);
 1525:     spr_register(env, SPR_BOOKE_TCR, "TCR",
 1526:                  SPR_NOACCESS, SPR_NOACCESS,
 1527:                  &spr_read_generic, &spr_write_booke_tcr,
 1528:                  0x00000000);
 1529:     spr_register(env, SPR_BOOKE_TSR, "TSR",
 1530:                  SPR_NOACCESS, SPR_NOACCESS,
 1531:                  &spr_read_generic, &spr_write_booke_tsr,
 1532:                  0x00000000);
 1533:     /* Timer */
 1534:     spr_register(env, SPR_DECR, "DECR",
 1535:                  SPR_NOACCESS, SPR_NOACCESS,
 1536:                  &spr_read_decr, &spr_write_decr,
 1537:                  0x00000000);
 1538:     spr_register(env, SPR_BOOKE_DECAR, "DECAR",
 1539:                  SPR_NOACCESS, SPR_NOACCESS,
 1540:                  SPR_NOACCESS, &spr_write_generic,
 1541:                  0x00000000);
 1542:     /* SPRGs */
 1543:     spr_register(env, SPR_USPRG0, "USPRG0",
 1544:                  &spr_read_generic, &spr_write_generic,
 1545:                  &spr_read_generic, &spr_write_generic,
 1546:                  0x00000000);
 1547:     spr_register(env, SPR_SPRG4, "SPRG4",
 1548:                  SPR_NOACCESS, SPR_NOACCESS,
 1549:                  &spr_read_generic, &spr_write_generic,
 1550:                  0x00000000);
 1551:     spr_register(env, SPR_SPRG5, "SPRG5",
 1552:                  SPR_NOACCESS, SPR_NOACCESS,
 1553:                  &spr_read_generic, &spr_write_generic,
 1554:                  0x00000000);
 1555:     spr_register(env, SPR_SPRG6, "SPRG6",
 1556:                  SPR_NOACCESS, SPR_NOACCESS,
 1557:                  &spr_read_generic, &spr_write_generic,
 1558:                  0x00000000);
 1559:     spr_register(env, SPR_SPRG7, "SPRG7",
 1560:                  SPR_NOACCESS, SPR_NOACCESS,
 1561:                  &spr_read_generic, &spr_write_generic,
 1562:                  0x00000000);
 1563: }
 1564: 
 1565: static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
 1566:                                    uint32_t maxsize, uint32_t flags,
 1567:                                    uint32_t nentries)
 1568: {
 1569:     return (assoc << TLBnCFG_ASSOC_SHIFT) |
 1570:            (minsize << TLBnCFG_MINSIZE_SHIFT) |
 1571:            (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
 1572:            flags | nentries;
 1573: }
 1574: 
 1575: /* BookE 2.06 storage control registers */
 1576: static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
 1577:                               uint32_t *tlbncfg)
 1578: {
 1579: #if !defined(CONFIG_USER_ONLY)
 1580:     const char *mas_names[8] = {
 1581:         "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
 1582:     };
 1583:     int mas_sprn[8] = {
 1584:         SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
 1585:         SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
 1586:     };
 1587:     int i;
 1588: 
 1589:     /* TLB assist registers */
 1590:     /* XXX : not implemented */
 1591:     for (i = 0; i < 8; i++) {
 1592:         if (mas_mask & (1 << i)) {
 1593:             spr_register(env, mas_sprn[i], mas_names[i],
 1594:                          SPR_NOACCESS, SPR_NOACCESS,
 1595:                          &spr_read_generic, &spr_write_generic,
 1596:                          0x00000000);
 1597:         }
 1598:     }
 1599:     if (env->nb_pids > 1) {
 1600:         /* XXX : not implemented */
 1601:         spr_register(env, SPR_BOOKE_PID1, "PID1",
 1602:                      SPR_NOACCESS, SPR_NOACCESS,
 1603:                      &spr_read_generic, &spr_write_booke_pid,
 1604:                      0x00000000);
 1605:     }
 1606:     if (env->nb_pids > 2) {
 1607:         /* XXX : not implemented */
 1608:         spr_register(env, SPR_BOOKE_PID2, "PID2",
 1609:                      SPR_NOACCESS, SPR_NOACCESS,
 1610:                      &spr_read_generic, &spr_write_booke_pid,
 1611:                      0x00000000);
 1612:     }
 1613:     /* XXX : not implemented */
 1614:     spr_register(env, SPR_MMUCFG, "MMUCFG",
 1615:                  SPR_NOACCESS, SPR_NOACCESS,
 1616:                  &spr_read_generic, SPR_NOACCESS,
 1617:                  0x00000000); /* TOFIX */
 1618:     switch (env->nb_ways) {
 1619:     case 4:
 1620:         spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
 1621:                      SPR_NOACCESS, SPR_NOACCESS,
 1622:                      &spr_read_generic, SPR_NOACCESS,
 1623:                      tlbncfg[3]);
 1624:         /* Fallthru */
 1625:     case 3:
 1626:         spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
 1627:                      SPR_NOACCESS, SPR_NOACCESS,
 1628:                      &spr_read_generic, SPR_NOACCESS,
 1629:                      tlbncfg[2]);
 1630:         /* Fallthru */
 1631:     case 2:
 1632:         spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
 1633:                      SPR_NOACCESS, SPR_NOACCESS,
 1634:                      &spr_read_generic, SPR_NOACCESS,
 1635:                      tlbncfg[1]);
 1636:         /* Fallthru */
 1637:     case 1:
 1638:         spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
 1639:                      SPR_NOACCESS, SPR_NOACCESS,
 1640:                      &spr_read_generic, SPR_NOACCESS,
 1641:                      tlbncfg[0]);
 1642:         /* Fallthru */
 1643:     case 0:
 1644:     default:
 1645:         break;
 1646:     }
 1647: #endif
 1648: 
 1649:     gen_spr_usprgh(env);
 1650: }
 1651: 
 1652: /* SPR specific to PowerPC 440 implementation */
 1653: static void gen_spr_440 (CPUPPCState *env)
 1654: {
 1655:     /* Cache control */
 1656:     /* XXX : not implemented */
 1657:     spr_register(env, SPR_440_DNV0, "DNV0",
 1658:                  SPR_NOACCESS, SPR_NOACCESS,
 1659:                  &spr_read_generic, &spr_write_generic,
 1660:                  0x00000000);
 1661:     /* XXX : not implemented */
 1662:     spr_register(env, SPR_440_DNV1, "DNV1",
 1663:                  SPR_NOACCESS, SPR_NOACCESS,
 1664:                  &spr_read_generic, &spr_write_generic,
 1665:                  0x00000000);
 1666:     /* XXX : not implemented */
 1667:     spr_register(env, SPR_440_DNV2, "DNV2",
 1668:                  SPR_NOACCESS, SPR_NOACCESS,
 1669:                  &spr_read_generic, &spr_write_generic,
 1670:                  0x00000000);
 1671:     /* XXX : not implemented */
 1672:     spr_register(env, SPR_440_DNV3, "DNV3",
 1673:                  SPR_NOACCESS, SPR_NOACCESS,
 1674:                  &spr_read_generic, &spr_write_generic,
 1675:                  0x00000000);
 1676:     /* XXX : not implemented */
 1677:     spr_register(env, SPR_440_DTV0, "DTV0",
 1678:                  SPR_NOACCESS, SPR_NOACCESS,
 1679:                  &spr_read_generic, &spr_write_generic,
 1680:                  0x00000000);
 1681:     /* XXX : not implemented */
 1682:     spr_register(env, SPR_440_DTV1, "DTV1",
 1683:                  SPR_NOACCESS, SPR_NOACCESS,
 1684:                  &spr_read_generic, &spr_write_generic,
 1685:                  0x00000000);
 1686:     /* XXX : not implemented */
 1687:     spr_register(env, SPR_440_DTV2, "DTV2",
 1688:                  SPR_NOACCESS, SPR_NOACCESS,
 1689:                  &spr_read_generic, &spr_write_generic,
 1690:                  0x00000000);
 1691:     /* XXX : not implemented */
 1692:     spr_register(env, SPR_440_DTV3, "DTV3",
 1693:                  SPR_NOACCESS, SPR_NOACCESS,
 1694:                  &spr_read_generic, &spr_write_generic,
 1695:                  0x00000000);
 1696:     /* XXX : not implemented */
 1697:     spr_register(env, SPR_440_DVLIM, "DVLIM",
 1698:                  SPR_NOACCESS, SPR_NOACCESS,
 1699:                  &spr_read_generic, &spr_write_generic,
 1700:                  0x00000000);
 1701:     /* XXX : not implemented */
 1702:     spr_register(env, SPR_440_INV0, "INV0",
 1703:                  SPR_NOACCESS, SPR_NOACCESS,
 1704:                  &spr_read_generic, &spr_write_generic,
 1705:                  0x00000000);
 1706:     /* XXX : not implemented */
 1707:     spr_register(env, SPR_440_INV1, "INV1",
 1708:                  SPR_NOACCESS, SPR_NOACCESS,
 1709:                  &spr_read_generic, &spr_write_generic,
 1710:                  0x00000000);
 1711:     /* XXX : not implemented */
 1712:     spr_register(env, SPR_440_INV2, "INV2",
 1713:                  SPR_NOACCESS, SPR_NOACCESS,
 1714:                  &spr_read_generic, &spr_write_generic,
 1715:                  0x00000000);
 1716:     /* XXX : not implemented */
 1717:     spr_register(env, SPR_440_INV3, "INV3",
 1718:                  SPR_NOACCESS, SPR_NOACCESS,
 1719:                  &spr_read_generic, &spr_write_generic,
 1720:                  0x00000000);
 1721:     /* XXX : not implemented */
 1722:     spr_register(env, SPR_440_ITV0, "ITV0",
 1723:                  SPR_NOACCESS, SPR_NOACCESS,
 1724:                  &spr_read_generic, &spr_write_generic,
 1725:                  0x00000000);
 1726:     /* XXX : not implemented */
 1727:     spr_register(env, SPR_440_ITV1, "ITV1",
 1728:                  SPR_NOACCESS, SPR_NOACCESS,
 1729:                  &spr_read_generic, &spr_write_generic,
 1730:                  0x00000000);
 1731:     /* XXX : not implemented */
 1732:     spr_register(env, SPR_440_ITV2, "ITV2",
 1733:                  SPR_NOACCESS, SPR_NOACCESS,
 1734:                  &spr_read_generic, &spr_write_generic,
 1735:                  0x00000000);
 1736:     /* XXX : not implemented */
 1737:     spr_register(env, SPR_440_ITV3, "ITV3",
 1738:                  SPR_NOACCESS, SPR_NOACCESS,
 1739:                  &spr_read_generic, &spr_write_generic,
 1740:                  0x00000000);
 1741:     /* XXX : not implemented */
 1742:     spr_register(env, SPR_440_IVLIM, "IVLIM",
 1743:                  SPR_NOACCESS, SPR_NOACCESS,
 1744:                  &spr_read_generic, &spr_write_generic,
 1745:                  0x00000000);
 1746:     /* Cache debug */
 1747:     /* XXX : not implemented */
 1748:     spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
 1749:                  SPR_NOACCESS, SPR_NOACCESS,
 1750:                  &spr_read_generic, SPR_NOACCESS,
 1751:                  0x00000000);
 1752:     /* XXX : not implemented */
 1753:     spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
 1754:                  SPR_NOACCESS, SPR_NOACCESS,
 1755:                  &spr_read_generic, SPR_NOACCESS,
 1756:                  0x00000000);
 1757:     /* XXX : not implemented */
 1758:     spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
 1759:                  SPR_NOACCESS, SPR_NOACCESS,
 1760:                  &spr_read_generic, SPR_NOACCESS,
 1761:                  0x00000000);
 1762:     /* XXX : not implemented */
 1763:     spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
 1764:                  SPR_NOACCESS, SPR_NOACCESS,
 1765:                  &spr_read_generic, SPR_NOACCESS,
 1766:                  0x00000000);
 1767:     /* XXX : not implemented */
 1768:     spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
 1769:                  SPR_NOACCESS, SPR_NOACCESS,
 1770:                  &spr_read_generic, SPR_NOACCESS,
 1771:                  0x00000000);
 1772:     /* XXX : not implemented */
 1773:     spr_register(env, SPR_440_DBDR, "DBDR",
 1774:                  SPR_NOACCESS, SPR_NOACCESS,
 1775:                  &spr_read_generic, &spr_write_generic,
 1776:                  0x00000000);
 1777:     /* Processor control */
 1778:     spr_register(env, SPR_4xx_CCR0, "CCR0",
 1779:                  SPR_NOACCESS, SPR_NOACCESS,
 1780:                  &spr_read_generic, &spr_write_generic,
 1781:                  0x00000000);
 1782:     spr_register(env, SPR_440_RSTCFG, "RSTCFG",
 1783:                  SPR_NOACCESS, SPR_NOACCESS,
 1784:                  &spr_read_generic, SPR_NOACCESS,
 1785:                  0x00000000);
 1786:     /* Storage control */
 1787:     spr_register(env, SPR_440_MMUCR, "MMUCR",
 1788:                  SPR_NOACCESS, SPR_NOACCESS,
 1789:                  &spr_read_generic, &spr_write_generic,
 1790:                  0x00000000);
 1791: }
 1792: 
 1793: /* SPR shared between PowerPC 40x implementations */
 1794: static void gen_spr_40x (CPUPPCState *env)
 1795: {
 1796:     /* Cache */
 1797:     /* not emulated, as Qemu do not emulate caches */
 1798:     spr_register(env, SPR_40x_DCCR, "DCCR",
 1799:                  SPR_NOACCESS, SPR_NOACCESS,
 1800:                  &spr_read_generic, &spr_write_generic,
 1801:                  0x00000000);
 1802:     /* not emulated, as Qemu do not emulate caches */
 1803:     spr_register(env, SPR_40x_ICCR, "ICCR",
 1804:                  SPR_NOACCESS, SPR_NOACCESS,
 1805:                  &spr_read_generic, &spr_write_generic,
 1806:                  0x00000000);
 1807:     /* not emulated, as Qemu do not emulate caches */
 1808:     spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
 1809:                  SPR_NOACCESS, SPR_NOACCESS,
 1810:                  &spr_read_generic, SPR_NOACCESS,
 1811:                  0x00000000);
 1812:     /* Exception */
 1813:     spr_register(env, SPR_40x_DEAR, "DEAR",
 1814:                  SPR_NOACCESS, SPR_NOACCESS,
 1815:                  &spr_read_generic, &spr_write_generic,
 1816:                  0x00000000);
 1817:     spr_register(env, SPR_40x_ESR, "ESR",
 1818:                  SPR_NOACCESS, SPR_NOACCESS,
 1819:                  &spr_read_generic, &spr_write_generic,
 1820:                  0x00000000);
 1821:     spr_register(env, SPR_40x_EVPR, "EVPR",
 1822:                  SPR_NOACCESS, SPR_NOACCESS,
 1823:                  &spr_read_generic, &spr_write_excp_prefix,
 1824:                  0x00000000);
 1825:     spr_register(env, SPR_40x_SRR2, "SRR2",
 1826:                  &spr_read_generic, &spr_write_generic,
 1827:                  &spr_read_generic, &spr_write_generic,
 1828:                  0x00000000);
 1829:     spr_register(env, SPR_40x_SRR3, "SRR3",
 1830:                  &spr_read_generic, &spr_write_generic,
 1831:                  &spr_read_generic, &spr_write_generic,
 1832:                  0x00000000);
 1833:     /* Timers */
 1834:     spr_register(env, SPR_40x_PIT, "PIT",
 1835:                  SPR_NOACCESS, SPR_NOACCESS,
 1836:                  &spr_read_40x_pit, &spr_write_40x_pit,
 1837:                  0x00000000);
 1838:     spr_register(env, SPR_40x_TCR, "TCR",
 1839:                  SPR_NOACCESS, SPR_NOACCESS,
 1840:                  &spr_read_generic, &spr_write_booke_tcr,
 1841:                  0x00000000);
 1842:     spr_register(env, SPR_40x_TSR, "TSR",
 1843:                  SPR_NOACCESS, SPR_NOACCESS,
 1844:                  &spr_read_generic, &spr_write_booke_tsr,
 1845:                  0x00000000);
 1846: }
 1847: 
 1848: /* SPR specific to PowerPC 405 implementation */
 1849: static void gen_spr_405 (CPUPPCState *env)
 1850: {
 1851:     /* MMU */
 1852:     spr_register(env, SPR_40x_PID, "PID",
 1853:                  SPR_NOACCESS, SPR_NOACCESS,
 1854:                  &spr_read_generic, &spr_write_generic,
 1855:                  0x00000000);
 1856:     spr_register(env, SPR_4xx_CCR0, "CCR0",
 1857:                  SPR_NOACCESS, SPR_NOACCESS,
 1858:                  &spr_read_generic, &spr_write_generic,
 1859:                  0x00700000);
 1860:     /* Debug interface */
 1861:     /* XXX : not implemented */
 1862:     spr_register(env, SPR_40x_DBCR0, "DBCR0",
 1863:                  SPR_NOACCESS, SPR_NOACCESS,
 1864:                  &spr_read_generic, &spr_write_40x_dbcr0,
 1865:                  0x00000000);
 1866:     /* XXX : not implemented */
 1867:     spr_register(env, SPR_405_DBCR1, "DBCR1",
 1868:                  SPR_NOACCESS, SPR_NOACCESS,
 1869:                  &spr_read_generic, &spr_write_generic,
 1870:                  0x00000000);
 1871:     /* XXX : not implemented */
 1872:     spr_register(env, SPR_40x_DBSR, "DBSR",
 1873:                  SPR_NOACCESS, SPR_NOACCESS,
 1874:                  &spr_read_generic, &spr_write_clear,
 1875:                  /* Last reset was system reset */
 1876:                  0x00000300);
 1877:     /* XXX : not implemented */
 1878:     spr_register(env, SPR_40x_DAC1, "DAC1",
 1879:                  SPR_NOACCESS, SPR_NOACCESS,
 1880:                  &spr_read_generic, &spr_write_generic,
 1881:                  0x00000000);
 1882:     spr_register(env, SPR_40x_DAC2, "DAC2",
 1883:                  SPR_NOACCESS, SPR_NOACCESS,
 1884:                  &spr_read_generic, &spr_write_generic,
 1885:                  0x00000000);
 1886:     /* XXX : not implemented */
 1887:     spr_register(env, SPR_405_DVC1, "DVC1",
 1888:                  SPR_NOACCESS, SPR_NOACCESS,
 1889:                  &spr_read_generic, &spr_write_generic,
 1890:                  0x00000000);
 1891:     /* XXX : not implemented */
 1892:     spr_register(env, SPR_405_DVC2, "DVC2",
 1893:                  SPR_NOACCESS, SPR_NOACCESS,
 1894:                  &spr_read_generic, &spr_write_generic,
 1895:                  0x00000000);
 1896:     /* XXX : not implemented */
 1897:     spr_register(env, SPR_40x_IAC1, "IAC1",
 1898:                  SPR_NOACCESS, SPR_NOACCESS,
 1899:                  &spr_read_generic, &spr_write_generic,
 1900:                  0x00000000);
 1901:     spr_register(env, SPR_40x_IAC2, "IAC2",
 1902:                  SPR_NOACCESS, SPR_NOACCESS,
 1903:                  &spr_read_generic, &spr_write_generic,
 1904:                  0x00000000);
 1905:     /* XXX : not implemented */
 1906:     spr_register(env, SPR_405_IAC3, "IAC3",
 1907:                  SPR_NOACCESS, SPR_NOACCESS,
 1908:                  &spr_read_generic, &spr_write_generic,
 1909:                  0x00000000);
 1910:     /* XXX : not implemented */
 1911:     spr_register(env, SPR_405_IAC4, "IAC4",
 1912:                  SPR_NOACCESS, SPR_NOACCESS,
 1913:                  &spr_read_generic, &spr_write_generic,
 1914:                  0x00000000);
 1915:     /* Storage control */
 1916:     /* XXX: TODO: not implemented */
 1917:     spr_register(env, SPR_405_SLER, "SLER",
 1918:                  SPR_NOACCESS, SPR_NOACCESS,
 1919:                  &spr_read_generic, &spr_write_40x_sler,
 1920:                  0x00000000);
 1921:     spr_register(env, SPR_40x_ZPR, "ZPR",
 1922:                  SPR_NOACCESS, SPR_NOACCESS,
 1923:                  &spr_read_generic, &spr_write_generic,
 1924:                  0x00000000);
 1925:     /* XXX : not implemented */
 1926:     spr_register(env, SPR_405_SU0R, "SU0R",
 1927:                  SPR_NOACCESS, SPR_NOACCESS,
 1928:                  &spr_read_generic, &spr_write_generic,
 1929:                  0x00000000);
 1930:     /* SPRG */
 1931:     spr_register(env, SPR_USPRG0, "USPRG0",
 1932:                  &spr_read_ureg, SPR_NOACCESS,
 1933:                  &spr_read_ureg, SPR_NOACCESS,
 1934:                  0x00000000);
 1935:     spr_register(env, SPR_SPRG4, "SPRG4",
 1936:                  SPR_NOACCESS, SPR_NOACCESS,
 1937:                  &spr_read_generic, &spr_write_generic,
 1938:                  0x00000000);
 1939:     spr_register(env, SPR_SPRG5, "SPRG5",
 1940:                  SPR_NOACCESS, SPR_NOACCESS,
 1941:                  spr_read_generic, &spr_write_generic,
 1942:                  0x00000000);
 1943:     spr_register(env, SPR_SPRG6, "SPRG6",
 1944:                  SPR_NOACCESS, SPR_NOACCESS,
 1945:                  spr_read_generic, &spr_write_generic,
 1946:                  0x00000000);
 1947:     spr_register(env, SPR_SPRG7, "SPRG7",
 1948:                  SPR_NOACCESS, SPR_NOACCESS,
 1949:                  spr_read_generic, &spr_write_generic,
 1950:                  0x00000000);
 1951:     gen_spr_usprgh(env);
 1952: }
 1953: 
 1954: /* SPR shared between PowerPC 401 & 403 implementations */
 1955: static void gen_spr_401_403 (CPUPPCState *env)
 1956: {
 1957:     /* Time base */
 1958:     spr_register(env, SPR_403_VTBL,  "TBL",
 1959:                  &spr_read_tbl, SPR_NOACCESS,
 1960:                  &spr_read_tbl, SPR_NOACCESS,
 1961:                  0x00000000);
 1962:     spr_register(env, SPR_403_TBL,   "TBL",
 1963:                  SPR_NOACCESS, SPR_NOACCESS,
 1964:                  SPR_NOACCESS, &spr_write_tbl,
 1965:                  0x00000000);
 1966:     spr_register(env, SPR_403_VTBU,  "TBU",
 1967:                  &spr_read_tbu, SPR_NOACCESS,
 1968:                  &spr_read_tbu, SPR_NOACCESS,
 1969:                  0x00000000);
 1970:     spr_register(env, SPR_403_TBU,   "TBU",
 1971:                  SPR_NOACCESS, SPR_NOACCESS,
 1972:                  SPR_NOACCESS, &spr_write_tbu,
 1973:                  0x00000000);
 1974:     /* Debug */
 1975:     /* not emulated, as Qemu do not emulate caches */
 1976:     spr_register(env, SPR_403_CDBCR, "CDBCR",
 1977:                  SPR_NOACCESS, SPR_NOACCESS,
 1978:                  &spr_read_generic, &spr_write_generic,
 1979:                  0x00000000);
 1980: }
 1981: 
 1982: /* SPR specific to PowerPC 401 implementation */
 1983: static void gen_spr_401 (CPUPPCState *env)
 1984: {
 1985:     /* Debug interface */
 1986:     /* XXX : not implemented */
 1987:     spr_register(env, SPR_40x_DBCR0, "DBCR",
 1988:                  SPR_NOACCESS, SPR_NOACCESS,
 1989:                  &spr_read_generic, &spr_write_40x_dbcr0,
 1990:                  0x00000000);
 1991:     /* XXX : not implemented */
 1992:     spr_register(env, SPR_40x_DBSR, "DBSR",
 1993:                  SPR_NOACCESS, SPR_NOACCESS,
 1994:                  &spr_read_generic, &spr_write_clear,
 1995:                  /* Last reset was system reset */
 1996:                  0x00000300);
 1997:     /* XXX : not implemented */
 1998:     spr_register(env, SPR_40x_DAC1, "DAC",
 1999:                  SPR_NOACCESS, SPR_NOACCESS,
 2000:                  &spr_read_generic, &spr_write_generic,
 2001:                  0x00000000);
 2002:     /* XXX : not implemented */
 2003:     spr_register(env, SPR_40x_IAC1, "IAC",
 2004:                  SPR_NOACCESS, SPR_NOACCESS,
 2005:                  &spr_read_generic, &spr_write_generic,
 2006:                  0x00000000);
 2007:     /* Storage control */
 2008:     /* XXX: TODO: not implemented */
 2009:     spr_register(env, SPR_405_SLER, "SLER",
 2010:                  SPR_NOACCESS, SPR_NOACCESS,
 2011:                  &spr_read_generic, &spr_write_40x_sler,
 2012:                  0x00000000);
 2013:     /* not emulated, as Qemu never does speculative access */
 2014:     spr_register(env, SPR_40x_SGR, "SGR",
 2015:                  SPR_NOACCESS, SPR_NOACCESS,
 2016:                  &spr_read_generic, &spr_write_generic,
 2017:                  0xFFFFFFFF);
 2018:     /* not emulated, as Qemu do not emulate caches */
 2019:     spr_register(env, SPR_40x_DCWR, "DCWR",
 2020:                  SPR_NOACCESS, SPR_NOACCESS,
 2021:                  &spr_read_generic, &spr_write_generic,
 2022:                  0x00000000);
 2023: }
 2024: 
 2025: static void gen_spr_401x2 (CPUPPCState *env)
 2026: {
 2027:     gen_spr_401(env);
 2028:     spr_register(env, SPR_40x_PID, "PID",
 2029:                  SPR_NOACCESS, SPR_NOACCESS,
 2030:                  &spr_read_generic, &spr_write_generic,
 2031:                  0x00000000);
 2032:     spr_register(env, SPR_40x_ZPR, "ZPR",
 2033:                  SPR_NOACCESS, SPR_NOACCESS,
 2034:                  &spr_read_generic, &spr_write_generic,
 2035:                  0x00000000);
 2036: }
 2037: 
 2038: /* SPR specific to PowerPC 403 implementation */
 2039: static void gen_spr_403 (CPUPPCState *env)
 2040: {
 2041:     /* Debug interface */
 2042:     /* XXX : not implemented */
 2043:     spr_register(env, SPR_40x_DBCR0, "DBCR0",
 2044:                  SPR_NOACCESS, SPR_NOACCESS,
 2045:                  &spr_read_generic, &spr_write_40x_dbcr0,
 2046:                  0x00000000);
 2047:     /* XXX : not implemented */
 2048:     spr_register(env, SPR_40x_DBSR, "DBSR",
 2049:                  SPR_NOACCESS, SPR_NOACCESS,
 2050:                  &spr_read_generic, &spr_write_clear,
 2051:                  /* Last reset was system reset */
 2052:                  0x00000300);
 2053:     /* XXX : not implemented */
 2054:     spr_register(env, SPR_40x_DAC1, "DAC1",
 2055:                  SPR_NOACCESS, SPR_NOACCESS,
 2056:                  &spr_read_generic, &spr_write_generic,
 2057:                  0x00000000);
 2058:     /* XXX : not implemented */
 2059:     spr_register(env, SPR_40x_DAC2, "DAC2",
 2060:                  SPR_NOACCESS, SPR_NOACCESS,
 2061:                  &spr_read_generic, &spr_write_generic,
 2062:                  0x00000000);
 2063:     /* XXX : not implemented */
 2064:     spr_register(env, SPR_40x_IAC1, "IAC1",
 2065:                  SPR_NOACCESS, SPR_NOACCESS,
 2066:                  &spr_read_generic, &spr_write_generic,
 2067:                  0x00000000);
 2068:     /* XXX : not implemented */
 2069:     spr_register(env, SPR_40x_IAC2, "IAC2",
 2070:                  SPR_NOACCESS, SPR_NOACCESS,
 2071:                  &spr_read_generic, &spr_write_generic,
 2072:                  0x00000000);
 2073: }
 2074: 
 2075: static void gen_spr_403_real (CPUPPCState *env)
 2076: {
 2077:     spr_register(env, SPR_403_PBL1,  "PBL1",
 2078:                  SPR_NOACCESS, SPR_NOACCESS,
 2079:                  &spr_read_403_pbr, &spr_write_403_pbr,
 2080:                  0x00000000);
 2081:     spr_register(env, SPR_403_PBU1,  "PBU1",
 2082:                  SPR_NOACCESS, SPR_NOACCESS,
 2083:                  &spr_read_403_pbr, &spr_write_403_pbr,
 2084:                  0x00000000);
 2085:     spr_register(env, SPR_403_PBL2,  "PBL2",
 2086:                  SPR_NOACCESS, SPR_NOACCESS,
 2087:                  &spr_read_403_pbr, &spr_write_403_pbr,
 2088:                  0x00000000);
 2089:     spr_register(env, SPR_403_PBU2,  "PBU2",
 2090:                  SPR_NOACCESS, SPR_NOACCESS,
 2091:                  &spr_read_403_pbr, &spr_write_403_pbr,
 2092:                  0x00000000);
 2093: }
 2094: 
 2095: static void gen_spr_403_mmu (CPUPPCState *env)
 2096: {
 2097:     /* MMU */
 2098:     spr_register(env, SPR_40x_PID, "PID",
 2099:                  SPR_NOACCESS, SPR_NOACCESS,
 2100:                  &spr_read_generic, &spr_write_generic,
 2101:                  0x00000000);
 2102:     spr_register(env, SPR_40x_ZPR, "ZPR",
 2103:                  SPR_NOACCESS, SPR_NOACCESS,
 2104:                  &spr_read_generic, &spr_write_generic,
 2105:                  0x00000000);
 2106: }
 2107: 
 2108: /* SPR specific to PowerPC compression coprocessor extension */
 2109: static void gen_spr_compress (CPUPPCState *env)
 2110: {
 2111:     /* XXX : not implemented */
 2112:     spr_register(env, SPR_401_SKR, "SKR",
 2113:                  SPR_NOACCESS, SPR_NOACCESS,
 2114:                  &spr_read_generic, &spr_write_generic,
 2115:                  0x00000000);
 2116: }
 2117: 
 2118: #if defined (TARGET_PPC64)
 2119: /* SPR specific to PowerPC 620 */
 2120: static void gen_spr_620 (CPUPPCState *env)
 2121: {
 2122:     /* Processor identification */
 2123:     spr_register(env, SPR_PIR, "PIR",
 2124:                  SPR_NOACCESS, SPR_NOACCESS,
 2125:                  &spr_read_generic, &spr_write_pir,
 2126:                  0x00000000);
 2127:     spr_register(env, SPR_ASR, "ASR",
 2128:                  SPR_NOACCESS, SPR_NOACCESS,
 2129:                  &spr_read_asr, &spr_write_asr,
 2130:                  0x00000000);
 2131:     /* Breakpoints */
 2132:     /* XXX : not implemented */
 2133:     spr_register(env, SPR_IABR, "IABR",
 2134:                  SPR_NOACCESS, SPR_NOACCESS,
 2135:                  &spr_read_generic, &spr_write_generic,
 2136:                  0x00000000);
 2137:     /* XXX : not implemented */
 2138:     spr_register(env, SPR_DABR, "DABR",
 2139:                  SPR_NOACCESS, SPR_NOACCESS,
 2140:                  &spr_read_generic, &spr_write_generic,
 2141:                  0x00000000);
 2142:     /* XXX : not implemented */
 2143:     spr_register(env, SPR_SIAR, "SIAR",
 2144:                  SPR_NOACCESS, SPR_NOACCESS,
 2145:                  &spr_read_generic, SPR_NOACCESS,
 2146:                  0x00000000);
 2147:     /* XXX : not implemented */
 2148:     spr_register(env, SPR_SDA, "SDA",
 2149:                  SPR_NOACCESS, SPR_NOACCESS,
 2150:                  &spr_read_generic, SPR_NOACCESS,
 2151:                  0x00000000);
 2152:     /* XXX : not implemented */
 2153:     spr_register(env, SPR_620_PMC1R, "PMC1",
 2154:                  SPR_NOACCESS, SPR_NOACCESS,
 2155:                  &spr_read_generic, SPR_NOACCESS,
 2156:                  0x00000000);
 2157:     spr_register(env, SPR_620_PMC1W, "PMC1",
 2158:                  SPR_NOACCESS, SPR_NOACCESS,
 2159:                   SPR_NOACCESS, &spr_write_generic,
 2160:                  0x00000000);
 2161:     /* XXX : not implemented */
 2162:     spr_register(env, SPR_620_PMC2R, "PMC2",
 2163:                  SPR_NOACCESS, SPR_NOACCESS,
 2164:                  &spr_read_generic, SPR_NOACCESS,
 2165:                  0x00000000);
 2166:     spr_register(env, SPR_620_PMC2W, "PMC2",
 2167:                  SPR_NOACCESS, SPR_NOACCESS,
 2168:                   SPR_NOACCESS, &spr_write_generic,
 2169:                  0x00000000);
 2170:     /* XXX : not implemented */
 2171:     spr_register(env, SPR_620_MMCR0R, "MMCR0",
 2172:                  SPR_NOACCESS, SPR_NOACCESS,
 2173:                  &spr_read_generic, SPR_NOACCESS,
 2174:                  0x00000000);
 2175:     spr_register(env, SPR_620_MMCR0W, "MMCR0",
 2176:                  SPR_NOACCESS, SPR_NOACCESS,
 2177:                   SPR_NOACCESS, &spr_write_generic,
 2178:                  0x00000000);
 2179:     /* External access control */
 2180:     /* XXX : not implemented */
 2181:     spr_register(env, SPR_EAR, "EAR",
 2182:                  SPR_NOACCESS, SPR_NOACCESS,
 2183:                  &spr_read_generic, &spr_write_generic,
 2184:                  0x00000000);
 2185: #if 0 // XXX: check this
 2186:     /* XXX : not implemented */
 2187:     spr_register(env, SPR_620_PMR0, "PMR0",
 2188:                  SPR_NOACCESS, SPR_NOACCESS,
 2189:                  &spr_read_generic, &spr_write_generic,
 2190:                  0x00000000);
 2191:     /* XXX : not implemented */
 2192:     spr_register(env, SPR_620_PMR1, "PMR1",
 2193:                  SPR_NOACCESS, SPR_NOACCESS,
 2194:                  &spr_read_generic, &spr_write_generic,
 2195:                  0x00000000);
 2196:     /* XXX : not implemented */
 2197:     spr_register(env, SPR_620_PMR2, "PMR2",
 2198:                  SPR_NOACCESS, SPR_NOACCESS,
 2199:                  &spr_read_generic, &spr_write_generic,
 2200:                  0x00000000);
 2201:     /* XXX : not implemented */
 2202:     spr_register(env, SPR_620_PMR3, "PMR3",
 2203:                  SPR_NOACCESS, SPR_NOACCESS,
 2204:                  &spr_read_generic, &spr_write_generic,
 2205:                  0x00000000);
 2206:     /* XXX : not implemented */
 2207:     spr_register(env, SPR_620_PMR4, "PMR4",
 2208:                  SPR_NOACCESS, SPR_NOACCESS,
 2209:                  &spr_read_generic, &spr_write_generic,
 2210:                  0x00000000);
 2211:     /* XXX : not implemented */
 2212:     spr_register(env, SPR_620_PMR5, "PMR5",
 2213:                  SPR_NOACCESS, SPR_NOACCESS,
 2214:                  &spr_read_generic, &spr_write_generic,
 2215:                  0x00000000);
 2216:     /* XXX : not implemented */
 2217:     spr_register(env, SPR_620_PMR6, "PMR6",
 2218:                  SPR_NOACCESS, SPR_NOACCESS,
 2219:                  &spr_read_generic, &spr_write_generic,
 2220:                  0x00000000);
 2221:     /* XXX : not implemented */
 2222:     spr_register(env, SPR_620_PMR7, "PMR7",
 2223:                  SPR_NOACCESS, SPR_NOACCESS,
 2224:                  &spr_read_generic, &spr_write_generic,
 2225:                  0x00000000);
 2226:     /* XXX : not implemented */
 2227:     spr_register(env, SPR_620_PMR8, "PMR8",
 2228:                  SPR_NOACCESS, SPR_NOACCESS,
 2229:                  &spr_read_generic, &spr_write_generic,
 2230:                  0x00000000);
 2231:     /* XXX : not implemented */
 2232:     spr_register(env, SPR_620_PMR9, "PMR9",
 2233:                  SPR_NOACCESS, SPR_NOACCESS,
 2234:                  &spr_read_generic, &spr_write_generic,
 2235:                  0x00000000);
 2236:     /* XXX : not implemented */
 2237:     spr_register(env, SPR_620_PMRA, "PMR10",
 2238:                  SPR_NOACCESS, SPR_NOACCESS,
 2239:                  &spr_read_generic, &spr_write_generic,
 2240:                  0x00000000);
 2241:     /* XXX : not implemented */
 2242:     spr_register(env, SPR_620_PMRB, "PMR11",
 2243:                  SPR_NOACCESS, SPR_NOACCESS,
 2244:                  &spr_read_generic, &spr_write_generic,
 2245:                  0x00000000);
 2246:     /* XXX : not implemented */
 2247:     spr_register(env, SPR_620_PMRC, "PMR12",
 2248:                  SPR_NOACCESS, SPR_NOACCESS,
 2249:                  &spr_read_generic, &spr_write_generic,
 2250:                  0x00000000);
 2251:     /* XXX : not implemented */
 2252:     spr_register(env, SPR_620_PMRD, "PMR13",
 2253:                  SPR_NOACCESS, SPR_NOACCESS,
 2254:                  &spr_read_generic, &spr_write_generic,
 2255:                  0x00000000);
 2256:     /* XXX : not implemented */
 2257:     spr_register(env, SPR_620_PMRE, "PMR14",
 2258:                  SPR_NOACCESS, SPR_NOACCESS,
 2259:                  &spr_read_generic, &spr_write_generic,
 2260:                  0x00000000);
 2261:     /* XXX : not implemented */
 2262:     spr_register(env, SPR_620_PMRF, "PMR15",
 2263:                  SPR_NOACCESS, SPR_NOACCESS,
 2264:                  &spr_read_generic, &spr_write_generic,
 2265:                  0x00000000);
 2266: #endif
 2267:     /* XXX : not implemented */
 2268:     spr_register(env, SPR_620_BUSCSR, "BUSCSR",
 2269:                  SPR_NOACCESS, SPR_NOACCESS,
 2270:                  &spr_read_generic, &spr_write_generic,
 2271:                  0x00000000);
 2272:     /* XXX : not implemented */
 2273:     spr_register(env, SPR_620_L2CR, "L2CR",
 2274:                  SPR_NOACCESS, SPR_NOACCESS,
 2275:                  &spr_read_generic, &spr_write_generic,
 2276:                  0x00000000);
 2277:     /* XXX : not implemented */
 2278:     spr_register(env, SPR_620_L2SR, "L2SR",
 2279:                  SPR_NOACCESS, SPR_NOACCESS,
 2280:                  &spr_read_generic, &spr_write_generic,
 2281:                  0x00000000);
 2282: }
 2283: #endif /* defined (TARGET_PPC64) */
 2284: 
 2285: static void gen_spr_5xx_8xx (CPUPPCState *env)
 2286: {
 2287:     /* Exception processing */
 2288:     spr_register(env, SPR_DSISR, "DSISR",
 2289:                  SPR_NOACCESS, SPR_NOACCESS,
 2290:                  &spr_read_generic, &spr_write_generic,
 2291:                  0x00000000);
 2292:     spr_register(env, SPR_DAR, "DAR",
 2293:                  SPR_NOACCESS, SPR_NOACCESS,
 2294:                  &spr_read_generic, &spr_write_generic,
 2295:                  0x00000000);
 2296:     /* Timer */
 2297:     spr_register(env, SPR_DECR, "DECR",
 2298:                  SPR_NOACCESS, SPR_NOACCESS,
 2299:                  &spr_read_decr, &spr_write_decr,
 2300:                  0x00000000);
 2301:     /* XXX : not implemented */
 2302:     spr_register(env, SPR_MPC_EIE, "EIE",
 2303:                  SPR_NOACCESS, SPR_NOACCESS,
 2304:                  &spr_read_generic, &spr_write_generic,
 2305:                  0x00000000);
 2306:     /* XXX : not implemented */
 2307:     spr_register(env, SPR_MPC_EID, "EID",
 2308:                  SPR_NOACCESS, SPR_NOACCESS,
 2309:                  &spr_read_generic, &spr_write_generic,
 2310:                  0x00000000);
 2311:     /* XXX : not implemented */
 2312:     spr_register(env, SPR_MPC_NRI, "NRI",
 2313:                  SPR_NOACCESS, SPR_NOACCESS,
 2314:                  &spr_read_generic, &spr_write_generic,
 2315:                  0x00000000);
 2316:     /* XXX : not implemented */
 2317:     spr_register(env, SPR_MPC_CMPA, "CMPA",
 2318:                  SPR_NOACCESS, SPR_NOACCESS,
 2319:                  &spr_read_generic, &spr_write_generic,
 2320:                  0x00000000);
 2321:     /* XXX : not implemented */
 2322:     spr_register(env, SPR_MPC_CMPB, "CMPB",
 2323:                  SPR_NOACCESS, SPR_NOACCESS,
 2324:                  &spr_read_generic, &spr_write_generic,
 2325:                  0x00000000);
 2326:     /* XXX : not implemented */
 2327:     spr_register(env, SPR_MPC_CMPC, "CMPC",
 2328:                  SPR_NOACCESS, SPR_NOACCESS,
 2329:                  &spr_read_generic, &spr_write_generic,
 2330:                  0x00000000);
 2331:     /* XXX : not implemented */
 2332:     spr_register(env, SPR_MPC_CMPD, "CMPD",
 2333:                  SPR_NOACCESS, SPR_NOACCESS,
 2334:                  &spr_read_generic, &spr_write_generic,
 2335:                  0x00000000);
 2336:     /* XXX : not implemented */
 2337:     spr_register(env, SPR_MPC_ECR, "ECR",
 2338:                  SPR_NOACCESS, SPR_NOACCESS,
 2339:                  &spr_read_generic, &spr_write_generic,
 2340:                  0x00000000);
 2341:     /* XXX : not implemented */
 2342:     spr_register(env, SPR_MPC_DER, "DER",
 2343:                  SPR_NOACCESS, SPR_NOACCESS,
 2344:                  &spr_read_generic, &spr_write_generic,
 2345:                  0x00000000);
 2346:     /* XXX : not implemented */
 2347:     spr_register(env, SPR_MPC_COUNTA, "COUNTA",
 2348:                  SPR_NOACCESS, SPR_NOACCESS,
 2349:                  &spr_read_generic, &spr_write_generic,
 2350:                  0x00000000);
 2351:     /* XXX : not implemented */
 2352:     spr_register(env, SPR_MPC_COUNTB, "COUNTB",
 2353:                  SPR_NOACCESS, SPR_NOACCESS,
 2354:                  &spr_read_generic, &spr_write_generic,
 2355:                  0x00000000);
 2356:     /* XXX : not implemented */
 2357:     spr_register(env, SPR_MPC_CMPE, "CMPE",
 2358:                  SPR_NOACCESS, SPR_NOACCESS,
 2359:                  &spr_read_generic, &spr_write_generic,
 2360:                  0x00000000);
 2361:     /* XXX : not implemented */
 2362:     spr_register(env, SPR_MPC_CMPF, "CMPF",
 2363:                  SPR_NOACCESS, SPR_NOACCESS,
 2364:                  &spr_read_generic, &spr_write_generic,
 2365:                  0x00000000);
 2366:     /* XXX : not implemented */
 2367:     spr_register(env, SPR_MPC_CMPG, "CMPG",
 2368:                  SPR_NOACCESS, SPR_NOACCESS,
 2369:                  &spr_read_generic, &spr_write_generic,
 2370:                  0x00000000);
 2371:     /* XXX : not implemented */
 2372:     spr_register(env, SPR_MPC_CMPH, "CMPH",
 2373:                  SPR_NOACCESS, SPR_NOACCESS,
 2374:                  &spr_read_generic, &spr_write_generic,
 2375:                  0x00000000);
 2376:     /* XXX : not implemented */
 2377:     spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
 2378:                  SPR_NOACCESS, SPR_NOACCESS,
 2379:                  &spr_read_generic, &spr_write_generic,
 2380:                  0x00000000);
 2381:     /* XXX : not implemented */
 2382:     spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
 2383:                  SPR_NOACCESS, SPR_NOACCESS,
 2384:                  &spr_read_generic, &spr_write_generic,
 2385:                  0x00000000);
 2386:     /* XXX : not implemented */
 2387:     spr_register(env, SPR_MPC_BAR, "BAR",
 2388:                  SPR_NOACCESS, SPR_NOACCESS,
 2389:                  &spr_read_generic, &spr_write_generic,
 2390:                  0x00000000);
 2391:     /* XXX : not implemented */
 2392:     spr_register(env, SPR_MPC_DPDR, "DPDR",
 2393:                  SPR_NOACCESS, SPR_NOACCESS,
 2394:                  &spr_read_generic, &spr_write_generic,
 2395:                  0x00000000);
 2396:     /* XXX : not implemented */
 2397:     spr_register(env, SPR_MPC_IMMR, "IMMR",
 2398:                  SPR_NOACCESS, SPR_NOACCESS,
 2399:                  &spr_read_generic, &spr_write_generic,
 2400:                  0x00000000);
 2401: }
 2402: 
 2403: static void gen_spr_5xx (CPUPPCState *env)
 2404: {
 2405:     /* XXX : not implemented */
 2406:     spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
 2407:                  SPR_NOACCESS, SPR_NOACCESS,
 2408:                  &spr_read_generic, &spr_write_generic,
 2409:                  0x00000000);
 2410:     /* XXX : not implemented */
 2411:     spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
 2412:                  SPR_NOACCESS, SPR_NOACCESS,
 2413:                  &spr_read_generic, &spr_write_generic,
 2414:                  0x00000000);
 2415:     /* XXX : not implemented */
 2416:     spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
 2417:                  SPR_NOACCESS, SPR_NOACCESS,
 2418:                  &spr_read_generic, &spr_write_generic,
 2419:                  0x00000000);
 2420:     /* XXX : not implemented */
 2421:     spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
 2422:                  SPR_NOACCESS, SPR_NOACCESS,
 2423:                  &spr_read_generic, &spr_write_generic,
 2424:                  0x00000000);
 2425:     /* XXX : not implemented */
 2426:     spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
 2427:                  SPR_NOACCESS, SPR_NOACCESS,
 2428:                  &spr_read_generic, &spr_write_generic,
 2429:                  0x00000000);
 2430:     /* XXX : not implemented */
 2431:     spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
 2432:                  SPR_NOACCESS, SPR_NOACCESS,
 2433:                  &spr_read_generic, &spr_write_generic,
 2434:                  0x00000000);
 2435:     /* XXX : not implemented */
 2436:     spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
 2437:                  SPR_NOACCESS, SPR_NOACCESS,
 2438:                  &spr_read_generic, &spr_write_generic,
 2439:                  0x00000000);
 2440:     /* XXX : not implemented */
 2441:     spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
 2442:                  SPR_NOACCESS, SPR_NOACCESS,
 2443:                  &spr_read_generic, &spr_write_generic,
 2444:                  0x00000000);
 2445:     /* XXX : not implemented */
 2446:     spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
 2447:                  SPR_NOACCESS, SPR_NOACCESS,
 2448:                  &spr_read_generic, &spr_write_generic,
 2449:                  0x00000000);
 2450:     /* XXX : not implemented */
 2451:     spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
 2452:                  SPR_NOACCESS, SPR_NOACCESS,
 2453:                  &spr_read_generic, &spr_write_generic,
 2454:                  0x00000000);
 2455:     /* XXX : not implemented */
 2456:     spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
 2457:                  SPR_NOACCESS, SPR_NOACCESS,
 2458:                  &spr_read_generic, &spr_write_generic,
 2459:                  0x00000000);
 2460:     /* XXX : not implemented */
 2461:     spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
 2462:                  SPR_NOACCESS, SPR_NOACCESS,
 2463:                  &spr_read_generic, &spr_write_generic,
 2464:                  0x00000000);
 2465:     /* XXX : not implemented */
 2466:     spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
 2467:                  SPR_NOACCESS, SPR_NOACCESS,
 2468:                  &spr_read_generic, &spr_write_generic,
 2469:                  0x00000000);
 2470:     /* XXX : not implemented */
 2471:     spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
 2472:                  SPR_NOACCESS, SPR_NOACCESS,
 2473:                  &spr_read_generic, &spr_write_generic,
 2474:                  0x00000000);
 2475:     /* XXX : not implemented */
 2476:     spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
 2477:                  SPR_NOACCESS, SPR_NOACCESS,
 2478:                  &spr_read_generic, &spr_write_generic,
 2479:                  0x00000000);
 2480:     /* XXX : not implemented */
 2481:     spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
 2482:                  SPR_NOACCESS, SPR_NOACCESS,
 2483:                  &spr_read_generic, &spr_write_generic,
 2484:                  0x00000000);
 2485:     /* XXX : not implemented */
 2486:     spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
 2487:                  SPR_NOACCESS, SPR_NOACCESS,
 2488:                  &spr_read_generic, &spr_write_generic,
 2489:                  0x00000000);
 2490:     /* XXX : not implemented */
 2491:     spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
 2492:                  SPR_NOACCESS, SPR_NOACCESS,
 2493:                  &spr_read_generic, &spr_write_generic,
 2494:                  0x00000000);
 2495:     /* XXX : not implemented */
 2496:     spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
 2497:                  SPR_NOACCESS, SPR_NOACCESS,
 2498:                  &spr_read_generic, &spr_write_generic,
 2499:                  0x00000000);
 2500:     /* XXX : not implemented */
 2501:     spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
 2502:                  SPR_NOACCESS, SPR_NOACCESS,
 2503:                  &spr_read_generic, &spr_write_generic,
 2504:                  0x00000000);
 2505:     /* XXX : not implemented */
 2506:     spr_register(env, SPR_RCPU_FPECR, "FPECR",
 2507:                  SPR_NOACCESS, SPR_NOACCESS,
 2508:                  &spr_read_generic, &spr_write_generic,
 2509:                  0x00000000);
 2510: }
 2511: 
 2512: static void gen_spr_8xx (CPUPPCState *env)
 2513: {
 2514:     /* XXX : not implemented */
 2515:     spr_register(env, SPR_MPC_IC_CST, "IC_CST",
 2516:                  SPR_NOACCESS, SPR_NOACCESS,
 2517:                  &spr_read_generic, &spr_write_generic,
 2518:                  0x00000000);
 2519:     /* XXX : not implemented */
 2520:     spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
 2521:                  SPR_NOACCESS, SPR_NOACCESS,
 2522:                  &spr_read_generic, &spr_write_generic,
 2523:                  0x00000000);
 2524:     /* XXX : not implemented */
 2525:     spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
 2526:                  SPR_NOACCESS, SPR_NOACCESS,
 2527:                  &spr_read_generic, &spr_write_generic,
 2528:                  0x00000000);
 2529:     /* XXX : not implemented */
 2530:     spr_register(env, SPR_MPC_DC_CST, "DC_CST",
 2531:                  SPR_NOACCESS, SPR_NOACCESS,
 2532:                  &spr_read_generic, &spr_write_generic,
 2533:                  0x00000000);
 2534:     /* XXX : not implemented */
 2535:     spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
 2536:                  SPR_NOACCESS, SPR_NOACCESS,
 2537:                  &spr_read_generic, &spr_write_generic,
 2538:                  0x00000000);
 2539:     /* XXX : not implemented */
 2540:     spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
 2541:                  SPR_NOACCESS, SPR_NOACCESS,
 2542:                  &spr_read_generic, &spr_write_generic,
 2543:                  0x00000000);
 2544:     /* XXX : not implemented */
 2545:     spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
 2546:                  SPR_NOACCESS, SPR_NOACCESS,
 2547:                  &spr_read_generic, &spr_write_generic,
 2548:                  0x00000000);
 2549:     /* XXX : not implemented */
 2550:     spr_register(env, SPR_MPC_MI_AP, "MI_AP",
 2551:                  SPR_NOACCESS, SPR_NOACCESS,
 2552:                  &spr_read_generic, &spr_write_generic,
 2553:                  0x00000000);
 2554:     /* XXX : not implemented */
 2555:     spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
 2556:                  SPR_NOACCESS, SPR_NOACCESS,
 2557:                  &spr_read_generic, &spr_write_generic,
 2558:                  0x00000000);
 2559:     /* XXX : not implemented */
 2560:     spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
 2561:                  SPR_NOACCESS, SPR_NOACCESS,
 2562:                  &spr_read_generic, &spr_write_generic,
 2563:                  0x00000000);
 2564:     /* XXX : not implemented */
 2565:     spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
 2566:                  SPR_NOACCESS, SPR_NOACCESS,
 2567:                  &spr_read_generic, &spr_write_generic,
 2568:                  0x00000000);
 2569:     /* XXX : not implemented */
 2570:     spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
 2571:                  SPR_NOACCESS, SPR_NOACCESS,
 2572:                  &spr_read_generic, &spr_write_generic,
 2573:                  0x00000000);
 2574:     /* XXX : not implemented */
 2575:     spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
 2576:                  SPR_NOACCESS, SPR_NOACCESS,
 2577:                  &spr_read_generic, &spr_write_generic,
 2578:                  0x00000000);
 2579:     /* XXX : not implemented */
 2580:     spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
 2581:                  SPR_NOACCESS, SPR_NOACCESS,
 2582:                  &spr_read_generic, &spr_write_generic,
 2583:                  0x00000000);
 2584:     /* XXX : not implemented */
 2585:     spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
 2586:                  SPR_NOACCESS, SPR_NOACCESS,
 2587:                  &spr_read_generic, &spr_write_generic,
 2588:                  0x00000000);
 2589:     /* XXX : not implemented */
 2590:     spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
 2591:                  SPR_NOACCESS, SPR_NOACCESS,
 2592:                  &spr_read_generic, &spr_write_generic,
 2593:                  0x00000000);
 2594:     /* XXX : not implemented */
 2595:     spr_register(env, SPR_MPC_MD_AP, "MD_AP",
 2596:                  SPR_NOACCESS, SPR_NOACCESS,
 2597:                  &spr_read_generic, &spr_write_generic,
 2598:                  0x00000000);
 2599:     /* XXX : not implemented */
 2600:     spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
 2601:                  SPR_NOACCESS, SPR_NOACCESS,
 2602:                  &spr_read_generic, &spr_write_generic,
 2603:                  0x00000000);
 2604:     /* XXX : not implemented */
 2605:     spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
 2606:                  SPR_NOACCESS, SPR_NOACCESS,
 2607:                  &spr_read_generic, &spr_write_generic,
 2608:                  0x00000000);
 2609:     /* XXX : not implemented */
 2610:     spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
 2611:                  SPR_NOACCESS, SPR_NOACCESS,
 2612:                  &spr_read_generic, &spr_write_generic,
 2613:                  0x00000000);
 2614:     /* XXX : not implemented */
 2615:     spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
 2616:                  SPR_NOACCESS, SPR_NOACCESS,
 2617:                  &spr_read_generic, &spr_write_generic,
 2618:                  0x00000000);
 2619:     /* XXX : not implemented */
 2620:     spr_register(env, SPR_MPC_MD_TW, "MD_TW",
 2621:                  SPR_NOACCESS, SPR_NOACCESS,
 2622:                  &spr_read_generic, &spr_write_generic,
 2623:                  0x00000000);
 2624:     /* XXX : not implemented */
 2625:     spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
 2626:                  SPR_NOACCESS, SPR_NOACCESS,
 2627:                  &spr_read_generic, &spr_write_generic,
 2628:                  0x00000000);
 2629:     /* XXX : not implemented */
 2630:     spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
 2631:                  SPR_NOACCESS, SPR_NOACCESS,
 2632:                  &spr_read_generic, &spr_write_generic,
 2633:                  0x00000000);
 2634:     /* XXX : not implemented */
 2635:     spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
 2636:                  SPR_NOACCESS, SPR_NOACCESS,
 2637:                  &spr_read_generic, &spr_write_generic,
 2638:                  0x00000000);
 2639: }
 2640: 
 2641: // XXX: TODO
 2642: /*
 2643:  * AMR     => SPR 29 (Power 2.04)
 2644:  * CTRL    => SPR 136 (Power 2.04)
 2645:  * CTRL    => SPR 152 (Power 2.04)
 2646:  * SCOMC   => SPR 276 (64 bits ?)
 2647:  * SCOMD   => SPR 277 (64 bits ?)
 2648:  * TBU40   => SPR 286 (Power 2.04 hypv)
 2649:  * HSPRG0  => SPR 304 (Power 2.04 hypv)
 2650:  * HSPRG1  => SPR 305 (Power 2.04 hypv)
 2651:  * HDSISR  => SPR 306 (Power 2.04 hypv)
 2652:  * HDAR    => SPR 307 (Power 2.04 hypv)
 2653:  * PURR    => SPR 309 (Power 2.04 hypv)
 2654:  * HDEC    => SPR 310 (Power 2.04 hypv)
 2655:  * HIOR    => SPR 311 (hypv)
 2656:  * RMOR    => SPR 312 (970)
 2657:  * HRMOR   => SPR 313 (Power 2.04 hypv)
 2658:  * HSRR0   => SPR 314 (Power 2.04 hypv)
 2659:  * HSRR1   => SPR 315 (Power 2.04 hypv)
 2660:  * LPCR    => SPR 316 (970)
 2661:  * LPIDR   => SPR 317 (970)
 2662:  * EPR     => SPR 702 (Power 2.04 emb)
 2663:  * perf    => 768-783 (Power 2.04)
 2664:  * perf    => 784-799 (Power 2.04)
 2665:  * PPR     => SPR 896 (Power 2.04)
 2666:  * EPLC    => SPR 947 (Power 2.04 emb)
 2667:  * EPSC    => SPR 948 (Power 2.04 emb)
 2668:  * DABRX   => 1015    (Power 2.04 hypv)
 2669:  * FPECR   => SPR 1022 (?)
 2670:  * ... and more (thermal management, performance counters, ...)
 2671:  */
 2672: 
 2673: /*****************************************************************************/
 2674: /* Exception vectors models                                                  */
 2675: static void init_excp_4xx_real (CPUPPCState *env)
 2676: {
 2677: #if !defined(CONFIG_USER_ONLY)
 2678:     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
 2679:     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
 2680:     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
 2681:     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
 2682:     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
 2683:     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
 2684:     env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
 2685:     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
 2686:     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
 2687:     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
 2688:     env->hreset_excp_prefix = 0x00000000UL;
 2689:     env->ivor_mask = 0x0000FFF0UL;
 2690:     env->ivpr_mask = 0xFFFF0000UL;
 2691:     /* Hardware reset vector */
 2692:     env->hreset_vector = 0xFFFFFFFCUL;
 2693: #endif
 2694: }
 2695: 
 2696: static void init_excp_4xx_softmmu (CPUPPCState *env)
 2697: {
 2698: #if !defined(CONFIG_USER_ONLY)
 2699:     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
 2700:     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
 2701:     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
 2702:     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
 2703:     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
 2704:     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
 2705:     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
 2706:     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
 2707:     env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
 2708:     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
 2709:     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
 2710:     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
 2711:     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
 2712:     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
 2713:     env->hreset_excp_prefix = 0x00000000UL;
 2714:     env->ivor_mask = 0x0000FFF0UL;
 2715:     env->ivpr_mask = 0xFFFF0000UL;
 2716:     /* Hardware reset vector */
 2717:     env->hreset_vector = 0xFFFFFFFCUL;
 2718: #endif
 2719: }
 2720: 
 2721: static void init_excp_MPC5xx (CPUPPCState *env)
 2722: {
 2723: #if !defined(CONFIG_USER_ONLY)
 2724:     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
 2725:     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
 2726:     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
 2727:     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
 2728:     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
 2729:     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
 2730:     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
 2731:     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
 2732:     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
 2733:     env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
 2734:     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
 2735:     env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
 2736:     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
 2737:     env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
 2738:     env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
 2739:     env->hreset_excp_prefix = 0x00000000UL;
 2740:     env->ivor_mask = 0x0000FFF0UL;
 2741:     env->ivpr_mask = 0xFFFF0000UL;
 2742:     /* Hardware reset vector */
 2743:     env->hreset_vector = 0xFFFFFFFCUL;
 2744: #endif
 2745: }
 2746: 
 2747: static void init_excp_MPC8xx (CPUPPCState *env)
 2748: {
 2749: #if !defined(CONFIG_USER_ONLY)
 2750:     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
 2751:     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
 2752:     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
 2753:     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
 2754:     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
 2755:     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
 2756:     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
 2757:     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
 2758:     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
 2759:     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
 2760:     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
 2761:     env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
 2762:     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
 2763:     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001100;
 2764:     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001200;
 2765:     env->excp_vectors[POWERPC_EXCP_ITLBE]    = 0x00001300;
 2766:     env->excp_vectors[POWERPC_EXCP_DTLBE]    = 0x00001400;
 2767:     env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
 2768:     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
 2769:     env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
 2770:     env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
 2771:     env->hreset_excp_prefix = 0x00000000UL;
 2772:     env->ivor_mask = 0x0000FFF0UL;
 2773:     env->ivpr_mask = 0xFFFF0000UL;
 2774:     /* Hardware reset vector */
 2775:     env->hreset_vector = 0xFFFFFFFCUL;
 2776: #endif
 2777: }
 2778: 
 2779: static void init_excp_G2 (CPUPPCState *env)
 2780: {
 2781: #if !defined(CONFIG_USER_ONLY)
 2782:     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
 2783:     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
 2784:     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
 2785:     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
 2786:     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
 2787:     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
 2788:     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
 2789:     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
 2790:     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
 2791:     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
 2792:     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
 2793:     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
 2794:     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
 2795:     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
 2796:     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
 2797:     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
 2798:     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
 2799:     env->hreset_excp_prefix = 0x00000000UL;
 2800:     /* Hardware reset vector */
 2801:     env->hreset_vector = 0xFFFFFFFCUL;
 2802: #endif
 2803: }
 2804: 
 2805: static void init_excp_e200 (CPUPPCState *env)
 2806: {
 2807: #if !defined(CONFIG_USER_ONLY)
 2808:     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000FFC;
 2809:     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
 2810:     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
 2811:     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
 2812:     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
 2813:     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
 2814:     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
 2815:     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
 2816:     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
 2817:     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
 2818:     env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
 2819:     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
 2820:     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
 2821:     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
 2822:     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
 2823:     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
 2824:     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
 2825:     env->excp_vectors[POWERPC_EXCP_SPEU]     = 0x00000000;
 2826:     env->excp_vectors[POWERPC_EXCP_EFPDI]    = 0x00000000;
 2827:     env->excp_vectors[POWERPC_EXCP_EFPRI]    = 0x00000000;
 2828:     env->hreset_excp_prefix = 0x00000000UL;
 2829:     env->ivor_mask = 0x0000FFF7UL;
 2830:     env->ivpr_mask = 0xFFFF0000UL;
 2831:     /* Hardware reset vector */
 2832:     env->hreset_vector = 0xFFFFFFFCUL;
 2833: #endif
 2834: }
 2835: 
 2836: static void init_excp_BookE (CPUPPCState *env)
 2837: {
 2838: #if !defined(CONFIG_USER_ONLY)
 2839:     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
 2840:     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
 2841:     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
 2842:     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
 2843:     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
 2844:     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
 2845:     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
 2846:     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
 2847:     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
 2848:     env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
 2849:     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
 2850:     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
 2851:     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
 2852:     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
 2853:     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
 2854:     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
 2855:     env->hreset_excp_prefix = 0x00000000UL;
 2856:     env->ivor_mask = 0x0000FFE0UL;
 2857:     env->ivpr_mask = 0xFFFF0000UL;
 2858:     /* Hardware reset vector */
 2859:     env->hreset_vector = 0xFFFFFFFCUL;
 2860: #endif
 2861: }
 2862: 
 2863: static void init_excp_601 (CPUPPCState *env)
 2864: {
 2865: #if !defined(CONFIG_USER_ONLY)
 2866:     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
 2867:     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
 2868:     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
 2869:     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
 2870:     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
 2871:     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
 2872:     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
 2873:     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
 2874:     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
 2875:     env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
 2876:     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
 2877:     env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
 2878:     env->hreset_excp_prefix = 0xFFF00000UL;
 2879:     /* Hardware reset vector */
 2880:     env->hreset_vector = 0x00000100UL;
 2881: #endif
 2882: }
 2883: 
 2884: static void init_excp_602 (CPUPPCState *env)
 2885: {
 2886: #if !defined(CONFIG_USER_ONLY)
 2887:     /* XXX: exception prefix has a special behavior on 602 */
 2888:     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
 2889:     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
 2890:     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
 2891:     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
 2892:     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
 2893:     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
 2894:     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
 2895:     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
 2896:     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
 2897:     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
 2898:     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
 2899:     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
 2900:     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
 2901:     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
 2902:     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
 2903:     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
 2904:     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
 2905:     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
 2906:     env->hreset_excp_prefix = 0xFFF00000UL;
 2907:     /* Hardware reset vector */
 2908:     env->hreset_vector = 0xFFFFFFFCUL;
 2909: #endif
 2910: }
 2911: 
 2912: static void init_excp_603 (CPUPPCState *env)
 2913: {
 2914: #if !defined(CONFIG_USER_ONLY)
 2915:     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
 2916:     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
 2917:     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
 2918:     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
 2919:     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
 2920:     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
 2921:     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
 2922:     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
 2923:     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
 2924:     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
 2925:     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
 2926:     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
 2927:     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
 2928:     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
 2929:     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
 2930:     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
 2931:     env->hreset_excp_prefix = 0x00000000UL;
 2932:     /* Hardware reset vector */
 2933:     env->hreset_vector = 0xFFFFFFFCUL;
 2934: #endif
 2935: }
 2936: 
 2937: static void init_excp_604 (CPUPPCState *env)
 2938: {
 2939: #if !defined(CONFIG_USER_ONLY)
 2940:     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
 2941:     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
 2942:     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
 2943:     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
 2944:     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
 2945:     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
 2946:     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
 2947:     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
 2948:     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
 2949:     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
 2950:     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
 2951:     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
 2952:     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
 2953:     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
 2954:     env->hreset_excp_prefix = 0xFFF00000UL;
 2955:     /* Hardware reset vector */
 2956:     env->hreset_vector = 0x00000100UL;
 2957: #endif
 2958: }
 2959: 
 2960: #if defined(TARGET_PPC64)
 2961: static void init_excp_620 (CPUPPCState *env)
 2962: {
 2963: #if !defined(CONFIG_USER_ONLY)
 2964:     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
 2965:     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
 2966:     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
 2967:     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
 2968:     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
 2969:     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
 2970:     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
 2971:     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
 2972:     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
 2973:     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
 2974:     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
 2975:     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
 2976:     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
 2977:     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
 2978:     env->hreset_excp_prefix = 0xFFF00000UL;
 2979:     /* Hardware reset vector */
 2980:     env->hreset_vector = 0x0000000000000100ULL;
 2981: #endif
 2982: }
 2983: #endif /* defined(TARGET_PPC64) */
 2984: 
 2985: static void init_excp_7x0 (CPUPPCState *env)
 2986: {
 2987: #if !defined(CONFIG_USER_ONLY)
 2988:     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
 2989:     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
 2990:     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
 2991:     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
 2992:     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
 2993:     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
 2994:     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
 2995:     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
 2996:     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
 2997:     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
 2998:     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
 2999:     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
 3000:     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
 3001:     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
 3002:     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
 3003:     env->hreset_excp_prefix = 0x00000000UL;
 3004:     /* Hardware reset vector */
 3005:     env->hreset_vector = 0xFFFFFFFCUL;
 3006: #endif
 3007: }
 3008: 
 3009: static void init_excp_750cl (CPUPPCState *env)
 3010: {
 3011: #if !defined(CONFIG_USER_ONLY)
 3012:     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
 3013:     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
 3014:     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
 3015:     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
 3016:     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
 3017:     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
 3018:     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
 3019:     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
 3020:     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
 3021:     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
 3022:     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
 3023:     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
 3024:     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
 3025:     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
 3026:     env->hreset_excp_prefix = 0x00000000UL;
 3027:     /* Hardware reset vector */
 3028:     env->hreset_vector = 0xFFFFFFFCUL;
 3029: #endif
 3030: }
 3031: 
 3032: static void init_excp_750cx (CPUPPCState *env)
 3033: {
 3034: #if !defined(CONFIG_USER_ONLY)
 3035:     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
 3036:     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
 3037:     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
 3038:     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
 3039:     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
 3040:     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
 3041:     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
 3042:     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
 3043:     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
 3044:     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
 3045:     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
 3046:     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
 3047:     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
 3048:     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
 3049:     env->hreset_excp_prefix = 0x00000000UL;
 3050:     /* Hardware reset vector */
 3051:     env->hreset_vector = 0xFFFFFFFCUL;
 3052: #endif
 3053: }
 3054: 
 3055: /* XXX: Check if this is correct */
 3056: static void init_excp_7x5 (CPUPPCState *env)
 3057: {
 3058: #if !defined(CONFIG_USER_ONLY)
 3059:     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
 3060:     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
 3061:     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
 3062:     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
 3063:     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
 3064:     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
 3065:     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
 3066:     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
 3067:     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
 3068:     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
 3069:     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
 3070:     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
 3071:     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
 3072:     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
 3073:     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
 3074:     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
 3075:     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
 3076:     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
 3077:     env->hreset_excp_prefix = 0x00000000UL;
 3078:     /* Hardware reset vector */
 3079:     env->hreset_vector = 0xFFFFFFFCUL;
 3080: #endif
 3081: }
 3082: 
 3083: static void init_excp_7400 (CPUPPCState *env)
 3084: {
 3085: #if !defined(CONFIG_USER_ONLY)
 3086:     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
 3087:     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
 3088:     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
 3089:     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
 3090:     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
 3091:     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
 3092:     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
 3093:     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
 3094:     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
 3095:     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
 3096:     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
 3097:     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
 3098:     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
 3099:     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
 3100:     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
 3101:     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
 3102:     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
 3103:     env->hreset_excp_prefix = 0x00000000UL;
 3104:     /* Hardware reset vector */
 3105:     env->hreset_vector = 0xFFFFFFFCUL;
 3106: #endif
 3107: }
 3108: 
 3109: static void init_excp_7450 (CPUPPCState *env)
 3110: {
 3111: #if !defined(CONFIG_USER_ONLY)
 3112:     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
 3113:     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
 3114:     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
 3115:     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
 3116:     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
 3117:     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
 3118:     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
 3119:     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
 3120:     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
 3121:     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
 3122:     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
 3123:     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
 3124:     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
 3125:     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
 3126:     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
 3127:     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
 3128:     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
 3129:     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
 3130:     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
 3131:     env->hreset_excp_prefix = 0x00000000UL;
 3132:     /* Hardware reset vector */
 3133:     env->hreset_vector = 0xFFFFFFFCUL;
 3134: #endif
 3135: }
 3136: 
 3137: #if defined (TARGET_PPC64)
 3138: static void init_excp_970 (CPUPPCState *env)
 3139: {
 3140: #if !defined(CONFIG_USER_ONLY)
 3141:     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
 3142:     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
 3143:     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
 3144:     env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
 3145:     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
 3146:     env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
 3147:     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
 3148:     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
 3149:     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
 3150:     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
 3151:     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
 3152:     env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
 3153:     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
 3154:     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
 3155:     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
 3156:     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
 3157:     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
 3158:     env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
 3159:     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
 3160:     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
 3161:     env->hreset_excp_prefix = 0x00000000FFF00000ULL;
 3162:     /* Hardware reset vector */
 3163:     env->hreset_vector = 0x0000000000000100ULL;
 3164: #endif
 3165: }
 3166: 
 3167: static void init_excp_POWER7 (CPUPPCState *env)
 3168: {
 3169: #if !defined(CONFIG_USER_ONLY)
 3170:     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
 3171:     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
 3172:     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
 3173:     env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
 3174:     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
 3175:     env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
 3176:     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
 3177:     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
 3178:     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
 3179:     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
 3180:     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
 3181:     env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
 3182:     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
 3183:     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
 3184:     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
 3185:     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
 3186:     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
 3187:     env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
 3188:     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
 3189:     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
 3190:     env->hreset_excp_prefix = 0;
 3191:     /* Hardware reset vector */
 3192:     env->hreset_vector = 0x0000000000000100ULL;
 3193: #endif
 3194: }
 3195: #endif
 3196: 
 3197: /*****************************************************************************/
 3198: /* Power management enable checks                                            */
 3199: static int check_pow_none (CPUPPCState *env)
 3200: {
 3201:     return 0;
 3202: }
 3203: 
 3204: static int check_pow_nocheck (CPUPPCState *env)
 3205: {
 3206:     return 1;
 3207: }
 3208: 
 3209: static int check_pow_hid0 (CPUPPCState *env)
 3210: {
 3211:     if (env->spr[SPR_HID0] & 0x00E00000)
 3212:         return 1;
 3213: 
 3214:     return 0;
 3215: }
 3216: 
 3217: static int check_pow_hid0_74xx (CPUPPCState *env)
 3218: {
 3219:     if (env->spr[SPR_HID0] & 0x00600000)
 3220:         return 1;
 3221: 
 3222:     return 0;
 3223: }
 3224: 
 3225: /*****************************************************************************/
 3226: /* PowerPC implementations definitions                                       */
 3227: 
 3228: /* PowerPC 401                                                               */
 3229: #define POWERPC_INSNS_401    (PPC_INSNS_BASE | PPC_STRING |                   \
 3230:                               PPC_WRTEE | PPC_DCR |                           \
 3231:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
 3232:                               PPC_CACHE_DCBZ |                                \
 3233:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 3234:                               PPC_4xx_COMMON | PPC_40x_EXCP)
 3235: #define POWERPC_INSNS2_401   (PPC_NONE)
 3236: #define POWERPC_MSRM_401     (0x00000000000FD201ULL)
 3237: #define POWERPC_MMU_401      (POWERPC_MMU_REAL)
 3238: #define POWERPC_EXCP_401     (POWERPC_EXCP_40x)
 3239: #define POWERPC_INPUT_401    (PPC_FLAGS_INPUT_401)
 3240: #define POWERPC_BFDM_401     (bfd_mach_ppc_403)
 3241: #define POWERPC_FLAG_401     (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
 3242:                               POWERPC_FLAG_BUS_CLK)
 3243: #define check_pow_401        check_pow_nocheck
 3244: 
 3245: static void init_proc_401 (CPUPPCState *env)
 3246: {
 3247:     gen_spr_40x(env);
 3248:     gen_spr_401_403(env);
 3249:     gen_spr_401(env);
 3250:     init_excp_4xx_real(env);
 3251:     env->dcache_line_size = 32;
 3252:     env->icache_line_size = 32;
 3253:     /* Allocate hardware IRQ controller */
 3254:     ppc40x_irq_init(env);
 3255: 
 3256:     SET_FIT_PERIOD(12, 16, 20, 24);
 3257:     SET_WDT_PERIOD(16, 20, 24, 28);
 3258: }
 3259: 
 3260: /* PowerPC 401x2                                                             */
 3261: #define POWERPC_INSNS_401x2  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 3262:                               PPC_DCR | PPC_WRTEE |                           \
 3263:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
 3264:                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
 3265:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 3266:                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
 3267:                               PPC_4xx_COMMON | PPC_40x_EXCP)
 3268: #define POWERPC_INSNS2_401x2 (PPC_NONE)
 3269: #define POWERPC_MSRM_401x2   (0x00000000001FD231ULL)
 3270: #define POWERPC_MMU_401x2    (POWERPC_MMU_SOFT_4xx_Z)
 3271: #define POWERPC_EXCP_401x2   (POWERPC_EXCP_40x)
 3272: #define POWERPC_INPUT_401x2  (PPC_FLAGS_INPUT_401)
 3273: #define POWERPC_BFDM_401x2   (bfd_mach_ppc_403)
 3274: #define POWERPC_FLAG_401x2   (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
 3275:                               POWERPC_FLAG_BUS_CLK)
 3276: #define check_pow_401x2      check_pow_nocheck
 3277: 
 3278: static void init_proc_401x2 (CPUPPCState *env)
 3279: {
 3280:     gen_spr_40x(env);
 3281:     gen_spr_401_403(env);
 3282:     gen_spr_401x2(env);
 3283:     gen_spr_compress(env);
 3284:     /* Memory management */
 3285: #if !defined(CONFIG_USER_ONLY)
 3286:     env->nb_tlb = 64;
 3287:     env->nb_ways = 1;
 3288:     env->id_tlbs = 0;
 3289:     env->tlb_type = TLB_EMB;
 3290: #endif
 3291:     init_excp_4xx_softmmu(env);
 3292:     env->dcache_line_size = 32;
 3293:     env->icache_line_size = 32;
 3294:     /* Allocate hardware IRQ controller */
 3295:     ppc40x_irq_init(env);
 3296: 
 3297:     SET_FIT_PERIOD(12, 16, 20, 24);
 3298:     SET_WDT_PERIOD(16, 20, 24, 28);
 3299: }
 3300: 
 3301: /* PowerPC 401x3                                                             */
 3302: #define POWERPC_INSNS_401x3  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 3303:                               PPC_DCR | PPC_WRTEE |                           \
 3304:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
 3305:                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
 3306:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 3307:                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
 3308:                               PPC_4xx_COMMON | PPC_40x_EXCP)
 3309: #define POWERPC_INSNS2_401x3 (PPC_NONE)
 3310: #define POWERPC_MSRM_401x3   (0x00000000001FD631ULL)
 3311: #define POWERPC_MMU_401x3    (POWERPC_MMU_SOFT_4xx_Z)
 3312: #define POWERPC_EXCP_401x3   (POWERPC_EXCP_40x)
 3313: #define POWERPC_INPUT_401x3  (PPC_FLAGS_INPUT_401)
 3314: #define POWERPC_BFDM_401x3   (bfd_mach_ppc_403)
 3315: #define POWERPC_FLAG_401x3   (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
 3316:                               POWERPC_FLAG_BUS_CLK)
 3317: #define check_pow_401x3      check_pow_nocheck
 3318: 
 3319: __attribute__ (( unused ))
 3320: static void init_proc_401x3 (CPUPPCState *env)
 3321: {
 3322:     gen_spr_40x(env);
 3323:     gen_spr_401_403(env);
 3324:     gen_spr_401(env);
 3325:     gen_spr_401x2(env);
 3326:     gen_spr_compress(env);
 3327:     init_excp_4xx_softmmu(env);
 3328:     env->dcache_line_size = 32;
 3329:     env->icache_line_size = 32;
 3330:     /* Allocate hardware IRQ controller */
 3331:     ppc40x_irq_init(env);
 3332: 
 3333:     SET_FIT_PERIOD(12, 16, 20, 24);
 3334:     SET_WDT_PERIOD(16, 20, 24, 28);
 3335: }
 3336: 
 3337: /* IOP480                                                                    */
 3338: #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING |                   \
 3339:                               PPC_DCR | PPC_WRTEE |                           \
 3340:                               PPC_CACHE | PPC_CACHE_ICBI |  PPC_40x_ICBT |    \
 3341:                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
 3342:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 3343:                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
 3344:                               PPC_4xx_COMMON | PPC_40x_EXCP)
 3345: #define POWERPC_INSNS2_IOP480 (PPC_NONE)
 3346: #define POWERPC_MSRM_IOP480  (0x00000000001FD231ULL)
 3347: #define POWERPC_MMU_IOP480   (POWERPC_MMU_SOFT_4xx_Z)
 3348: #define POWERPC_EXCP_IOP480  (POWERPC_EXCP_40x)
 3349: #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
 3350: #define POWERPC_BFDM_IOP480  (bfd_mach_ppc_403)
 3351: #define POWERPC_FLAG_IOP480  (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
 3352:                               POWERPC_FLAG_BUS_CLK)
 3353: #define check_pow_IOP480     check_pow_nocheck
 3354: 
 3355: static void init_proc_IOP480 (CPUPPCState *env)
 3356: {
 3357:     gen_spr_40x(env);
 3358:     gen_spr_401_403(env);
 3359:     gen_spr_401x2(env);
 3360:     gen_spr_compress(env);
 3361:     /* Memory management */
 3362: #if !defined(CONFIG_USER_ONLY)
 3363:     env->nb_tlb = 64;
 3364:     env->nb_ways = 1;
 3365:     env->id_tlbs = 0;
 3366:     env->tlb_type = TLB_EMB;
 3367: #endif
 3368:     init_excp_4xx_softmmu(env);
 3369:     env->dcache_line_size = 32;
 3370:     env->icache_line_size = 32;
 3371:     /* Allocate hardware IRQ controller */
 3372:     ppc40x_irq_init(env);
 3373: 
 3374:     SET_FIT_PERIOD(8, 12, 16, 20);
 3375:     SET_WDT_PERIOD(16, 20, 24, 28);
 3376: }
 3377: 
 3378: /* PowerPC 403                                                               */
 3379: #define POWERPC_INSNS_403    (PPC_INSNS_BASE | PPC_STRING |                   \
 3380:                               PPC_DCR | PPC_WRTEE |                           \
 3381:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
 3382:                               PPC_CACHE_DCBZ |                                \
 3383:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 3384:                               PPC_4xx_COMMON | PPC_40x_EXCP)
 3385: #define POWERPC_INSNS2_403   (PPC_NONE)
 3386: #define POWERPC_MSRM_403     (0x000000000007D00DULL)
 3387: #define POWERPC_MMU_403      (POWERPC_MMU_REAL)
 3388: #define POWERPC_EXCP_403     (POWERPC_EXCP_40x)
 3389: #define POWERPC_INPUT_403    (PPC_FLAGS_INPUT_401)
 3390: #define POWERPC_BFDM_403     (bfd_mach_ppc_403)
 3391: #define POWERPC_FLAG_403     (POWERPC_FLAG_CE | POWERPC_FLAG_PX |             \
 3392:                               POWERPC_FLAG_BUS_CLK)
 3393: #define check_pow_403        check_pow_nocheck
 3394: 
 3395: static void init_proc_403 (CPUPPCState *env)
 3396: {
 3397:     gen_spr_40x(env);
 3398:     gen_spr_401_403(env);
 3399:     gen_spr_403(env);
 3400:     gen_spr_403_real(env);
 3401:     init_excp_4xx_real(env);
 3402:     env->dcache_line_size = 32;
 3403:     env->icache_line_size = 32;
 3404:     /* Allocate hardware IRQ controller */
 3405:     ppc40x_irq_init(env);
 3406: 
 3407:     SET_FIT_PERIOD(8, 12, 16, 20);
 3408:     SET_WDT_PERIOD(16, 20, 24, 28);
 3409: }
 3410: 
 3411: /* PowerPC 403 GCX                                                           */
 3412: #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING |                   \
 3413:                               PPC_DCR | PPC_WRTEE |                           \
 3414:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
 3415:                               PPC_CACHE_DCBZ |                                \
 3416:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 3417:                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
 3418:                               PPC_4xx_COMMON | PPC_40x_EXCP)
 3419: #define POWERPC_INSNS2_403GCX (PPC_NONE)
 3420: #define POWERPC_MSRM_403GCX  (0x000000000007D00DULL)
 3421: #define POWERPC_MMU_403GCX   (POWERPC_MMU_SOFT_4xx_Z)
 3422: #define POWERPC_EXCP_403GCX  (POWERPC_EXCP_40x)
 3423: #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
 3424: #define POWERPC_BFDM_403GCX  (bfd_mach_ppc_403)
 3425: #define POWERPC_FLAG_403GCX  (POWERPC_FLAG_CE | POWERPC_FLAG_PX |             \
 3426:                               POWERPC_FLAG_BUS_CLK)
 3427: #define check_pow_403GCX     check_pow_nocheck
 3428: 
 3429: static void init_proc_403GCX (CPUPPCState *env)
 3430: {
 3431:     gen_spr_40x(env);
 3432:     gen_spr_401_403(env);
 3433:     gen_spr_403(env);
 3434:     gen_spr_403_real(env);
 3435:     gen_spr_403_mmu(env);
 3436:     /* Bus access control */
 3437:     /* not emulated, as Qemu never does speculative access */
 3438:     spr_register(env, SPR_40x_SGR, "SGR",
 3439:                  SPR_NOACCESS, SPR_NOACCESS,
 3440:                  &spr_read_generic, &spr_write_generic,
 3441:                  0xFFFFFFFF);
 3442:     /* not emulated, as Qemu do not emulate caches */
 3443:     spr_register(env, SPR_40x_DCWR, "DCWR",
 3444:                  SPR_NOACCESS, SPR_NOACCESS,
 3445:                  &spr_read_generic, &spr_write_generic,
 3446:                  0x00000000);
 3447:     /* Memory management */
 3448: #if !defined(CONFIG_USER_ONLY)
 3449:     env->nb_tlb = 64;
 3450:     env->nb_ways = 1;
 3451:     env->id_tlbs = 0;
 3452:     env->tlb_type = TLB_EMB;
 3453: #endif
 3454:     init_excp_4xx_softmmu(env);
 3455:     env->dcache_line_size = 32;
 3456:     env->icache_line_size = 32;
 3457:     /* Allocate hardware IRQ controller */
 3458:     ppc40x_irq_init(env);
 3459: 
 3460:     SET_FIT_PERIOD(8, 12, 16, 20);
 3461:     SET_WDT_PERIOD(16, 20, 24, 28);
 3462: }
 3463: 
 3464: /* PowerPC 405                                                               */
 3465: #define POWERPC_INSNS_405    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 3466:                               PPC_DCR | PPC_WRTEE |                           \
 3467:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
 3468:                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
 3469:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 3470:                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
 3471:                               PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
 3472: #define POWERPC_INSNS2_405   (PPC_NONE)
 3473: #define POWERPC_MSRM_405     (0x000000000006E630ULL)
 3474: #define POWERPC_MMU_405      (POWERPC_MMU_SOFT_4xx)
 3475: #define POWERPC_EXCP_405     (POWERPC_EXCP_40x)
 3476: #define POWERPC_INPUT_405    (PPC_FLAGS_INPUT_405)
 3477: #define POWERPC_BFDM_405     (bfd_mach_ppc_403)
 3478: #define POWERPC_FLAG_405     (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
 3479:                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
 3480: #define check_pow_405        check_pow_nocheck
 3481: 
 3482: static void init_proc_405 (CPUPPCState *env)
 3483: {
 3484:     /* Time base */
 3485:     gen_tbl(env);
 3486:     gen_spr_40x(env);
 3487:     gen_spr_405(env);
 3488:     /* Bus access control */
 3489:     /* not emulated, as Qemu never does speculative access */
 3490:     spr_register(env, SPR_40x_SGR, "SGR",
 3491:                  SPR_NOACCESS, SPR_NOACCESS,
 3492:                  &spr_read_generic, &spr_write_generic,
 3493:                  0xFFFFFFFF);
 3494:     /* not emulated, as Qemu do not emulate caches */
 3495:     spr_register(env, SPR_40x_DCWR, "DCWR",
 3496:                  SPR_NOACCESS, SPR_NOACCESS,
 3497:                  &spr_read_generic, &spr_write_generic,
 3498:                  0x00000000);
 3499:     /* Memory management */
 3500: #if !defined(CONFIG_USER_ONLY)
 3501:     env->nb_tlb = 64;
 3502:     env->nb_ways = 1;
 3503:     env->id_tlbs = 0;
 3504:     env->tlb_type = TLB_EMB;
 3505: #endif
 3506:     init_excp_4xx_softmmu(env);
 3507:     env->dcache_line_size = 32;
 3508:     env->icache_line_size = 32;
 3509:     /* Allocate hardware IRQ controller */
 3510:     ppc40x_irq_init(env);
 3511: 
 3512:     SET_FIT_PERIOD(8, 12, 16, 20);
 3513:     SET_WDT_PERIOD(16, 20, 24, 28);
 3514: }
 3515: 
 3516: /* PowerPC 440 EP                                                            */
 3517: #define POWERPC_INSNS_440EP  (PPC_INSNS_BASE | PPC_STRING |                   \
 3518:                               PPC_DCR | PPC_WRTEE | PPC_RFMCI |               \
 3519:                               PPC_CACHE | PPC_CACHE_ICBI |                    \
 3520:                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
 3521:                               PPC_MEM_TLBSYNC | PPC_MFTB |                    \
 3522:                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
 3523:                               PPC_440_SPEC)
 3524: #define POWERPC_INSNS2_440EP (PPC_NONE)
 3525: #define POWERPC_MSRM_440EP   (0x000000000006D630ULL)
 3526: #define POWERPC_MMU_440EP    (POWERPC_MMU_BOOKE)
 3527: #define POWERPC_EXCP_440EP   (POWERPC_EXCP_BOOKE)
 3528: #define POWERPC_INPUT_440EP  (PPC_FLAGS_INPUT_BookE)
 3529: #define POWERPC_BFDM_440EP   (bfd_mach_ppc_403)
 3530: #define POWERPC_FLAG_440EP   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
 3531:                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
 3532: #define check_pow_440EP      check_pow_nocheck
 3533: 
 3534: __attribute__ (( unused ))
 3535: static void init_proc_440EP (CPUPPCState *env)
 3536: {
 3537:     /* Time base */
 3538:     gen_tbl(env);
 3539:     gen_spr_BookE(env, 0x000000000000FFFFULL);
 3540:     gen_spr_440(env);
 3541:     gen_spr_usprgh(env);
 3542:     /* Processor identification */
 3543:     spr_register(env, SPR_BOOKE_PIR, "PIR",
 3544:                  SPR_NOACCESS, SPR_NOACCESS,
 3545:                  &spr_read_generic, &spr_write_pir,
 3546:                  0x00000000);
 3547:     /* XXX : not implemented */
 3548:     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
 3549:                  SPR_NOACCESS, SPR_NOACCESS,
 3550:                  &spr_read_generic, &spr_write_generic,
 3551:                  0x00000000);
 3552:     /* XXX : not implemented */
 3553:     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
 3554:                  SPR_NOACCESS, SPR_NOACCESS,
 3555:                  &spr_read_generic, &spr_write_generic,
 3556:                  0x00000000);
 3557:     /* XXX : not implemented */
 3558:     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
 3559:                  SPR_NOACCESS, SPR_NOACCESS,
 3560:                  &spr_read_generic, &spr_write_generic,
 3561:                  0x00000000);
 3562:     /* XXX : not implemented */
 3563:     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
 3564:                  SPR_NOACCESS, SPR_NOACCESS,
 3565:                  &spr_read_generic, &spr_write_generic,
 3566:                  0x00000000);
 3567:     /* XXX : not implemented */
 3568:     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
 3569:                  SPR_NOACCESS, SPR_NOACCESS,
 3570:                  &spr_read_generic, &spr_write_generic,
 3571:                  0x00000000);
 3572:     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
 3573:                  SPR_NOACCESS, SPR_NOACCESS,
 3574:                  &spr_read_generic, &spr_write_generic,
 3575:                  0x00000000);
 3576:     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
 3577:                  SPR_NOACCESS, SPR_NOACCESS,
 3578:                  &spr_read_generic, &spr_write_generic,
 3579:                  0x00000000);
 3580:     /* XXX : not implemented */
 3581:     spr_register(env, SPR_440_CCR1, "CCR1",
 3582:                  SPR_NOACCESS, SPR_NOACCESS,
 3583:                  &spr_read_generic, &spr_write_generic,
 3584:                  0x00000000);
 3585:     /* Memory management */
 3586: #if !defined(CONFIG_USER_ONLY)
 3587:     env->nb_tlb = 64;
 3588:     env->nb_ways = 1;
 3589:     env->id_tlbs = 0;
 3590:     env->tlb_type = TLB_EMB;
 3591: #endif
 3592:     init_excp_BookE(env);
 3593:     env->dcache_line_size = 32;
 3594:     env->icache_line_size = 32;
 3595:     /* XXX: TODO: allocate internal IRQ controller */
 3596: 
 3597:     SET_FIT_PERIOD(12, 16, 20, 24);
 3598:     SET_WDT_PERIOD(20, 24, 28, 32);
 3599: }
 3600: 
 3601: /* PowerPC 440 GP                                                            */
 3602: #define POWERPC_INSNS_440GP  (PPC_INSNS_BASE | PPC_STRING |                   \
 3603:                               PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |  \
 3604:                               PPC_CACHE | PPC_CACHE_ICBI |                    \
 3605:                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
 3606:                               PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |       \
 3607:                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
 3608:                               PPC_440_SPEC)
 3609: #define POWERPC_INSNS2_440GP (PPC_NONE)
 3610: #define POWERPC_MSRM_440GP   (0x000000000006FF30ULL)
 3611: #define POWERPC_MMU_440GP    (POWERPC_MMU_BOOKE)
 3612: #define POWERPC_EXCP_440GP   (POWERPC_EXCP_BOOKE)
 3613: #define POWERPC_INPUT_440GP  (PPC_FLAGS_INPUT_BookE)
 3614: #define POWERPC_BFDM_440GP   (bfd_mach_ppc_403)
 3615: #define POWERPC_FLAG_440GP   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
 3616:                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
 3617: #define check_pow_440GP      check_pow_nocheck
 3618: 
 3619: __attribute__ (( unused ))
 3620: static void init_proc_440GP (CPUPPCState *env)
 3621: {
 3622:     /* Time base */
 3623:     gen_tbl(env);
 3624:     gen_spr_BookE(env, 0x000000000000FFFFULL);
 3625:     gen_spr_440(env);
 3626:     gen_spr_usprgh(env);
 3627:     /* Processor identification */
 3628:     spr_register(env, SPR_BOOKE_PIR, "PIR",
 3629:                  SPR_NOACCESS, SPR_NOACCESS,
 3630:                  &spr_read_generic, &spr_write_pir,
 3631:                  0x00000000);
 3632:     /* XXX : not implemented */
 3633:     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
 3634:                  SPR_NOACCESS, SPR_NOACCESS,
 3635:                  &spr_read_generic, &spr_write_generic,
 3636:                  0x00000000);
 3637:     /* XXX : not implemented */
 3638:     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
 3639:                  SPR_NOACCESS, SPR_NOACCESS,
 3640:                  &spr_read_generic, &spr_write_generic,
 3641:                  0x00000000);
 3642:     /* XXX : not implemented */
 3643:     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
 3644:                  SPR_NOACCESS, SPR_NOACCESS,
 3645:                  &spr_read_generic, &spr_write_generic,
 3646:                  0x00000000);
 3647:     /* XXX : not implemented */
 3648:     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
 3649:                  SPR_NOACCESS, SPR_NOACCESS,
 3650:                  &spr_read_generic, &spr_write_generic,
 3651:                  0x00000000);
 3652:     /* Memory management */
 3653: #if !defined(CONFIG_USER_ONLY)
 3654:     env->nb_tlb = 64;
 3655:     env->nb_ways = 1;
 3656:     env->id_tlbs = 0;
 3657:     env->tlb_type = TLB_EMB;
 3658: #endif
 3659:     init_excp_BookE(env);
 3660:     env->dcache_line_size = 32;
 3661:     env->icache_line_size = 32;
 3662:     /* XXX: TODO: allocate internal IRQ controller */
 3663: 
 3664:     SET_FIT_PERIOD(12, 16, 20, 24);
 3665:     SET_WDT_PERIOD(20, 24, 28, 32);
 3666: }
 3667: 
 3668: /* PowerPC 440x4                                                             */
 3669: #define POWERPC_INSNS_440x4  (PPC_INSNS_BASE | PPC_STRING |                   \
 3670:                               PPC_DCR | PPC_WRTEE |                           \
 3671:                               PPC_CACHE | PPC_CACHE_ICBI |                    \
 3672:                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
 3673:                               PPC_MEM_TLBSYNC | PPC_MFTB |                    \
 3674:                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
 3675:                               PPC_440_SPEC)
 3676: #define POWERPC_INSNS2_440x4 (PPC_NONE)
 3677: #define POWERPC_MSRM_440x4   (0x000000000006FF30ULL)
 3678: #define POWERPC_MMU_440x4    (POWERPC_MMU_BOOKE)
 3679: #define POWERPC_EXCP_440x4   (POWERPC_EXCP_BOOKE)
 3680: #define POWERPC_INPUT_440x4  (PPC_FLAGS_INPUT_BookE)
 3681: #define POWERPC_BFDM_440x4   (bfd_mach_ppc_403)
 3682: #define POWERPC_FLAG_440x4   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
 3683:                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
 3684: #define check_pow_440x4      check_pow_nocheck
 3685: 
 3686: __attribute__ (( unused ))
 3687: static void init_proc_440x4 (CPUPPCState *env)
 3688: {
 3689:     /* Time base */
 3690:     gen_tbl(env);
 3691:     gen_spr_BookE(env, 0x000000000000FFFFULL);
 3692:     gen_spr_440(env);
 3693:     gen_spr_usprgh(env);
 3694:     /* Processor identification */
 3695:     spr_register(env, SPR_BOOKE_PIR, "PIR",
 3696:                  SPR_NOACCESS, SPR_NOACCESS,
 3697:                  &spr_read_generic, &spr_write_pir,
 3698:                  0x00000000);
 3699:     /* XXX : not implemented */
 3700:     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
 3701:                  SPR_NOACCESS, SPR_NOACCESS,
 3702:                  &spr_read_generic, &spr_write_generic,
 3703:                  0x00000000);
 3704:     /* XXX : not implemented */
 3705:     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
 3706:                  SPR_NOACCESS, SPR_NOACCESS,
 3707:                  &spr_read_generic, &spr_write_generic,
 3708:                  0x00000000);
 3709:     /* XXX : not implemented */
 3710:     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
 3711:                  SPR_NOACCESS, SPR_NOACCESS,
 3712:                  &spr_read_generic, &spr_write_generic,
 3713:                  0x00000000);
 3714:     /* XXX : not implemented */
 3715:     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
 3716:                  SPR_NOACCESS, SPR_NOACCESS,
 3717:                  &spr_read_generic, &spr_write_generic,
 3718:                  0x00000000);
 3719:     /* Memory management */
 3720: #if !defined(CONFIG_USER_ONLY)
 3721:     env->nb_tlb = 64;
 3722:     env->nb_ways = 1;
 3723:     env->id_tlbs = 0;
 3724:     env->tlb_type = TLB_EMB;
 3725: #endif
 3726:     init_excp_BookE(env);
 3727:     env->dcache_line_size = 32;
 3728:     env->icache_line_size = 32;
 3729:     /* XXX: TODO: allocate internal IRQ controller */
 3730: 
 3731:     SET_FIT_PERIOD(12, 16, 20, 24);
 3732:     SET_WDT_PERIOD(20, 24, 28, 32);
 3733: }
 3734: 
 3735: /* PowerPC 440x5                                                             */
 3736: #define POWERPC_INSNS_440x5  (PPC_INSNS_BASE | PPC_STRING |                   \
 3737:                               PPC_DCR | PPC_WRTEE | PPC_RFMCI |               \
 3738:                               PPC_CACHE | PPC_CACHE_ICBI |                    \
 3739:                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
 3740:                               PPC_MEM_TLBSYNC | PPC_MFTB |                    \
 3741:                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
 3742:                               PPC_440_SPEC)
 3743: #define POWERPC_INSNS2_440x5 (PPC_NONE)
 3744: #define POWERPC_MSRM_440x5   (0x000000000006FF30ULL)
 3745: #define POWERPC_MMU_440x5    (POWERPC_MMU_BOOKE)
 3746: #define POWERPC_EXCP_440x5   (POWERPC_EXCP_BOOKE)
 3747: #define POWERPC_INPUT_440x5  (PPC_FLAGS_INPUT_BookE)
 3748: #define POWERPC_BFDM_440x5   (bfd_mach_ppc_403)
 3749: #define POWERPC_FLAG_440x5   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |           \
 3750:                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
 3751: #define check_pow_440x5      check_pow_nocheck
 3752: 
 3753: static void init_proc_440x5 (CPUPPCState *env)
 3754: {
 3755:     /* Time base */
 3756:     gen_tbl(env);
 3757:     gen_spr_BookE(env, 0x000000000000FFFFULL);
 3758:     gen_spr_440(env);
 3759:     gen_spr_usprgh(env);
 3760:     /* Processor identification */
 3761:     spr_register(env, SPR_BOOKE_PIR, "PIR",
 3762:                  SPR_NOACCESS, SPR_NOACCESS,
 3763:                  &spr_read_generic, &spr_write_pir,
 3764:                  0x00000000);
 3765:     /* XXX : not implemented */
 3766:     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
 3767:                  SPR_NOACCESS, SPR_NOACCESS,
 3768:                  &spr_read_generic, &spr_write_generic,
 3769:                  0x00000000);
 3770:     /* XXX : not implemented */
 3771:     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
 3772:                  SPR_NOACCESS, SPR_NOACCESS,
 3773:                  &spr_read_generic, &spr_write_generic,
 3774:                  0x00000000);
 3775:     /* XXX : not implemented */
 3776:     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
 3777:                  SPR_NOACCESS, SPR_NOACCESS,
 3778:                  &spr_read_generic, &spr_write_generic,
 3779:                  0x00000000);
 3780:     /* XXX : not implemented */
 3781:     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
 3782:                  SPR_NOACCESS, SPR_NOACCESS,
 3783:                  &spr_read_generic, &spr_write_generic,
 3784:                  0x00000000);
 3785:     /* XXX : not implemented */
 3786:     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
 3787:                  SPR_NOACCESS, SPR_NOACCESS,
 3788:                  &spr_read_generic, &spr_write_generic,
 3789:                  0x00000000);
 3790:     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
 3791:                  SPR_NOACCESS, SPR_NOACCESS,
 3792:                  &spr_read_generic, &spr_write_generic,
 3793:                  0x00000000);
 3794:     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
 3795:                  SPR_NOACCESS, SPR_NOACCESS,
 3796:                  &spr_read_generic, &spr_write_generic,
 3797:                  0x00000000);
 3798:     /* XXX : not implemented */
 3799:     spr_register(env, SPR_440_CCR1, "CCR1",
 3800:                  SPR_NOACCESS, SPR_NOACCESS,
 3801:                  &spr_read_generic, &spr_write_generic,
 3802:                  0x00000000);
 3803:     /* Memory management */
 3804: #if !defined(CONFIG_USER_ONLY)
 3805:     env->nb_tlb = 64;
 3806:     env->nb_ways = 1;
 3807:     env->id_tlbs = 0;
 3808:     env->tlb_type = TLB_EMB;
 3809: #endif
 3810:     init_excp_BookE(env);
 3811:     env->dcache_line_size = 32;
 3812:     env->icache_line_size = 32;
 3813:     ppc40x_irq_init(env);
 3814: 
 3815:     SET_FIT_PERIOD(12, 16, 20, 24);
 3816:     SET_WDT_PERIOD(20, 24, 28, 32);
 3817: }
 3818: 
 3819: /* PowerPC 460 (guessed)                                                     */
 3820: #define POWERPC_INSNS_460    (PPC_INSNS_BASE | PPC_STRING |                   \
 3821:                               PPC_DCR | PPC_DCRX  | PPC_DCRUX |               \
 3822:                               PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |            \
 3823:                               PPC_CACHE | PPC_CACHE_ICBI |                    \
 3824:                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
 3825:                               PPC_MEM_TLBSYNC | PPC_TLBIVA |                  \
 3826:                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
 3827:                               PPC_440_SPEC)
 3828: #define POWERPC_INSNS2_460   (PPC_NONE)
 3829: #define POWERPC_MSRM_460     (0x000000000006FF30ULL)
 3830: #define POWERPC_MMU_460      (POWERPC_MMU_BOOKE)
 3831: #define POWERPC_EXCP_460     (POWERPC_EXCP_BOOKE)
 3832: #define POWERPC_INPUT_460    (PPC_FLAGS_INPUT_BookE)
 3833: #define POWERPC_BFDM_460     (bfd_mach_ppc_403)
 3834: #define POWERPC_FLAG_460     (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
 3835:                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
 3836: #define check_pow_460        check_pow_nocheck
 3837: 
 3838: __attribute__ (( unused ))
 3839: static void init_proc_460 (CPUPPCState *env)
 3840: {
 3841:     /* Time base */
 3842:     gen_tbl(env);
 3843:     gen_spr_BookE(env, 0x000000000000FFFFULL);
 3844:     gen_spr_440(env);
 3845:     gen_spr_usprgh(env);
 3846:     /* Processor identification */
 3847:     spr_register(env, SPR_BOOKE_PIR, "PIR",
 3848:                  SPR_NOACCESS, SPR_NOACCESS,
 3849:                  &spr_read_generic, &spr_write_pir,
 3850:                  0x00000000);
 3851:     /* XXX : not implemented */
 3852:     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
 3853:                  SPR_NOACCESS, SPR_NOACCESS,
 3854:                  &spr_read_generic, &spr_write_generic,
 3855:                  0x00000000);
 3856:     /* XXX : not implemented */
 3857:     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
 3858:                  SPR_NOACCESS, SPR_NOACCESS,
 3859:                  &spr_read_generic, &spr_write_generic,
 3860:                  0x00000000);
 3861:     /* XXX : not implemented */
 3862:     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
 3863:                  SPR_NOACCESS, SPR_NOACCESS,
 3864:                  &spr_read_generic, &spr_write_generic,
 3865:                  0x00000000);
 3866:     /* XXX : not implemented */
 3867:     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
 3868:                  SPR_NOACCESS, SPR_NOACCESS,
 3869:                  &spr_read_generic, &spr_write_generic,
 3870:                  0x00000000);
 3871:     /* XXX : not implemented */
 3872:     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
 3873:                  SPR_NOACCESS, SPR_NOACCESS,
 3874:                  &spr_read_generic, &spr_write_generic,
 3875:                  0x00000000);
 3876:     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
 3877:                  SPR_NOACCESS, SPR_NOACCESS,
 3878:                  &spr_read_generic, &spr_write_generic,
 3879:                  0x00000000);
 3880:     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
 3881:                  SPR_NOACCESS, SPR_NOACCESS,
 3882:                  &spr_read_generic, &spr_write_generic,
 3883:                  0x00000000);
 3884:     /* XXX : not implemented */
 3885:     spr_register(env, SPR_440_CCR1, "CCR1",
 3886:                  SPR_NOACCESS, SPR_NOACCESS,
 3887:                  &spr_read_generic, &spr_write_generic,
 3888:                  0x00000000);
 3889:     /* XXX : not implemented */
 3890:     spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
 3891:                  &spr_read_generic, &spr_write_generic,
 3892:                  &spr_read_generic, &spr_write_generic,
 3893:                  0x00000000);
 3894:     /* Memory management */
 3895: #if !defined(CONFIG_USER_ONLY)
 3896:     env->nb_tlb = 64;
 3897:     env->nb_ways = 1;
 3898:     env->id_tlbs = 0;
 3899:     env->tlb_type = TLB_EMB;
 3900: #endif
 3901:     init_excp_BookE(env);
 3902:     env->dcache_line_size = 32;
 3903:     env->icache_line_size = 32;
 3904:     /* XXX: TODO: allocate internal IRQ controller */
 3905: 
 3906:     SET_FIT_PERIOD(12, 16, 20, 24);
 3907:     SET_WDT_PERIOD(20, 24, 28, 32);
 3908: }
 3909: 
 3910: /* PowerPC 460F (guessed)                                                    */
 3911: #define POWERPC_INSNS_460F   (PPC_INSNS_BASE | PPC_STRING |                   \
 3912:                               PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |   \
 3913:                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
 3914:                               PPC_FLOAT_STFIWX | PPC_MFTB |                   \
 3915:                               PPC_DCR | PPC_DCRX | PPC_DCRUX |                \
 3916:                               PPC_WRTEE | PPC_MFAPIDI |                       \
 3917:                               PPC_CACHE | PPC_CACHE_ICBI |                    \
 3918:                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
 3919:                               PPC_MEM_TLBSYNC | PPC_TLBIVA |                  \
 3920:                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
 3921:                               PPC_440_SPEC)
 3922: #define POWERPC_INSNS2_460F  (PPC_NONE)
 3923: #define POWERPC_MSRM_460     (0x000000000006FF30ULL)
 3924: #define POWERPC_MMU_460F     (POWERPC_MMU_BOOKE)
 3925: #define POWERPC_EXCP_460F    (POWERPC_EXCP_BOOKE)
 3926: #define POWERPC_INPUT_460F   (PPC_FLAGS_INPUT_BookE)
 3927: #define POWERPC_BFDM_460F    (bfd_mach_ppc_403)
 3928: #define POWERPC_FLAG_460F    (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
 3929:                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
 3930: #define check_pow_460F       check_pow_nocheck
 3931: 
 3932: __attribute__ (( unused ))
 3933: static void init_proc_460F (CPUPPCState *env)
 3934: {
 3935:     /* Time base */
 3936:     gen_tbl(env);
 3937:     gen_spr_BookE(env, 0x000000000000FFFFULL);
 3938:     gen_spr_440(env);
 3939:     gen_spr_usprgh(env);
 3940:     /* Processor identification */
 3941:     spr_register(env, SPR_BOOKE_PIR, "PIR",
 3942:                  SPR_NOACCESS, SPR_NOACCESS,
 3943:                  &spr_read_generic, &spr_write_pir,
 3944:                  0x00000000);
 3945:     /* XXX : not implemented */
 3946:     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
 3947:                  SPR_NOACCESS, SPR_NOACCESS,
 3948:                  &spr_read_generic, &spr_write_generic,
 3949:                  0x00000000);
 3950:     /* XXX : not implemented */
 3951:     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
 3952:                  SPR_NOACCESS, SPR_NOACCESS,
 3953:                  &spr_read_generic, &spr_write_generic,
 3954:                  0x00000000);
 3955:     /* XXX : not implemented */
 3956:     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
 3957:                  SPR_NOACCESS, SPR_NOACCESS,
 3958:                  &spr_read_generic, &spr_write_generic,
 3959:                  0x00000000);
 3960:     /* XXX : not implemented */
 3961:     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
 3962:                  SPR_NOACCESS, SPR_NOACCESS,
 3963:                  &spr_read_generic, &spr_write_generic,
 3964:                  0x00000000);
 3965:     /* XXX : not implemented */
 3966:     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
 3967:                  SPR_NOACCESS, SPR_NOACCESS,
 3968:                  &spr_read_generic, &spr_write_generic,
 3969:                  0x00000000);
 3970:     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
 3971:                  SPR_NOACCESS, SPR_NOACCESS,
 3972:                  &spr_read_generic, &spr_write_generic,
 3973:                  0x00000000);
 3974:     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
 3975:                  SPR_NOACCESS, SPR_NOACCESS,
 3976:                  &spr_read_generic, &spr_write_generic,
 3977:                  0x00000000);
 3978:     /* XXX : not implemented */
 3979:     spr_register(env, SPR_440_CCR1, "CCR1",
 3980:                  SPR_NOACCESS, SPR_NOACCESS,
 3981:                  &spr_read_generic, &spr_write_generic,
 3982:                  0x00000000);
 3983:     /* XXX : not implemented */
 3984:     spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
 3985:                  &spr_read_generic, &spr_write_generic,
 3986:                  &spr_read_generic, &spr_write_generic,
 3987:                  0x00000000);
 3988:     /* Memory management */
 3989: #if !defined(CONFIG_USER_ONLY)
 3990:     env->nb_tlb = 64;
 3991:     env->nb_ways = 1;
 3992:     env->id_tlbs = 0;
 3993:     env->tlb_type = TLB_EMB;
 3994: #endif
 3995:     init_excp_BookE(env);
 3996:     env->dcache_line_size = 32;
 3997:     env->icache_line_size = 32;
 3998:     /* XXX: TODO: allocate internal IRQ controller */
 3999: 
 4000:     SET_FIT_PERIOD(12, 16, 20, 24);
 4001:     SET_WDT_PERIOD(20, 24, 28, 32);
 4002: }
 4003: 
 4004: /* Freescale 5xx cores (aka RCPU) */
 4005: #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING |                   \
 4006:                               PPC_MEM_EIEIO | PPC_MEM_SYNC |                  \
 4007:                               PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
 4008:                               PPC_MFTB)
 4009: #define POWERPC_INSNS2_MPC5xx (PPC_NONE)
 4010: #define POWERPC_MSRM_MPC5xx  (0x000000000001FF43ULL)
 4011: #define POWERPC_MMU_MPC5xx   (POWERPC_MMU_REAL)
 4012: #define POWERPC_EXCP_MPC5xx  (POWERPC_EXCP_603)
 4013: #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
 4014: #define POWERPC_BFDM_MPC5xx  (bfd_mach_ppc_505)
 4015: #define POWERPC_FLAG_MPC5xx  (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
 4016:                               POWERPC_FLAG_BUS_CLK)
 4017: #define check_pow_MPC5xx     check_pow_none
 4018: 
 4019: __attribute__ (( unused ))
 4020: static void init_proc_MPC5xx (CPUPPCState *env)
 4021: {
 4022:     /* Time base */
 4023:     gen_tbl(env);
 4024:     gen_spr_5xx_8xx(env);
 4025:     gen_spr_5xx(env);
 4026:     init_excp_MPC5xx(env);
 4027:     env->dcache_line_size = 32;
 4028:     env->icache_line_size = 32;
 4029:     /* XXX: TODO: allocate internal IRQ controller */
 4030: }
 4031: 
 4032: /* Freescale 8xx cores (aka PowerQUICC) */
 4033: #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING  |                  \
 4034:                               PPC_MEM_EIEIO | PPC_MEM_SYNC |                  \
 4035:                               PPC_CACHE_ICBI | PPC_MFTB)
 4036: #define POWERPC_INSNS2_MPC8xx (PPC_NONE)
 4037: #define POWERPC_MSRM_MPC8xx  (0x000000000001F673ULL)
 4038: #define POWERPC_MMU_MPC8xx   (POWERPC_MMU_MPC8xx)
 4039: #define POWERPC_EXCP_MPC8xx  (POWERPC_EXCP_603)
 4040: #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
 4041: #define POWERPC_BFDM_MPC8xx  (bfd_mach_ppc_860)
 4042: #define POWERPC_FLAG_MPC8xx  (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
 4043:                               POWERPC_FLAG_BUS_CLK)
 4044: #define check_pow_MPC8xx     check_pow_none
 4045: 
 4046: __attribute__ (( unused ))
 4047: static void init_proc_MPC8xx (CPUPPCState *env)
 4048: {
 4049:     /* Time base */
 4050:     gen_tbl(env);
 4051:     gen_spr_5xx_8xx(env);
 4052:     gen_spr_8xx(env);
 4053:     init_excp_MPC8xx(env);
 4054:     env->dcache_line_size = 32;
 4055:     env->icache_line_size = 32;
 4056:     /* XXX: TODO: allocate internal IRQ controller */
 4057: }
 4058: 
 4059: /* Freescale 82xx cores (aka PowerQUICC-II)                                  */
 4060: /* PowerPC G2                                                                */
 4061: #define POWERPC_INSNS_G2     (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 4062:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 4063:                               PPC_FLOAT_STFIWX |                              \
 4064:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
 4065:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 4066:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
 4067:                               PPC_SEGMENT | PPC_EXTERN)
 4068: #define POWERPC_INSNS2_G2    (PPC_NONE)
 4069: #define POWERPC_MSRM_G2      (0x000000000006FFF2ULL)
 4070: #define POWERPC_MMU_G2       (POWERPC_MMU_SOFT_6xx)
 4071: //#define POWERPC_EXCP_G2      (POWERPC_EXCP_G2)
 4072: #define POWERPC_INPUT_G2     (PPC_FLAGS_INPUT_6xx)
 4073: #define POWERPC_BFDM_G2      (bfd_mach_ppc_ec603e)
 4074: #define POWERPC_FLAG_G2      (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
 4075:                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
 4076: #define check_pow_G2         check_pow_hid0
 4077: 
 4078: static void init_proc_G2 (CPUPPCState *env)
 4079: {
 4080:     gen_spr_ne_601(env);
 4081:     gen_spr_G2_755(env);
 4082:     gen_spr_G2(env);
 4083:     /* Time base */
 4084:     gen_tbl(env);
 4085:     /* External access control */
 4086:     /* XXX : not implemented */
 4087:     spr_register(env, SPR_EAR, "EAR",
 4088:                  SPR_NOACCESS, SPR_NOACCESS,
 4089:                  &spr_read_generic, &spr_write_generic,
 4090:                  0x00000000);
 4091:     /* Hardware implementation register */
 4092:     /* XXX : not implemented */
 4093:     spr_register(env, SPR_HID0, "HID0",
 4094:                  SPR_NOACCESS, SPR_NOACCESS,
 4095:                  &spr_read_generic, &spr_write_generic,
 4096:                  0x00000000);
 4097:     /* XXX : not implemented */
 4098:     spr_register(env, SPR_HID1, "HID1",
 4099:                  SPR_NOACCESS, SPR_NOACCESS,
 4100:                  &spr_read_generic, &spr_write_generic,
 4101:                  0x00000000);
 4102:     /* XXX : not implemented */
 4103:     spr_register(env, SPR_HID2, "HID2",
 4104:                  SPR_NOACCESS, SPR_NOACCESS,
 4105:                  &spr_read_generic, &spr_write_generic,
 4106:                  0x00000000);
 4107:     /* Memory management */
 4108:     gen_low_BATs(env);
 4109:     gen_high_BATs(env);
 4110:     gen_6xx_7xx_soft_tlb(env, 64, 2);
 4111:     init_excp_G2(env);
 4112:     env->dcache_line_size = 32;
 4113:     env->icache_line_size = 32;
 4114:     /* Allocate hardware IRQ controller */
 4115:     ppc6xx_irq_init(env);
 4116: }
 4117: 
 4118: /* PowerPC G2LE                                                              */
 4119: #define POWERPC_INSNS_G2LE   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 4120:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 4121:                               PPC_FLOAT_STFIWX |                              \
 4122:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
 4123:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 4124:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
 4125:                               PPC_SEGMENT | PPC_EXTERN)
 4126: #define POWERPC_INSNS2_G2LE  (PPC_NONE)
 4127: #define POWERPC_MSRM_G2LE    (0x000000000007FFF3ULL)
 4128: #define POWERPC_MMU_G2LE     (POWERPC_MMU_SOFT_6xx)
 4129: #define POWERPC_EXCP_G2LE    (POWERPC_EXCP_G2)
 4130: #define POWERPC_INPUT_G2LE   (PPC_FLAGS_INPUT_6xx)
 4131: #define POWERPC_BFDM_G2LE    (bfd_mach_ppc_ec603e)
 4132: #define POWERPC_FLAG_G2LE    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
 4133:                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
 4134: #define check_pow_G2LE       check_pow_hid0
 4135: 
 4136: static void init_proc_G2LE (CPUPPCState *env)
 4137: {
 4138:     gen_spr_ne_601(env);
 4139:     gen_spr_G2_755(env);
 4140:     gen_spr_G2(env);
 4141:     /* Time base */
 4142:     gen_tbl(env);
 4143:     /* External access control */
 4144:     /* XXX : not implemented */
 4145:     spr_register(env, SPR_EAR, "EAR",
 4146:                  SPR_NOACCESS, SPR_NOACCESS,
 4147:                  &spr_read_generic, &spr_write_generic,
 4148:                  0x00000000);
 4149:     /* Hardware implementation register */
 4150:     /* XXX : not implemented */
 4151:     spr_register(env, SPR_HID0, "HID0",
 4152:                  SPR_NOACCESS, SPR_NOACCESS,
 4153:                  &spr_read_generic, &spr_write_generic,
 4154:                  0x00000000);
 4155:     /* XXX : not implemented */
 4156:     spr_register(env, SPR_HID1, "HID1",
 4157:                  SPR_NOACCESS, SPR_NOACCESS,
 4158:                  &spr_read_generic, &spr_write_generic,
 4159:                  0x00000000);
 4160:     /* XXX : not implemented */
 4161:     spr_register(env, SPR_HID2, "HID2",
 4162:                  SPR_NOACCESS, SPR_NOACCESS,
 4163:                  &spr_read_generic, &spr_write_generic,
 4164:                  0x00000000);
 4165:     /* Memory management */
 4166:     gen_low_BATs(env);
 4167:     gen_high_BATs(env);
 4168:     gen_6xx_7xx_soft_tlb(env, 64, 2);
 4169:     init_excp_G2(env);
 4170:     env->dcache_line_size = 32;
 4171:     env->icache_line_size = 32;
 4172:     /* Allocate hardware IRQ controller */
 4173:     ppc6xx_irq_init(env);
 4174: }
 4175: 
 4176: /* e200 core                                                                 */
 4177: /* XXX: unimplemented instructions:
 4178:  * dcblc
 4179:  * dcbtlst
 4180:  * dcbtstls
 4181:  * icblc
 4182:  * icbtls
 4183:  * tlbivax
 4184:  * all SPE multiply-accumulate instructions
 4185:  */
 4186: #define POWERPC_INSNS_e200   (PPC_INSNS_BASE | PPC_ISEL |                     \
 4187:                               PPC_SPE | PPC_SPE_SINGLE |                      \
 4188:                               PPC_WRTEE | PPC_RFDI |                          \
 4189:                               PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |   \
 4190:                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
 4191:                               PPC_MEM_TLBSYNC | PPC_TLBIVAX |                 \
 4192:                               PPC_BOOKE)
 4193: #define POWERPC_INSNS2_e200  (PPC_NONE)
 4194: #define POWERPC_MSRM_e200    (0x000000000606FF30ULL)
 4195: #define POWERPC_MMU_e200     (POWERPC_MMU_BOOKE206)
 4196: #define POWERPC_EXCP_e200    (POWERPC_EXCP_BOOKE)
 4197: #define POWERPC_INPUT_e200   (PPC_FLAGS_INPUT_BookE)
 4198: #define POWERPC_BFDM_e200    (bfd_mach_ppc_860)
 4199: #define POWERPC_FLAG_e200    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |            \
 4200:                               POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |           \
 4201:                               POWERPC_FLAG_BUS_CLK)
 4202: #define check_pow_e200       check_pow_hid0
 4203: 
 4204: __attribute__ (( unused ))
 4205: static void init_proc_e200 (CPUPPCState *env)
 4206: {
 4207:     /* Time base */
 4208:     gen_tbl(env);
 4209:     gen_spr_BookE(env, 0x000000070000FFFFULL);
 4210:     /* XXX : not implemented */
 4211:     spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
 4212:                  &spr_read_spefscr, &spr_write_spefscr,
 4213:                  &spr_read_spefscr, &spr_write_spefscr,
 4214:                  0x00000000);
 4215:     /* Memory management */
 4216:     gen_spr_BookE206(env, 0x0000005D, NULL);
 4217:     /* XXX : not implemented */
 4218:     spr_register(env, SPR_HID0, "HID0",
 4219:                  SPR_NOACCESS, SPR_NOACCESS,
 4220:                  &spr_read_generic, &spr_write_generic,
 4221:                  0x00000000);
 4222:     /* XXX : not implemented */
 4223:     spr_register(env, SPR_HID1, "HID1",
 4224:                  SPR_NOACCESS, SPR_NOACCESS,
 4225:                  &spr_read_generic, &spr_write_generic,
 4226:                  0x00000000);
 4227:     /* XXX : not implemented */
 4228:     spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
 4229:                  SPR_NOACCESS, SPR_NOACCESS,
 4230:                  &spr_read_generic, &spr_write_generic,
 4231:                  0x00000000);
 4232:     /* XXX : not implemented */
 4233:     spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
 4234:                  SPR_NOACCESS, SPR_NOACCESS,
 4235:                  &spr_read_generic, &spr_write_generic,
 4236:                  0x00000000);
 4237:     /* XXX : not implemented */
 4238:     spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
 4239:                  SPR_NOACCESS, SPR_NOACCESS,
 4240:                  &spr_read_generic, &spr_write_generic,
 4241:                  0x00000000);
 4242:     /* XXX : not implemented */
 4243:     spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
 4244:                  SPR_NOACCESS, SPR_NOACCESS,
 4245:                  &spr_read_generic, &spr_write_generic,
 4246:                  0x00000000);
 4247:     /* XXX : not implemented */
 4248:     spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
 4249:                  SPR_NOACCESS, SPR_NOACCESS,
 4250:                  &spr_read_generic, &spr_write_generic,
 4251:                  0x00000000);
 4252:     /* XXX : not implemented */
 4253:     spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
 4254:                  SPR_NOACCESS, SPR_NOACCESS,
 4255:                  &spr_read_generic, &spr_write_generic,
 4256:                  0x00000000);
 4257:     /* XXX : not implemented */
 4258:     spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
 4259:                  SPR_NOACCESS, SPR_NOACCESS,
 4260:                  &spr_read_generic, &spr_write_generic,
 4261:                  0x00000000);
 4262:     /* XXX : not implemented */
 4263:     spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
 4264:                  SPR_NOACCESS, SPR_NOACCESS,
 4265:                  &spr_read_generic, &spr_write_generic,
 4266:                  0x00000000);
 4267:     /* XXX : not implemented */
 4268:     spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
 4269:                  SPR_NOACCESS, SPR_NOACCESS,
 4270:                  &spr_read_generic, &spr_write_generic,
 4271:                  0x00000000);
 4272:     /* XXX : not implemented */
 4273:     spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
 4274:                  SPR_NOACCESS, SPR_NOACCESS,
 4275:                  &spr_read_generic, &spr_write_generic,
 4276:                  0x00000000);
 4277:     /* XXX : not implemented */
 4278:     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
 4279:                  SPR_NOACCESS, SPR_NOACCESS,
 4280:                  &spr_read_generic, &spr_write_generic,
 4281:                  0x00000000);
 4282:     /* XXX : not implemented */
 4283:     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
 4284:                  SPR_NOACCESS, SPR_NOACCESS,
 4285:                  &spr_read_generic, &spr_write_generic,
 4286:                  0x00000000);
 4287:     /* XXX : not implemented */
 4288:     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
 4289:                  SPR_NOACCESS, SPR_NOACCESS,
 4290:                  &spr_read_generic, &spr_write_generic,
 4291:                  0x00000000); /* TOFIX */
 4292:     spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
 4293:                  SPR_NOACCESS, SPR_NOACCESS,
 4294:                  &spr_read_generic, &spr_write_generic,
 4295:                  0x00000000);
 4296:     spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
 4297:                  SPR_NOACCESS, SPR_NOACCESS,
 4298:                  &spr_read_generic, &spr_write_generic,
 4299:                  0x00000000);
 4300: #if !defined(CONFIG_USER_ONLY)
 4301:     env->nb_tlb = 64;
 4302:     env->nb_ways = 1;
 4303:     env->id_tlbs = 0;
 4304:     env->tlb_type = TLB_EMB;
 4305: #endif
 4306:     init_excp_e200(env);
 4307:     env->dcache_line_size = 32;
 4308:     env->icache_line_size = 32;
 4309:     /* XXX: TODO: allocate internal IRQ controller */
 4310: }
 4311: 
 4312: /* e300 core                                                                 */
 4313: #define POWERPC_INSNS_e300   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 4314:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 4315:                               PPC_FLOAT_STFIWX |                              \
 4316:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
 4317:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 4318:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
 4319:                               PPC_SEGMENT | PPC_EXTERN)
 4320: #define POWERPC_INSNS2_e300  (PPC_NONE)
 4321: #define POWERPC_MSRM_e300    (0x000000000007FFF3ULL)
 4322: #define POWERPC_MMU_e300     (POWERPC_MMU_SOFT_6xx)
 4323: #define POWERPC_EXCP_e300    (POWERPC_EXCP_603)
 4324: #define POWERPC_INPUT_e300   (PPC_FLAGS_INPUT_6xx)
 4325: #define POWERPC_BFDM_e300    (bfd_mach_ppc_603)
 4326: #define POWERPC_FLAG_e300    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
 4327:                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
 4328: #define check_pow_e300       check_pow_hid0
 4329: 
 4330: __attribute__ (( unused ))
 4331: static void init_proc_e300 (CPUPPCState *env)
 4332: {
 4333:     gen_spr_ne_601(env);
 4334:     gen_spr_603(env);
 4335:     /* Time base */
 4336:     gen_tbl(env);
 4337:     /* hardware implementation registers */
 4338:     /* XXX : not implemented */
 4339:     spr_register(env, SPR_HID0, "HID0",
 4340:                  SPR_NOACCESS, SPR_NOACCESS,
 4341:                  &spr_read_generic, &spr_write_generic,
 4342:                  0x00000000);
 4343:     /* XXX : not implemented */
 4344:     spr_register(env, SPR_HID1, "HID1",
 4345:                  SPR_NOACCESS, SPR_NOACCESS,
 4346:                  &spr_read_generic, &spr_write_generic,
 4347:                  0x00000000);
 4348:     /* XXX : not implemented */
 4349:     spr_register(env, SPR_HID2, "HID2",
 4350:                  SPR_NOACCESS, SPR_NOACCESS,
 4351:                  &spr_read_generic, &spr_write_generic,
 4352:                  0x00000000);
 4353:     /* Memory management */
 4354:     gen_low_BATs(env);
 4355:     gen_high_BATs(env);
 4356:     gen_6xx_7xx_soft_tlb(env, 64, 2);
 4357:     init_excp_603(env);
 4358:     env->dcache_line_size = 32;
 4359:     env->icache_line_size = 32;
 4360:     /* Allocate hardware IRQ controller */
 4361:     ppc6xx_irq_init(env);
 4362: }
 4363: 
 4364: /* e500v1 core                                                               */
 4365: #define POWERPC_INSNS_e500v1   (PPC_INSNS_BASE | PPC_ISEL |             \
 4366:                                 PPC_SPE | PPC_SPE_SINGLE |              \
 4367:                                 PPC_WRTEE | PPC_RFDI |                  \
 4368:                                 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
 4369:                                 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |       \
 4370:                                 PPC_MEM_TLBSYNC | PPC_TLBIVAX)
 4371: #define POWERPC_INSNS2_e500v1  (PPC2_BOOKE206)
 4372: #define POWERPC_MSRM_e500v1    (0x000000000606FF30ULL)
 4373: #define POWERPC_MMU_e500v1     (POWERPC_MMU_BOOKE206)
 4374: #define POWERPC_EXCP_e500v1    (POWERPC_EXCP_BOOKE)
 4375: #define POWERPC_INPUT_e500v1   (PPC_FLAGS_INPUT_BookE)
 4376: #define POWERPC_BFDM_e500v1    (bfd_mach_ppc_860)
 4377: #define POWERPC_FLAG_e500v1    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |    \
 4378:                                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |   \
 4379:                                 POWERPC_FLAG_BUS_CLK)
 4380: #define check_pow_e500v1       check_pow_hid0
 4381: #define init_proc_e500v1       init_proc_e500v1
 4382: 
 4383: /* e500v2 core                                                               */
 4384: #define POWERPC_INSNS_e500v2   (PPC_INSNS_BASE | PPC_ISEL |             \
 4385:                                 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |   \
 4386:                                 PPC_WRTEE | PPC_RFDI |                  \
 4387:                                 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
 4388:                                 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |       \
 4389:                                 PPC_MEM_TLBSYNC | PPC_TLBIVAX)
 4390: #define POWERPC_INSNS2_e500v2  (PPC2_BOOKE206)
 4391: #define POWERPC_MSRM_e500v2    (0x000000000606FF30ULL)
 4392: #define POWERPC_MMU_e500v2     (POWERPC_MMU_BOOKE206)
 4393: #define POWERPC_EXCP_e500v2    (POWERPC_EXCP_BOOKE)
 4394: #define POWERPC_INPUT_e500v2   (PPC_FLAGS_INPUT_BookE)
 4395: #define POWERPC_BFDM_e500v2    (bfd_mach_ppc_860)
 4396: #define POWERPC_FLAG_e500v2    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |    \
 4397:                                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |   \
 4398:                                 POWERPC_FLAG_BUS_CLK)
 4399: #define check_pow_e500v2       check_pow_hid0
 4400: #define init_proc_e500v2       init_proc_e500v2
 4401: 
 4402: static void init_proc_e500 (CPUPPCState *env, int version)
 4403: {
 4404:     uint32_t tlbncfg[2];
 4405: #if !defined(CONFIG_USER_ONLY)
 4406:     int i;
 4407: #endif
 4408: 
 4409:     /* Time base */
 4410:     gen_tbl(env);
 4411:     /*
 4412:      * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
 4413:      *     complain when accessing them.
 4414:      * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
 4415:      */
 4416:     gen_spr_BookE(env, 0x0000000F0000FFFFULL);
 4417:     /* Processor identification */
 4418:     spr_register(env, SPR_BOOKE_PIR, "PIR",
 4419:                  SPR_NOACCESS, SPR_NOACCESS,
 4420:                  &spr_read_generic, &spr_write_pir,
 4421:                  0x00000000);
 4422:     /* XXX : not implemented */
 4423:     spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
 4424:                  &spr_read_spefscr, &spr_write_spefscr,
 4425:                  &spr_read_spefscr, &spr_write_spefscr,
 4426:                  0x00000000);
 4427:     /* Memory management */
 4428: #if !defined(CONFIG_USER_ONLY)
 4429:     env->nb_pids = 3;
 4430:     env->nb_ways = 2;
 4431:     env->id_tlbs = 0;
 4432:     switch (version) {
 4433:     case 1:
 4434:         /* e500v1 */
 4435:         tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
 4436:         tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
 4437:         break;
 4438:     case 2:
 4439:         /* e500v2 */
 4440:         tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
 4441:         tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
 4442:         break;
 4443:     default:
 4444:         cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
 4445:     }
 4446: #endif
 4447:     gen_spr_BookE206(env, 0x000000DF, tlbncfg);
 4448:     /* XXX : not implemented */
 4449:     spr_register(env, SPR_HID0, "HID0",
 4450:                  SPR_NOACCESS, SPR_NOACCESS,
 4451:                  &spr_read_generic, &spr_write_generic,
 4452:                  0x00000000);
 4453:     /* XXX : not implemented */
 4454:     spr_register(env, SPR_HID1, "HID1",
 4455:                  SPR_NOACCESS, SPR_NOACCESS,
 4456:                  &spr_read_generic, &spr_write_generic,
 4457:                  0x00000000);
 4458:     /* XXX : not implemented */
 4459:     spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
 4460:                  SPR_NOACCESS, SPR_NOACCESS,
 4461:                  &spr_read_generic, &spr_write_generic,
 4462:                  0x00000000);
 4463:     /* XXX : not implemented */
 4464:     spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
 4465:                  SPR_NOACCESS, SPR_NOACCESS,
 4466:                  &spr_read_generic, &spr_write_generic,
 4467:                  0x00000000);
 4468:     /* XXX : not implemented */
 4469:     spr_register(env, SPR_Exxx_MCAR, "MCAR",
 4470:                  SPR_NOACCESS, SPR_NOACCESS,
 4471:                  &spr_read_generic, &spr_write_generic,
 4472:                  0x00000000);
 4473:     /* XXX : not implemented */
 4474:     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
 4475:                  SPR_NOACCESS, SPR_NOACCESS,
 4476:                  &spr_read_generic, &spr_write_generic,
 4477:                  0x00000000);
 4478:     /* XXX : not implemented */
 4479:     spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
 4480:                  SPR_NOACCESS, SPR_NOACCESS,
 4481:                  &spr_read_generic, &spr_write_generic,
 4482:                  0x00000000);
 4483:     /* XXX : not implemented */
 4484:     spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
 4485:                  SPR_NOACCESS, SPR_NOACCESS,
 4486:                  &spr_read_generic, &spr_write_generic,
 4487:                  0x00000000);
 4488:     /* XXX : not implemented */
 4489:     spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
 4490:                  SPR_NOACCESS, SPR_NOACCESS,
 4491:                  &spr_read_generic, &spr_write_generic,
 4492:                  0x00000000);
 4493:     /* XXX : not implemented */
 4494:     spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
 4495:                  SPR_NOACCESS, SPR_NOACCESS,
 4496:                  &spr_read_generic, &spr_write_e500_l1csr0,
 4497:                  0x00000000);
 4498:     /* XXX : not implemented */
 4499:     spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
 4500:                  SPR_NOACCESS, SPR_NOACCESS,
 4501:                  &spr_read_generic, &spr_write_generic,
 4502:                  0x00000000);
 4503:     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
 4504:                  SPR_NOACCESS, SPR_NOACCESS,
 4505:                  &spr_read_generic, &spr_write_generic,
 4506:                  0x00000000);
 4507:     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
 4508:                  SPR_NOACCESS, SPR_NOACCESS,
 4509:                  &spr_read_generic, &spr_write_generic,
 4510:                  0x00000000);
 4511:     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
 4512:                  SPR_NOACCESS, SPR_NOACCESS,
 4513:                  &spr_read_generic, &spr_write_booke206_mmucsr0,
 4514:                  0x00000000);
 4515: 
 4516: #if !defined(CONFIG_USER_ONLY)
 4517:     env->nb_tlb = 0;
 4518:     env->tlb_type = TLB_MAS;
 4519:     for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
 4520:         env->nb_tlb += booke206_tlb_size(env, i);
 4521:     }
 4522: #endif
 4523: 
 4524:     init_excp_e200(env);
 4525:     env->dcache_line_size = 32;
 4526:     env->icache_line_size = 32;
 4527:     /* Allocate hardware IRQ controller */
 4528:     ppce500_irq_init(env);
 4529: }
 4530: 
 4531: static void init_proc_e500v1(CPUPPCState *env)
 4532: {
 4533:     init_proc_e500(env, 1);
 4534: }
 4535: 
 4536: static void init_proc_e500v2(CPUPPCState *env)
 4537: {
 4538:     init_proc_e500(env, 2);
 4539: }
 4540: 
 4541: /* Non-embedded PowerPC                                                      */
 4542: 
 4543: /* POWER : same as 601, without mfmsr, mfsr                                  */
 4544: #if defined(TODO)
 4545: #define POWERPC_INSNS_POWER  (XXX_TODO)
 4546: /* POWER RSC (from RAD6000) */
 4547: #define POWERPC_MSRM_POWER   (0x00000000FEF0ULL)
 4548: #endif /* TODO */
 4549: 
 4550: /* PowerPC 601                                                               */
 4551: #define POWERPC_INSNS_601    (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |    \
 4552:                               PPC_FLOAT |                                     \
 4553:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
 4554:                               PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |  \
 4555:                               PPC_SEGMENT | PPC_EXTERN)
 4556: #define POWERPC_INSNS2_601   (PPC_NONE)
 4557: #define POWERPC_MSRM_601     (0x000000000000FD70ULL)
 4558: #define POWERPC_MSRR_601     (0x0000000000001040ULL)
 4559: //#define POWERPC_MMU_601      (POWERPC_MMU_601)
 4560: //#define POWERPC_EXCP_601     (POWERPC_EXCP_601)
 4561: #define POWERPC_INPUT_601    (PPC_FLAGS_INPUT_6xx)
 4562: #define POWERPC_BFDM_601     (bfd_mach_ppc_601)
 4563: #define POWERPC_FLAG_601     (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
 4564: #define check_pow_601        check_pow_none
 4565: 
 4566: static void init_proc_601 (CPUPPCState *env)
 4567: {
 4568:     gen_spr_ne_601(env);
 4569:     gen_spr_601(env);
 4570:     /* Hardware implementation registers */
 4571:     /* XXX : not implemented */
 4572:     spr_register(env, SPR_HID0, "HID0",
 4573:                  SPR_NOACCESS, SPR_NOACCESS,
 4574:                  &spr_read_generic, &spr_write_hid0_601,
 4575:                  0x80010080);
 4576:     /* XXX : not implemented */
 4577:     spr_register(env, SPR_HID1, "HID1",
 4578:                  SPR_NOACCESS, SPR_NOACCESS,
 4579:                  &spr_read_generic, &spr_write_generic,
 4580:                  0x00000000);
 4581:     /* XXX : not implemented */
 4582:     spr_register(env, SPR_601_HID2, "HID2",
 4583:                  SPR_NOACCESS, SPR_NOACCESS,
 4584:                  &spr_read_generic, &spr_write_generic,
 4585:                  0x00000000);
 4586:     /* XXX : not implemented */
 4587:     spr_register(env, SPR_601_HID5, "HID5",
 4588:                  SPR_NOACCESS, SPR_NOACCESS,
 4589:                  &spr_read_generic, &spr_write_generic,
 4590:                  0x00000000);
 4591:     /* Memory management */
 4592:     init_excp_601(env);
 4593:     /* XXX: beware that dcache line size is 64 
 4594:      *      but dcbz uses 32 bytes "sectors"
 4595:      * XXX: this breaks clcs instruction !
 4596:      */
 4597:     env->dcache_line_size = 32;
 4598:     env->icache_line_size = 64;
 4599:     /* Allocate hardware IRQ controller */
 4600:     ppc6xx_irq_init(env);
 4601: }
 4602: 
 4603: /* PowerPC 601v                                                              */
 4604: #define POWERPC_INSNS_601v   (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |    \
 4605:                               PPC_FLOAT |                                     \
 4606:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
 4607:                               PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |  \
 4608:                               PPC_SEGMENT | PPC_EXTERN)
 4609: #define POWERPC_INSNS2_601v  (PPC_NONE)
 4610: #define POWERPC_MSRM_601v    (0x000000000000FD70ULL)
 4611: #define POWERPC_MSRR_601v    (0x0000000000001040ULL)
 4612: #define POWERPC_MMU_601v     (POWERPC_MMU_601)
 4613: #define POWERPC_EXCP_601v    (POWERPC_EXCP_601)
 4614: #define POWERPC_INPUT_601v   (PPC_FLAGS_INPUT_6xx)
 4615: #define POWERPC_BFDM_601v    (bfd_mach_ppc_601)
 4616: #define POWERPC_FLAG_601v    (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
 4617: #define check_pow_601v       check_pow_none
 4618: 
 4619: static void init_proc_601v (CPUPPCState *env)
 4620: {
 4621:     init_proc_601(env);
 4622:     /* XXX : not implemented */
 4623:     spr_register(env, SPR_601_HID15, "HID15",
 4624:                  SPR_NOACCESS, SPR_NOACCESS,
 4625:                  &spr_read_generic, &spr_write_generic,
 4626:                  0x00000000);
 4627: }
 4628: 
 4629: /* PowerPC 602                                                               */
 4630: #define POWERPC_INSNS_602    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 4631:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 4632:                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
 4633:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
 4634:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 4635:                               PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
 4636:                               PPC_SEGMENT | PPC_602_SPEC)
 4637: #define POWERPC_INSNS2_602   (PPC_NONE)
 4638: #define POWERPC_MSRM_602     (0x0000000000C7FF73ULL)
 4639: /* XXX: 602 MMU is quite specific. Should add a special case */
 4640: #define POWERPC_MMU_602      (POWERPC_MMU_SOFT_6xx)
 4641: //#define POWERPC_EXCP_602     (POWERPC_EXCP_602)
 4642: #define POWERPC_INPUT_602    (PPC_FLAGS_INPUT_6xx)
 4643: #define POWERPC_BFDM_602     (bfd_mach_ppc_602)
 4644: #define POWERPC_FLAG_602     (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
 4645:                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
 4646: #define check_pow_602        check_pow_hid0
 4647: 
 4648: static void init_proc_602 (CPUPPCState *env)
 4649: {
 4650:     gen_spr_ne_601(env);
 4651:     gen_spr_602(env);
 4652:     /* Time base */
 4653:     gen_tbl(env);
 4654:     /* hardware implementation registers */
 4655:     /* XXX : not implemented */
 4656:     spr_register(env, SPR_HID0, "HID0",
 4657:                  SPR_NOACCESS, SPR_NOACCESS,
 4658:                  &spr_read_generic, &spr_write_generic,
 4659:                  0x00000000);
 4660:     /* XXX : not implemented */
 4661:     spr_register(env, SPR_HID1, "HID1",
 4662:                  SPR_NOACCESS, SPR_NOACCESS,
 4663:                  &spr_read_generic, &spr_write_generic,
 4664:                  0x00000000);
 4665:     /* Memory management */
 4666:     gen_low_BATs(env);
 4667:     gen_6xx_7xx_soft_tlb(env, 64, 2);
 4668:     init_excp_602(env);
 4669:     env->dcache_line_size = 32;
 4670:     env->icache_line_size = 32;
 4671:     /* Allocate hardware IRQ controller */
 4672:     ppc6xx_irq_init(env);
 4673: }
 4674: 
 4675: /* PowerPC 603                                                               */
 4676: #define POWERPC_INSNS_603    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 4677:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 4678:                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
 4679:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
 4680:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 4681:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
 4682:                               PPC_SEGMENT | PPC_EXTERN)
 4683: #define POWERPC_INSNS2_603   (PPC_NONE)
 4684: #define POWERPC_MSRM_603     (0x000000000007FF73ULL)
 4685: #define POWERPC_MMU_603      (POWERPC_MMU_SOFT_6xx)
 4686: //#define POWERPC_EXCP_603     (POWERPC_EXCP_603)
 4687: #define POWERPC_INPUT_603    (PPC_FLAGS_INPUT_6xx)
 4688: #define POWERPC_BFDM_603     (bfd_mach_ppc_603)
 4689: #define POWERPC_FLAG_603     (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
 4690:                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
 4691: #define check_pow_603        check_pow_hid0
 4692: 
 4693: static void init_proc_603 (CPUPPCState *env)
 4694: {
 4695:     gen_spr_ne_601(env);
 4696:     gen_spr_603(env);
 4697:     /* Time base */
 4698:     gen_tbl(env);
 4699:     /* hardware implementation registers */
 4700:     /* XXX : not implemented */
 4701:     spr_register(env, SPR_HID0, "HID0",
 4702:                  SPR_NOACCESS, SPR_NOACCESS,
 4703:                  &spr_read_generic, &spr_write_generic,
 4704:                  0x00000000);
 4705:     /* XXX : not implemented */
 4706:     spr_register(env, SPR_HID1, "HID1",
 4707:                  SPR_NOACCESS, SPR_NOACCESS,
 4708:                  &spr_read_generic, &spr_write_generic,
 4709:                  0x00000000);
 4710:     /* Memory management */
 4711:     gen_low_BATs(env);
 4712:     gen_6xx_7xx_soft_tlb(env, 64, 2);
 4713:     init_excp_603(env);
 4714:     env->dcache_line_size = 32;
 4715:     env->icache_line_size = 32;
 4716:     /* Allocate hardware IRQ controller */
 4717:     ppc6xx_irq_init(env);
 4718: }
 4719: 
 4720: /* PowerPC 603e                                                              */
 4721: #define POWERPC_INSNS_603E   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 4722:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 4723:                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
 4724:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
 4725:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 4726:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
 4727:                               PPC_SEGMENT | PPC_EXTERN)
 4728: #define POWERPC_INSNS2_603E  (PPC_NONE)
 4729: #define POWERPC_MSRM_603E    (0x000000000007FF73ULL)
 4730: #define POWERPC_MMU_603E     (POWERPC_MMU_SOFT_6xx)
 4731: //#define POWERPC_EXCP_603E    (POWERPC_EXCP_603E)
 4732: #define POWERPC_INPUT_603E   (PPC_FLAGS_INPUT_6xx)
 4733: #define POWERPC_BFDM_603E    (bfd_mach_ppc_ec603e)
 4734: #define POWERPC_FLAG_603E    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
 4735:                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
 4736: #define check_pow_603E       check_pow_hid0
 4737: 
 4738: static void init_proc_603E (CPUPPCState *env)
 4739: {
 4740:     gen_spr_ne_601(env);
 4741:     gen_spr_603(env);
 4742:     /* Time base */
 4743:     gen_tbl(env);
 4744:     /* hardware implementation registers */
 4745:     /* XXX : not implemented */
 4746:     spr_register(env, SPR_HID0, "HID0",
 4747:                  SPR_NOACCESS, SPR_NOACCESS,
 4748:                  &spr_read_generic, &spr_write_generic,
 4749:                  0x00000000);
 4750:     /* XXX : not implemented */
 4751:     spr_register(env, SPR_HID1, "HID1",
 4752:                  SPR_NOACCESS, SPR_NOACCESS,
 4753:                  &spr_read_generic, &spr_write_generic,
 4754:                  0x00000000);
 4755:     /* XXX : not implemented */
 4756:     spr_register(env, SPR_IABR, "IABR",
 4757:                  SPR_NOACCESS, SPR_NOACCESS,
 4758:                  &spr_read_generic, &spr_write_generic,
 4759:                  0x00000000);
 4760:     /* Memory management */
 4761:     gen_low_BATs(env);
 4762:     gen_6xx_7xx_soft_tlb(env, 64, 2);
 4763:     init_excp_603(env);
 4764:     env->dcache_line_size = 32;
 4765:     env->icache_line_size = 32;
 4766:     /* Allocate hardware IRQ controller */
 4767:     ppc6xx_irq_init(env);
 4768: }
 4769: 
 4770: /* PowerPC 604                                                               */
 4771: #define POWERPC_INSNS_604    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 4772:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 4773:                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
 4774:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
 4775:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 4776:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 4777:                               PPC_SEGMENT | PPC_EXTERN)
 4778: #define POWERPC_INSNS2_604   (PPC_NONE)
 4779: #define POWERPC_MSRM_604     (0x000000000005FF77ULL)
 4780: #define POWERPC_MMU_604      (POWERPC_MMU_32B)
 4781: //#define POWERPC_EXCP_604     (POWERPC_EXCP_604)
 4782: #define POWERPC_INPUT_604    (PPC_FLAGS_INPUT_6xx)
 4783: #define POWERPC_BFDM_604     (bfd_mach_ppc_604)
 4784: #define POWERPC_FLAG_604     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
 4785:                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
 4786: #define check_pow_604        check_pow_nocheck
 4787: 
 4788: static void init_proc_604 (CPUPPCState *env)
 4789: {
 4790:     gen_spr_ne_601(env);
 4791:     gen_spr_604(env);
 4792:     /* Time base */
 4793:     gen_tbl(env);
 4794:     /* Hardware implementation registers */
 4795:     /* XXX : not implemented */
 4796:     spr_register(env, SPR_HID0, "HID0",
 4797:                  SPR_NOACCESS, SPR_NOACCESS,
 4798:                  &spr_read_generic, &spr_write_generic,
 4799:                  0x00000000);
 4800:     /* Memory management */
 4801:     gen_low_BATs(env);
 4802:     init_excp_604(env);
 4803:     env->dcache_line_size = 32;
 4804:     env->icache_line_size = 32;
 4805:     /* Allocate hardware IRQ controller */
 4806:     ppc6xx_irq_init(env);
 4807: }
 4808: 
 4809: /* PowerPC 604E                                                              */
 4810: #define POWERPC_INSNS_604E   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 4811:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 4812:                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
 4813:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
 4814:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 4815:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 4816:                               PPC_SEGMENT | PPC_EXTERN)
 4817: #define POWERPC_INSNS2_604E  (PPC_NONE)
 4818: #define POWERPC_MSRM_604E    (0x000000000005FF77ULL)
 4819: #define POWERPC_MMU_604E     (POWERPC_MMU_32B)
 4820: #define POWERPC_EXCP_604E    (POWERPC_EXCP_604)
 4821: #define POWERPC_INPUT_604E   (PPC_FLAGS_INPUT_6xx)
 4822: #define POWERPC_BFDM_604E    (bfd_mach_ppc_604)
 4823: #define POWERPC_FLAG_604E    (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
 4824:                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
 4825: #define check_pow_604E       check_pow_nocheck
 4826: 
 4827: static void init_proc_604E (CPUPPCState *env)
 4828: {
 4829:     gen_spr_ne_601(env);
 4830:     gen_spr_604(env);
 4831:     /* XXX : not implemented */
 4832:     spr_register(env, SPR_MMCR1, "MMCR1",
 4833:                  SPR_NOACCESS, SPR_NOACCESS,
 4834:                  &spr_read_generic, &spr_write_generic,
 4835:                  0x00000000);
 4836:     /* XXX : not implemented */
 4837:     spr_register(env, SPR_PMC3, "PMC3",
 4838:                  SPR_NOACCESS, SPR_NOACCESS,
 4839:                  &spr_read_generic, &spr_write_generic,
 4840:                  0x00000000);
 4841:     /* XXX : not implemented */
 4842:     spr_register(env, SPR_PMC4, "PMC4",
 4843:                  SPR_NOACCESS, SPR_NOACCESS,
 4844:                  &spr_read_generic, &spr_write_generic,
 4845:                  0x00000000);
 4846:     /* Time base */
 4847:     gen_tbl(env);
 4848:     /* Hardware implementation registers */
 4849:     /* XXX : not implemented */
 4850:     spr_register(env, SPR_HID0, "HID0",
 4851:                  SPR_NOACCESS, SPR_NOACCESS,
 4852:                  &spr_read_generic, &spr_write_generic,
 4853:                  0x00000000);
 4854:     /* XXX : not implemented */
 4855:     spr_register(env, SPR_HID1, "HID1",
 4856:                  SPR_NOACCESS, SPR_NOACCESS,
 4857:                  &spr_read_generic, &spr_write_generic,
 4858:                  0x00000000);
 4859:     /* Memory management */
 4860:     gen_low_BATs(env);
 4861:     init_excp_604(env);
 4862:     env->dcache_line_size = 32;
 4863:     env->icache_line_size = 32;
 4864:     /* Allocate hardware IRQ controller */
 4865:     ppc6xx_irq_init(env);
 4866: }
 4867: 
 4868: /* PowerPC 740                                                               */
 4869: #define POWERPC_INSNS_740    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 4870:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 4871:                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
 4872:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
 4873:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 4874:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 4875:                               PPC_SEGMENT | PPC_EXTERN)
 4876: #define POWERPC_INSNS2_740   (PPC_NONE)
 4877: #define POWERPC_MSRM_740     (0x000000000005FF77ULL)
 4878: #define POWERPC_MMU_740      (POWERPC_MMU_32B)
 4879: #define POWERPC_EXCP_740     (POWERPC_EXCP_7x0)
 4880: #define POWERPC_INPUT_740    (PPC_FLAGS_INPUT_6xx)
 4881: #define POWERPC_BFDM_740     (bfd_mach_ppc_750)
 4882: #define POWERPC_FLAG_740     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
 4883:                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
 4884: #define check_pow_740        check_pow_hid0
 4885: 
 4886: static void init_proc_740 (CPUPPCState *env)
 4887: {
 4888:     gen_spr_ne_601(env);
 4889:     gen_spr_7xx(env);
 4890:     /* Time base */
 4891:     gen_tbl(env);
 4892:     /* Thermal management */
 4893:     gen_spr_thrm(env);
 4894:     /* Hardware implementation registers */
 4895:     /* XXX : not implemented */
 4896:     spr_register(env, SPR_HID0, "HID0",
 4897:                  SPR_NOACCESS, SPR_NOACCESS,
 4898:                  &spr_read_generic, &spr_write_generic,
 4899:                  0x00000000);
 4900:     /* XXX : not implemented */
 4901:     spr_register(env, SPR_HID1, "HID1",
 4902:                  SPR_NOACCESS, SPR_NOACCESS,
 4903:                  &spr_read_generic, &spr_write_generic,
 4904:                  0x00000000);
 4905:     /* Memory management */
 4906:     gen_low_BATs(env);
 4907:     init_excp_7x0(env);
 4908:     env->dcache_line_size = 32;
 4909:     env->icache_line_size = 32;
 4910:     /* Allocate hardware IRQ controller */
 4911:     ppc6xx_irq_init(env);
 4912: }
 4913: 
 4914: /* PowerPC 750                                                               */
 4915: #define POWERPC_INSNS_750    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 4916:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 4917:                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
 4918:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
 4919:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 4920:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 4921:                               PPC_SEGMENT | PPC_EXTERN)
 4922: #define POWERPC_INSNS2_750   (PPC_NONE)
 4923: #define POWERPC_MSRM_750     (0x000000000005FF77ULL)
 4924: #define POWERPC_MMU_750      (POWERPC_MMU_32B)
 4925: #define POWERPC_EXCP_750     (POWERPC_EXCP_7x0)
 4926: #define POWERPC_INPUT_750    (PPC_FLAGS_INPUT_6xx)
 4927: #define POWERPC_BFDM_750     (bfd_mach_ppc_750)
 4928: #define POWERPC_FLAG_750     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
 4929:                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
 4930: #define check_pow_750        check_pow_hid0
 4931: 
 4932: static void init_proc_750 (CPUPPCState *env)
 4933: {
 4934:     gen_spr_ne_601(env);
 4935:     gen_spr_7xx(env);
 4936:     /* XXX : not implemented */
 4937:     spr_register(env, SPR_L2CR, "L2CR",
 4938:                  SPR_NOACCESS, SPR_NOACCESS,
 4939:                  &spr_read_generic, &spr_write_generic,
 4940:                  0x00000000);
 4941:     /* Time base */
 4942:     gen_tbl(env);
 4943:     /* Thermal management */
 4944:     gen_spr_thrm(env);
 4945:     /* Hardware implementation registers */
 4946:     /* XXX : not implemented */
 4947:     spr_register(env, SPR_HID0, "HID0",
 4948:                  SPR_NOACCESS, SPR_NOACCESS,
 4949:                  &spr_read_generic, &spr_write_generic,
 4950:                  0x00000000);
 4951:     /* XXX : not implemented */
 4952:     spr_register(env, SPR_HID1, "HID1",
 4953:                  SPR_NOACCESS, SPR_NOACCESS,
 4954:                  &spr_read_generic, &spr_write_generic,
 4955:                  0x00000000);
 4956:     /* Memory management */
 4957:     gen_low_BATs(env);
 4958:     /* XXX: high BATs are also present but are known to be bugged on
 4959:      *      die version 1.x
 4960:      */
 4961:     init_excp_7x0(env);
 4962:     env->dcache_line_size = 32;
 4963:     env->icache_line_size = 32;
 4964:     /* Allocate hardware IRQ controller */
 4965:     ppc6xx_irq_init(env);
 4966: }
 4967: 
 4968: /* PowerPC 750 CL                                                            */
 4969: /* XXX: not implemented:
 4970:  * cache lock instructions:
 4971:  * dcbz_l
 4972:  * floating point paired instructions
 4973:  * psq_lux
 4974:  * psq_lx
 4975:  * psq_stux
 4976:  * psq_stx
 4977:  * ps_abs
 4978:  * ps_add
 4979:  * ps_cmpo0
 4980:  * ps_cmpo1
 4981:  * ps_cmpu0
 4982:  * ps_cmpu1
 4983:  * ps_div
 4984:  * ps_madd
 4985:  * ps_madds0
 4986:  * ps_madds1
 4987:  * ps_merge00
 4988:  * ps_merge01
 4989:  * ps_merge10
 4990:  * ps_merge11
 4991:  * ps_mr
 4992:  * ps_msub
 4993:  * ps_mul
 4994:  * ps_muls0
 4995:  * ps_muls1
 4996:  * ps_nabs
 4997:  * ps_neg
 4998:  * ps_nmadd
 4999:  * ps_nmsub
 5000:  * ps_res
 5001:  * ps_rsqrte
 5002:  * ps_sel
 5003:  * ps_sub
 5004:  * ps_sum0
 5005:  * ps_sum1
 5006:  */
 5007: #define POWERPC_INSNS_750cl  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 5008:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 5009:                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
 5010:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
 5011:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 5012:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 5013:                               PPC_SEGMENT | PPC_EXTERN)
 5014: #define POWERPC_INSNS2_750cl (PPC_NONE)
 5015: #define POWERPC_MSRM_750cl   (0x000000000005FF77ULL)
 5016: #define POWERPC_MMU_750cl    (POWERPC_MMU_32B)
 5017: #define POWERPC_EXCP_750cl   (POWERPC_EXCP_7x0)
 5018: #define POWERPC_INPUT_750cl  (PPC_FLAGS_INPUT_6xx)
 5019: #define POWERPC_BFDM_750cl   (bfd_mach_ppc_750)
 5020: #define POWERPC_FLAG_750cl   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
 5021:                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
 5022: #define check_pow_750cl      check_pow_hid0
 5023: 
 5024: static void init_proc_750cl (CPUPPCState *env)
 5025: {
 5026:     gen_spr_ne_601(env);
 5027:     gen_spr_7xx(env);
 5028:     /* XXX : not implemented */
 5029:     spr_register(env, SPR_L2CR, "L2CR",
 5030:                  SPR_NOACCESS, SPR_NOACCESS,
 5031:                  &spr_read_generic, &spr_write_generic,
 5032:                  0x00000000);
 5033:     /* Time base */
 5034:     gen_tbl(env);
 5035:     /* Thermal management */
 5036:     /* Those registers are fake on 750CL */
 5037:     spr_register(env, SPR_THRM1, "THRM1",
 5038:                  SPR_NOACCESS, SPR_NOACCESS,
 5039:                  &spr_read_generic, &spr_write_generic,
 5040:                  0x00000000);
 5041:     spr_register(env, SPR_THRM2, "THRM2",
 5042:                  SPR_NOACCESS, SPR_NOACCESS,
 5043:                  &spr_read_generic, &spr_write_generic,
 5044:                  0x00000000);
 5045:     spr_register(env, SPR_THRM3, "THRM3",
 5046:                  SPR_NOACCESS, SPR_NOACCESS,
 5047:                  &spr_read_generic, &spr_write_generic,
 5048:                  0x00000000);
 5049:     /* XXX: not implemented */
 5050:     spr_register(env, SPR_750_TDCL, "TDCL",
 5051:                  SPR_NOACCESS, SPR_NOACCESS,
 5052:                  &spr_read_generic, &spr_write_generic,
 5053:                  0x00000000);
 5054:     spr_register(env, SPR_750_TDCH, "TDCH",
 5055:                  SPR_NOACCESS, SPR_NOACCESS,
 5056:                  &spr_read_generic, &spr_write_generic,
 5057:                  0x00000000);
 5058:     /* DMA */
 5059:     /* XXX : not implemented */
 5060:     spr_register(env, SPR_750_WPAR, "WPAR",
 5061:                  SPR_NOACCESS, SPR_NOACCESS,
 5062:                  &spr_read_generic, &spr_write_generic,
 5063:                  0x00000000);
 5064:     spr_register(env, SPR_750_DMAL, "DMAL",
 5065:                  SPR_NOACCESS, SPR_NOACCESS,
 5066:                  &spr_read_generic, &spr_write_generic,
 5067:                  0x00000000);
 5068:     spr_register(env, SPR_750_DMAU, "DMAU",
 5069:                  SPR_NOACCESS, SPR_NOACCESS,
 5070:                  &spr_read_generic, &spr_write_generic,
 5071:                  0x00000000);
 5072:     /* Hardware implementation registers */
 5073:     /* XXX : not implemented */
 5074:     spr_register(env, SPR_HID0, "HID0",
 5075:                  SPR_NOACCESS, SPR_NOACCESS,
 5076:                  &spr_read_generic, &spr_write_generic,
 5077:                  0x00000000);
 5078:     /* XXX : not implemented */
 5079:     spr_register(env, SPR_HID1, "HID1",
 5080:                  SPR_NOACCESS, SPR_NOACCESS,
 5081:                  &spr_read_generic, &spr_write_generic,
 5082:                  0x00000000);
 5083:     /* XXX : not implemented */
 5084:     spr_register(env, SPR_750CL_HID2, "HID2",
 5085:                  SPR_NOACCESS, SPR_NOACCESS,
 5086:                  &spr_read_generic, &spr_write_generic,
 5087:                  0x00000000);
 5088:     /* XXX : not implemented */
 5089:     spr_register(env, SPR_750CL_HID4, "HID4",
 5090:                  SPR_NOACCESS, SPR_NOACCESS,
 5091:                  &spr_read_generic, &spr_write_generic,
 5092:                  0x00000000);
 5093:     /* Quantization registers */
 5094:     /* XXX : not implemented */
 5095:     spr_register(env, SPR_750_GQR0, "GQR0",
 5096:                  SPR_NOACCESS, SPR_NOACCESS,
 5097:                  &spr_read_generic, &spr_write_generic,
 5098:                  0x00000000);
 5099:     /* XXX : not implemented */
 5100:     spr_register(env, SPR_750_GQR1, "GQR1",
 5101:                  SPR_NOACCESS, SPR_NOACCESS,
 5102:                  &spr_read_generic, &spr_write_generic,
 5103:                  0x00000000);
 5104:     /* XXX : not implemented */
 5105:     spr_register(env, SPR_750_GQR2, "GQR2",
 5106:                  SPR_NOACCESS, SPR_NOACCESS,
 5107:                  &spr_read_generic, &spr_write_generic,
 5108:                  0x00000000);
 5109:     /* XXX : not implemented */
 5110:     spr_register(env, SPR_750_GQR3, "GQR3",
 5111:                  SPR_NOACCESS, SPR_NOACCESS,
 5112:                  &spr_read_generic, &spr_write_generic,
 5113:                  0x00000000);
 5114:     /* XXX : not implemented */
 5115:     spr_register(env, SPR_750_GQR4, "GQR4",
 5116:                  SPR_NOACCESS, SPR_NOACCESS,
 5117:                  &spr_read_generic, &spr_write_generic,
 5118:                  0x00000000);
 5119:     /* XXX : not implemented */
 5120:     spr_register(env, SPR_750_GQR5, "GQR5",
 5121:                  SPR_NOACCESS, SPR_NOACCESS,
 5122:                  &spr_read_generic, &spr_write_generic,
 5123:                  0x00000000);
 5124:     /* XXX : not implemented */
 5125:     spr_register(env, SPR_750_GQR6, "GQR6",
 5126:                  SPR_NOACCESS, SPR_NOACCESS,
 5127:                  &spr_read_generic, &spr_write_generic,
 5128:                  0x00000000);
 5129:     /* XXX : not implemented */
 5130:     spr_register(env, SPR_750_GQR7, "GQR7",
 5131:                  SPR_NOACCESS, SPR_NOACCESS,
 5132:                  &spr_read_generic, &spr_write_generic,
 5133:                  0x00000000);
 5134:     /* Memory management */
 5135:     gen_low_BATs(env);
 5136:     /* PowerPC 750cl has 8 DBATs and 8 IBATs */
 5137:     gen_high_BATs(env);
 5138:     init_excp_750cl(env);
 5139:     env->dcache_line_size = 32;
 5140:     env->icache_line_size = 32;
 5141:     /* Allocate hardware IRQ controller */
 5142:     ppc6xx_irq_init(env);
 5143: }
 5144: 
 5145: /* PowerPC 750CX                                                             */
 5146: #define POWERPC_INSNS_750cx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 5147:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 5148:                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
 5149:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
 5150:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 5151:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 5152:                               PPC_SEGMENT | PPC_EXTERN)
 5153: #define POWERPC_INSNS2_750cx (PPC_NONE)
 5154: #define POWERPC_MSRM_750cx   (0x000000000005FF77ULL)
 5155: #define POWERPC_MMU_750cx    (POWERPC_MMU_32B)
 5156: #define POWERPC_EXCP_750cx   (POWERPC_EXCP_7x0)
 5157: #define POWERPC_INPUT_750cx  (PPC_FLAGS_INPUT_6xx)
 5158: #define POWERPC_BFDM_750cx   (bfd_mach_ppc_750)
 5159: #define POWERPC_FLAG_750cx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
 5160:                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
 5161: #define check_pow_750cx      check_pow_hid0
 5162: 
 5163: static void init_proc_750cx (CPUPPCState *env)
 5164: {
 5165:     gen_spr_ne_601(env);
 5166:     gen_spr_7xx(env);
 5167:     /* XXX : not implemented */
 5168:     spr_register(env, SPR_L2CR, "L2CR",
 5169:                  SPR_NOACCESS, SPR_NOACCESS,
 5170:                  &spr_read_generic, &spr_write_generic,
 5171:                  0x00000000);
 5172:     /* Time base */
 5173:     gen_tbl(env);
 5174:     /* Thermal management */
 5175:     gen_spr_thrm(env);
 5176:     /* This register is not implemented but is present for compatibility */
 5177:     spr_register(env, SPR_SDA, "SDA",
 5178:                  SPR_NOACCESS, SPR_NOACCESS,
 5179:                  &spr_read_generic, &spr_write_generic,
 5180:                  0x00000000);
 5181:     /* Hardware implementation registers */
 5182:     /* XXX : not implemented */
 5183:     spr_register(env, SPR_HID0, "HID0",
 5184:                  SPR_NOACCESS, SPR_NOACCESS,
 5185:                  &spr_read_generic, &spr_write_generic,
 5186:                  0x00000000);
 5187:     /* XXX : not implemented */
 5188:     spr_register(env, SPR_HID1, "HID1",
 5189:                  SPR_NOACCESS, SPR_NOACCESS,
 5190:                  &spr_read_generic, &spr_write_generic,
 5191:                  0x00000000);
 5192:     /* Memory management */
 5193:     gen_low_BATs(env);
 5194:     /* PowerPC 750cx has 8 DBATs and 8 IBATs */
 5195:     gen_high_BATs(env);
 5196:     init_excp_750cx(env);
 5197:     env->dcache_line_size = 32;
 5198:     env->icache_line_size = 32;
 5199:     /* Allocate hardware IRQ controller */
 5200:     ppc6xx_irq_init(env);
 5201: }
 5202: 
 5203: /* PowerPC 750FX                                                             */
 5204: #define POWERPC_INSNS_750fx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 5205:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 5206:                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
 5207:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
 5208:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 5209:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 5210:                               PPC_SEGMENT  | PPC_EXTERN)
 5211: #define POWERPC_INSNS2_750fx (PPC_NONE)
 5212: #define POWERPC_MSRM_750fx   (0x000000000005FF77ULL)
 5213: #define POWERPC_MMU_750fx    (POWERPC_MMU_32B)
 5214: #define POWERPC_EXCP_750fx   (POWERPC_EXCP_7x0)
 5215: #define POWERPC_INPUT_750fx  (PPC_FLAGS_INPUT_6xx)
 5216: #define POWERPC_BFDM_750fx   (bfd_mach_ppc_750)
 5217: #define POWERPC_FLAG_750fx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
 5218:                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
 5219: #define check_pow_750fx      check_pow_hid0
 5220: 
 5221: static void init_proc_750fx (CPUPPCState *env)
 5222: {
 5223:     gen_spr_ne_601(env);
 5224:     gen_spr_7xx(env);
 5225:     /* XXX : not implemented */
 5226:     spr_register(env, SPR_L2CR, "L2CR",
 5227:                  SPR_NOACCESS, SPR_NOACCESS,
 5228:                  &spr_read_generic, &spr_write_generic,
 5229:                  0x00000000);
 5230:     /* Time base */
 5231:     gen_tbl(env);
 5232:     /* Thermal management */
 5233:     gen_spr_thrm(env);
 5234:     /* XXX : not implemented */
 5235:     spr_register(env, SPR_750_THRM4, "THRM4",
 5236:                  SPR_NOACCESS, SPR_NOACCESS,
 5237:                  &spr_read_generic, &spr_write_generic,
 5238:                  0x00000000);
 5239:     /* Hardware implementation registers */
 5240:     /* XXX : not implemented */
 5241:     spr_register(env, SPR_HID0, "HID0",
 5242:                  SPR_NOACCESS, SPR_NOACCESS,
 5243:                  &spr_read_generic, &spr_write_generic,
 5244:                  0x00000000);
 5245:     /* XXX : not implemented */
 5246:     spr_register(env, SPR_HID1, "HID1",
 5247:                  SPR_NOACCESS, SPR_NOACCESS,
 5248:                  &spr_read_generic, &spr_write_generic,
 5249:                  0x00000000);
 5250:     /* XXX : not implemented */
 5251:     spr_register(env, SPR_750FX_HID2, "HID2",
 5252:                  SPR_NOACCESS, SPR_NOACCESS,
 5253:                  &spr_read_generic, &spr_write_generic,
 5254:                  0x00000000);
 5255:     /* Memory management */
 5256:     gen_low_BATs(env);
 5257:     /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
 5258:     gen_high_BATs(env);
 5259:     init_excp_7x0(env);
 5260:     env->dcache_line_size = 32;
 5261:     env->icache_line_size = 32;
 5262:     /* Allocate hardware IRQ controller */
 5263:     ppc6xx_irq_init(env);
 5264: }
 5265: 
 5266: /* PowerPC 750GX                                                             */
 5267: #define POWERPC_INSNS_750gx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 5268:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 5269:                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
 5270:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
 5271:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 5272:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 5273:                               PPC_SEGMENT  | PPC_EXTERN)
 5274: #define POWERPC_INSNS2_750gx (PPC_NONE)
 5275: #define POWERPC_MSRM_750gx   (0x000000000005FF77ULL)
 5276: #define POWERPC_MMU_750gx    (POWERPC_MMU_32B)
 5277: #define POWERPC_EXCP_750gx   (POWERPC_EXCP_7x0)
 5278: #define POWERPC_INPUT_750gx  (PPC_FLAGS_INPUT_6xx)
 5279: #define POWERPC_BFDM_750gx   (bfd_mach_ppc_750)
 5280: #define POWERPC_FLAG_750gx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
 5281:                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
 5282: #define check_pow_750gx      check_pow_hid0
 5283: 
 5284: static void init_proc_750gx (CPUPPCState *env)
 5285: {
 5286:     gen_spr_ne_601(env);
 5287:     gen_spr_7xx(env);
 5288:     /* XXX : not implemented (XXX: different from 750fx) */
 5289:     spr_register(env, SPR_L2CR, "L2CR",
 5290:                  SPR_NOACCESS, SPR_NOACCESS,
 5291:                  &spr_read_generic, &spr_write_generic,
 5292:                  0x00000000);
 5293:     /* Time base */
 5294:     gen_tbl(env);
 5295:     /* Thermal management */
 5296:     gen_spr_thrm(env);
 5297:     /* XXX : not implemented */
 5298:     spr_register(env, SPR_750_THRM4, "THRM4",
 5299:                  SPR_NOACCESS, SPR_NOACCESS,
 5300:                  &spr_read_generic, &spr_write_generic,
 5301:                  0x00000000);
 5302:     /* Hardware implementation registers */
 5303:     /* XXX : not implemented (XXX: different from 750fx) */
 5304:     spr_register(env, SPR_HID0, "HID0",
 5305:                  SPR_NOACCESS, SPR_NOACCESS,
 5306:                  &spr_read_generic, &spr_write_generic,
 5307:                  0x00000000);
 5308:     /* XXX : not implemented */
 5309:     spr_register(env, SPR_HID1, "HID1",
 5310:                  SPR_NOACCESS, SPR_NOACCESS,
 5311:                  &spr_read_generic, &spr_write_generic,
 5312:                  0x00000000);
 5313:     /* XXX : not implemented (XXX: different from 750fx) */
 5314:     spr_register(env, SPR_750FX_HID2, "HID2",
 5315:                  SPR_NOACCESS, SPR_NOACCESS,
 5316:                  &spr_read_generic, &spr_write_generic,
 5317:                  0x00000000);
 5318:     /* Memory management */
 5319:     gen_low_BATs(env);
 5320:     /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
 5321:     gen_high_BATs(env);
 5322:     init_excp_7x0(env);
 5323:     env->dcache_line_size = 32;
 5324:     env->icache_line_size = 32;
 5325:     /* Allocate hardware IRQ controller */
 5326:     ppc6xx_irq_init(env);
 5327: }
 5328: 
 5329: /* PowerPC 745                                                               */
 5330: #define POWERPC_INSNS_745    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 5331:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 5332:                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
 5333:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
 5334:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 5335:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
 5336:                               PPC_SEGMENT | PPC_EXTERN)
 5337: #define POWERPC_INSNS2_745   (PPC_NONE)
 5338: #define POWERPC_MSRM_745     (0x000000000005FF77ULL)
 5339: #define POWERPC_MMU_745      (POWERPC_MMU_SOFT_6xx)
 5340: #define POWERPC_EXCP_745     (POWERPC_EXCP_7x5)
 5341: #define POWERPC_INPUT_745    (PPC_FLAGS_INPUT_6xx)
 5342: #define POWERPC_BFDM_745     (bfd_mach_ppc_750)
 5343: #define POWERPC_FLAG_745     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
 5344:                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
 5345: #define check_pow_745        check_pow_hid0
 5346: 
 5347: static void init_proc_745 (CPUPPCState *env)
 5348: {
 5349:     gen_spr_ne_601(env);
 5350:     gen_spr_7xx(env);
 5351:     gen_spr_G2_755(env);
 5352:     /* Time base */
 5353:     gen_tbl(env);
 5354:     /* Thermal management */
 5355:     gen_spr_thrm(env);
 5356:     /* Hardware implementation registers */
 5357:     /* XXX : not implemented */
 5358:     spr_register(env, SPR_HID0, "HID0",
 5359:                  SPR_NOACCESS, SPR_NOACCESS,
 5360:                  &spr_read_generic, &spr_write_generic,
 5361:                  0x00000000);
 5362:     /* XXX : not implemented */
 5363:     spr_register(env, SPR_HID1, "HID1",
 5364:                  SPR_NOACCESS, SPR_NOACCESS,
 5365:                  &spr_read_generic, &spr_write_generic,
 5366:                  0x00000000);
 5367:     /* XXX : not implemented */
 5368:     spr_register(env, SPR_HID2, "HID2",
 5369:                  SPR_NOACCESS, SPR_NOACCESS,
 5370:                  &spr_read_generic, &spr_write_generic,
 5371:                  0x00000000);
 5372:     /* Memory management */
 5373:     gen_low_BATs(env);
 5374:     gen_high_BATs(env);
 5375:     gen_6xx_7xx_soft_tlb(env, 64, 2);
 5376:     init_excp_7x5(env);
 5377:     env->dcache_line_size = 32;
 5378:     env->icache_line_size = 32;
 5379:     /* Allocate hardware IRQ controller */
 5380:     ppc6xx_irq_init(env);
 5381: }
 5382: 
 5383: /* PowerPC 755                                                               */
 5384: #define POWERPC_INSNS_755    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 5385:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 5386:                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
 5387:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
 5388:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 5389:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
 5390:                               PPC_SEGMENT | PPC_EXTERN)
 5391: #define POWERPC_INSNS2_755   (PPC_NONE)
 5392: #define POWERPC_MSRM_755     (0x000000000005FF77ULL)
 5393: #define POWERPC_MMU_755      (POWERPC_MMU_SOFT_6xx)
 5394: #define POWERPC_EXCP_755     (POWERPC_EXCP_7x5)
 5395: #define POWERPC_INPUT_755    (PPC_FLAGS_INPUT_6xx)
 5396: #define POWERPC_BFDM_755     (bfd_mach_ppc_750)
 5397: #define POWERPC_FLAG_755     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
 5398:                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
 5399: #define check_pow_755        check_pow_hid0
 5400: 
 5401: static void init_proc_755 (CPUPPCState *env)
 5402: {
 5403:     gen_spr_ne_601(env);
 5404:     gen_spr_7xx(env);
 5405:     gen_spr_G2_755(env);
 5406:     /* Time base */
 5407:     gen_tbl(env);
 5408:     /* L2 cache control */
 5409:     /* XXX : not implemented */
 5410:     spr_register(env, SPR_L2CR, "L2CR",
 5411:                  SPR_NOACCESS, SPR_NOACCESS,
 5412:                  &spr_read_generic, &spr_write_generic,
 5413:                  0x00000000);
 5414:     /* XXX : not implemented */
 5415:     spr_register(env, SPR_L2PMCR, "L2PMCR",
 5416:                  SPR_NOACCESS, SPR_NOACCESS,
 5417:                  &spr_read_generic, &spr_write_generic,
 5418:                  0x00000000);
 5419:     /* Thermal management */
 5420:     gen_spr_thrm(env);
 5421:     /* Hardware implementation registers */
 5422:     /* XXX : not implemented */
 5423:     spr_register(env, SPR_HID0, "HID0",
 5424:                  SPR_NOACCESS, SPR_NOACCESS,
 5425:                  &spr_read_generic, &spr_write_generic,
 5426:                  0x00000000);
 5427:     /* XXX : not implemented */
 5428:     spr_register(env, SPR_HID1, "HID1",
 5429:                  SPR_NOACCESS, SPR_NOACCESS,
 5430:                  &spr_read_generic, &spr_write_generic,
 5431:                  0x00000000);
 5432:     /* XXX : not implemented */
 5433:     spr_register(env, SPR_HID2, "HID2",
 5434:                  SPR_NOACCESS, SPR_NOACCESS,
 5435:                  &spr_read_generic, &spr_write_generic,
 5436:                  0x00000000);
 5437:     /* Memory management */
 5438:     gen_low_BATs(env);
 5439:     gen_high_BATs(env);
 5440:     gen_6xx_7xx_soft_tlb(env, 64, 2);
 5441:     init_excp_7x5(env);
 5442:     env->dcache_line_size = 32;
 5443:     env->icache_line_size = 32;
 5444:     /* Allocate hardware IRQ controller */
 5445:     ppc6xx_irq_init(env);
 5446: }
 5447: 
 5448: /* PowerPC 7400 (aka G4)                                                     */
 5449: #define POWERPC_INSNS_7400   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 5450:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 5451:                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
 5452:                               PPC_FLOAT_STFIWX |                              \
 5453:                               PPC_CACHE | PPC_CACHE_ICBI |                    \
 5454:                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
 5455:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 5456:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 5457:                               PPC_MEM_TLBIA |                                 \
 5458:                               PPC_SEGMENT | PPC_EXTERN |                      \
 5459:                               PPC_ALTIVEC)
 5460: #define POWERPC_INSNS2_7400  (PPC_NONE)
 5461: #define POWERPC_MSRM_7400    (0x000000000205FF77ULL)
 5462: #define POWERPC_MMU_7400     (POWERPC_MMU_32B)
 5463: #define POWERPC_EXCP_7400    (POWERPC_EXCP_74xx)
 5464: #define POWERPC_INPUT_7400   (PPC_FLAGS_INPUT_6xx)
 5465: #define POWERPC_BFDM_7400    (bfd_mach_ppc_7400)
 5466: #define POWERPC_FLAG_7400    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
 5467:                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
 5468:                               POWERPC_FLAG_BUS_CLK)
 5469: #define check_pow_7400       check_pow_hid0
 5470: 
 5471: static void init_proc_7400 (CPUPPCState *env)
 5472: {
 5473:     gen_spr_ne_601(env);
 5474:     gen_spr_7xx(env);
 5475:     /* Time base */
 5476:     gen_tbl(env);
 5477:     /* 74xx specific SPR */
 5478:     gen_spr_74xx(env);
 5479:     /* XXX : not implemented */
 5480:     spr_register(env, SPR_UBAMR, "UBAMR",
 5481:                  &spr_read_ureg, SPR_NOACCESS,
 5482:                  &spr_read_ureg, SPR_NOACCESS,
 5483:                  0x00000000);
 5484:     /* XXX: this seems not implemented on all revisions. */
 5485:     /* XXX : not implemented */
 5486:     spr_register(env, SPR_MSSCR1, "MSSCR1",
 5487:                  SPR_NOACCESS, SPR_NOACCESS,
 5488:                  &spr_read_generic, &spr_write_generic,
 5489:                  0x00000000);
 5490:     /* Thermal management */
 5491:     gen_spr_thrm(env);
 5492:     /* Memory management */
 5493:     gen_low_BATs(env);
 5494:     init_excp_7400(env);
 5495:     env->dcache_line_size = 32;
 5496:     env->icache_line_size = 32;
 5497:     /* Allocate hardware IRQ controller */
 5498:     ppc6xx_irq_init(env);
 5499: }
 5500: 
 5501: /* PowerPC 7410 (aka G4)                                                     */
 5502: #define POWERPC_INSNS_7410   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 5503:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 5504:                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
 5505:                               PPC_FLOAT_STFIWX |                              \
 5506:                               PPC_CACHE | PPC_CACHE_ICBI |                    \
 5507:                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
 5508:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 5509:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 5510:                               PPC_MEM_TLBIA |                                 \
 5511:                               PPC_SEGMENT | PPC_EXTERN |                      \
 5512:                               PPC_ALTIVEC)
 5513: #define POWERPC_INSNS2_7410  (PPC_NONE)
 5514: #define POWERPC_MSRM_7410    (0x000000000205FF77ULL)
 5515: #define POWERPC_MMU_7410     (POWERPC_MMU_32B)
 5516: #define POWERPC_EXCP_7410    (POWERPC_EXCP_74xx)
 5517: #define POWERPC_INPUT_7410   (PPC_FLAGS_INPUT_6xx)
 5518: #define POWERPC_BFDM_7410    (bfd_mach_ppc_7400)
 5519: #define POWERPC_FLAG_7410    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
 5520:                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
 5521:                               POWERPC_FLAG_BUS_CLK)
 5522: #define check_pow_7410       check_pow_hid0
 5523: 
 5524: static void init_proc_7410 (CPUPPCState *env)
 5525: {
 5526:     gen_spr_ne_601(env);
 5527:     gen_spr_7xx(env);
 5528:     /* Time base */
 5529:     gen_tbl(env);
 5530:     /* 74xx specific SPR */
 5531:     gen_spr_74xx(env);
 5532:     /* XXX : not implemented */
 5533:     spr_register(env, SPR_UBAMR, "UBAMR",
 5534:                  &spr_read_ureg, SPR_NOACCESS,
 5535:                  &spr_read_ureg, SPR_NOACCESS,
 5536:                  0x00000000);
 5537:     /* Thermal management */
 5538:     gen_spr_thrm(env);
 5539:     /* L2PMCR */
 5540:     /* XXX : not implemented */
 5541:     spr_register(env, SPR_L2PMCR, "L2PMCR",
 5542:                  SPR_NOACCESS, SPR_NOACCESS,
 5543:                  &spr_read_generic, &spr_write_generic,
 5544:                  0x00000000);
 5545:     /* LDSTDB */
 5546:     /* XXX : not implemented */
 5547:     spr_register(env, SPR_LDSTDB, "LDSTDB",
 5548:                  SPR_NOACCESS, SPR_NOACCESS,
 5549:                  &spr_read_generic, &spr_write_generic,
 5550:                  0x00000000);
 5551:     /* Memory management */
 5552:     gen_low_BATs(env);
 5553:     init_excp_7400(env);
 5554:     env->dcache_line_size = 32;
 5555:     env->icache_line_size = 32;
 5556:     /* Allocate hardware IRQ controller */
 5557:     ppc6xx_irq_init(env);
 5558: }
 5559: 
 5560: /* PowerPC 7440 (aka G4)                                                     */
 5561: #define POWERPC_INSNS_7440   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 5562:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 5563:                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
 5564:                               PPC_FLOAT_STFIWX |                              \
 5565:                               PPC_CACHE | PPC_CACHE_ICBI |                    \
 5566:                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
 5567:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 5568:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 5569:                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
 5570:                               PPC_SEGMENT | PPC_EXTERN |                      \
 5571:                               PPC_ALTIVEC)
 5572: #define POWERPC_INSNS2_7440  (PPC_NONE)
 5573: #define POWERPC_MSRM_7440    (0x000000000205FF77ULL)
 5574: #define POWERPC_MMU_7440     (POWERPC_MMU_SOFT_74xx)
 5575: #define POWERPC_EXCP_7440    (POWERPC_EXCP_74xx)
 5576: #define POWERPC_INPUT_7440   (PPC_FLAGS_INPUT_6xx)
 5577: #define POWERPC_BFDM_7440    (bfd_mach_ppc_7400)
 5578: #define POWERPC_FLAG_7440    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
 5579:                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
 5580:                               POWERPC_FLAG_BUS_CLK)
 5581: #define check_pow_7440       check_pow_hid0_74xx
 5582: 
 5583: __attribute__ (( unused ))
 5584: static void init_proc_7440 (CPUPPCState *env)
 5585: {
 5586:     gen_spr_ne_601(env);
 5587:     gen_spr_7xx(env);
 5588:     /* Time base */
 5589:     gen_tbl(env);
 5590:     /* 74xx specific SPR */
 5591:     gen_spr_74xx(env);
 5592:     /* XXX : not implemented */
 5593:     spr_register(env, SPR_UBAMR, "UBAMR",
 5594:                  &spr_read_ureg, SPR_NOACCESS,
 5595:                  &spr_read_ureg, SPR_NOACCESS,
 5596:                  0x00000000);
 5597:     /* LDSTCR */
 5598:     /* XXX : not implemented */
 5599:     spr_register(env, SPR_LDSTCR, "LDSTCR",
 5600:                  SPR_NOACCESS, SPR_NOACCESS,
 5601:                  &spr_read_generic, &spr_write_generic,
 5602:                  0x00000000);
 5603:     /* ICTRL */
 5604:     /* XXX : not implemented */
 5605:     spr_register(env, SPR_ICTRL, "ICTRL",
 5606:                  SPR_NOACCESS, SPR_NOACCESS,
 5607:                  &spr_read_generic, &spr_write_generic,
 5608:                  0x00000000);
 5609:     /* MSSSR0 */
 5610:     /* XXX : not implemented */
 5611:     spr_register(env, SPR_MSSSR0, "MSSSR0",
 5612:                  SPR_NOACCESS, SPR_NOACCESS,
 5613:                  &spr_read_generic, &spr_write_generic,
 5614:                  0x00000000);
 5615:     /* PMC */
 5616:     /* XXX : not implemented */
 5617:     spr_register(env, SPR_PMC5, "PMC5",
 5618:                  SPR_NOACCESS, SPR_NOACCESS,
 5619:                  &spr_read_generic, &spr_write_generic,
 5620:                  0x00000000);
 5621:     /* XXX : not implemented */
 5622:     spr_register(env, SPR_UPMC5, "UPMC5",
 5623:                  &spr_read_ureg, SPR_NOACCESS,
 5624:                  &spr_read_ureg, SPR_NOACCESS,
 5625:                  0x00000000);
 5626:     /* XXX : not implemented */
 5627:     spr_register(env, SPR_PMC6, "PMC6",
 5628:                  SPR_NOACCESS, SPR_NOACCESS,
 5629:                  &spr_read_generic, &spr_write_generic,
 5630:                  0x00000000);
 5631:     /* XXX : not implemented */
 5632:     spr_register(env, SPR_UPMC6, "UPMC6",
 5633:                  &spr_read_ureg, SPR_NOACCESS,
 5634:                  &spr_read_ureg, SPR_NOACCESS,
 5635:                  0x00000000);
 5636:     /* Memory management */
 5637:     gen_low_BATs(env);
 5638:     gen_74xx_soft_tlb(env, 128, 2);
 5639:     init_excp_7450(env);
 5640:     env->dcache_line_size = 32;
 5641:     env->icache_line_size = 32;
 5642:     /* Allocate hardware IRQ controller */
 5643:     ppc6xx_irq_init(env);
 5644: }
 5645: 
 5646: /* PowerPC 7450 (aka G4)                                                     */
 5647: #define POWERPC_INSNS_7450   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 5648:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 5649:                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
 5650:                               PPC_FLOAT_STFIWX |                              \
 5651:                               PPC_CACHE | PPC_CACHE_ICBI |                    \
 5652:                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
 5653:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 5654:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 5655:                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
 5656:                               PPC_SEGMENT | PPC_EXTERN |                      \
 5657:                               PPC_ALTIVEC)
 5658: #define POWERPC_INSNS2_7450  (PPC_NONE)
 5659: #define POWERPC_MSRM_7450    (0x000000000205FF77ULL)
 5660: #define POWERPC_MMU_7450     (POWERPC_MMU_SOFT_74xx)
 5661: #define POWERPC_EXCP_7450    (POWERPC_EXCP_74xx)
 5662: #define POWERPC_INPUT_7450   (PPC_FLAGS_INPUT_6xx)
 5663: #define POWERPC_BFDM_7450    (bfd_mach_ppc_7400)
 5664: #define POWERPC_FLAG_7450    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
 5665:                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
 5666:                               POWERPC_FLAG_BUS_CLK)
 5667: #define check_pow_7450       check_pow_hid0_74xx
 5668: 
 5669: __attribute__ (( unused ))
 5670: static void init_proc_7450 (CPUPPCState *env)
 5671: {
 5672:     gen_spr_ne_601(env);
 5673:     gen_spr_7xx(env);
 5674:     /* Time base */
 5675:     gen_tbl(env);
 5676:     /* 74xx specific SPR */
 5677:     gen_spr_74xx(env);
 5678:     /* Level 3 cache control */
 5679:     gen_l3_ctrl(env);
 5680:     /* L3ITCR1 */
 5681:     /* XXX : not implemented */
 5682:     spr_register(env, SPR_L3ITCR1, "L3ITCR1",
 5683:                  SPR_NOACCESS, SPR_NOACCESS,
 5684:                  &spr_read_generic, &spr_write_generic,
 5685:                  0x00000000);
 5686:     /* L3ITCR2 */
 5687:     /* XXX : not implemented */
 5688:     spr_register(env, SPR_L3ITCR2, "L3ITCR2",
 5689:                  SPR_NOACCESS, SPR_NOACCESS,
 5690:                  &spr_read_generic, &spr_write_generic,
 5691:                  0x00000000);
 5692:     /* L3ITCR3 */
 5693:     /* XXX : not implemented */
 5694:     spr_register(env, SPR_L3ITCR3, "L3ITCR3",
 5695:                  SPR_NOACCESS, SPR_NOACCESS,
 5696:                  &spr_read_generic, &spr_write_generic,
 5697:                  0x00000000);
 5698:     /* L3OHCR */
 5699:     /* XXX : not implemented */
 5700:     spr_register(env, SPR_L3OHCR, "L3OHCR",
 5701:                  SPR_NOACCESS, SPR_NOACCESS,
 5702:                  &spr_read_generic, &spr_write_generic,
 5703:                  0x00000000);
 5704:     /* XXX : not implemented */
 5705:     spr_register(env, SPR_UBAMR, "UBAMR",
 5706:                  &spr_read_ureg, SPR_NOACCESS,
 5707:                  &spr_read_ureg, SPR_NOACCESS,
 5708:                  0x00000000);
 5709:     /* LDSTCR */
 5710:     /* XXX : not implemented */
 5711:     spr_register(env, SPR_LDSTCR, "LDSTCR",
 5712:                  SPR_NOACCESS, SPR_NOACCESS,
 5713:                  &spr_read_generic, &spr_write_generic,
 5714:                  0x00000000);
 5715:     /* ICTRL */
 5716:     /* XXX : not implemented */
 5717:     spr_register(env, SPR_ICTRL, "ICTRL",
 5718:                  SPR_NOACCESS, SPR_NOACCESS,
 5719:                  &spr_read_generic, &spr_write_generic,
 5720:                  0x00000000);
 5721:     /* MSSSR0 */
 5722:     /* XXX : not implemented */
 5723:     spr_register(env, SPR_MSSSR0, "MSSSR0",
 5724:                  SPR_NOACCESS, SPR_NOACCESS,
 5725:                  &spr_read_generic, &spr_write_generic,
 5726:                  0x00000000);
 5727:     /* PMC */
 5728:     /* XXX : not implemented */
 5729:     spr_register(env, SPR_PMC5, "PMC5",
 5730:                  SPR_NOACCESS, SPR_NOACCESS,
 5731:                  &spr_read_generic, &spr_write_generic,
 5732:                  0x00000000);
 5733:     /* XXX : not implemented */
 5734:     spr_register(env, SPR_UPMC5, "UPMC5",
 5735:                  &spr_read_ureg, SPR_NOACCESS,
 5736:                  &spr_read_ureg, SPR_NOACCESS,
 5737:                  0x00000000);
 5738:     /* XXX : not implemented */
 5739:     spr_register(env, SPR_PMC6, "PMC6",
 5740:                  SPR_NOACCESS, SPR_NOACCESS,
 5741:                  &spr_read_generic, &spr_write_generic,
 5742:                  0x00000000);
 5743:     /* XXX : not implemented */
 5744:     spr_register(env, SPR_UPMC6, "UPMC6",
 5745:                  &spr_read_ureg, SPR_NOACCESS,
 5746:                  &spr_read_ureg, SPR_NOACCESS,
 5747:                  0x00000000);
 5748:     /* Memory management */
 5749:     gen_low_BATs(env);
 5750:     gen_74xx_soft_tlb(env, 128, 2);
 5751:     init_excp_7450(env);
 5752:     env->dcache_line_size = 32;
 5753:     env->icache_line_size = 32;
 5754:     /* Allocate hardware IRQ controller */
 5755:     ppc6xx_irq_init(env);
 5756: }
 5757: 
 5758: /* PowerPC 7445 (aka G4)                                                     */
 5759: #define POWERPC_INSNS_7445   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 5760:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 5761:                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
 5762:                               PPC_FLOAT_STFIWX |                              \
 5763:                               PPC_CACHE | PPC_CACHE_ICBI |                    \
 5764:                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
 5765:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 5766:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 5767:                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
 5768:                               PPC_SEGMENT | PPC_EXTERN |                      \
 5769:                               PPC_ALTIVEC)
 5770: #define POWERPC_INSNS2_7445  (PPC_NONE)
 5771: #define POWERPC_MSRM_7445    (0x000000000205FF77ULL)
 5772: #define POWERPC_MMU_7445     (POWERPC_MMU_SOFT_74xx)
 5773: #define POWERPC_EXCP_7445    (POWERPC_EXCP_74xx)
 5774: #define POWERPC_INPUT_7445   (PPC_FLAGS_INPUT_6xx)
 5775: #define POWERPC_BFDM_7445    (bfd_mach_ppc_7400)
 5776: #define POWERPC_FLAG_7445    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
 5777:                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
 5778:                               POWERPC_FLAG_BUS_CLK)
 5779: #define check_pow_7445       check_pow_hid0_74xx
 5780: 
 5781: __attribute__ (( unused ))
 5782: static void init_proc_7445 (CPUPPCState *env)
 5783: {
 5784:     gen_spr_ne_601(env);
 5785:     gen_spr_7xx(env);
 5786:     /* Time base */
 5787:     gen_tbl(env);
 5788:     /* 74xx specific SPR */
 5789:     gen_spr_74xx(env);
 5790:     /* LDSTCR */
 5791:     /* XXX : not implemented */
 5792:     spr_register(env, SPR_LDSTCR, "LDSTCR",
 5793:                  SPR_NOACCESS, SPR_NOACCESS,
 5794:                  &spr_read_generic, &spr_write_generic,
 5795:                  0x00000000);
 5796:     /* ICTRL */
 5797:     /* XXX : not implemented */
 5798:     spr_register(env, SPR_ICTRL, "ICTRL",
 5799:                  SPR_NOACCESS, SPR_NOACCESS,
 5800:                  &spr_read_generic, &spr_write_generic,
 5801:                  0x00000000);
 5802:     /* MSSSR0 */
 5803:     /* XXX : not implemented */
 5804:     spr_register(env, SPR_MSSSR0, "MSSSR0",
 5805:                  SPR_NOACCESS, SPR_NOACCESS,
 5806:                  &spr_read_generic, &spr_write_generic,
 5807:                  0x00000000);
 5808:     /* PMC */
 5809:     /* XXX : not implemented */
 5810:     spr_register(env, SPR_PMC5, "PMC5",
 5811:                  SPR_NOACCESS, SPR_NOACCESS,
 5812:                  &spr_read_generic, &spr_write_generic,
 5813:                  0x00000000);
 5814:     /* XXX : not implemented */
 5815:     spr_register(env, SPR_UPMC5, "UPMC5",
 5816:                  &spr_read_ureg, SPR_NOACCESS,
 5817:                  &spr_read_ureg, SPR_NOACCESS,
 5818:                  0x00000000);
 5819:     /* XXX : not implemented */
 5820:     spr_register(env, SPR_PMC6, "PMC6",
 5821:                  SPR_NOACCESS, SPR_NOACCESS,
 5822:                  &spr_read_generic, &spr_write_generic,
 5823:                  0x00000000);
 5824:     /* XXX : not implemented */
 5825:     spr_register(env, SPR_UPMC6, "UPMC6",
 5826:                  &spr_read_ureg, SPR_NOACCESS,
 5827:                  &spr_read_ureg, SPR_NOACCESS,
 5828:                  0x00000000);
 5829:     /* SPRGs */
 5830:     spr_register(env, SPR_SPRG4, "SPRG4",
 5831:                  SPR_NOACCESS, SPR_NOACCESS,
 5832:                  &spr_read_generic, &spr_write_generic,
 5833:                  0x00000000);
 5834:     spr_register(env, SPR_USPRG4, "USPRG4",
 5835:                  &spr_read_ureg, SPR_NOACCESS,
 5836:                  &spr_read_ureg, SPR_NOACCESS,
 5837:                  0x00000000);
 5838:     spr_register(env, SPR_SPRG5, "SPRG5",
 5839:                  SPR_NOACCESS, SPR_NOACCESS,
 5840:                  &spr_read_generic, &spr_write_generic,
 5841:                  0x00000000);
 5842:     spr_register(env, SPR_USPRG5, "USPRG5",
 5843:                  &spr_read_ureg, SPR_NOACCESS,
 5844:                  &spr_read_ureg, SPR_NOACCESS,
 5845:                  0x00000000);
 5846:     spr_register(env, SPR_SPRG6, "SPRG6",
 5847:                  SPR_NOACCESS, SPR_NOACCESS,
 5848:                  &spr_read_generic, &spr_write_generic,
 5849:                  0x00000000);
 5850:     spr_register(env, SPR_USPRG6, "USPRG6",
 5851:                  &spr_read_ureg, SPR_NOACCESS,
 5852:                  &spr_read_ureg, SPR_NOACCESS,
 5853:                  0x00000000);
 5854:     spr_register(env, SPR_SPRG7, "SPRG7",
 5855:                  SPR_NOACCESS, SPR_NOACCESS,
 5856:                  &spr_read_generic, &spr_write_generic,
 5857:                  0x00000000);
 5858:     spr_register(env, SPR_USPRG7, "USPRG7",
 5859:                  &spr_read_ureg, SPR_NOACCESS,
 5860:                  &spr_read_ureg, SPR_NOACCESS,
 5861:                  0x00000000);
 5862:     /* Memory management */
 5863:     gen_low_BATs(env);
 5864:     gen_high_BATs(env);
 5865:     gen_74xx_soft_tlb(env, 128, 2);
 5866:     init_excp_7450(env);
 5867:     env->dcache_line_size = 32;
 5868:     env->icache_line_size = 32;
 5869:     /* Allocate hardware IRQ controller */
 5870:     ppc6xx_irq_init(env);
 5871: }
 5872: 
 5873: /* PowerPC 7455 (aka G4)                                                     */
 5874: #define POWERPC_INSNS_7455   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 5875:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 5876:                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
 5877:                               PPC_FLOAT_STFIWX |                              \
 5878:                               PPC_CACHE | PPC_CACHE_ICBI |                    \
 5879:                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
 5880:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 5881:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 5882:                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
 5883:                               PPC_SEGMENT | PPC_EXTERN |                      \
 5884:                               PPC_ALTIVEC)
 5885: #define POWERPC_INSNS2_7455  (PPC_NONE)
 5886: #define POWERPC_MSRM_7455    (0x000000000205FF77ULL)
 5887: #define POWERPC_MMU_7455     (POWERPC_MMU_SOFT_74xx)
 5888: #define POWERPC_EXCP_7455    (POWERPC_EXCP_74xx)
 5889: #define POWERPC_INPUT_7455   (PPC_FLAGS_INPUT_6xx)
 5890: #define POWERPC_BFDM_7455    (bfd_mach_ppc_7400)
 5891: #define POWERPC_FLAG_7455    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
 5892:                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
 5893:                               POWERPC_FLAG_BUS_CLK)
 5894: #define check_pow_7455       check_pow_hid0_74xx
 5895: 
 5896: __attribute__ (( unused ))
 5897: static void init_proc_7455 (CPUPPCState *env)
 5898: {
 5899:     gen_spr_ne_601(env);
 5900:     gen_spr_7xx(env);
 5901:     /* Time base */
 5902:     gen_tbl(env);
 5903:     /* 74xx specific SPR */
 5904:     gen_spr_74xx(env);
 5905:     /* Level 3 cache control */
 5906:     gen_l3_ctrl(env);
 5907:     /* LDSTCR */
 5908:     /* XXX : not implemented */
 5909:     spr_register(env, SPR_LDSTCR, "LDSTCR",
 5910:                  SPR_NOACCESS, SPR_NOACCESS,
 5911:                  &spr_read_generic, &spr_write_generic,
 5912:                  0x00000000);
 5913:     /* ICTRL */
 5914:     /* XXX : not implemented */
 5915:     spr_register(env, SPR_ICTRL, "ICTRL",
 5916:                  SPR_NOACCESS, SPR_NOACCESS,
 5917:                  &spr_read_generic, &spr_write_generic,
 5918:                  0x00000000);
 5919:     /* MSSSR0 */
 5920:     /* XXX : not implemented */
 5921:     spr_register(env, SPR_MSSSR0, "MSSSR0",
 5922:                  SPR_NOACCESS, SPR_NOACCESS,
 5923:                  &spr_read_generic, &spr_write_generic,
 5924:                  0x00000000);
 5925:     /* PMC */
 5926:     /* XXX : not implemented */
 5927:     spr_register(env, SPR_PMC5, "PMC5",
 5928:                  SPR_NOACCESS, SPR_NOACCESS,
 5929:                  &spr_read_generic, &spr_write_generic,
 5930:                  0x00000000);
 5931:     /* XXX : not implemented */
 5932:     spr_register(env, SPR_UPMC5, "UPMC5",
 5933:                  &spr_read_ureg, SPR_NOACCESS,
 5934:                  &spr_read_ureg, SPR_NOACCESS,
 5935:                  0x00000000);
 5936:     /* XXX : not implemented */
 5937:     spr_register(env, SPR_PMC6, "PMC6",
 5938:                  SPR_NOACCESS, SPR_NOACCESS,
 5939:                  &spr_read_generic, &spr_write_generic,
 5940:                  0x00000000);
 5941:     /* XXX : not implemented */
 5942:     spr_register(env, SPR_UPMC6, "UPMC6",
 5943:                  &spr_read_ureg, SPR_NOACCESS,
 5944:                  &spr_read_ureg, SPR_NOACCESS,
 5945:                  0x00000000);
 5946:     /* SPRGs */
 5947:     spr_register(env, SPR_SPRG4, "SPRG4",
 5948:                  SPR_NOACCESS, SPR_NOACCESS,
 5949:                  &spr_read_generic, &spr_write_generic,
 5950:                  0x00000000);
 5951:     spr_register(env, SPR_USPRG4, "USPRG4",
 5952:                  &spr_read_ureg, SPR_NOACCESS,
 5953:                  &spr_read_ureg, SPR_NOACCESS,
 5954:                  0x00000000);
 5955:     spr_register(env, SPR_SPRG5, "SPRG5",
 5956:                  SPR_NOACCESS, SPR_NOACCESS,
 5957:                  &spr_read_generic, &spr_write_generic,
 5958:                  0x00000000);
 5959:     spr_register(env, SPR_USPRG5, "USPRG5",
 5960:                  &spr_read_ureg, SPR_NOACCESS,
 5961:                  &spr_read_ureg, SPR_NOACCESS,
 5962:                  0x00000000);
 5963:     spr_register(env, SPR_SPRG6, "SPRG6",
 5964:                  SPR_NOACCESS, SPR_NOACCESS,
 5965:                  &spr_read_generic, &spr_write_generic,
 5966:                  0x00000000);
 5967:     spr_register(env, SPR_USPRG6, "USPRG6",
 5968:                  &spr_read_ureg, SPR_NOACCESS,
 5969:                  &spr_read_ureg, SPR_NOACCESS,
 5970:                  0x00000000);
 5971:     spr_register(env, SPR_SPRG7, "SPRG7",
 5972:                  SPR_NOACCESS, SPR_NOACCESS,
 5973:                  &spr_read_generic, &spr_write_generic,
 5974:                  0x00000000);
 5975:     spr_register(env, SPR_USPRG7, "USPRG7",
 5976:                  &spr_read_ureg, SPR_NOACCESS,
 5977:                  &spr_read_ureg, SPR_NOACCESS,
 5978:                  0x00000000);
 5979:     /* Memory management */
 5980:     gen_low_BATs(env);
 5981:     gen_high_BATs(env);
 5982:     gen_74xx_soft_tlb(env, 128, 2);
 5983:     init_excp_7450(env);
 5984:     env->dcache_line_size = 32;
 5985:     env->icache_line_size = 32;
 5986:     /* Allocate hardware IRQ controller */
 5987:     ppc6xx_irq_init(env);
 5988: }
 5989: 
 5990: /* PowerPC 7457 (aka G4)                                                     */
 5991: #define POWERPC_INSNS_7457   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 5992:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 5993:                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
 5994:                               PPC_FLOAT_STFIWX |                              \
 5995:                               PPC_CACHE | PPC_CACHE_ICBI |                    \
 5996:                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
 5997:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 5998:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 5999:                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
 6000:                               PPC_SEGMENT | PPC_EXTERN |                      \
 6001:                               PPC_ALTIVEC)
 6002: #define POWERPC_INSNS2_7457  (PPC_NONE)
 6003: #define POWERPC_MSRM_7457    (0x000000000205FF77ULL)
 6004: #define POWERPC_MMU_7457     (POWERPC_MMU_SOFT_74xx)
 6005: #define POWERPC_EXCP_7457    (POWERPC_EXCP_74xx)
 6006: #define POWERPC_INPUT_7457   (PPC_FLAGS_INPUT_6xx)
 6007: #define POWERPC_BFDM_7457    (bfd_mach_ppc_7400)
 6008: #define POWERPC_FLAG_7457    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
 6009:                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
 6010:                               POWERPC_FLAG_BUS_CLK)
 6011: #define check_pow_7457       check_pow_hid0_74xx
 6012: 
 6013: __attribute__ (( unused ))
 6014: static void init_proc_7457 (CPUPPCState *env)
 6015: {
 6016:     gen_spr_ne_601(env);
 6017:     gen_spr_7xx(env);
 6018:     /* Time base */
 6019:     gen_tbl(env);
 6020:     /* 74xx specific SPR */
 6021:     gen_spr_74xx(env);
 6022:     /* Level 3 cache control */
 6023:     gen_l3_ctrl(env);
 6024:     /* L3ITCR1 */
 6025:     /* XXX : not implemented */
 6026:     spr_register(env, SPR_L3ITCR1, "L3ITCR1",
 6027:                  SPR_NOACCESS, SPR_NOACCESS,
 6028:                  &spr_read_generic, &spr_write_generic,
 6029:                  0x00000000);
 6030:     /* L3ITCR2 */
 6031:     /* XXX : not implemented */
 6032:     spr_register(env, SPR_L3ITCR2, "L3ITCR2",
 6033:                  SPR_NOACCESS, SPR_NOACCESS,
 6034:                  &spr_read_generic, &spr_write_generic,
 6035:                  0x00000000);
 6036:     /* L3ITCR3 */
 6037:     /* XXX : not implemented */
 6038:     spr_register(env, SPR_L3ITCR3, "L3ITCR3",
 6039:                  SPR_NOACCESS, SPR_NOACCESS,
 6040:                  &spr_read_generic, &spr_write_generic,
 6041:                  0x00000000);
 6042:     /* L3OHCR */
 6043:     /* XXX : not implemented */
 6044:     spr_register(env, SPR_L3OHCR, "L3OHCR",
 6045:                  SPR_NOACCESS, SPR_NOACCESS,
 6046:                  &spr_read_generic, &spr_write_generic,
 6047:                  0x00000000);
 6048:     /* LDSTCR */
 6049:     /* XXX : not implemented */
 6050:     spr_register(env, SPR_LDSTCR, "LDSTCR",
 6051:                  SPR_NOACCESS, SPR_NOACCESS,
 6052:                  &spr_read_generic, &spr_write_generic,
 6053:                  0x00000000);
 6054:     /* ICTRL */
 6055:     /* XXX : not implemented */
 6056:     spr_register(env, SPR_ICTRL, "ICTRL",
 6057:                  SPR_NOACCESS, SPR_NOACCESS,
 6058:                  &spr_read_generic, &spr_write_generic,
 6059:                  0x00000000);
 6060:     /* MSSSR0 */
 6061:     /* XXX : not implemented */
 6062:     spr_register(env, SPR_MSSSR0, "MSSSR0",
 6063:                  SPR_NOACCESS, SPR_NOACCESS,
 6064:                  &spr_read_generic, &spr_write_generic,
 6065:                  0x00000000);
 6066:     /* PMC */
 6067:     /* XXX : not implemented */
 6068:     spr_register(env, SPR_PMC5, "PMC5",
 6069:                  SPR_NOACCESS, SPR_NOACCESS,
 6070:                  &spr_read_generic, &spr_write_generic,
 6071:                  0x00000000);
 6072:     /* XXX : not implemented */
 6073:     spr_register(env, SPR_UPMC5, "UPMC5",
 6074:                  &spr_read_ureg, SPR_NOACCESS,
 6075:                  &spr_read_ureg, SPR_NOACCESS,
 6076:                  0x00000000);
 6077:     /* XXX : not implemented */
 6078:     spr_register(env, SPR_PMC6, "PMC6",
 6079:                  SPR_NOACCESS, SPR_NOACCESS,
 6080:                  &spr_read_generic, &spr_write_generic,
 6081:                  0x00000000);
 6082:     /* XXX : not implemented */
 6083:     spr_register(env, SPR_UPMC6, "UPMC6",
 6084:                  &spr_read_ureg, SPR_NOACCESS,
 6085:                  &spr_read_ureg, SPR_NOACCESS,
 6086:                  0x00000000);
 6087:     /* SPRGs */
 6088:     spr_register(env, SPR_SPRG4, "SPRG4",
 6089:                  SPR_NOACCESS, SPR_NOACCESS,
 6090:                  &spr_read_generic, &spr_write_generic,
 6091:                  0x00000000);
 6092:     spr_register(env, SPR_USPRG4, "USPRG4",
 6093:                  &spr_read_ureg, SPR_NOACCESS,
 6094:                  &spr_read_ureg, SPR_NOACCESS,
 6095:                  0x00000000);
 6096:     spr_register(env, SPR_SPRG5, "SPRG5",
 6097:                  SPR_NOACCESS, SPR_NOACCESS,
 6098:                  &spr_read_generic, &spr_write_generic,
 6099:                  0x00000000);
 6100:     spr_register(env, SPR_USPRG5, "USPRG5",
 6101:                  &spr_read_ureg, SPR_NOACCESS,
 6102:                  &spr_read_ureg, SPR_NOACCESS,
 6103:                  0x00000000);
 6104:     spr_register(env, SPR_SPRG6, "SPRG6",
 6105:                  SPR_NOACCESS, SPR_NOACCESS,
 6106:                  &spr_read_generic, &spr_write_generic,
 6107:                  0x00000000);
 6108:     spr_register(env, SPR_USPRG6, "USPRG6",
 6109:                  &spr_read_ureg, SPR_NOACCESS,
 6110:                  &spr_read_ureg, SPR_NOACCESS,
 6111:                  0x00000000);
 6112:     spr_register(env, SPR_SPRG7, "SPRG7",
 6113:                  SPR_NOACCESS, SPR_NOACCESS,
 6114:                  &spr_read_generic, &spr_write_generic,
 6115:                  0x00000000);
 6116:     spr_register(env, SPR_USPRG7, "USPRG7",
 6117:                  &spr_read_ureg, SPR_NOACCESS,
 6118:                  &spr_read_ureg, SPR_NOACCESS,
 6119:                  0x00000000);
 6120:     /* Memory management */
 6121:     gen_low_BATs(env);
 6122:     gen_high_BATs(env);
 6123:     gen_74xx_soft_tlb(env, 128, 2);
 6124:     init_excp_7450(env);
 6125:     env->dcache_line_size = 32;
 6126:     env->icache_line_size = 32;
 6127:     /* Allocate hardware IRQ controller */
 6128:     ppc6xx_irq_init(env);
 6129: }
 6130: 
 6131: #if defined (TARGET_PPC64)
 6132: /* PowerPC 970                                                               */
 6133: #define POWERPC_INSNS_970    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 6134:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 6135:                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
 6136:                               PPC_FLOAT_STFIWX |                              \
 6137:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
 6138:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 6139:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 6140:                               PPC_64B | PPC_ALTIVEC |                         \
 6141:                               PPC_SEGMENT_64B | PPC_SLBI)
 6142: #define POWERPC_INSNS2_970   (PPC_NONE)
 6143: #define POWERPC_MSRM_970     (0x900000000204FF36ULL)
 6144: #define POWERPC_MMU_970      (POWERPC_MMU_64B)
 6145: //#define POWERPC_EXCP_970     (POWERPC_EXCP_970)
 6146: #define POWERPC_INPUT_970    (PPC_FLAGS_INPUT_970)
 6147: #define POWERPC_BFDM_970     (bfd_mach_ppc64)
 6148: #define POWERPC_FLAG_970     (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
 6149:                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
 6150:                               POWERPC_FLAG_BUS_CLK)
 6151: 
 6152: #if defined(CONFIG_USER_ONLY)
 6153: #define POWERPC970_HID5_INIT 0x00000080
 6154: #else
 6155: #define POWERPC970_HID5_INIT 0x00000000
 6156: #endif
 6157: 
 6158: static int check_pow_970 (CPUPPCState *env)
 6159: {
 6160:     if (env->spr[SPR_HID0] & 0x00600000)
 6161:         return 1;
 6162: 
 6163:     return 0;
 6164: }
 6165: 
 6166: static void init_proc_970 (CPUPPCState *env)
 6167: {
 6168:     gen_spr_ne_601(env);
 6169:     gen_spr_7xx(env);
 6170:     /* Time base */
 6171:     gen_tbl(env);
 6172:     /* Hardware implementation registers */
 6173:     /* XXX : not implemented */
 6174:     spr_register(env, SPR_HID0, "HID0",
 6175:                  SPR_NOACCESS, SPR_NOACCESS,
 6176:                  &spr_read_generic, &spr_write_clear,
 6177:                  0x60000000);
 6178:     /* XXX : not implemented */
 6179:     spr_register(env, SPR_HID1, "HID1",
 6180:                  SPR_NOACCESS, SPR_NOACCESS,
 6181:                  &spr_read_generic, &spr_write_generic,
 6182:                  0x00000000);
 6183:     /* XXX : not implemented */
 6184:     spr_register(env, SPR_750FX_HID2, "HID2",
 6185:                  SPR_NOACCESS, SPR_NOACCESS,
 6186:                  &spr_read_generic, &spr_write_generic,
 6187:                  0x00000000);
 6188:     /* XXX : not implemented */
 6189:     spr_register(env, SPR_970_HID5, "HID5",
 6190:                  SPR_NOACCESS, SPR_NOACCESS,
 6191:                  &spr_read_generic, &spr_write_generic,
 6192:                  POWERPC970_HID5_INIT);
 6193:     /* XXX : not implemented */
 6194:     spr_register(env, SPR_L2CR, "L2CR",
 6195:                  SPR_NOACCESS, SPR_NOACCESS,
 6196:                  &spr_read_generic, &spr_write_generic,
 6197:                  0x00000000);
 6198:     /* Memory management */
 6199:     /* XXX: not correct */
 6200:     gen_low_BATs(env);
 6201:     /* XXX : not implemented */
 6202:     spr_register(env, SPR_MMUCFG, "MMUCFG",
 6203:                  SPR_NOACCESS, SPR_NOACCESS,
 6204:                  &spr_read_generic, SPR_NOACCESS,
 6205:                  0x00000000); /* TOFIX */
 6206:     /* XXX : not implemented */
 6207:     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
 6208:                  SPR_NOACCESS, SPR_NOACCESS,
 6209:                  &spr_read_generic, &spr_write_generic,
 6210:                  0x00000000); /* TOFIX */
 6211:     spr_register(env, SPR_HIOR, "SPR_HIOR",
 6212:                  SPR_NOACCESS, SPR_NOACCESS,
 6213:                  &spr_read_hior, &spr_write_hior,
 6214:                  0x00000000);
 6215: #if !defined(CONFIG_USER_ONLY)
 6216:     env->slb_nr = 32;
 6217: #endif
 6218:     init_excp_970(env);
 6219:     env->dcache_line_size = 128;
 6220:     env->icache_line_size = 128;
 6221:     /* Allocate hardware IRQ controller */
 6222:     ppc970_irq_init(env);
 6223:     /* Can't find information on what this should be on reset.  This
 6224:      * value is the one used by 74xx processors. */
 6225:     vscr_init(env, 0x00010000);
 6226: }
 6227: 
 6228: /* PowerPC 970FX (aka G5)                                                    */
 6229: #define POWERPC_INSNS_970FX  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 6230:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 6231:                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
 6232:                               PPC_FLOAT_STFIWX |                              \
 6233:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
 6234:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 6235:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 6236:                               PPC_64B | PPC_ALTIVEC |                         \
 6237:                               PPC_SEGMENT_64B | PPC_SLBI)
 6238: #define POWERPC_INSNS2_970FX (PPC_NONE)
 6239: #define POWERPC_MSRM_970FX   (0x800000000204FF36ULL)
 6240: #define POWERPC_MMU_970FX    (POWERPC_MMU_64B)
 6241: #define POWERPC_EXCP_970FX   (POWERPC_EXCP_970)
 6242: #define POWERPC_INPUT_970FX  (PPC_FLAGS_INPUT_970)
 6243: #define POWERPC_BFDM_970FX   (bfd_mach_ppc64)
 6244: #define POWERPC_FLAG_970FX   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
 6245:                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
 6246:                               POWERPC_FLAG_BUS_CLK)
 6247: 
 6248: static int check_pow_970FX (CPUPPCState *env)
 6249: {
 6250:     if (env->spr[SPR_HID0] & 0x00600000)
 6251:         return 1;
 6252: 
 6253:     return 0;
 6254: }
 6255: 
 6256: static void init_proc_970FX (CPUPPCState *env)
 6257: {
 6258:     gen_spr_ne_601(env);
 6259:     gen_spr_7xx(env);
 6260:     /* Time base */
 6261:     gen_tbl(env);
 6262:     /* Hardware implementation registers */
 6263:     /* XXX : not implemented */
 6264:     spr_register(env, SPR_HID0, "HID0",
 6265:                  SPR_NOACCESS, SPR_NOACCESS,
 6266:                  &spr_read_generic, &spr_write_clear,
 6267:                  0x60000000);
 6268:     /* XXX : not implemented */
 6269:     spr_register(env, SPR_HID1, "HID1",
 6270:                  SPR_NOACCESS, SPR_NOACCESS,
 6271:                  &spr_read_generic, &spr_write_generic,
 6272:                  0x00000000);
 6273:     /* XXX : not implemented */
 6274:     spr_register(env, SPR_750FX_HID2, "HID2",
 6275:                  SPR_NOACCESS, SPR_NOACCESS,
 6276:                  &spr_read_generic, &spr_write_generic,
 6277:                  0x00000000);
 6278:     /* XXX : not implemented */
 6279:     spr_register(env, SPR_970_HID5, "HID5",
 6280:                  SPR_NOACCESS, SPR_NOACCESS,
 6281:                  &spr_read_generic, &spr_write_generic,
 6282:                  POWERPC970_HID5_INIT);
 6283:     /* XXX : not implemented */
 6284:     spr_register(env, SPR_L2CR, "L2CR",
 6285:                  SPR_NOACCESS, SPR_NOACCESS,
 6286:                  &spr_read_generic, &spr_write_generic,
 6287:                  0x00000000);
 6288:     /* Memory management */
 6289:     /* XXX: not correct */
 6290:     gen_low_BATs(env);
 6291:     /* XXX : not implemented */
 6292:     spr_register(env, SPR_MMUCFG, "MMUCFG",
 6293:                  SPR_NOACCESS, SPR_NOACCESS,
 6294:                  &spr_read_generic, SPR_NOACCESS,
 6295:                  0x00000000); /* TOFIX */
 6296:     /* XXX : not implemented */
 6297:     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
 6298:                  SPR_NOACCESS, SPR_NOACCESS,
 6299:                  &spr_read_generic, &spr_write_generic,
 6300:                  0x00000000); /* TOFIX */
 6301:     spr_register(env, SPR_HIOR, "SPR_HIOR",
 6302:                  SPR_NOACCESS, SPR_NOACCESS,
 6303:                  &spr_read_hior, &spr_write_hior,
 6304:                  0x00000000);
 6305:     spr_register(env, SPR_CTRL, "SPR_CTRL",
 6306:                  SPR_NOACCESS, SPR_NOACCESS,
 6307:                  &spr_read_generic, &spr_write_generic,
 6308:                  0x00000000);
 6309:     spr_register(env, SPR_UCTRL, "SPR_UCTRL",
 6310:                  SPR_NOACCESS, SPR_NOACCESS,
 6311:                  &spr_read_generic, &spr_write_generic,
 6312:                  0x00000000);
 6313:     spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
 6314:                  &spr_read_generic, &spr_write_generic,
 6315:                  &spr_read_generic, &spr_write_generic,
 6316:                  0x00000000);
 6317: #if !defined(CONFIG_USER_ONLY)
 6318:     env->slb_nr = 64;
 6319: #endif
 6320:     init_excp_970(env);
 6321:     env->dcache_line_size = 128;
 6322:     env->icache_line_size = 128;
 6323:     /* Allocate hardware IRQ controller */
 6324:     ppc970_irq_init(env);
 6325:     /* Can't find information on what this should be on reset.  This
 6326:      * value is the one used by 74xx processors. */
 6327:     vscr_init(env, 0x00010000);
 6328: }
 6329: 
 6330: /* PowerPC 970 GX                                                            */
 6331: #define POWERPC_INSNS_970GX  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 6332:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 6333:                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
 6334:                               PPC_FLOAT_STFIWX |                              \
 6335:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
 6336:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 6337:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 6338:                               PPC_64B | PPC_ALTIVEC |                         \
 6339:                               PPC_SEGMENT_64B | PPC_SLBI)
 6340: #define POWERPC_INSNS2_970GX (PPC_NONE)
 6341: #define POWERPC_MSRM_970GX   (0x800000000204FF36ULL)
 6342: #define POWERPC_MMU_970GX    (POWERPC_MMU_64B)
 6343: #define POWERPC_EXCP_970GX   (POWERPC_EXCP_970)
 6344: #define POWERPC_INPUT_970GX  (PPC_FLAGS_INPUT_970)
 6345: #define POWERPC_BFDM_970GX   (bfd_mach_ppc64)
 6346: #define POWERPC_FLAG_970GX   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
 6347:                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
 6348:                               POWERPC_FLAG_BUS_CLK)
 6349: 
 6350: static int check_pow_970GX (CPUPPCState *env)
 6351: {
 6352:     if (env->spr[SPR_HID0] & 0x00600000)
 6353:         return 1;
 6354: 
 6355:     return 0;
 6356: }
 6357: 
 6358: static void init_proc_970GX (CPUPPCState *env)
 6359: {
 6360:     gen_spr_ne_601(env);
 6361:     gen_spr_7xx(env);
 6362:     /* Time base */
 6363:     gen_tbl(env);
 6364:     /* Hardware implementation registers */
 6365:     /* XXX : not implemented */
 6366:     spr_register(env, SPR_HID0, "HID0",
 6367:                  SPR_NOACCESS, SPR_NOACCESS,
 6368:                  &spr_read_generic, &spr_write_clear,
 6369:                  0x60000000);
 6370:     /* XXX : not implemented */
 6371:     spr_register(env, SPR_HID1, "HID1",
 6372:                  SPR_NOACCESS, SPR_NOACCESS,
 6373:                  &spr_read_generic, &spr_write_generic,
 6374:                  0x00000000);
 6375:     /* XXX : not implemented */
 6376:     spr_register(env, SPR_750FX_HID2, "HID2",
 6377:                  SPR_NOACCESS, SPR_NOACCESS,
 6378:                  &spr_read_generic, &spr_write_generic,
 6379:                  0x00000000);
 6380:     /* XXX : not implemented */
 6381:     spr_register(env, SPR_970_HID5, "HID5",
 6382:                  SPR_NOACCESS, SPR_NOACCESS,
 6383:                  &spr_read_generic, &spr_write_generic,
 6384:                  POWERPC970_HID5_INIT);
 6385:     /* XXX : not implemented */
 6386:     spr_register(env, SPR_L2CR, "L2CR",
 6387:                  SPR_NOACCESS, SPR_NOACCESS,
 6388:                  &spr_read_generic, &spr_write_generic,
 6389:                  0x00000000);
 6390:     /* Memory management */
 6391:     /* XXX: not correct */
 6392:     gen_low_BATs(env);
 6393:     /* XXX : not implemented */
 6394:     spr_register(env, SPR_MMUCFG, "MMUCFG",
 6395:                  SPR_NOACCESS, SPR_NOACCESS,
 6396:                  &spr_read_generic, SPR_NOACCESS,
 6397:                  0x00000000); /* TOFIX */
 6398:     /* XXX : not implemented */
 6399:     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
 6400:                  SPR_NOACCESS, SPR_NOACCESS,
 6401:                  &spr_read_generic, &spr_write_generic,
 6402:                  0x00000000); /* TOFIX */
 6403:     spr_register(env, SPR_HIOR, "SPR_HIOR",
 6404:                  SPR_NOACCESS, SPR_NOACCESS,
 6405:                  &spr_read_hior, &spr_write_hior,
 6406:                  0x00000000);
 6407: #if !defined(CONFIG_USER_ONLY)
 6408:     env->slb_nr = 32;
 6409: #endif
 6410:     init_excp_970(env);
 6411:     env->dcache_line_size = 128;
 6412:     env->icache_line_size = 128;
 6413:     /* Allocate hardware IRQ controller */
 6414:     ppc970_irq_init(env);
 6415:     /* Can't find information on what this should be on reset.  This
 6416:      * value is the one used by 74xx processors. */
 6417:     vscr_init(env, 0x00010000);
 6418: }
 6419: 
 6420: /* PowerPC 970 MP                                                            */
 6421: #define POWERPC_INSNS_970MP  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 6422:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 6423:                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
 6424:                               PPC_FLOAT_STFIWX |                              \
 6425:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
 6426:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 6427:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 6428:                               PPC_64B | PPC_ALTIVEC |                         \
 6429:                               PPC_SEGMENT_64B | PPC_SLBI)
 6430: #define POWERPC_INSNS2_970MP (PPC_NONE)
 6431: #define POWERPC_MSRM_970MP   (0x900000000204FF36ULL)
 6432: #define POWERPC_MMU_970MP    (POWERPC_MMU_64B)
 6433: #define POWERPC_EXCP_970MP   (POWERPC_EXCP_970)
 6434: #define POWERPC_INPUT_970MP  (PPC_FLAGS_INPUT_970)
 6435: #define POWERPC_BFDM_970MP   (bfd_mach_ppc64)
 6436: #define POWERPC_FLAG_970MP   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
 6437:                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
 6438:                               POWERPC_FLAG_BUS_CLK)
 6439: 
 6440: static int check_pow_970MP (CPUPPCState *env)
 6441: {
 6442:     if (env->spr[SPR_HID0] & 0x01C00000)
 6443:         return 1;
 6444: 
 6445:     return 0;
 6446: }
 6447: 
 6448: static void init_proc_970MP (CPUPPCState *env)
 6449: {
 6450:     gen_spr_ne_601(env);
 6451:     gen_spr_7xx(env);
 6452:     /* Time base */
 6453:     gen_tbl(env);
 6454:     /* Hardware implementation registers */
 6455:     /* XXX : not implemented */
 6456:     spr_register(env, SPR_HID0, "HID0",
 6457:                  SPR_NOACCESS, SPR_NOACCESS,
 6458:                  &spr_read_generic, &spr_write_clear,
 6459:                  0x60000000);
 6460:     /* XXX : not implemented */
 6461:     spr_register(env, SPR_HID1, "HID1",
 6462:                  SPR_NOACCESS, SPR_NOACCESS,
 6463:                  &spr_read_generic, &spr_write_generic,
 6464:                  0x00000000);
 6465:     /* XXX : not implemented */
 6466:     spr_register(env, SPR_750FX_HID2, "HID2",
 6467:                  SPR_NOACCESS, SPR_NOACCESS,
 6468:                  &spr_read_generic, &spr_write_generic,
 6469:                  0x00000000);
 6470:     /* XXX : not implemented */
 6471:     spr_register(env, SPR_970_HID5, "HID5",
 6472:                  SPR_NOACCESS, SPR_NOACCESS,
 6473:                  &spr_read_generic, &spr_write_generic,
 6474:                  POWERPC970_HID5_INIT);
 6475:     /* XXX : not implemented */
 6476:     spr_register(env, SPR_L2CR, "L2CR",
 6477:                  SPR_NOACCESS, SPR_NOACCESS,
 6478:                  &spr_read_generic, &spr_write_generic,
 6479:                  0x00000000);
 6480:     /* Memory management */
 6481:     /* XXX: not correct */
 6482:     gen_low_BATs(env);
 6483:     /* XXX : not implemented */
 6484:     spr_register(env, SPR_MMUCFG, "MMUCFG",
 6485:                  SPR_NOACCESS, SPR_NOACCESS,
 6486:                  &spr_read_generic, SPR_NOACCESS,
 6487:                  0x00000000); /* TOFIX */
 6488:     /* XXX : not implemented */
 6489:     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
 6490:                  SPR_NOACCESS, SPR_NOACCESS,
 6491:                  &spr_read_generic, &spr_write_generic,
 6492:                  0x00000000); /* TOFIX */
 6493:     spr_register(env, SPR_HIOR, "SPR_HIOR",
 6494:                  SPR_NOACCESS, SPR_NOACCESS,
 6495:                  &spr_read_hior, &spr_write_hior,
 6496:                  0x00000000);
 6497: #if !defined(CONFIG_USER_ONLY)
 6498:     env->slb_nr = 32;
 6499: #endif
 6500:     init_excp_970(env);
 6501:     env->dcache_line_size = 128;
 6502:     env->icache_line_size = 128;
 6503:     /* Allocate hardware IRQ controller */
 6504:     ppc970_irq_init(env);
 6505:     /* Can't find information on what this should be on reset.  This
 6506:      * value is the one used by 74xx processors. */
 6507:     vscr_init(env, 0x00010000);
 6508: }
 6509: 
 6510: #if defined(TARGET_PPC64)
 6511: /* POWER7 */
 6512: #define POWERPC_INSNS_POWER7  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 6513:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 6514:                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
 6515:                               PPC_FLOAT_STFIWX |                              \
 6516:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
 6517:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 6518:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 6519:                               PPC_64B | PPC_ALTIVEC |                         \
 6520:                               PPC_SEGMENT_64B | PPC_SLBI |                    \
 6521:                               PPC_POPCNTB | PPC_POPCNTWD)
 6522: #define POWERPC_INSNS2_POWER7 (PPC2_VSX | PPC2_DFP)
 6523: #define POWERPC_MSRM_POWER7   (0x800000000204FF36ULL)
 6524: #define POWERPC_MMU_POWER7    (POWERPC_MMU_2_06)
 6525: #define POWERPC_EXCP_POWER7   (POWERPC_EXCP_POWER7)
 6526: #define POWERPC_INPUT_POWER7  (PPC_FLAGS_INPUT_POWER7)
 6527: #define POWERPC_BFDM_POWER7   (bfd_mach_ppc64)
 6528: #define POWERPC_FLAG_POWER7   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
 6529:                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
 6530:                               POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR)
 6531: #define check_pow_POWER7    check_pow_nocheck
 6532: 
 6533: static void init_proc_POWER7 (CPUPPCState *env)
 6534: {
 6535:     gen_spr_ne_601(env);
 6536:     gen_spr_7xx(env);
 6537:     /* Time base */
 6538:     gen_tbl(env);
 6539: #if !defined(CONFIG_USER_ONLY)
 6540:     /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
 6541:     spr_register(env, SPR_PURR,   "PURR",
 6542:                  &spr_read_purr, SPR_NOACCESS,
 6543:                  &spr_read_purr, SPR_NOACCESS,
 6544:                  0x00000000);
 6545:     spr_register(env, SPR_SPURR,   "SPURR",
 6546:                  &spr_read_purr, SPR_NOACCESS,
 6547:                  &spr_read_purr, SPR_NOACCESS,
 6548:                  0x00000000);
 6549:     spr_register(env, SPR_CFAR, "SPR_CFAR",
 6550:                  SPR_NOACCESS, SPR_NOACCESS,
 6551:                  &spr_read_cfar, &spr_write_cfar,
 6552:                  0x00000000);
 6553:     spr_register(env, SPR_DSCR, "SPR_DSCR",
 6554:                  SPR_NOACCESS, SPR_NOACCESS,
 6555:                  &spr_read_generic, &spr_write_generic,
 6556:                  0x00000000);
 6557: #endif /* !CONFIG_USER_ONLY */
 6558:     /* Memory management */
 6559:     /* XXX : not implemented */
 6560:     spr_register(env, SPR_MMUCFG, "MMUCFG",
 6561:                  SPR_NOACCESS, SPR_NOACCESS,
 6562:                  &spr_read_generic, SPR_NOACCESS,
 6563:                  0x00000000); /* TOFIX */
 6564:     /* XXX : not implemented */
 6565:     spr_register(env, SPR_CTRL, "SPR_CTRLT",
 6566:                  SPR_NOACCESS, SPR_NOACCESS,
 6567:                  &spr_read_generic, &spr_write_generic,
 6568:                  0x80800000);
 6569:     spr_register(env, SPR_UCTRL, "SPR_CTRLF",
 6570:                  SPR_NOACCESS, SPR_NOACCESS,
 6571:                  &spr_read_generic, &spr_write_generic,
 6572:                  0x80800000);
 6573:     spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
 6574:                  &spr_read_generic, &spr_write_generic,
 6575:                  &spr_read_generic, &spr_write_generic,
 6576:                  0x00000000);
 6577: #if !defined(CONFIG_USER_ONLY)
 6578:     env->slb_nr = 32;
 6579: #endif
 6580:     init_excp_POWER7(env);
 6581:     env->dcache_line_size = 128;
 6582:     env->icache_line_size = 128;
 6583:     /* Allocate hardware IRQ controller */
 6584:     ppcPOWER7_irq_init(env);
 6585:     /* Can't find information on what this should be on reset.  This
 6586:      * value is the one used by 74xx processors. */
 6587:     vscr_init(env, 0x00010000);
 6588: }
 6589: #endif /* TARGET_PPC64 */
 6590: 
 6591: /* PowerPC 620                                                               */
 6592: #define POWERPC_INSNS_620    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
 6593:                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
 6594:                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
 6595:                               PPC_FLOAT_STFIWX |                              \
 6596:                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
 6597:                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
 6598:                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
 6599:                               PPC_SEGMENT | PPC_EXTERN |                      \
 6600:                               PPC_64B | PPC_SLBI)
 6601: #define POWERPC_INSNS2_620   (PPC_NONE)
 6602: #define POWERPC_MSRM_620     (0x800000000005FF77ULL)
 6603: //#define POWERPC_MMU_620      (POWERPC_MMU_620)
 6604: #define POWERPC_EXCP_620     (POWERPC_EXCP_970)
 6605: #define POWERPC_INPUT_620    (PPC_FLAGS_INPUT_6xx)
 6606: #define POWERPC_BFDM_620     (bfd_mach_ppc64)
 6607: #define POWERPC_FLAG_620     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |            \
 6608:                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
 6609: #define check_pow_620        check_pow_nocheck /* Check this */
 6610: 
 6611: __attribute__ (( unused ))
 6612: static void init_proc_620 (CPUPPCState *env)
 6613: {
 6614:     gen_spr_ne_601(env);
 6615:     gen_spr_620(env);
 6616:     /* Time base */
 6617:     gen_tbl(env);
 6618:     /* Hardware implementation registers */
 6619:     /* XXX : not implemented */
 6620:     spr_register(env, SPR_HID0, "HID0",
 6621:                  SPR_NOACCESS, SPR_NOACCESS,
 6622:                  &spr_read_generic, &spr_write_generic,
 6623:                  0x00000000);
 6624:     /* Memory management */
 6625:     gen_low_BATs(env);
 6626:     init_excp_620(env);
 6627:     env->dcache_line_size = 64;
 6628:     env->icache_line_size = 64;
 6629:     /* Allocate hardware IRQ controller */
 6630:     ppc6xx_irq_init(env);
 6631: }
 6632: #endif /* defined (TARGET_PPC64) */
 6633: 
 6634: /* Default 32 bits PowerPC target will be 604 */
 6635: #define CPU_POWERPC_PPC32     CPU_POWERPC_604
 6636: #define POWERPC_INSNS_PPC32   POWERPC_INSNS_604
 6637: #define POWERPC_INSNS2_PPC32  POWERPC_INSNS2_604
 6638: #define POWERPC_MSRM_PPC32    POWERPC_MSRM_604
 6639: #define POWERPC_MMU_PPC32     POWERPC_MMU_604
 6640: #define POWERPC_EXCP_PPC32    POWERPC_EXCP_604
 6641: #define POWERPC_INPUT_PPC32   POWERPC_INPUT_604
 6642: #define POWERPC_BFDM_PPC32    POWERPC_BFDM_604
 6643: #define POWERPC_FLAG_PPC32    POWERPC_FLAG_604
 6644: #define check_pow_PPC32       check_pow_604
 6645: #define init_proc_PPC32       init_proc_604
 6646: 
 6647: /* Default 64 bits PowerPC target will be 970 FX */
 6648: #define CPU_POWERPC_PPC64     CPU_POWERPC_970FX
 6649: #define POWERPC_INSNS_PPC64   POWERPC_INSNS_970FX
 6650: #define POWERPC_INSNS2_PPC64  POWERPC_INSNS2_970FX
 6651: #define POWERPC_MSRM_PPC64    POWERPC_MSRM_970FX
 6652: #define POWERPC_MMU_PPC64     POWERPC_MMU_970FX
 6653: #define POWERPC_EXCP_PPC64    POWERPC_EXCP_970FX
 6654: #define POWERPC_INPUT_PPC64   POWERPC_INPUT_970FX
 6655: #define POWERPC_BFDM_PPC64    POWERPC_BFDM_970FX
 6656: #define POWERPC_FLAG_PPC64    POWERPC_FLAG_970FX
 6657: #define check_pow_PPC64       check_pow_970FX
 6658: #define init_proc_PPC64       init_proc_970FX
 6659: 
 6660: /* Default PowerPC target will be PowerPC 32 */
 6661: #if defined (TARGET_PPC64) && 0 // XXX: TODO
 6662: #define CPU_POWERPC_DEFAULT    CPU_POWERPC_PPC64
 6663: #define POWERPC_INSNS_DEFAULT  POWERPC_INSNS_PPC64
 6664: #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC64
 6665: #define POWERPC_MSRM_DEFAULT   POWERPC_MSRM_PPC64
 6666: #define POWERPC_MMU_DEFAULT    POWERPC_MMU_PPC64
 6667: #define POWERPC_EXCP_DEFAULT   POWERPC_EXCP_PPC64
 6668: #define POWERPC_INPUT_DEFAULT  POWERPC_INPUT_PPC64
 6669: #define POWERPC_BFDM_DEFAULT   POWERPC_BFDM_PPC64
 6670: #define POWERPC_FLAG_DEFAULT   POWERPC_FLAG_PPC64
 6671: #define check_pow_DEFAULT      check_pow_PPC64
 6672: #define init_proc_DEFAULT      init_proc_PPC64
 6673: #else
 6674: #define CPU_POWERPC_DEFAULT    CPU_POWERPC_PPC32
 6675: #define POWERPC_INSNS_DEFAULT  POWERPC_INSNS_PPC32
 6676: #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC32
 6677: #define POWERPC_MSRM_DEFAULT   POWERPC_MSRM_PPC32
 6678: #define POWERPC_MMU_DEFAULT    POWERPC_MMU_PPC32
 6679: #define POWERPC_EXCP_DEFAULT   POWERPC_EXCP_PPC32
 6680: #define POWERPC_INPUT_DEFAULT  POWERPC_INPUT_PPC32
 6681: #define POWERPC_BFDM_DEFAULT   POWERPC_BFDM_PPC32
 6682: #define POWERPC_FLAG_DEFAULT   POWERPC_FLAG_PPC32
 6683: #define check_pow_DEFAULT      check_pow_PPC32
 6684: #define init_proc_DEFAULT      init_proc_PPC32
 6685: #endif
 6686: 
 6687: /*****************************************************************************/
 6688: /* PVR definitions for most known PowerPC                                    */
 6689: enum {
 6690:     /* PowerPC 401 family */
 6691:     /* Generic PowerPC 401 */
 6692: #define CPU_POWERPC_401              CPU_POWERPC_401G2
 6693:     /* PowerPC 401 cores */
 6694:     CPU_POWERPC_401A1              = 0x00210000,
 6695:     CPU_POWERPC_401B2              = 0x00220000,
 6696: #if 0
 6697:     CPU_POWERPC_401B3              = xxx,
 6698: #endif
 6699:     CPU_POWERPC_401C2              = 0x00230000,
 6700:     CPU_POWERPC_401D2              = 0x00240000,
 6701:     CPU_POWERPC_401E2              = 0x00250000,
 6702:     CPU_POWERPC_401F2              = 0x00260000,
 6703:     CPU_POWERPC_401G2              = 0x00270000,
 6704:     /* PowerPC 401 microcontrolers */
 6705: #if 0
 6706:     CPU_POWERPC_401GF              = xxx,
 6707: #endif
 6708: #define CPU_POWERPC_IOP480           CPU_POWERPC_401B2
 6709:     /* IBM Processor for Network Resources */
 6710:     CPU_POWERPC_COBRA              = 0x10100000, /* XXX: 405 ? */
 6711: #if 0
 6712:     CPU_POWERPC_XIPCHIP            = xxx,
 6713: #endif
 6714:     /* PowerPC 403 family */
 6715:     /* Generic PowerPC 403 */
 6716: #define CPU_POWERPC_403              CPU_POWERPC_403GC
 6717:     /* PowerPC 403 microcontrollers */
 6718:     CPU_POWERPC_403GA              = 0x00200011,
 6719:     CPU_POWERPC_403GB              = 0x00200100,
 6720:     CPU_POWERPC_403GC              = 0x00200200,
 6721:     CPU_POWERPC_403GCX             = 0x00201400,
 6722: #if 0
 6723:     CPU_POWERPC_403GP              = xxx,
 6724: #endif
 6725:     /* PowerPC 405 family */
 6726:     /* Generic PowerPC 405 */
 6727: #define CPU_POWERPC_405              CPU_POWERPC_405D4
 6728:     /* PowerPC 405 cores */
 6729: #if 0
 6730:     CPU_POWERPC_405A3              = xxx,
 6731: #endif
 6732: #if 0
 6733:     CPU_POWERPC_405A4              = xxx,
 6734: #endif
 6735: #if 0
 6736:     CPU_POWERPC_405B3              = xxx,
 6737: #endif
 6738: #if 0
 6739:     CPU_POWERPC_405B4              = xxx,
 6740: #endif
 6741: #if 0
 6742:     CPU_POWERPC_405C3              = xxx,
 6743: #endif
 6744: #if 0
 6745:     CPU_POWERPC_405C4              = xxx,
 6746: #endif
 6747:     CPU_POWERPC_405D2              = 0x20010000,
 6748: #if 0
 6749:     CPU_POWERPC_405D3              = xxx,
 6750: #endif
 6751:     CPU_POWERPC_405D4              = 0x41810000,
 6752: #if 0
 6753:     CPU_POWERPC_405D5              = xxx,
 6754: #endif
 6755: #if 0
 6756:     CPU_POWERPC_405E4              = xxx,
 6757: #endif
 6758: #if 0
 6759:     CPU_POWERPC_405F4              = xxx,
 6760: #endif
 6761: #if 0
 6762:     CPU_POWERPC_405F5              = xxx,
 6763: #endif
 6764: #if 0
 6765:     CPU_POWERPC_405F6              = xxx,
 6766: #endif
 6767:     /* PowerPC 405 microcontrolers */
 6768:     /* XXX: missing 0x200108a0 */
 6769: #define CPU_POWERPC_405CR            CPU_POWERPC_405CRc
 6770:     CPU_POWERPC_405CRa             = 0x40110041,
 6771:     CPU_POWERPC_405CRb             = 0x401100C5,
 6772:     CPU_POWERPC_405CRc             = 0x40110145,
 6773:     CPU_POWERPC_405EP              = 0x51210950,
 6774: #if 0
 6775:     CPU_POWERPC_405EXr             = xxx,
 6776: #endif
 6777:     CPU_POWERPC_405EZ              = 0x41511460, /* 0x51210950 ? */
 6778: #if 0
 6779:     CPU_POWERPC_405FX              = xxx,
 6780: #endif
 6781: #define CPU_POWERPC_405GP            CPU_POWERPC_405GPd
 6782:     CPU_POWERPC_405GPa             = 0x40110000,
 6783:     CPU_POWERPC_405GPb             = 0x40110040,
 6784:     CPU_POWERPC_405GPc             = 0x40110082,
 6785:     CPU_POWERPC_405GPd             = 0x401100C4,
 6786: #define CPU_POWERPC_405GPe           CPU_POWERPC_405CRc
 6787:     CPU_POWERPC_405GPR             = 0x50910951,
 6788: #if 0
 6789:     CPU_POWERPC_405H               = xxx,
 6790: #endif
 6791: #if 0
 6792:     CPU_POWERPC_405L               = xxx,
 6793: #endif
 6794:     CPU_POWERPC_405LP              = 0x41F10000,
 6795: #if 0
 6796:     CPU_POWERPC_405PM              = xxx,
 6797: #endif
 6798: #if 0
 6799:     CPU_POWERPC_405PS              = xxx,
 6800: #endif
 6801: #if 0
 6802:     CPU_POWERPC_405S               = xxx,
 6803: #endif
 6804:     /* IBM network processors */
 6805:     CPU_POWERPC_NPE405H            = 0x414100C0,
 6806:     CPU_POWERPC_NPE405H2           = 0x41410140,
 6807:     CPU_POWERPC_NPE405L            = 0x416100C0,
 6808:     CPU_POWERPC_NPE4GS3            = 0x40B10000,
 6809: #if 0
 6810:     CPU_POWERPC_NPCxx1             = xxx,
 6811: #endif
 6812: #if 0
 6813:     CPU_POWERPC_NPR161             = xxx,
 6814: #endif
 6815: #if 0
 6816:     CPU_POWERPC_LC77700            = xxx,
 6817: #endif
 6818:     /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
 6819: #if 0
 6820:     CPU_POWERPC_STB01000           = xxx,
 6821: #endif
 6822: #if 0
 6823:     CPU_POWERPC_STB01010           = xxx,
 6824: #endif
 6825: #if 0
 6826:     CPU_POWERPC_STB0210            = xxx, /* 401B3 */
 6827: #endif
 6828:     CPU_POWERPC_STB03              = 0x40310000, /* 0x40130000 ? */
 6829: #if 0
 6830:     CPU_POWERPC_STB043             = xxx,
 6831: #endif
 6832: #if 0
 6833:     CPU_POWERPC_STB045             = xxx,
 6834: #endif
 6835:     CPU_POWERPC_STB04              = 0x41810000,
 6836:     CPU_POWERPC_STB25              = 0x51510950,
 6837: #if 0
 6838:     CPU_POWERPC_STB130             = xxx,
 6839: #endif
 6840:     /* Xilinx cores */
 6841:     CPU_POWERPC_X2VP4              = 0x20010820,
 6842: #define CPU_POWERPC_X2VP7            CPU_POWERPC_X2VP4
 6843:     CPU_POWERPC_X2VP20             = 0x20010860,
 6844: #define CPU_POWERPC_X2VP50           CPU_POWERPC_X2VP20
 6845: #if 0
 6846:     CPU_POWERPC_ZL10310            = xxx,
 6847: #endif
 6848: #if 0
 6849:     CPU_POWERPC_ZL10311            = xxx,
 6850: #endif
 6851: #if 0
 6852:     CPU_POWERPC_ZL10320            = xxx,
 6853: #endif
 6854: #if 0
 6855:     CPU_POWERPC_ZL10321            = xxx,
 6856: #endif
 6857:     /* PowerPC 440 family */
 6858:     /* Generic PowerPC 440 */
 6859: #define CPU_POWERPC_440              CPU_POWERPC_440GXf
 6860:     /* PowerPC 440 cores */
 6861: #if 0
 6862:     CPU_POWERPC_440A4              = xxx,
 6863: #endif
 6864:     CPU_POWERPC_440_XILINX         = 0x7ff21910,
 6865: #if 0
 6866:     CPU_POWERPC_440A5              = xxx,
 6867: #endif
 6868: #if 0
 6869:     CPU_POWERPC_440B4              = xxx,
 6870: #endif
 6871: #if 0
 6872:     CPU_POWERPC_440F5              = xxx,
 6873: #endif
 6874: #if 0
 6875:     CPU_POWERPC_440G5              = xxx,
 6876: #endif
 6877: #if 0
 6878:     CPU_POWERPC_440H4              = xxx,
 6879: #endif
 6880: #if 0
 6881:     CPU_POWERPC_440H6              = xxx,
 6882: #endif
 6883:     /* PowerPC 440 microcontrolers */
 6884: #define CPU_POWERPC_440EP            CPU_POWERPC_440EPb
 6885:     CPU_POWERPC_440EPa             = 0x42221850,
 6886:     CPU_POWERPC_440EPb             = 0x422218D3,
 6887: #define CPU_POWERPC_440GP            CPU_POWERPC_440GPc
 6888:     CPU_POWERPC_440GPb             = 0x40120440,
 6889:     CPU_POWERPC_440GPc             = 0x40120481,
 6890: #define CPU_POWERPC_440GR            CPU_POWERPC_440GRa
 6891: #define CPU_POWERPC_440GRa           CPU_POWERPC_440EPb
 6892:     CPU_POWERPC_440GRX             = 0x200008D0,
 6893: #define CPU_POWERPC_440EPX           CPU_POWERPC_440GRX
 6894: #define CPU_POWERPC_440GX            CPU_POWERPC_440GXf
 6895:     CPU_POWERPC_440GXa             = 0x51B21850,
 6896:     CPU_POWERPC_440GXb             = 0x51B21851,
 6897:     CPU_POWERPC_440GXc             = 0x51B21892,
 6898:     CPU_POWERPC_440GXf             = 0x51B21894,
 6899: #if 0
 6900:     CPU_POWERPC_440S               = xxx,
 6901: #endif
 6902:     CPU_POWERPC_440SP              = 0x53221850,
 6903:     CPU_POWERPC_440SP2             = 0x53221891,
 6904:     CPU_POWERPC_440SPE             = 0x53421890,
 6905:     /* PowerPC 460 family */
 6906: #if 0
 6907:     /* Generic PowerPC 464 */
 6908: #define CPU_POWERPC_464              CPU_POWERPC_464H90
 6909: #endif
 6910:     /* PowerPC 464 microcontrolers */
 6911: #if 0
 6912:     CPU_POWERPC_464H90             = xxx,
 6913: #endif
 6914: #if 0
 6915:     CPU_POWERPC_464H90FP           = xxx,
 6916: #endif
 6917:     /* Freescale embedded PowerPC cores */
 6918:     /* PowerPC MPC 5xx cores (aka RCPU) */
 6919:     CPU_POWERPC_MPC5xx             = 0x00020020,
 6920: #define CPU_POWERPC_MGT560           CPU_POWERPC_MPC5xx
 6921: #define CPU_POWERPC_MPC509           CPU_POWERPC_MPC5xx
 6922: #define CPU_POWERPC_MPC533           CPU_POWERPC_MPC5xx
 6923: #define CPU_POWERPC_MPC534           CPU_POWERPC_MPC5xx
 6924: #define CPU_POWERPC_MPC555           CPU_POWERPC_MPC5xx
 6925: #define CPU_POWERPC_MPC556           CPU_POWERPC_MPC5xx
 6926: #define CPU_POWERPC_MPC560           CPU_POWERPC_MPC5xx
 6927: #define CPU_POWERPC_MPC561           CPU_POWERPC_MPC5xx
 6928: #define CPU_POWERPC_MPC562           CPU_POWERPC_MPC5xx
 6929: #define CPU_POWERPC_MPC563           CPU_POWERPC_MPC5xx
 6930: #define CPU_POWERPC_MPC564           CPU_POWERPC_MPC5xx
 6931: #define CPU_POWERPC_MPC565           CPU_POWERPC_MPC5xx
 6932: #define CPU_POWERPC_MPC566           CPU_POWERPC_MPC5xx
 6933:     /* PowerPC MPC 8xx cores (aka PowerQUICC) */
 6934:     CPU_POWERPC_MPC8xx             = 0x00500000,
 6935: #define CPU_POWERPC_MGT823           CPU_POWERPC_MPC8xx
 6936: #define CPU_POWERPC_MPC821           CPU_POWERPC_MPC8xx
 6937: #define CPU_POWERPC_MPC823           CPU_POWERPC_MPC8xx
 6938: #define CPU_POWERPC_MPC850           CPU_POWERPC_MPC8xx
 6939: #define CPU_POWERPC_MPC852T          CPU_POWERPC_MPC8xx
 6940: #define CPU_POWERPC_MPC855T          CPU_POWERPC_MPC8xx
 6941: #define CPU_POWERPC_MPC857           CPU_POWERPC_MPC8xx
 6942: #define CPU_POWERPC_MPC859           CPU_POWERPC_MPC8xx
 6943: #define CPU_POWERPC_MPC860           CPU_POWERPC_MPC8xx
 6944: #define CPU_POWERPC_MPC862           CPU_POWERPC_MPC8xx
 6945: #define CPU_POWERPC_MPC866           CPU_POWERPC_MPC8xx
 6946: #define CPU_POWERPC_MPC870           CPU_POWERPC_MPC8xx
 6947: #define CPU_POWERPC_MPC875           CPU_POWERPC_MPC8xx
 6948: #define CPU_POWERPC_MPC880           CPU_POWERPC_MPC8xx
 6949: #define CPU_POWERPC_MPC885           CPU_POWERPC_MPC8xx
 6950:     /* G2 cores (aka PowerQUICC-II) */
 6951:     CPU_POWERPC_G2                 = 0x00810011,
 6952:     CPU_POWERPC_G2H4               = 0x80811010,
 6953:     CPU_POWERPC_G2gp               = 0x80821010,
 6954:     CPU_POWERPC_G2ls               = 0x90810010,
 6955:     CPU_POWERPC_MPC603             = 0x00810100,
 6956:     CPU_POWERPC_G2_HIP3            = 0x00810101,
 6957:     CPU_POWERPC_G2_HIP4            = 0x80811014,
 6958:     /*   G2_LE core (aka PowerQUICC-II) */
 6959:     CPU_POWERPC_G2LE               = 0x80820010,
 6960:     CPU_POWERPC_G2LEgp             = 0x80822010,
 6961:     CPU_POWERPC_G2LEls             = 0xA0822010,
 6962:     CPU_POWERPC_G2LEgp1            = 0x80822011,
 6963:     CPU_POWERPC_G2LEgp3            = 0x80822013,
 6964:     /* MPC52xx microcontrollers  */
 6965:     /* XXX: MPC 5121 ? */
 6966: #define CPU_POWERPC_MPC52xx          CPU_POWERPC_MPC5200
 6967: #define CPU_POWERPC_MPC5200          CPU_POWERPC_MPC5200_v12
 6968: #define CPU_POWERPC_MPC5200_v10      CPU_POWERPC_G2LEgp1
 6969: #define CPU_POWERPC_MPC5200_v11      CPU_POWERPC_G2LEgp1
 6970: #define CPU_POWERPC_MPC5200_v12      CPU_POWERPC_G2LEgp1
 6971: #define CPU_POWERPC_MPC5200B         CPU_POWERPC_MPC5200B_v21
 6972: #define CPU_POWERPC_MPC5200B_v20     CPU_POWERPC_G2LEgp1
 6973: #define CPU_POWERPC_MPC5200B_v21     CPU_POWERPC_G2LEgp1
 6974:     /* MPC82xx microcontrollers */
 6975: #define CPU_POWERPC_MPC82xx          CPU_POWERPC_MPC8280
 6976: #define CPU_POWERPC_MPC8240          CPU_POWERPC_MPC603
 6977: #define CPU_POWERPC_MPC8241          CPU_POWERPC_G2_HIP4
 6978: #define CPU_POWERPC_MPC8245          CPU_POWERPC_G2_HIP4
 6979: #define CPU_POWERPC_MPC8247          CPU_POWERPC_G2LEgp3
 6980: #define CPU_POWERPC_MPC8248          CPU_POWERPC_G2LEgp3
 6981: #define CPU_POWERPC_MPC8250          CPU_POWERPC_MPC8250_HiP4
 6982: #define CPU_POWERPC_MPC8250_HiP3     CPU_POWERPC_G2_HIP3
 6983: #define CPU_POWERPC_MPC8250_HiP4     CPU_POWERPC_G2_HIP4
 6984: #define CPU_POWERPC_MPC8255          CPU_POWERPC_MPC8255_HiP4
 6985: #define CPU_POWERPC_MPC8255_HiP3     CPU_POWERPC_G2_HIP3
 6986: #define CPU_POWERPC_MPC8255_HiP4     CPU_POWERPC_G2_HIP4
 6987: #define CPU_POWERPC_MPC8260          CPU_POWERPC_MPC8260_HiP4
 6988: #define CPU_POWERPC_MPC8260_HiP3     CPU_POWERPC_G2_HIP3
 6989: #define CPU_POWERPC_MPC8260_HiP4     CPU_POWERPC_G2_HIP4
 6990: #define CPU_POWERPC_MPC8264          CPU_POWERPC_MPC8264_HiP4
 6991: #define CPU_POWERPC_MPC8264_HiP3     CPU_POWERPC_G2_HIP3
 6992: #define CPU_POWERPC_MPC8264_HiP4     CPU_POWERPC_G2_HIP4
 6993: #define CPU_POWERPC_MPC8265          CPU_POWERPC_MPC8265_HiP4
 6994: #define CPU_POWERPC_MPC8265_HiP3     CPU_POWERPC_G2_HIP3
 6995: #define CPU_POWERPC_MPC8265_HiP4     CPU_POWERPC_G2_HIP4
 6996: #define CPU_POWERPC_MPC8266          CPU_POWERPC_MPC8266_HiP4
 6997: #define CPU_POWERPC_MPC8266_HiP3     CPU_POWERPC_G2_HIP3
 6998: #define CPU_POWERPC_MPC8266_HiP4     CPU_POWERPC_G2_HIP4
 6999: #define CPU_POWERPC_MPC8270          CPU_POWERPC_G2LEgp3
 7000: #define CPU_POWERPC_MPC8271          CPU_POWERPC_G2LEgp3
 7001: #define CPU_POWERPC_MPC8272          CPU_POWERPC_G2LEgp3
 7002: #define CPU_POWERPC_MPC8275          CPU_POWERPC_G2LEgp3
 7003: #define CPU_POWERPC_MPC8280          CPU_POWERPC_G2LEgp3
 7004:     /* e200 family */
 7005:     /* e200 cores */
 7006: #define CPU_POWERPC_e200             CPU_POWERPC_e200z6
 7007: #if 0
 7008:     CPU_POWERPC_e200z0             = xxx,
 7009: #endif
 7010: #if 0
 7011:     CPU_POWERPC_e200z1             = xxx,
 7012: #endif
 7013: #if 0 /* ? */
 7014:     CPU_POWERPC_e200z3             = 0x81120000,
 7015: #endif
 7016:     CPU_POWERPC_e200z5             = 0x81000000,
 7017:     CPU_POWERPC_e200z6             = 0x81120000,
 7018:     /* MPC55xx microcontrollers */
 7019: #define CPU_POWERPC_MPC55xx          CPU_POWERPC_MPC5567
 7020: #if 0
 7021: #define CPU_POWERPC_MPC5514E         CPU_POWERPC_MPC5514E_v1
 7022: #define CPU_POWERPC_MPC5514E_v0      CPU_POWERPC_e200z0
 7023: #define CPU_POWERPC_MPC5514E_v1      CPU_POWERPC_e200z1
 7024: #define CPU_POWERPC_MPC5514G         CPU_POWERPC_MPC5514G_v1
 7025: #define CPU_POWERPC_MPC5514G_v0      CPU_POWERPC_e200z0
 7026: #define CPU_POWERPC_MPC5514G_v1      CPU_POWERPC_e200z1
 7027: #define CPU_POWERPC_MPC5515S         CPU_POWERPC_e200z1
 7028: #define CPU_POWERPC_MPC5516E         CPU_POWERPC_MPC5516E_v1
 7029: #define CPU_POWERPC_MPC5516E_v0      CPU_POWERPC_e200z0
 7030: #define CPU_POWERPC_MPC5516E_v1      CPU_POWERPC_e200z1
 7031: #define CPU_POWERPC_MPC5516G         CPU_POWERPC_MPC5516G_v1
 7032: #define CPU_POWERPC_MPC5516G_v0      CPU_POWERPC_e200z0
 7033: #define CPU_POWERPC_MPC5516G_v1      CPU_POWERPC_e200z1
 7034: #define CPU_POWERPC_MPC5516S         CPU_POWERPC_e200z1
 7035: #endif
 7036: #if 0
 7037: #define CPU_POWERPC_MPC5533          CPU_POWERPC_e200z3
 7038: #define CPU_POWERPC_MPC5534          CPU_POWERPC_e200z3
 7039: #endif
 7040: #define CPU_POWERPC_MPC5553          CPU_POWERPC_e200z6
 7041: #define CPU_POWERPC_MPC5554          CPU_POWERPC_e200z6
 7042: #define CPU_POWERPC_MPC5561          CPU_POWERPC_e200z6
 7043: #define CPU_POWERPC_MPC5565          CPU_POWERPC_e200z6
 7044: #define CPU_POWERPC_MPC5566          CPU_POWERPC_e200z6
 7045: #define CPU_POWERPC_MPC5567          CPU_POWERPC_e200z6
 7046:     /* e300 family */
 7047:     /* e300 cores */
 7048: #define CPU_POWERPC_e300             CPU_POWERPC_e300c3
 7049:     CPU_POWERPC_e300c1             = 0x00830010,
 7050:     CPU_POWERPC_e300c2             = 0x00840010,
 7051:     CPU_POWERPC_e300c3             = 0x00850010,
 7052:     CPU_POWERPC_e300c4             = 0x00860010,
 7053:     /* MPC83xx microcontrollers */
 7054: #define CPU_POWERPC_MPC831x          CPU_POWERPC_e300c3
 7055: #define CPU_POWERPC_MPC832x          CPU_POWERPC_e300c2
 7056: #define CPU_POWERPC_MPC834x          CPU_POWERPC_e300c1
 7057: #define CPU_POWERPC_MPC835x          CPU_POWERPC_e300c1
 7058: #define CPU_POWERPC_MPC836x          CPU_POWERPC_e300c1
 7059: #define CPU_POWERPC_MPC837x          CPU_POWERPC_e300c4
 7060:     /* e500 family */
 7061:     /* e500 cores  */
 7062: #define CPU_POWERPC_e500             CPU_POWERPC_e500v2_v22
 7063: #define CPU_POWERPC_e500v1           CPU_POWERPC_e500v1_v20
 7064: #define CPU_POWERPC_e500v2           CPU_POWERPC_e500v2_v22
 7065:     CPU_POWERPC_e500v1_v10         = 0x80200010,
 7066:     CPU_POWERPC_e500v1_v20         = 0x80200020,
 7067:     CPU_POWERPC_e500v2_v10         = 0x80210010,
 7068:     CPU_POWERPC_e500v2_v11         = 0x80210011,
 7069:     CPU_POWERPC_e500v2_v20         = 0x80210020,
 7070:     CPU_POWERPC_e500v2_v21         = 0x80210021,
 7071:     CPU_POWERPC_e500v2_v22         = 0x80210022,
 7072:     CPU_POWERPC_e500v2_v30         = 0x80210030,
 7073:     /* MPC85xx microcontrollers */
 7074: #define CPU_POWERPC_MPC8533          CPU_POWERPC_MPC8533_v11
 7075: #define CPU_POWERPC_MPC8533_v10      CPU_POWERPC_e500v2_v21
 7076: #define CPU_POWERPC_MPC8533_v11      CPU_POWERPC_e500v2_v22
 7077: #define CPU_POWERPC_MPC8533E         CPU_POWERPC_MPC8533E_v11
 7078: #define CPU_POWERPC_MPC8533E_v10     CPU_POWERPC_e500v2_v21
 7079: #define CPU_POWERPC_MPC8533E_v11     CPU_POWERPC_e500v2_v22
 7080: #define CPU_POWERPC_MPC8540          CPU_POWERPC_MPC8540_v21
 7081: #define CPU_POWERPC_MPC8540_v10      CPU_POWERPC_e500v1_v10
 7082: #define CPU_POWERPC_MPC8540_v20      CPU_POWERPC_e500v1_v20
 7083: #define CPU_POWERPC_MPC8540_v21      CPU_POWERPC_e500v1_v20
 7084: #define CPU_POWERPC_MPC8541          CPU_POWERPC_MPC8541_v11
 7085: #define CPU_POWERPC_MPC8541_v10      CPU_POWERPC_e500v1_v20
 7086: #define CPU_POWERPC_MPC8541_v11      CPU_POWERPC_e500v1_v20
 7087: #define CPU_POWERPC_MPC8541E         CPU_POWERPC_MPC8541E_v11
 7088: #define CPU_POWERPC_MPC8541E_v10     CPU_POWERPC_e500v1_v20
 7089: #define CPU_POWERPC_MPC8541E_v11     CPU_POWERPC_e500v1_v20
 7090: #define CPU_POWERPC_MPC8543          CPU_POWERPC_MPC8543_v21
 7091: #define CPU_POWERPC_MPC8543_v10      CPU_POWERPC_e500v2_v10
 7092: #define CPU_POWERPC_MPC8543_v11      CPU_POWERPC_e500v2_v11
 7093: #define CPU_POWERPC_MPC8543_v20      CPU_POWERPC_e500v2_v20
 7094: #define CPU_POWERPC_MPC8543_v21      CPU_POWERPC_e500v2_v21
 7095: #define CPU_POWERPC_MPC8543E         CPU_POWERPC_MPC8543E_v21
 7096: #define CPU_POWERPC_MPC8543E_v10     CPU_POWERPC_e500v2_v10
 7097: #define CPU_POWERPC_MPC8543E_v11     CPU_POWERPC_e500v2_v11
 7098: #define CPU_POWERPC_MPC8543E_v20     CPU_POWERPC_e500v2_v20
 7099: #define CPU_POWERPC_MPC8543E_v21     CPU_POWERPC_e500v2_v21
 7100: #define CPU_POWERPC_MPC8544          CPU_POWERPC_MPC8544_v11
 7101: #define CPU_POWERPC_MPC8544_v10      CPU_POWERPC_e500v2_v21
 7102: #define CPU_POWERPC_MPC8544_v11      CPU_POWERPC_e500v2_v22
 7103: #define CPU_POWERPC_MPC8544E_v11     CPU_POWERPC_e500v2_v22
 7104: #define CPU_POWERPC_MPC8544E         CPU_POWERPC_MPC8544E_v11
 7105: #define CPU_POWERPC_MPC8544E_v10     CPU_POWERPC_e500v2_v21
 7106: #define CPU_POWERPC_MPC8545          CPU_POWERPC_MPC8545_v21
 7107: #define CPU_POWERPC_MPC8545_v10      CPU_POWERPC_e500v2_v10
 7108: #define CPU_POWERPC_MPC8545_v20      CPU_POWERPC_e500v2_v20
 7109: #define CPU_POWERPC_MPC8545_v21      CPU_POWERPC_e500v2_v21
 7110: #define CPU_POWERPC_MPC8545E         CPU_POWERPC_MPC8545E_v21
 7111: #define CPU_POWERPC_MPC8545E_v10     CPU_POWERPC_e500v2_v10
 7112: #define CPU_POWERPC_MPC8545E_v20     CPU_POWERPC_e500v2_v20
 7113: #define CPU_POWERPC_MPC8545E_v21     CPU_POWERPC_e500v2_v21
 7114: #define CPU_POWERPC_MPC8547E         CPU_POWERPC_MPC8545E_v21
 7115: #define CPU_POWERPC_MPC8547E_v10     CPU_POWERPC_e500v2_v10
 7116: #define CPU_POWERPC_MPC8547E_v20     CPU_POWERPC_e500v2_v20
 7117: #define CPU_POWERPC_MPC8547E_v21     CPU_POWERPC_e500v2_v21
 7118: #define CPU_POWERPC_MPC8548          CPU_POWERPC_MPC8548_v21
 7119: #define CPU_POWERPC_MPC8548_v10      CPU_POWERPC_e500v2_v10
 7120: #define CPU_POWERPC_MPC8548_v11      CPU_POWERPC_e500v2_v11
 7121: #define CPU_POWERPC_MPC8548_v20      CPU_POWERPC_e500v2_v20
 7122: #define CPU_POWERPC_MPC8548_v21      CPU_POWERPC_e500v2_v21
 7123: #define CPU_POWERPC_MPC8548E         CPU_POWERPC_MPC8548E_v21
 7124: #define CPU_POWERPC_MPC8548E_v10     CPU_POWERPC_e500v2_v10
 7125: #define CPU_POWERPC_MPC8548E_v11     CPU_POWERPC_e500v2_v11
 7126: #define CPU_POWERPC_MPC8548E_v20     CPU_POWERPC_e500v2_v20
 7127: #define CPU_POWERPC_MPC8548E_v21     CPU_POWERPC_e500v2_v21
 7128: #define CPU_POWERPC_MPC8555          CPU_POWERPC_MPC8555_v11
 7129: #define CPU_POWERPC_MPC8555_v10      CPU_POWERPC_e500v2_v10
 7130: #define CPU_POWERPC_MPC8555_v11      CPU_POWERPC_e500v2_v11
 7131: #define CPU_POWERPC_MPC8555E         CPU_POWERPC_MPC8555E_v11
 7132: #define CPU_POWERPC_MPC8555E_v10     CPU_POWERPC_e500v2_v10
 7133: #define CPU_POWERPC_MPC8555E_v11     CPU_POWERPC_e500v2_v11
 7134: #define CPU_POWERPC_MPC8560          CPU_POWERPC_MPC8560_v21
 7135: #define CPU_POWERPC_MPC8560_v10      CPU_POWERPC_e500v2_v10
 7136: #define CPU_POWERPC_MPC8560_v20      CPU_POWERPC_e500v2_v20
 7137: #define CPU_POWERPC_MPC8560_v21      CPU_POWERPC_e500v2_v21
 7138: #define CPU_POWERPC_MPC8567          CPU_POWERPC_e500v2_v22
 7139: #define CPU_POWERPC_MPC8567E         CPU_POWERPC_e500v2_v22
 7140: #define CPU_POWERPC_MPC8568          CPU_POWERPC_e500v2_v22
 7141: #define CPU_POWERPC_MPC8568E         CPU_POWERPC_e500v2_v22
 7142: #define CPU_POWERPC_MPC8572          CPU_POWERPC_e500v2_v30
 7143: #define CPU_POWERPC_MPC8572E         CPU_POWERPC_e500v2_v30
 7144:     /* e600 family */
 7145:     /* e600 cores */
 7146:     CPU_POWERPC_e600               = 0x80040010,
 7147:     /* MPC86xx microcontrollers */
 7148: #define CPU_POWERPC_MPC8610          CPU_POWERPC_e600
 7149: #define CPU_POWERPC_MPC8641          CPU_POWERPC_e600
 7150: #define CPU_POWERPC_MPC8641D         CPU_POWERPC_e600
 7151:     /* PowerPC 6xx cores */
 7152: #define CPU_POWERPC_601              CPU_POWERPC_601_v2
 7153:     CPU_POWERPC_601_v0             = 0x00010001,
 7154:     CPU_POWERPC_601_v1             = 0x00010001,
 7155: #define CPU_POWERPC_601v             CPU_POWERPC_601_v2
 7156:     CPU_POWERPC_601_v2             = 0x00010002,
 7157:     CPU_POWERPC_602                = 0x00050100,
 7158:     CPU_POWERPC_603                = 0x00030100,
 7159: #define CPU_POWERPC_603E             CPU_POWERPC_603E_v41
 7160:     CPU_POWERPC_603E_v11           = 0x00060101,
 7161:     CPU_POWERPC_603E_v12           = 0x00060102,
 7162:     CPU_POWERPC_603E_v13           = 0x00060103,
 7163:     CPU_POWERPC_603E_v14           = 0x00060104,
 7164:     CPU_POWERPC_603E_v22           = 0x00060202,
 7165:     CPU_POWERPC_603E_v3            = 0x00060300,
 7166:     CPU_POWERPC_603E_v4            = 0x00060400,
 7167:     CPU_POWERPC_603E_v41           = 0x00060401,
 7168:     CPU_POWERPC_603E7t             = 0x00071201,
 7169:     CPU_POWERPC_603E7v             = 0x00070100,
 7170:     CPU_POWERPC_603E7v1            = 0x00070101,
 7171:     CPU_POWERPC_603E7v2            = 0x00070201,
 7172:     CPU_POWERPC_603E7              = 0x00070200,
 7173:     CPU_POWERPC_603P               = 0x00070000,
 7174: #define CPU_POWERPC_603R             CPU_POWERPC_603E7t
 7175:     /* XXX: missing 0x00040303 (604) */
 7176:     CPU_POWERPC_604                = 0x00040103,
 7177: #define CPU_POWERPC_604E             CPU_POWERPC_604E_v24
 7178:     /* XXX: missing 0x00091203 */
 7179:     /* XXX: missing 0x00092110 */
 7180:     /* XXX: missing 0x00092120 */
 7181:     CPU_POWERPC_604E_v10           = 0x00090100,
 7182:     CPU_POWERPC_604E_v22           = 0x00090202,
 7183:     CPU_POWERPC_604E_v24           = 0x00090204,
 7184:     /* XXX: missing 0x000a0100 */
 7185:     /* XXX: missing 0x00093102 */
 7186:     CPU_POWERPC_604R               = 0x000a0101,
 7187: #if 0
 7188:     CPU_POWERPC_604EV              = xxx, /* XXX: same as 604R ? */
 7189: #endif
 7190:     /* PowerPC 740/750 cores (aka G3) */
 7191:     /* XXX: missing 0x00084202 */
 7192: #define CPU_POWERPC_7x0              CPU_POWERPC_7x0_v31
 7193:     CPU_POWERPC_7x0_v10            = 0x00080100,
 7194:     CPU_POWERPC_7x0_v20            = 0x00080200,
 7195:     CPU_POWERPC_7x0_v21            = 0x00080201,
 7196:     CPU_POWERPC_7x0_v22            = 0x00080202,
 7197:     CPU_POWERPC_7x0_v30            = 0x00080300,
 7198:     CPU_POWERPC_7x0_v31            = 0x00080301,
 7199:     CPU_POWERPC_740E               = 0x00080100,
 7200:     CPU_POWERPC_750E               = 0x00080200,
 7201:     CPU_POWERPC_7x0P               = 0x10080000,
 7202:     /* XXX: missing 0x00087010 (CL ?) */
 7203: #define CPU_POWERPC_750CL            CPU_POWERPC_750CL_v20
 7204:     CPU_POWERPC_750CL_v10          = 0x00087200,
 7205:     CPU_POWERPC_750CL_v20          = 0x00087210, /* aka rev E */
 7206: #define CPU_POWERPC_750CX            CPU_POWERPC_750CX_v22
 7207:     CPU_POWERPC_750CX_v10          = 0x00082100,
 7208:     CPU_POWERPC_750CX_v20          = 0x00082200,
 7209:     CPU_POWERPC_750CX_v21          = 0x00082201,
 7210:     CPU_POWERPC_750CX_v22          = 0x00082202,
 7211: #define CPU_POWERPC_750CXE           CPU_POWERPC_750CXE_v31b
 7212:     CPU_POWERPC_750CXE_v21         = 0x00082211,
 7213:     CPU_POWERPC_750CXE_v22         = 0x00082212,
 7214:     CPU_POWERPC_750CXE_v23         = 0x00082213,
 7215:     CPU_POWERPC_750CXE_v24         = 0x00082214,
 7216:     CPU_POWERPC_750CXE_v24b        = 0x00083214,
 7217:     CPU_POWERPC_750CXE_v30         = 0x00082310,
 7218:     CPU_POWERPC_750CXE_v31         = 0x00082311,
 7219:     CPU_POWERPC_750CXE_v31b        = 0x00083311,
 7220:     CPU_POWERPC_750CXR             = 0x00083410,
 7221:     CPU_POWERPC_750FL              = 0x70000203,
 7222: #define CPU_POWERPC_750FX            CPU_POWERPC_750FX_v23
 7223:     CPU_POWERPC_750FX_v10          = 0x70000100,
 7224:     CPU_POWERPC_750FX_v20          = 0x70000200,
 7225:     CPU_POWERPC_750FX_v21          = 0x70000201,
 7226:     CPU_POWERPC_750FX_v22          = 0x70000202,
 7227:     CPU_POWERPC_750FX_v23          = 0x70000203,
 7228:     CPU_POWERPC_750GL              = 0x70020102,
 7229: #define CPU_POWERPC_750GX            CPU_POWERPC_750GX_v12
 7230:     CPU_POWERPC_750GX_v10          = 0x70020100,
 7231:     CPU_POWERPC_750GX_v11          = 0x70020101,
 7232:     CPU_POWERPC_750GX_v12          = 0x70020102,
 7233: #define CPU_POWERPC_750L             CPU_POWERPC_750L_v32 /* Aka LoneStar */
 7234:     CPU_POWERPC_750L_v20           = 0x00088200,
 7235:     CPU_POWERPC_750L_v21           = 0x00088201,
 7236:     CPU_POWERPC_750L_v22           = 0x00088202,
 7237:     CPU_POWERPC_750L_v30           = 0x00088300,
 7238:     CPU_POWERPC_750L_v32           = 0x00088302,
 7239:     /* PowerPC 745/755 cores */
 7240: #define CPU_POWERPC_7x5              CPU_POWERPC_7x5_v28
 7241:     CPU_POWERPC_7x5_v10            = 0x00083100,
 7242:     CPU_POWERPC_7x5_v11            = 0x00083101,
 7243:     CPU_POWERPC_7x5_v20            = 0x00083200,
 7244:     CPU_POWERPC_7x5_v21            = 0x00083201,
 7245:     CPU_POWERPC_7x5_v22            = 0x00083202, /* aka D */
 7246:     CPU_POWERPC_7x5_v23            = 0x00083203, /* aka E */
 7247:     CPU_POWERPC_7x5_v24            = 0x00083204,
 7248:     CPU_POWERPC_7x5_v25            = 0x00083205,
 7249:     CPU_POWERPC_7x5_v26            = 0x00083206,
 7250:     CPU_POWERPC_7x5_v27            = 0x00083207,
 7251:     CPU_POWERPC_7x5_v28            = 0x00083208,
 7252: #if 0
 7253:     CPU_POWERPC_7x5P               = xxx,
 7254: #endif
 7255:     /* PowerPC 74xx cores (aka G4) */
 7256:     /* XXX: missing 0x000C1101 */
 7257: #define CPU_POWERPC_7400             CPU_POWERPC_7400_v29
 7258:     CPU_POWERPC_7400_v10           = 0x000C0100,
 7259:     CPU_POWERPC_7400_v11           = 0x000C0101,
 7260:     CPU_POWERPC_7400_v20           = 0x000C0200,
 7261:     CPU_POWERPC_7400_v21           = 0x000C0201,
 7262:     CPU_POWERPC_7400_v22           = 0x000C0202,
 7263:     CPU_POWERPC_7400_v26           = 0x000C0206,
 7264:     CPU_POWERPC_7400_v27           = 0x000C0207,
 7265:     CPU_POWERPC_7400_v28           = 0x000C0208,
 7266:     CPU_POWERPC_7400_v29           = 0x000C0209,
 7267: #define CPU_POWERPC_7410             CPU_POWERPC_7410_v14
 7268:     CPU_POWERPC_7410_v10           = 0x800C1100,
 7269:     CPU_POWERPC_7410_v11           = 0x800C1101,
 7270:     CPU_POWERPC_7410_v12           = 0x800C1102, /* aka C */
 7271:     CPU_POWERPC_7410_v13           = 0x800C1103, /* aka D */
 7272:     CPU_POWERPC_7410_v14           = 0x800C1104, /* aka E */
 7273: #define CPU_POWERPC_7448             CPU_POWERPC_7448_v21
 7274:     CPU_POWERPC_7448_v10           = 0x80040100,
 7275:     CPU_POWERPC_7448_v11           = 0x80040101,
 7276:     CPU_POWERPC_7448_v20           = 0x80040200,
 7277:     CPU_POWERPC_7448_v21           = 0x80040201,
 7278: #define CPU_POWERPC_7450             CPU_POWERPC_7450_v21
 7279:     CPU_POWERPC_7450_v10           = 0x80000100,
 7280:     CPU_POWERPC_7450_v11           = 0x80000101,
 7281:     CPU_POWERPC_7450_v12           = 0x80000102,
 7282:     CPU_POWERPC_7450_v20           = 0x80000200, /* aka A, B, C, D: 2.04 */
 7283:     CPU_POWERPC_7450_v21           = 0x80000201, /* aka E */
 7284: #define CPU_POWERPC_74x1             CPU_POWERPC_74x1_v23
 7285:     CPU_POWERPC_74x1_v23           = 0x80000203, /* aka G: 2.3 */
 7286:     /* XXX: this entry might be a bug in some documentation */
 7287:     CPU_POWERPC_74x1_v210          = 0x80000210, /* aka G: 2.3 ? */
 7288: #define CPU_POWERPC_74x5             CPU_POWERPC_74x5_v32
 7289:     CPU_POWERPC_74x5_v10           = 0x80010100,
 7290:     /* XXX: missing 0x80010200 */
 7291:     CPU_POWERPC_74x5_v21           = 0x80010201, /* aka C: 2.1 */
 7292:     CPU_POWERPC_74x5_v32           = 0x80010302,
 7293:     CPU_POWERPC_74x5_v33           = 0x80010303, /* aka F: 3.3 */
 7294:     CPU_POWERPC_74x5_v34           = 0x80010304, /* aka G: 3.4 */
 7295: #define CPU_POWERPC_74x7             CPU_POWERPC_74x7_v12
 7296:     CPU_POWERPC_74x7_v10           = 0x80020100, /* aka A: 1.0 */
 7297:     CPU_POWERPC_74x7_v11           = 0x80020101, /* aka B: 1.1 */
 7298:     CPU_POWERPC_74x7_v12           = 0x80020102, /* aka C: 1.2 */
 7299: #define CPU_POWERPC_74x7A            CPU_POWERPC_74x7A_v12
 7300:     CPU_POWERPC_74x7A_v10          = 0x80030100, /* aka A: 1.0 */
 7301:     CPU_POWERPC_74x7A_v11          = 0x80030101, /* aka B: 1.1 */
 7302:     CPU_POWERPC_74x7A_v12          = 0x80030102, /* aka C: 1.2 */
 7303:     /* 64 bits PowerPC */
 7304: #if defined(TARGET_PPC64)
 7305:     CPU_POWERPC_620                = 0x00140000,
 7306:     CPU_POWERPC_630                = 0x00400000,
 7307:     CPU_POWERPC_631                = 0x00410104,
 7308:     CPU_POWERPC_POWER4             = 0x00350000,
 7309:     CPU_POWERPC_POWER4P            = 0x00380000,
 7310:      /* XXX: missing 0x003A0201 */
 7311:     CPU_POWERPC_POWER5             = 0x003A0203,
 7312: #define CPU_POWERPC_POWER5GR         CPU_POWERPC_POWER5
 7313:     CPU_POWERPC_POWER5P            = 0x003B0000,
 7314: #define CPU_POWERPC_POWER5GS         CPU_POWERPC_POWER5P
 7315:     CPU_POWERPC_POWER6             = 0x003E0000,
 7316:     CPU_POWERPC_POWER6_5           = 0x0F000001, /* POWER6 in POWER5 mode */
 7317:     CPU_POWERPC_POWER6A            = 0x0F000002,
 7318: #define CPU_POWERPC_POWER7           CPU_POWERPC_POWER7_v20
 7319:     CPU_POWERPC_POWER7_v20         = 0x003F0200,
 7320:     CPU_POWERPC_POWER7_v21         = 0x003F0201,
 7321:     CPU_POWERPC_POWER7_v23         = 0x003F0203,
 7322:     CPU_POWERPC_970                = 0x00390202,
 7323: #define CPU_POWERPC_970FX            CPU_POWERPC_970FX_v31
 7324:     CPU_POWERPC_970FX_v10          = 0x00391100,
 7325:     CPU_POWERPC_970FX_v20          = 0x003C0200,
 7326:     CPU_POWERPC_970FX_v21          = 0x003C0201,
 7327:     CPU_POWERPC_970FX_v30          = 0x003C0300,
 7328:     CPU_POWERPC_970FX_v31          = 0x003C0301,
 7329:     CPU_POWERPC_970GX              = 0x00450000,
 7330: #define CPU_POWERPC_970MP            CPU_POWERPC_970MP_v11
 7331:     CPU_POWERPC_970MP_v10          = 0x00440100,
 7332:     CPU_POWERPC_970MP_v11          = 0x00440101,
 7333: #define CPU_POWERPC_CELL             CPU_POWERPC_CELL_v32
 7334:     CPU_POWERPC_CELL_v10           = 0x00700100,
 7335:     CPU_POWERPC_CELL_v20           = 0x00700400,
 7336:     CPU_POWERPC_CELL_v30           = 0x00700500,
 7337:     CPU_POWERPC_CELL_v31           = 0x00700501,
 7338: #define CPU_POWERPC_CELL_v32         CPU_POWERPC_CELL_v31
 7339:     CPU_POWERPC_RS64               = 0x00330000,
 7340:     CPU_POWERPC_RS64II             = 0x00340000,
 7341:     CPU_POWERPC_RS64III            = 0x00360000,
 7342:     CPU_POWERPC_RS64IV             = 0x00370000,
 7343: #endif /* defined(TARGET_PPC64) */
 7344:     /* Original POWER */
 7345:     /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
 7346:      * POWER2 (RIOS2) & RSC2 (P2SC) here
 7347:      */
 7348: #if 0
 7349:     CPU_POWER                      = xxx, /* 0x20000 ? 0x30000 for RSC ? */
 7350: #endif
 7351: #if 0
 7352:     CPU_POWER2                     = xxx, /* 0x40000 ? */
 7353: #endif
 7354:     /* PA Semi core */
 7355:     CPU_POWERPC_PA6T               = 0x00900000,
 7356: };
 7357: 
 7358: /* System version register (used on MPC 8xxx)                                */
 7359: enum {
 7360:     POWERPC_SVR_NONE               = 0x00000000,
 7361: #define POWERPC_SVR_52xx             POWERPC_SVR_5200
 7362: #define POWERPC_SVR_5200             POWERPC_SVR_5200_v12
 7363:     POWERPC_SVR_5200_v10           = 0x80110010,
 7364:     POWERPC_SVR_5200_v11           = 0x80110011,
 7365:     POWERPC_SVR_5200_v12           = 0x80110012,
 7366: #define POWERPC_SVR_5200B            POWERPC_SVR_5200B_v21
 7367:     POWERPC_SVR_5200B_v20          = 0x80110020,
 7368:     POWERPC_SVR_5200B_v21          = 0x80110021,
 7369: #define POWERPC_SVR_55xx             POWERPC_SVR_5567
 7370: #if 0
 7371:     POWERPC_SVR_5533               = xxx,
 7372: #endif
 7373: #if 0
 7374:     POWERPC_SVR_5534               = xxx,
 7375: #endif
 7376: #if 0
 7377:     POWERPC_SVR_5553               = xxx,
 7378: #endif
 7379: #if 0
 7380:     POWERPC_SVR_5554               = xxx,
 7381: #endif
 7382: #if 0
 7383:     POWERPC_SVR_5561               = xxx,
 7384: #endif
 7385: #if 0
 7386:     POWERPC_SVR_5565               = xxx,
 7387: #endif
 7388: #if 0
 7389:     POWERPC_SVR_5566               = xxx,
 7390: #endif
 7391: #if 0
 7392:     POWERPC_SVR_5567               = xxx,
 7393: #endif
 7394: #if 0
 7395:     POWERPC_SVR_8313               = xxx,
 7396: #endif
 7397: #if 0
 7398:     POWERPC_SVR_8313E              = xxx,
 7399: #endif
 7400: #if 0
 7401:     POWERPC_SVR_8314               = xxx,
 7402: #endif
 7403: #if 0
 7404:     POWERPC_SVR_8314E              = xxx,
 7405: #endif
 7406: #if 0
 7407:     POWERPC_SVR_8315               = xxx,
 7408: #endif
 7409: #if 0
 7410:     POWERPC_SVR_8315E              = xxx,
 7411: #endif
 7412: #if 0
 7413:     POWERPC_SVR_8321               = xxx,
 7414: #endif
 7415: #if 0
 7416:     POWERPC_SVR_8321E              = xxx,
 7417: #endif
 7418: #if 0
 7419:     POWERPC_SVR_8323               = xxx,
 7420: #endif
 7421: #if 0
 7422:     POWERPC_SVR_8323E              = xxx,
 7423: #endif
 7424:     POWERPC_SVR_8343               = 0x80570010,
 7425:     POWERPC_SVR_8343A              = 0x80570030,
 7426:     POWERPC_SVR_8343E              = 0x80560010,
 7427:     POWERPC_SVR_8343EA             = 0x80560030,
 7428: #define POWERPC_SVR_8347             POWERPC_SVR_8347T
 7429:     POWERPC_SVR_8347P              = 0x80550010, /* PBGA package */
 7430:     POWERPC_SVR_8347T              = 0x80530010, /* TBGA package */
 7431: #define POWERPC_SVR_8347A            POWERPC_SVR_8347AT
 7432:     POWERPC_SVR_8347AP             = 0x80550030, /* PBGA package */
 7433:     POWERPC_SVR_8347AT             = 0x80530030, /* TBGA package */
 7434: #define POWERPC_SVR_8347E            POWERPC_SVR_8347ET
 7435:     POWERPC_SVR_8347EP             = 0x80540010, /* PBGA package */
 7436:     POWERPC_SVR_8347ET             = 0x80520010, /* TBGA package */
 7437: #define POWERPC_SVR_8347EA            POWERPC_SVR_8347EAT
 7438:     POWERPC_SVR_8347EAP            = 0x80540030, /* PBGA package */
 7439:     POWERPC_SVR_8347EAT            = 0x80520030, /* TBGA package */
 7440:     POWERPC_SVR_8349               = 0x80510010,
 7441:     POWERPC_SVR_8349A              = 0x80510030,
 7442:     POWERPC_SVR_8349E              = 0x80500010,
 7443:     POWERPC_SVR_8349EA             = 0x80500030,
 7444: #if 0
 7445:     POWERPC_SVR_8358E              = xxx,
 7446: #endif
 7447: #if 0
 7448:     POWERPC_SVR_8360E              = xxx,
 7449: #endif
 7450: #define POWERPC_SVR_E500             0x40000000
 7451:     POWERPC_SVR_8377               = 0x80C70010 | POWERPC_SVR_E500,
 7452:     POWERPC_SVR_8377E              = 0x80C60010 | POWERPC_SVR_E500,
 7453:     POWERPC_SVR_8378               = 0x80C50010 | POWERPC_SVR_E500,
 7454:     POWERPC_SVR_8378E              = 0x80C40010 | POWERPC_SVR_E500,
 7455:     POWERPC_SVR_8379               = 0x80C30010 | POWERPC_SVR_E500,
 7456:     POWERPC_SVR_8379E              = 0x80C00010 | POWERPC_SVR_E500,
 7457: #define POWERPC_SVR_8533             POWERPC_SVR_8533_v11
 7458:     POWERPC_SVR_8533_v10           = 0x80340010 | POWERPC_SVR_E500,
 7459:     POWERPC_SVR_8533_v11           = 0x80340011 | POWERPC_SVR_E500,
 7460: #define POWERPC_SVR_8533E            POWERPC_SVR_8533E_v11
 7461:     POWERPC_SVR_8533E_v10          = 0x803C0010 | POWERPC_SVR_E500,
 7462:     POWERPC_SVR_8533E_v11          = 0x803C0011 | POWERPC_SVR_E500,
 7463: #define POWERPC_SVR_8540             POWERPC_SVR_8540_v21
 7464:     POWERPC_SVR_8540_v10           = 0x80300010 | POWERPC_SVR_E500,
 7465:     POWERPC_SVR_8540_v20           = 0x80300020 | POWERPC_SVR_E500,
 7466:     POWERPC_SVR_8540_v21           = 0x80300021 | POWERPC_SVR_E500,
 7467: #define POWERPC_SVR_8541             POWERPC_SVR_8541_v11
 7468:     POWERPC_SVR_8541_v10           = 0x80720010 | POWERPC_SVR_E500,
 7469:     POWERPC_SVR_8541_v11           = 0x80720011 | POWERPC_SVR_E500,
 7470: #define POWERPC_SVR_8541E            POWERPC_SVR_8541E_v11
 7471:     POWERPC_SVR_8541E_v10          = 0x807A0010 | POWERPC_SVR_E500,
 7472:     POWERPC_SVR_8541E_v11          = 0x807A0011 | POWERPC_SVR_E500,
 7473: #define POWERPC_SVR_8543             POWERPC_SVR_8543_v21
 7474:     POWERPC_SVR_8543_v10           = 0x80320010 | POWERPC_SVR_E500,
 7475:     POWERPC_SVR_8543_v11           = 0x80320011 | POWERPC_SVR_E500,
 7476:     POWERPC_SVR_8543_v20           = 0x80320020 | POWERPC_SVR_E500,
 7477:     POWERPC_SVR_8543_v21           = 0x80320021 | POWERPC_SVR_E500,
 7478: #define POWERPC_SVR_8543E            POWERPC_SVR_8543E_v21
 7479:     POWERPC_SVR_8543E_v10          = 0x803A0010 | POWERPC_SVR_E500,
 7480:     POWERPC_SVR_8543E_v11          = 0x803A0011 | POWERPC_SVR_E500,
 7481:     POWERPC_SVR_8543E_v20          = 0x803A0020 | POWERPC_SVR_E500,
 7482:     POWERPC_SVR_8543E_v21          = 0x803A0021 | POWERPC_SVR_E500,
 7483: #define POWERPC_SVR_8544             POWERPC_SVR_8544_v11
 7484:     POWERPC_SVR_8544_v10           = 0x80340110 | POWERPC_SVR_E500,
 7485:     POWERPC_SVR_8544_v11           = 0x80340111 | POWERPC_SVR_E500,
 7486: #define POWERPC_SVR_8544E            POWERPC_SVR_8544E_v11
 7487:     POWERPC_SVR_8544E_v10          = 0x803C0110 | POWERPC_SVR_E500,
 7488:     POWERPC_SVR_8544E_v11          = 0x803C0111 | POWERPC_SVR_E500,
 7489: #define POWERPC_SVR_8545             POWERPC_SVR_8545_v21
 7490:     POWERPC_SVR_8545_v20           = 0x80310220 | POWERPC_SVR_E500,
 7491:     POWERPC_SVR_8545_v21           = 0x80310221 | POWERPC_SVR_E500,
 7492: #define POWERPC_SVR_8545E            POWERPC_SVR_8545E_v21
 7493:     POWERPC_SVR_8545E_v20          = 0x80390220 | POWERPC_SVR_E500,
 7494:     POWERPC_SVR_8545E_v21          = 0x80390221 | POWERPC_SVR_E500,
 7495: #define POWERPC_SVR_8547E            POWERPC_SVR_8547E_v21
 7496:     POWERPC_SVR_8547E_v20          = 0x80390120 | POWERPC_SVR_E500,
 7497:     POWERPC_SVR_8547E_v21          = 0x80390121 | POWERPC_SVR_E500,
 7498: #define POWERPC_SVR_8548             POWERPC_SVR_8548_v21
 7499:     POWERPC_SVR_8548_v10           = 0x80310010 | POWERPC_SVR_E500,
 7500:     POWERPC_SVR_8548_v11           = 0x80310011 | POWERPC_SVR_E500,
 7501:     POWERPC_SVR_8548_v20           = 0x80310020 | POWERPC_SVR_E500,
 7502:     POWERPC_SVR_8548_v21           = 0x80310021 | POWERPC_SVR_E500,
 7503: #define POWERPC_SVR_8548E            POWERPC_SVR_8548E_v21
 7504:     POWERPC_SVR_8548E_v10          = 0x80390010 | POWERPC_SVR_E500,
 7505:     POWERPC_SVR_8548E_v11          = 0x80390011 | POWERPC_SVR_E500,
 7506:     POWERPC_SVR_8548E_v20          = 0x80390020 | POWERPC_SVR_E500,
 7507:     POWERPC_SVR_8548E_v21          = 0x80390021 | POWERPC_SVR_E500,
 7508: #define POWERPC_SVR_8555             POWERPC_SVR_8555_v11
 7509:     POWERPC_SVR_8555_v10           = 0x80710010 | POWERPC_SVR_E500,
 7510:     POWERPC_SVR_8555_v11           = 0x80710011 | POWERPC_SVR_E500,
 7511: #define POWERPC_SVR_8555E            POWERPC_SVR_8555_v11
 7512:     POWERPC_SVR_8555E_v10          = 0x80790010 | POWERPC_SVR_E500,
 7513:     POWERPC_SVR_8555E_v11          = 0x80790011 | POWERPC_SVR_E500,
 7514: #define POWERPC_SVR_8560             POWERPC_SVR_8560_v21
 7515:     POWERPC_SVR_8560_v10           = 0x80700010 | POWERPC_SVR_E500,
 7516:     POWERPC_SVR_8560_v20           = 0x80700020 | POWERPC_SVR_E500,
 7517:     POWERPC_SVR_8560_v21           = 0x80700021 | POWERPC_SVR_E500,
 7518:     POWERPC_SVR_8567               = 0x80750111 | POWERPC_SVR_E500,
 7519:     POWERPC_SVR_8567E              = 0x807D0111 | POWERPC_SVR_E500,
 7520:     POWERPC_SVR_8568               = 0x80750011 | POWERPC_SVR_E500,
 7521:     POWERPC_SVR_8568E              = 0x807D0011 | POWERPC_SVR_E500,
 7522:     POWERPC_SVR_8572               = 0x80E00010 | POWERPC_SVR_E500,
 7523:     POWERPC_SVR_8572E              = 0x80E80010 | POWERPC_SVR_E500,
 7524: #if 0
 7525:     POWERPC_SVR_8610               = xxx,
 7526: #endif
 7527:     POWERPC_SVR_8641               = 0x80900021,
 7528:     POWERPC_SVR_8641D              = 0x80900121,
 7529: };
 7530: 
 7531: /*****************************************************************************/
 7532: /* PowerPC CPU definitions                                                   */
 7533: #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type)                             \
 7534:     {                                                                         \
 7535:         .name         = _name,                                                \
 7536:         .pvr          = _pvr,                                                 \
 7537:         .svr          = _svr,                                                 \
 7538:         .insns_flags  = glue(POWERPC_INSNS_,_type),                           \
 7539:         .insns_flags2 = glue(POWERPC_INSNS2_,_type),                          \
 7540:         .msr_mask     = glue(POWERPC_MSRM_,_type),                            \
 7541:         .mmu_model    = glue(POWERPC_MMU_,_type),                             \
 7542:         .excp_model   = glue(POWERPC_EXCP_,_type),                            \
 7543:         .bus_model    = glue(POWERPC_INPUT_,_type),                           \
 7544:         .bfd_mach     = glue(POWERPC_BFDM_,_type),                            \
 7545:         .flags        = glue(POWERPC_FLAG_,_type),                            \
 7546:         .init_proc    = &glue(init_proc_,_type),                              \
 7547:         .check_pow    = &glue(check_pow_,_type),                              \
 7548:     }
 7549: #define POWERPC_DEF(_name, _pvr, _type)                                       \
 7550: POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
 7551: 
 7552: static const ppc_def_t ppc_defs[] = {
 7553:     /* Embedded PowerPC                                                      */
 7554:     /* PowerPC 401 family                                                    */
 7555:     /* Generic PowerPC 401 */
 7556:     POWERPC_DEF("401",           CPU_POWERPC_401,                    401),
 7557:     /* PowerPC 401 cores                                                     */
 7558:     /* PowerPC 401A1 */
 7559:     POWERPC_DEF("401A1",         CPU_POWERPC_401A1,                  401),
 7560:     /* PowerPC 401B2                                                         */
 7561:     POWERPC_DEF("401B2",         CPU_POWERPC_401B2,                  401x2),
 7562: #if defined (TODO)
 7563:     /* PowerPC 401B3                                                         */
 7564:     POWERPC_DEF("401B3",         CPU_POWERPC_401B3,                  401x3),
 7565: #endif
 7566:     /* PowerPC 401C2                                                         */
 7567:     POWERPC_DEF("401C2",         CPU_POWERPC_401C2,                  401x2),
 7568:     /* PowerPC 401D2                                                         */
 7569:     POWERPC_DEF("401D2",         CPU_POWERPC_401D2,                  401x2),
 7570:     /* PowerPC 401E2                                                         */
 7571:     POWERPC_DEF("401E2",         CPU_POWERPC_401E2,                  401x2),
 7572:     /* PowerPC 401F2                                                         */
 7573:     POWERPC_DEF("401F2",         CPU_POWERPC_401F2,                  401x2),
 7574:     /* PowerPC 401G2                                                         */
 7575:     /* XXX: to be checked */
 7576:     POWERPC_DEF("401G2",         CPU_POWERPC_401G2,                  401x2),
 7577:     /* PowerPC 401 microcontrolers                                           */
 7578: #if defined (TODO)
 7579:     /* PowerPC 401GF                                                         */
 7580:     POWERPC_DEF("401GF",         CPU_POWERPC_401GF,                  401),
 7581: #endif
 7582:     /* IOP480 (401 microcontroler)                                           */
 7583:     POWERPC_DEF("IOP480",        CPU_POWERPC_IOP480,                 IOP480),
 7584:     /* IBM Processor for Network Resources                                   */
 7585:     POWERPC_DEF("Cobra",         CPU_POWERPC_COBRA,                  401),
 7586: #if defined (TODO)
 7587:     POWERPC_DEF("Xipchip",       CPU_POWERPC_XIPCHIP,                401),
 7588: #endif
 7589:     /* PowerPC 403 family                                                    */
 7590:     /* Generic PowerPC 403                                                   */
 7591:     POWERPC_DEF("403",           CPU_POWERPC_403,                    403),
 7592:     /* PowerPC 403 microcontrolers                                           */
 7593:     /* PowerPC 403 GA                                                        */
 7594:     POWERPC_DEF("403GA",         CPU_POWERPC_403GA,                  403),
 7595:     /* PowerPC 403 GB                                                        */
 7596:     POWERPC_DEF("403GB",         CPU_POWERPC_403GB,                  403),
 7597:     /* PowerPC 403 GC                                                        */
 7598:     POWERPC_DEF("403GC",         CPU_POWERPC_403GC,                  403),
 7599:     /* PowerPC 403 GCX                                                       */
 7600:     POWERPC_DEF("403GCX",        CPU_POWERPC_403GCX,                 403GCX),
 7601: #if defined (TODO)
 7602:     /* PowerPC 403 GP                                                        */
 7603:     POWERPC_DEF("403GP",         CPU_POWERPC_403GP,                  403),
 7604: #endif
 7605:     /* PowerPC 405 family                                                    */
 7606:     /* Generic PowerPC 405                                                   */
 7607:     POWERPC_DEF("405",           CPU_POWERPC_405,                    405),
 7608:     /* PowerPC 405 cores                                                     */
 7609: #if defined (TODO)
 7610:     /* PowerPC 405 A3                                                        */
 7611:     POWERPC_DEF("405A3",         CPU_POWERPC_405A3,                  405),
 7612: #endif
 7613: #if defined (TODO)
 7614:     /* PowerPC 405 A4                                                        */
 7615:     POWERPC_DEF("405A4",         CPU_POWERPC_405A4,                  405),
 7616: #endif
 7617: #if defined (TODO)
 7618:     /* PowerPC 405 B3                                                        */
 7619:     POWERPC_DEF("405B3",         CPU_POWERPC_405B3,                  405),
 7620: #endif
 7621: #if defined (TODO)
 7622:     /* PowerPC 405 B4                                                        */
 7623:     POWERPC_DEF("405B4",         CPU_POWERPC_405B4,                  405),
 7624: #endif
 7625: #if defined (TODO)
 7626:     /* PowerPC 405 C3                                                        */
 7627:     POWERPC_DEF("405C3",         CPU_POWERPC_405C3,                  405),
 7628: #endif
 7629: #if defined (TODO)
 7630:     /* PowerPC 405 C4                                                        */
 7631:     POWERPC_DEF("405C4",         CPU_POWERPC_405C4,                  405),
 7632: #endif
 7633:     /* PowerPC 405 D2                                                        */
 7634:     POWERPC_DEF("405D2",         CPU_POWERPC_405D2,                  405),
 7635: #if defined (TODO)
 7636:     /* PowerPC 405 D3                                                        */
 7637:     POWERPC_DEF("405D3",         CPU_POWERPC_405D3,                  405),
 7638: #endif
 7639:     /* PowerPC 405 D4                                                        */
 7640:     POWERPC_DEF("405D4",         CPU_POWERPC_405D4,                  405),
 7641: #if defined (TODO)
 7642:     /* PowerPC 405 D5                                                        */
 7643:     POWERPC_DEF("405D5",         CPU_POWERPC_405D5,                  405),
 7644: #endif
 7645: #if defined (TODO)
 7646:     /* PowerPC 405 E4                                                        */
 7647:     POWERPC_DEF("405E4",         CPU_POWERPC_405E4,                  405),
 7648: #endif
 7649: #if defined (TODO)
 7650:     /* PowerPC 405 F4                                                        */
 7651:     POWERPC_DEF("405F4",         CPU_POWERPC_405F4,                  405),
 7652: #endif
 7653: #if defined (TODO)
 7654:     /* PowerPC 405 F5                                                        */
 7655:     POWERPC_DEF("405F5",         CPU_POWERPC_405F5,                  405),
 7656: #endif
 7657: #if defined (TODO)
 7658:     /* PowerPC 405 F6                                                        */
 7659:     POWERPC_DEF("405F6",         CPU_POWERPC_405F6,                  405),
 7660: #endif
 7661:     /* PowerPC 405 microcontrolers                                           */
 7662:     /* PowerPC 405 CR                                                        */
 7663:     POWERPC_DEF("405CR",         CPU_POWERPC_405CR,                  405),
 7664:     /* PowerPC 405 CRa                                                       */
 7665:     POWERPC_DEF("405CRa",        CPU_POWERPC_405CRa,                 405),
 7666:     /* PowerPC 405 CRb                                                       */
 7667:     POWERPC_DEF("405CRb",        CPU_POWERPC_405CRb,                 405),
 7668:     /* PowerPC 405 CRc                                                       */
 7669:     POWERPC_DEF("405CRc",        CPU_POWERPC_405CRc,                 405),
 7670:     /* PowerPC 405 EP                                                        */
 7671:     POWERPC_DEF("405EP",         CPU_POWERPC_405EP,                  405),
 7672: #if defined(TODO)
 7673:     /* PowerPC 405 EXr                                                       */
 7674:     POWERPC_DEF("405EXr",        CPU_POWERPC_405EXr,                 405),
 7675: #endif
 7676:     /* PowerPC 405 EZ                                                        */
 7677:     POWERPC_DEF("405EZ",         CPU_POWERPC_405EZ,                  405),
 7678: #if defined(TODO)
 7679:     /* PowerPC 405 FX                                                        */
 7680:     POWERPC_DEF("405FX",         CPU_POWERPC_405FX,                  405),
 7681: #endif
 7682:     /* PowerPC 405 GP                                                        */
 7683:     POWERPC_DEF("405GP",         CPU_POWERPC_405GP,                  405),
 7684:     /* PowerPC 405 GPa                                                       */
 7685:     POWERPC_DEF("405GPa",        CPU_POWERPC_405GPa,                 405),
 7686:     /* PowerPC 405 GPb                                                       */
 7687:     POWERPC_DEF("405GPb",        CPU_POWERPC_405GPb,                 405),
 7688:     /* PowerPC 405 GPc                                                       */
 7689:     POWERPC_DEF("405GPc",        CPU_POWERPC_405GPc,                 405),
 7690:     /* PowerPC 405 GPd                                                       */
 7691:     POWERPC_DEF("405GPd",        CPU_POWERPC_405GPd,                 405),
 7692:     /* PowerPC 405 GPe                                                       */
 7693:     POWERPC_DEF("405GPe",        CPU_POWERPC_405GPe,                 405),
 7694:     /* PowerPC 405 GPR                                                       */
 7695:     POWERPC_DEF("405GPR",        CPU_POWERPC_405GPR,                 405),
 7696: #if defined(TODO)
 7697:     /* PowerPC 405 H                                                         */
 7698:     POWERPC_DEF("405H",          CPU_POWERPC_405H,                   405),
 7699: #endif
 7700: #if defined(TODO)
 7701:     /* PowerPC 405 L                                                         */
 7702:     POWERPC_DEF("405L",          CPU_POWERPC_405L,                   405),
 7703: #endif
 7704:     /* PowerPC 405 LP                                                        */
 7705:     POWERPC_DEF("405LP",         CPU_POWERPC_405LP,                  405),
 7706: #if defined(TODO)
 7707:     /* PowerPC 405 PM                                                        */
 7708:     POWERPC_DEF("405PM",         CPU_POWERPC_405PM,                  405),
 7709: #endif
 7710: #if defined(TODO)
 7711:     /* PowerPC 405 PS                                                        */
 7712:     POWERPC_DEF("405PS",         CPU_POWERPC_405PS,                  405),
 7713: #endif
 7714: #if defined(TODO)
 7715:     /* PowerPC 405 S                                                         */
 7716:     POWERPC_DEF("405S",          CPU_POWERPC_405S,                   405),
 7717: #endif
 7718:     /* Npe405 H                                                              */
 7719:     POWERPC_DEF("Npe405H",       CPU_POWERPC_NPE405H,                405),
 7720:     /* Npe405 H2                                                             */
 7721:     POWERPC_DEF("Npe405H2",      CPU_POWERPC_NPE405H2,               405),
 7722:     /* Npe405 L                                                              */
 7723:     POWERPC_DEF("Npe405L",       CPU_POWERPC_NPE405L,                405),
 7724:     /* Npe4GS3                                                               */
 7725:     POWERPC_DEF("Npe4GS3",       CPU_POWERPC_NPE4GS3,                405),
 7726: #if defined (TODO)
 7727:     POWERPC_DEF("Npcxx1",        CPU_POWERPC_NPCxx1,                 405),
 7728: #endif
 7729: #if defined (TODO)
 7730:     POWERPC_DEF("Npr161",        CPU_POWERPC_NPR161,                 405),
 7731: #endif
 7732: #if defined (TODO)
 7733:     /* PowerPC LC77700 (Sanyo)                                               */
 7734:     POWERPC_DEF("LC77700",       CPU_POWERPC_LC77700,                405),
 7735: #endif
 7736:     /* PowerPC 401/403/405 based set-top-box microcontrolers                 */
 7737: #if defined (TODO)
 7738:     /* STB010000                                                             */
 7739:     POWERPC_DEF("STB01000",      CPU_POWERPC_STB01000,               401x2),
 7740: #endif
 7741: #if defined (TODO)
 7742:     /* STB01010                                                              */
 7743:     POWERPC_DEF("STB01010",      CPU_POWERPC_STB01010,               401x2),
 7744: #endif
 7745: #if defined (TODO)
 7746:     /* STB0210                                                               */
 7747:     POWERPC_DEF("STB0210",       CPU_POWERPC_STB0210,                401x3),
 7748: #endif
 7749:     /* STB03xx                                                               */
 7750:     POWERPC_DEF("STB03",         CPU_POWERPC_STB03,                  405),
 7751: #if defined (TODO)
 7752:     /* STB043x                                                               */
 7753:     POWERPC_DEF("STB043",        CPU_POWERPC_STB043,                 405),
 7754: #endif
 7755: #if defined (TODO)
 7756:     /* STB045x                                                               */
 7757:     POWERPC_DEF("STB045",        CPU_POWERPC_STB045,                 405),
 7758: #endif
 7759:     /* STB04xx                                                               */
 7760:     POWERPC_DEF("STB04",         CPU_POWERPC_STB04,                  405),
 7761:     /* STB25xx                                                               */
 7762:     POWERPC_DEF("STB25",         CPU_POWERPC_STB25,                  405),
 7763: #if defined (TODO)
 7764:     /* STB130                                                                */
 7765:     POWERPC_DEF("STB130",        CPU_POWERPC_STB130,                 405),
 7766: #endif
 7767:     /* Xilinx PowerPC 405 cores                                              */
 7768:     POWERPC_DEF("x2vp4",         CPU_POWERPC_X2VP4,                  405),
 7769:     POWERPC_DEF("x2vp7",         CPU_POWERPC_X2VP7,                  405),
 7770:     POWERPC_DEF("x2vp20",        CPU_POWERPC_X2VP20,                 405),
 7771:     POWERPC_DEF("x2vp50",        CPU_POWERPC_X2VP50,                 405),
 7772: #if defined (TODO)
 7773:     /* Zarlink ZL10310                                                       */
 7774:     POWERPC_DEF("zl10310",       CPU_POWERPC_ZL10310,                405),
 7775: #endif
 7776: #if defined (TODO)
 7777:     /* Zarlink ZL10311                                                       */
 7778:     POWERPC_DEF("zl10311",       CPU_POWERPC_ZL10311,                405),
 7779: #endif
 7780: #if defined (TODO)
 7781:     /* Zarlink ZL10320                                                       */
 7782:     POWERPC_DEF("zl10320",       CPU_POWERPC_ZL10320,                405),
 7783: #endif
 7784: #if defined (TODO)
 7785:     /* Zarlink ZL10321                                                       */
 7786:     POWERPC_DEF("zl10321",       CPU_POWERPC_ZL10321,                405),
 7787: #endif
 7788:     /* PowerPC 440 family                                                    */
 7789: #if defined(TODO_USER_ONLY)
 7790:     /* Generic PowerPC 440                                                   */
 7791:     POWERPC_DEF("440",           CPU_POWERPC_440,                    440GP),
 7792: #endif
 7793:     /* PowerPC 440 cores                                                     */
 7794: #if defined (TODO)
 7795:     /* PowerPC 440 A4                                                        */
 7796:     POWERPC_DEF("440A4",         CPU_POWERPC_440A4,                  440x4),
 7797: #endif
 7798:     /* PowerPC 440 Xilinx 5                                                  */
 7799:     POWERPC_DEF("440-Xilinx",    CPU_POWERPC_440_XILINX,             440x5),
 7800: #if defined (TODO)
 7801:     /* PowerPC 440 A5                                                        */
 7802:     POWERPC_DEF("440A5",         CPU_POWERPC_440A5,                  440x5),
 7803: #endif
 7804: #if defined (TODO)
 7805:     /* PowerPC 440 B4                                                        */
 7806:     POWERPC_DEF("440B4",         CPU_POWERPC_440B4,                  440x4),
 7807: #endif
 7808: #if defined (TODO)
 7809:     /* PowerPC 440 G4                                                        */
 7810:     POWERPC_DEF("440G4",         CPU_POWERPC_440G4,                  440x4),
 7811: #endif
 7812: #if defined (TODO)
 7813:     /* PowerPC 440 F5                                                        */
 7814:     POWERPC_DEF("440F5",         CPU_POWERPC_440F5,                  440x5),
 7815: #endif
 7816: #if defined (TODO)
 7817:     /* PowerPC 440 G5                                                        */
 7818:     POWERPC_DEF("440G5",         CPU_POWERPC_440G5,                  440x5),
 7819: #endif
 7820: #if defined (TODO)
 7821:     /* PowerPC 440H4                                                         */
 7822:     POWERPC_DEF("440H4",         CPU_POWERPC_440H4,                  440x4),
 7823: #endif
 7824: #if defined (TODO)
 7825:     /* PowerPC 440H6                                                         */
 7826:     POWERPC_DEF("440H6",         CPU_POWERPC_440H6,                  440Gx5),
 7827: #endif
 7828:     /* PowerPC 440 microcontrolers                                           */
 7829: #if defined(TODO_USER_ONLY)
 7830:     /* PowerPC 440 EP                                                        */
 7831:     POWERPC_DEF("440EP",         CPU_POWERPC_440EP,                  440EP),
 7832: #endif
 7833: #if defined(TODO_USER_ONLY)
 7834:     /* PowerPC 440 EPa                                                       */
 7835:     POWERPC_DEF("440EPa",        CPU_POWERPC_440EPa,                 440EP),
 7836: #endif
 7837: #if defined(TODO_USER_ONLY)
 7838:     /* PowerPC 440 EPb                                                       */
 7839:     POWERPC_DEF("440EPb",        CPU_POWERPC_440EPb,                 440EP),
 7840: #endif
 7841: #if defined(TODO_USER_ONLY)
 7842:     /* PowerPC 440 EPX                                                       */
 7843:     POWERPC_DEF("440EPX",        CPU_POWERPC_440EPX,                 440EP),
 7844: #endif
 7845: #if defined(TODO_USER_ONLY)
 7846:     /* PowerPC 440 GP                                                        */
 7847:     POWERPC_DEF("440GP",         CPU_POWERPC_440GP,                  440GP),
 7848: #endif
 7849: #if defined(TODO_USER_ONLY)
 7850:     /* PowerPC 440 GPb                                                       */
 7851:     POWERPC_DEF("440GPb",        CPU_POWERPC_440GPb,                 440GP),
 7852: #endif
 7853: #if defined(TODO_USER_ONLY)
 7854:     /* PowerPC 440 GPc                                                       */
 7855:     POWERPC_DEF("440GPc",        CPU_POWERPC_440GPc,                 440GP),
 7856: #endif
 7857: #if defined(TODO_USER_ONLY)
 7858:     /* PowerPC 440 GR                                                        */
 7859:     POWERPC_DEF("440GR",         CPU_POWERPC_440GR,                  440x5),
 7860: #endif
 7861: #if defined(TODO_USER_ONLY)
 7862:     /* PowerPC 440 GRa                                                       */
 7863:     POWERPC_DEF("440GRa",        CPU_POWERPC_440GRa,                 440x5),
 7864: #endif
 7865: #if defined(TODO_USER_ONLY)
 7866:     /* PowerPC 440 GRX                                                       */
 7867:     POWERPC_DEF("440GRX",        CPU_POWERPC_440GRX,                 440x5),
 7868: #endif
 7869: #if defined(TODO_USER_ONLY)
 7870:     /* PowerPC 440 GX                                                        */
 7871:     POWERPC_DEF("440GX",         CPU_POWERPC_440GX,                  440EP),
 7872: #endif
 7873: #if defined(TODO_USER_ONLY)
 7874:     /* PowerPC 440 GXa                                                       */
 7875:     POWERPC_DEF("440GXa",        CPU_POWERPC_440GXa,                 440EP),
 7876: #endif
 7877: #if defined(TODO_USER_ONLY)
 7878:     /* PowerPC 440 GXb                                                       */
 7879:     POWERPC_DEF("440GXb",        CPU_POWERPC_440GXb,                 440EP),
 7880: #endif
 7881: #if defined(TODO_USER_ONLY)
 7882:     /* PowerPC 440 GXc                                                       */
 7883:     POWERPC_DEF("440GXc",        CPU_POWERPC_440GXc,                 440EP),
 7884: #endif
 7885: #if defined(TODO_USER_ONLY)
 7886:     /* PowerPC 440 GXf                                                       */
 7887:     POWERPC_DEF("440GXf",        CPU_POWERPC_440GXf,                 440EP),
 7888: #endif
 7889: #if defined(TODO)
 7890:     /* PowerPC 440 S                                                         */
 7891:     POWERPC_DEF("440S",          CPU_POWERPC_440S,                   440),
 7892: #endif
 7893: #if defined(TODO_USER_ONLY)
 7894:     /* PowerPC 440 SP                                                        */
 7895:     POWERPC_DEF("440SP",         CPU_POWERPC_440SP,                  440EP),
 7896: #endif
 7897: #if defined(TODO_USER_ONLY)
 7898:     /* PowerPC 440 SP2                                                       */
 7899:     POWERPC_DEF("440SP2",        CPU_POWERPC_440SP2,                 440EP),
 7900: #endif
 7901: #if defined(TODO_USER_ONLY)
 7902:     /* PowerPC 440 SPE                                                       */
 7903:     POWERPC_DEF("440SPE",        CPU_POWERPC_440SPE,                 440EP),
 7904: #endif
 7905:     /* PowerPC 460 family                                                    */
 7906: #if defined (TODO)
 7907:     /* Generic PowerPC 464                                                   */
 7908:     POWERPC_DEF("464",           CPU_POWERPC_464,                    460),
 7909: #endif
 7910:     /* PowerPC 464 microcontrolers                                           */
 7911: #if defined (TODO)
 7912:     /* PowerPC 464H90                                                        */
 7913:     POWERPC_DEF("464H90",        CPU_POWERPC_464H90,                 460),
 7914: #endif
 7915: #if defined (TODO)
 7916:     /* PowerPC 464H90F                                                       */
 7917:     POWERPC_DEF("464H90F",       CPU_POWERPC_464H90F,                460F),
 7918: #endif
 7919:     /* Freescale embedded PowerPC cores                                      */
 7920:     /* MPC5xx family (aka RCPU)                                              */
 7921: #if defined(TODO_USER_ONLY)
 7922:     /* Generic MPC5xx core                                                   */
 7923:     POWERPC_DEF("MPC5xx",        CPU_POWERPC_MPC5xx,                 MPC5xx),
 7924: #endif
 7925: #if defined(TODO_USER_ONLY)
 7926:     /* Codename for MPC5xx core                                              */
 7927:     POWERPC_DEF("RCPU",          CPU_POWERPC_MPC5xx,                 MPC5xx),
 7928: #endif
 7929:     /* MPC5xx microcontrollers                                               */
 7930: #if defined(TODO_USER_ONLY)
 7931:     /* MGT560                                                                */
 7932:     POWERPC_DEF("MGT560",        CPU_POWERPC_MGT560,                 MPC5xx),
 7933: #endif
 7934: #if defined(TODO_USER_ONLY)
 7935:     /* MPC509                                                                */
 7936:     POWERPC_DEF("MPC509",        CPU_POWERPC_MPC509,                 MPC5xx),
 7937: #endif
 7938: #if defined(TODO_USER_ONLY)
 7939:     /* MPC533                                                                */
 7940:     POWERPC_DEF("MPC533",        CPU_POWERPC_MPC533,                 MPC5xx),
 7941: #endif
 7942: #if defined(TODO_USER_ONLY)
 7943:     /* MPC534                                                                */
 7944:     POWERPC_DEF("MPC534",        CPU_POWERPC_MPC534,                 MPC5xx),
 7945: #endif
 7946: #if defined(TODO_USER_ONLY)
 7947:     /* MPC555                                                                */
 7948:     POWERPC_DEF("MPC555",        CPU_POWERPC_MPC555,                 MPC5xx),
 7949: #endif
 7950: #if defined(TODO_USER_ONLY)
 7951:     /* MPC556                                                                */
 7952:     POWERPC_DEF("MPC556",        CPU_POWERPC_MPC556,                 MPC5xx),
 7953: #endif
 7954: #if defined(TODO_USER_ONLY)
 7955:     /* MPC560                                                                */
 7956:     POWERPC_DEF("MPC560",        CPU_POWERPC_MPC560,                 MPC5xx),
 7957: #endif
 7958: #if defined(TODO_USER_ONLY)
 7959:     /* MPC561                                                                */
 7960:     POWERPC_DEF("MPC561",        CPU_POWERPC_MPC561,                 MPC5xx),
 7961: #endif
 7962: #if defined(TODO_USER_ONLY)
 7963:     /* MPC562                                                                */
 7964:     POWERPC_DEF("MPC562",        CPU_POWERPC_MPC562,                 MPC5xx),
 7965: #endif
 7966: #if defined(TODO_USER_ONLY)
 7967:     /* MPC563                                                                */
 7968:     POWERPC_DEF("MPC563",        CPU_POWERPC_MPC563,                 MPC5xx),
 7969: #endif
 7970: #if defined(TODO_USER_ONLY)
 7971:     /* MPC564                                                                */
 7972:     POWERPC_DEF("MPC564",        CPU_POWERPC_MPC564,                 MPC5xx),
 7973: #endif
 7974: #if defined(TODO_USER_ONLY)
 7975:     /* MPC565                                                                */
 7976:     POWERPC_DEF("MPC565",        CPU_POWERPC_MPC565,                 MPC5xx),
 7977: #endif
 7978: #if defined(TODO_USER_ONLY)
 7979:     /* MPC566                                                                */
 7980:     POWERPC_DEF("MPC566",        CPU_POWERPC_MPC566,                 MPC5xx),
 7981: #endif
 7982:     /* MPC8xx family (aka PowerQUICC)                                        */
 7983: #if defined(TODO_USER_ONLY)
 7984:     /* Generic MPC8xx core                                                   */
 7985:     POWERPC_DEF("MPC8xx",        CPU_POWERPC_MPC8xx,                 MPC8xx),
 7986: #endif
 7987: #if defined(TODO_USER_ONLY)
 7988:     /* Codename for MPC8xx core                                              */
 7989:     POWERPC_DEF("PowerQUICC",    CPU_POWERPC_MPC8xx,                 MPC8xx),
 7990: #endif
 7991:     /* MPC8xx microcontrollers                                               */
 7992: #if defined(TODO_USER_ONLY)
 7993:     /* MGT823                                                                */
 7994:     POWERPC_DEF("MGT823",        CPU_POWERPC_MGT823,                 MPC8xx),
 7995: #endif
 7996: #if defined(TODO_USER_ONLY)
 7997:     /* MPC821                                                                */
 7998:     POWERPC_DEF("MPC821",        CPU_POWERPC_MPC821,                 MPC8xx),
 7999: #endif
 8000: #if defined(TODO_USER_ONLY)
 8001:     /* MPC823                                                                */
 8002:     POWERPC_DEF("MPC823",        CPU_POWERPC_MPC823,                 MPC8xx),
 8003: #endif
 8004: #if defined(TODO_USER_ONLY)
 8005:     /* MPC850                                                                */
 8006:     POWERPC_DEF("MPC850",        CPU_POWERPC_MPC850,                 MPC8xx),
 8007: #endif
 8008: #if defined(TODO_USER_ONLY)
 8009:     /* MPC852T                                                               */
 8010:     POWERPC_DEF("MPC852T",       CPU_POWERPC_MPC852T,                MPC8xx),
 8011: #endif
 8012: #if defined(TODO_USER_ONLY)
 8013:     /* MPC855T                                                               */
 8014:     POWERPC_DEF("MPC855T",       CPU_POWERPC_MPC855T,                MPC8xx),
 8015: #endif
 8016: #if defined(TODO_USER_ONLY)
 8017:     /* MPC857                                                                */
 8018:     POWERPC_DEF("MPC857",        CPU_POWERPC_MPC857,                 MPC8xx),
 8019: #endif
 8020: #if defined(TODO_USER_ONLY)
 8021:     /* MPC859                                                                */
 8022:     POWERPC_DEF("MPC859",        CPU_POWERPC_MPC859,                 MPC8xx),
 8023: #endif
 8024: #if defined(TODO_USER_ONLY)
 8025:     /* MPC860                                                                */
 8026:     POWERPC_DEF("MPC860",        CPU_POWERPC_MPC860,                 MPC8xx),
 8027: #endif
 8028: #if defined(TODO_USER_ONLY)
 8029:     /* MPC862                                                                */
 8030:     POWERPC_DEF("MPC862",        CPU_POWERPC_MPC862,                 MPC8xx),
 8031: #endif
 8032: #if defined(TODO_USER_ONLY)
 8033:     /* MPC866                                                                */
 8034:     POWERPC_DEF("MPC866",        CPU_POWERPC_MPC866,                 MPC8xx),
 8035: #endif
 8036: #if defined(TODO_USER_ONLY)
 8037:     /* MPC870                                                                */
 8038:     POWERPC_DEF("MPC870",        CPU_POWERPC_MPC870,                 MPC8xx),
 8039: #endif
 8040: #if defined(TODO_USER_ONLY)
 8041:     /* MPC875                                                                */
 8042:     POWERPC_DEF("MPC875",        CPU_POWERPC_MPC875,                 MPC8xx),
 8043: #endif
 8044: #if defined(TODO_USER_ONLY)
 8045:     /* MPC880                                                                */
 8046:     POWERPC_DEF("MPC880",        CPU_POWERPC_MPC880,                 MPC8xx),
 8047: #endif
 8048: #if defined(TODO_USER_ONLY)
 8049:     /* MPC885                                                                */
 8050:     POWERPC_DEF("MPC885",        CPU_POWERPC_MPC885,                 MPC8xx),
 8051: #endif
 8052:     /* MPC82xx family (aka PowerQUICC-II)                                    */
 8053:     /* Generic MPC52xx core                                                  */
 8054:     POWERPC_DEF_SVR("MPC52xx",
 8055:                     CPU_POWERPC_MPC52xx,      POWERPC_SVR_52xx,      G2LE),
 8056:     /* Generic MPC82xx core                                                  */
 8057:     POWERPC_DEF("MPC82xx",       CPU_POWERPC_MPC82xx,                G2),
 8058:     /* Codename for MPC82xx                                                  */
 8059:     POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx,                G2),
 8060:     /* PowerPC G2 core                                                       */
 8061:     POWERPC_DEF("G2",            CPU_POWERPC_G2,                     G2),
 8062:     /* PowerPC G2 H4 core                                                    */
 8063:     POWERPC_DEF("G2H4",          CPU_POWERPC_G2H4,                   G2),
 8064:     /* PowerPC G2 GP core                                                    */
 8065:     POWERPC_DEF("G2GP",          CPU_POWERPC_G2gp,                   G2),
 8066:     /* PowerPC G2 LS core                                                    */
 8067:     POWERPC_DEF("G2LS",          CPU_POWERPC_G2ls,                   G2),
 8068:     /* PowerPC G2 HiP3 core                                                  */
 8069:     POWERPC_DEF("G2HiP3",        CPU_POWERPC_G2_HIP3,                G2),
 8070:     /* PowerPC G2 HiP4 core                                                  */
 8071:     POWERPC_DEF("G2HiP4",        CPU_POWERPC_G2_HIP4,                G2),
 8072:     /* PowerPC MPC603 core                                                   */
 8073:     POWERPC_DEF("MPC603",        CPU_POWERPC_MPC603,                 603E),
 8074:     /* PowerPC G2le core (same as G2 plus little-endian mode support)        */
 8075:     POWERPC_DEF("G2le",          CPU_POWERPC_G2LE,                   G2LE),
 8076:     /* PowerPC G2LE GP core                                                  */
 8077:     POWERPC_DEF("G2leGP",        CPU_POWERPC_G2LEgp,                 G2LE),
 8078:     /* PowerPC G2LE LS core                                                  */
 8079:     POWERPC_DEF("G2leLS",        CPU_POWERPC_G2LEls,                 G2LE),
 8080:     /* PowerPC G2LE GP1 core                                                 */
 8081:     POWERPC_DEF("G2leGP1",       CPU_POWERPC_G2LEgp1,                G2LE),
 8082:     /* PowerPC G2LE GP3 core                                                 */
 8083:     POWERPC_DEF("G2leGP3",       CPU_POWERPC_G2LEgp1,                G2LE),
 8084:     /* PowerPC MPC603 microcontrollers                                       */
 8085:     /* MPC8240                                                               */
 8086:     POWERPC_DEF("MPC8240",       CPU_POWERPC_MPC8240,                603E),
 8087:     /* PowerPC G2 microcontrollers                                           */
 8088: #if defined(TODO)
 8089:     /* MPC5121                                                               */
 8090:     POWERPC_DEF_SVR("MPC5121",
 8091:                     CPU_POWERPC_MPC5121,      POWERPC_SVR_5121,      G2LE),
 8092: #endif
 8093:     /* MPC5200                                                               */
 8094:     POWERPC_DEF_SVR("MPC5200",
 8095:                     CPU_POWERPC_MPC5200,      POWERPC_SVR_5200,      G2LE),
 8096:     /* MPC5200 v1.0                                                          */
 8097:     POWERPC_DEF_SVR("MPC5200_v10",
 8098:                     CPU_POWERPC_MPC5200_v10,  POWERPC_SVR_5200_v10,  G2LE),
 8099:     /* MPC5200 v1.1                                                          */
 8100:     POWERPC_DEF_SVR("MPC5200_v11",
 8101:                     CPU_POWERPC_MPC5200_v11,  POWERPC_SVR_5200_v11,  G2LE),
 8102:     /* MPC5200 v1.2                                                          */
 8103:     POWERPC_DEF_SVR("MPC5200_v12",
 8104:                     CPU_POWERPC_MPC5200_v12,  POWERPC_SVR_5200_v12,  G2LE),
 8105:     /* MPC5200B                                                              */
 8106:     POWERPC_DEF_SVR("MPC5200B",
 8107:                     CPU_POWERPC_MPC5200B,     POWERPC_SVR_5200B,     G2LE),
 8108:     /* MPC5200B v2.0                                                         */
 8109:     POWERPC_DEF_SVR("MPC5200B_v20",
 8110:                     CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
 8111:     /* MPC5200B v2.1                                                         */
 8112:     POWERPC_DEF_SVR("MPC5200B_v21",
 8113:                     CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
 8114:     /* MPC8241                                                               */
 8115:     POWERPC_DEF("MPC8241",       CPU_POWERPC_MPC8241,                G2),
 8116:     /* MPC8245                                                               */
 8117:     POWERPC_DEF("MPC8245",       CPU_POWERPC_MPC8245,                G2),
 8118:     /* MPC8247                                                               */
 8119:     POWERPC_DEF("MPC8247",       CPU_POWERPC_MPC8247,                G2LE),
 8120:     /* MPC8248                                                               */
 8121:     POWERPC_DEF("MPC8248",       CPU_POWERPC_MPC8248,                G2LE),
 8122:     /* MPC8250                                                               */
 8123:     POWERPC_DEF("MPC8250",       CPU_POWERPC_MPC8250,                G2),
 8124:     /* MPC8250 HiP3                                                          */
 8125:     POWERPC_DEF("MPC8250_HiP3",  CPU_POWERPC_MPC8250_HiP3,           G2),
 8126:     /* MPC8250 HiP4                                                          */
 8127:     POWERPC_DEF("MPC8250_HiP4",  CPU_POWERPC_MPC8250_HiP4,           G2),
 8128:     /* MPC8255                                                               */
 8129:     POWERPC_DEF("MPC8255",       CPU_POWERPC_MPC8255,                G2),
 8130:     /* MPC8255 HiP3                                                          */
 8131:     POWERPC_DEF("MPC8255_HiP3",  CPU_POWERPC_MPC8255_HiP3,           G2),
 8132:     /* MPC8255 HiP4                                                          */
 8133:     POWERPC_DEF("MPC8255_HiP4",  CPU_POWERPC_MPC8255_HiP4,           G2),
 8134:     /* MPC8260                                                               */
 8135:     POWERPC_DEF("MPC8260",       CPU_POWERPC_MPC8260,                G2),
 8136:     /* MPC8260 HiP3                                                          */
 8137:     POWERPC_DEF("MPC8260_HiP3",  CPU_POWERPC_MPC8260_HiP3,           G2),
 8138:     /* MPC8260 HiP4                                                          */
 8139:     POWERPC_DEF("MPC8260_HiP4",  CPU_POWERPC_MPC8260_HiP4,           G2),
 8140:     /* MPC8264                                                               */
 8141:     POWERPC_DEF("MPC8264",       CPU_POWERPC_MPC8264,                G2),
 8142:     /* MPC8264 HiP3                                                          */
 8143:     POWERPC_DEF("MPC8264_HiP3",  CPU_POWERPC_MPC8264_HiP3,           G2),
 8144:     /* MPC8264 HiP4                                                          */
 8145:     POWERPC_DEF("MPC8264_HiP4",  CPU_POWERPC_MPC8264_HiP4,           G2),
 8146:     /* MPC8265                                                               */
 8147:     POWERPC_DEF("MPC8265",       CPU_POWERPC_MPC8265,                G2),
 8148:     /* MPC8265 HiP3                                                          */
 8149:     POWERPC_DEF("MPC8265_HiP3",  CPU_POWERPC_MPC8265_HiP3,           G2),
 8150:     /* MPC8265 HiP4                                                          */
 8151:     POWERPC_DEF("MPC8265_HiP4",  CPU_POWERPC_MPC8265_HiP4,           G2),
 8152:     /* MPC8266                                                               */
 8153:     POWERPC_DEF("MPC8266",       CPU_POWERPC_MPC8266,                G2),
 8154:     /* MPC8266 HiP3                                                          */
 8155:     POWERPC_DEF("MPC8266_HiP3",  CPU_POWERPC_MPC8266_HiP3,           G2),
 8156:     /* MPC8266 HiP4                                                          */
 8157:     POWERPC_DEF("MPC8266_HiP4",  CPU_POWERPC_MPC8266_HiP4,           G2),
 8158:     /* MPC8270                                                               */
 8159:     POWERPC_DEF("MPC8270",       CPU_POWERPC_MPC8270,                G2LE),
 8160:     /* MPC8271                                                               */
 8161:     POWERPC_DEF("MPC8271",       CPU_POWERPC_MPC8271,                G2LE),
 8162:     /* MPC8272                                                               */
 8163:     POWERPC_DEF("MPC8272",       CPU_POWERPC_MPC8272,                G2LE),
 8164:     /* MPC8275                                                               */
 8165:     POWERPC_DEF("MPC8275",       CPU_POWERPC_MPC8275,                G2LE),
 8166:     /* MPC8280                                                               */
 8167:     POWERPC_DEF("MPC8280",       CPU_POWERPC_MPC8280,                G2LE),
 8168:     /* e200 family                                                           */
 8169:     /* Generic PowerPC e200 core                                             */
 8170:     POWERPC_DEF("e200",          CPU_POWERPC_e200,                   e200),
 8171:     /* Generic MPC55xx core                                                  */
 8172: #if defined (TODO)
 8173:     POWERPC_DEF_SVR("MPC55xx",
 8174:                     CPU_POWERPC_MPC55xx,      POWERPC_SVR_55xx,      e200),
 8175: #endif
 8176: #if defined (TODO)
 8177:     /* PowerPC e200z0 core                                                   */
 8178:     POWERPC_DEF("e200z0",        CPU_POWERPC_e200z0,                 e200),
 8179: #endif
 8180: #if defined (TODO)
 8181:     /* PowerPC e200z1 core                                                   */
 8182:     POWERPC_DEF("e200z1",        CPU_POWERPC_e200z1,                 e200),
 8183: #endif
 8184: #if defined (TODO)
 8185:     /* PowerPC e200z3 core                                                   */
 8186:     POWERPC_DEF("e200z3",        CPU_POWERPC_e200z3,                 e200),
 8187: #endif
 8188:     /* PowerPC e200z5 core                                                   */
 8189:     POWERPC_DEF("e200z5",        CPU_POWERPC_e200z5,                 e200),
 8190:     /* PowerPC e200z6 core                                                   */
 8191:     POWERPC_DEF("e200z6",        CPU_POWERPC_e200z6,                 e200),
 8192:     /* PowerPC e200 microcontrollers                                         */
 8193: #if defined (TODO)
 8194:     /* MPC5514E                                                              */
 8195:     POWERPC_DEF_SVR("MPC5514E",
 8196:                     CPU_POWERPC_MPC5514E,     POWERPC_SVR_5514E,     e200),
 8197: #endif
 8198: #if defined (TODO)
 8199:     /* MPC5514E v0                                                           */
 8200:     POWERPC_DEF_SVR("MPC5514E_v0",
 8201:                     CPU_POWERPC_MPC5514E_v0,  POWERPC_SVR_5514E_v0,  e200),
 8202: #endif
 8203: #if defined (TODO)
 8204:     /* MPC5514E v1                                                           */
 8205:     POWERPC_DEF_SVR("MPC5514E_v1",
 8206:                     CPU_POWERPC_MPC5514E_v1,  POWERPC_SVR_5514E_v1,  e200),
 8207: #endif
 8208: #if defined (TODO)
 8209:     /* MPC5514G                                                              */
 8210:     POWERPC_DEF_SVR("MPC5514G",
 8211:                     CPU_POWERPC_MPC5514G,     POWERPC_SVR_5514G,     e200),
 8212: #endif
 8213: #if defined (TODO)
 8214:     /* MPC5514G v0                                                           */
 8215:     POWERPC_DEF_SVR("MPC5514G_v0",
 8216:                     CPU_POWERPC_MPC5514G_v0,  POWERPC_SVR_5514G_v0,  e200),
 8217: #endif
 8218: #if defined (TODO)
 8219:     /* MPC5514G v1                                                           */
 8220:     POWERPC_DEF_SVR("MPC5514G_v1",
 8221:                     CPU_POWERPC_MPC5514G_v1,  POWERPC_SVR_5514G_v1,  e200),
 8222: #endif
 8223: #if defined (TODO)
 8224:     /* MPC5515S                                                              */
 8225:     POWERPC_DEF_SVR("MPC5515S",
 8226:                     CPU_POWERPC_MPC5515S,     POWERPC_SVR_5515S,     e200),
 8227: #endif
 8228: #if defined (TODO)
 8229:     /* MPC5516E                                                              */
 8230:     POWERPC_DEF_SVR("MPC5516E",
 8231:                     CPU_POWERPC_MPC5516E,     POWERPC_SVR_5516E,     e200),
 8232: #endif
 8233: #if defined (TODO)
 8234:     /* MPC5516E v0                                                           */
 8235:     POWERPC_DEF_SVR("MPC5516E_v0",
 8236:                     CPU_POWERPC_MPC5516E_v0,  POWERPC_SVR_5516E_v0,  e200),
 8237: #endif
 8238: #if defined (TODO)
 8239:     /* MPC5516E v1                                                           */
 8240:     POWERPC_DEF_SVR("MPC5516E_v1",
 8241:                     CPU_POWERPC_MPC5516E_v1,  POWERPC_SVR_5516E_v1,  e200),
 8242: #endif
 8243: #if defined (TODO)
 8244:     /* MPC5516G                                                              */
 8245:     POWERPC_DEF_SVR("MPC5516G",
 8246:                     CPU_POWERPC_MPC5516G,     POWERPC_SVR_5516G,     e200),
 8247: #endif
 8248: #if defined (TODO)
 8249:     /* MPC5516G v0                                                           */
 8250:     POWERPC_DEF_SVR("MPC5516G_v0",
 8251:                     CPU_POWERPC_MPC5516G_v0,  POWERPC_SVR_5516G_v0,  e200),
 8252: #endif
 8253: #if defined (TODO)
 8254:     /* MPC5516G v1                                                           */
 8255:     POWERPC_DEF_SVR("MPC5516G_v1",
 8256:                     CPU_POWERPC_MPC5516G_v1,  POWERPC_SVR_5516G_v1,  e200),
 8257: #endif
 8258: #if defined (TODO)
 8259:     /* MPC5516S                                                              */
 8260:     POWERPC_DEF_SVR("MPC5516S",
 8261:                     CPU_POWERPC_MPC5516S,     POWERPC_SVR_5516S,     e200),
 8262: #endif
 8263: #if defined (TODO)
 8264:     /* MPC5533                                                               */
 8265:     POWERPC_DEF_SVR("MPC5533",
 8266:                     CPU_POWERPC_MPC5533,      POWERPC_SVR_5533,      e200),
 8267: #endif
 8268: #if defined (TODO)
 8269:     /* MPC5534                                                               */
 8270:     POWERPC_DEF_SVR("MPC5534",
 8271:                     CPU_POWERPC_MPC5534,      POWERPC_SVR_5534,      e200),
 8272: #endif
 8273: #if defined (TODO)
 8274:     /* MPC5553                                                               */
 8275:     POWERPC_DEF_SVR("MPC5553",
 8276:                     CPU_POWERPC_MPC5553,      POWERPC_SVR_5553,      e200),
 8277: #endif
 8278: #if defined (TODO)
 8279:     /* MPC5554                                                               */
 8280:     POWERPC_DEF_SVR("MPC5554",
 8281:                     CPU_POWERPC_MPC5554,      POWERPC_SVR_5554,      e200),
 8282: #endif
 8283: #if defined (TODO)
 8284:     /* MPC5561                                                               */
 8285:     POWERPC_DEF_SVR("MPC5561",
 8286:                     CPU_POWERPC_MPC5561,      POWERPC_SVR_5561,      e200),
 8287: #endif
 8288: #if defined (TODO)
 8289:     /* MPC5565                                                               */
 8290:     POWERPC_DEF_SVR("MPC5565",
 8291:                     CPU_POWERPC_MPC5565,      POWERPC_SVR_5565,      e200),
 8292: #endif
 8293: #if defined (TODO)
 8294:     /* MPC5566                                                               */
 8295:     POWERPC_DEF_SVR("MPC5566",
 8296:                     CPU_POWERPC_MPC5566,      POWERPC_SVR_5566,      e200),
 8297: #endif
 8298: #if defined (TODO)
 8299:     /* MPC5567                                                               */
 8300:     POWERPC_DEF_SVR("MPC5567",
 8301:                     CPU_POWERPC_MPC5567,      POWERPC_SVR_5567,      e200),
 8302: #endif
 8303:     /* e300 family                                                           */
 8304:     /* Generic PowerPC e300 core                                             */
 8305:     POWERPC_DEF("e300",          CPU_POWERPC_e300,                   e300),
 8306:     /* PowerPC e300c1 core                                                   */
 8307:     POWERPC_DEF("e300c1",        CPU_POWERPC_e300c1,                 e300),
 8308:     /* PowerPC e300c2 core                                                   */
 8309:     POWERPC_DEF("e300c2",        CPU_POWERPC_e300c2,                 e300),
 8310:     /* PowerPC e300c3 core                                                   */
 8311:     POWERPC_DEF("e300c3",        CPU_POWERPC_e300c3,                 e300),
 8312:     /* PowerPC e300c4 core                                                   */
 8313:     POWERPC_DEF("e300c4",        CPU_POWERPC_e300c4,                 e300),
 8314:     /* PowerPC e300 microcontrollers                                         */
 8315: #if defined (TODO)
 8316:     /* MPC8313                                                               */
 8317:     POWERPC_DEF_SVR("MPC8313",
 8318:                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8313,      e300),
 8319: #endif
 8320: #if defined (TODO)
 8321:     /* MPC8313E                                                              */
 8322:     POWERPC_DEF_SVR("MPC8313E",
 8323:                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8313E,     e300),
 8324: #endif
 8325: #if defined (TODO)
 8326:     /* MPC8314                                                               */
 8327:     POWERPC_DEF_SVR("MPC8314",
 8328:                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8314,      e300),
 8329: #endif
 8330: #if defined (TODO)
 8331:     /* MPC8314E                                                              */
 8332:     POWERPC_DEF_SVR("MPC8314E",
 8333:                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8314E,     e300),
 8334: #endif
 8335: #if defined (TODO)
 8336:     /* MPC8315                                                               */
 8337:     POWERPC_DEF_SVR("MPC8315",
 8338:                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8315,      e300),
 8339: #endif
 8340: #if defined (TODO)
 8341:     /* MPC8315E                                                              */
 8342:     POWERPC_DEF_SVR("MPC8315E",
 8343:                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8315E,     e300),
 8344: #endif
 8345: #if defined (TODO)
 8346:     /* MPC8321                                                               */
 8347:     POWERPC_DEF_SVR("MPC8321",
 8348:                     CPU_POWERPC_MPC832x,      POWERPC_SVR_8321,      e300),
 8349: #endif
 8350: #if defined (TODO)
 8351:     /* MPC8321E                                                              */
 8352:     POWERPC_DEF_SVR("MPC8321E",
 8353:                     CPU_POWERPC_MPC832x,      POWERPC_SVR_8321E,     e300),
 8354: #endif
 8355: #if defined (TODO)
 8356:     /* MPC8323                                                               */
 8357:     POWERPC_DEF_SVR("MPC8323",
 8358:                     CPU_POWERPC_MPC832x,      POWERPC_SVR_8323,      e300),
 8359: #endif
 8360: #if defined (TODO)
 8361:     /* MPC8323E                                                              */
 8362:     POWERPC_DEF_SVR("MPC8323E",
 8363:                     CPU_POWERPC_MPC832x,      POWERPC_SVR_8323E,     e300),
 8364: #endif
 8365:     /* MPC8343                                                               */
 8366:     POWERPC_DEF_SVR("MPC8343",
 8367:                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8343,      e300),
 8368:     /* MPC8343A                                                              */
 8369:     POWERPC_DEF_SVR("MPC8343A",
 8370:                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8343A,     e300),
 8371:     /* MPC8343E                                                              */
 8372:     POWERPC_DEF_SVR("MPC8343E",
 8373:                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8343E,     e300),
 8374:     /* MPC8343EA                                                             */
 8375:     POWERPC_DEF_SVR("MPC8343EA",
 8376:                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8343EA,    e300),
 8377:     /* MPC8347                                                               */
 8378:     POWERPC_DEF_SVR("MPC8347",
 8379:                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347,      e300),
 8380:     /* MPC8347T                                                              */
 8381:     POWERPC_DEF_SVR("MPC8347T",
 8382:                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347T,     e300),
 8383:     /* MPC8347P                                                              */
 8384:     POWERPC_DEF_SVR("MPC8347P",
 8385:                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347P,     e300),
 8386:     /* MPC8347A                                                              */
 8387:     POWERPC_DEF_SVR("MPC8347A",
 8388:                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347A,     e300),
 8389:     /* MPC8347AT                                                             */
 8390:     POWERPC_DEF_SVR("MPC8347AT",
 8391:                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347AT,    e300),
 8392:     /* MPC8347AP                                                             */
 8393:     POWERPC_DEF_SVR("MPC8347AP",
 8394:                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347AP,    e300),
 8395:     /* MPC8347E                                                              */
 8396:     POWERPC_DEF_SVR("MPC8347E",
 8397:                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347E,     e300),
 8398:     /* MPC8347ET                                                             */
 8399:     POWERPC_DEF_SVR("MPC8347ET",
 8400:                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347ET,    e300),
 8401:     /* MPC8343EP                                                             */
 8402:     POWERPC_DEF_SVR("MPC8347EP",
 8403:                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347EP,    e300),
 8404:     /* MPC8347EA                                                             */
 8405:     POWERPC_DEF_SVR("MPC8347EA",
 8406:                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347EA,    e300),
 8407:     /* MPC8347EAT                                                            */
 8408:     POWERPC_DEF_SVR("MPC8347EAT",
 8409:                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347EAT,   e300),
 8410:     /* MPC8343EAP                                                            */
 8411:     POWERPC_DEF_SVR("MPC8347EAP",
 8412:                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347EAP,   e300),
 8413:     /* MPC8349                                                               */
 8414:     POWERPC_DEF_SVR("MPC8349",
 8415:                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8349,      e300),
 8416:     /* MPC8349A                                                              */
 8417:     POWERPC_DEF_SVR("MPC8349A",
 8418:                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8349A,     e300),
 8419:     /* MPC8349E                                                              */
 8420:     POWERPC_DEF_SVR("MPC8349E",
 8421:                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8349E,     e300),
 8422:     /* MPC8349EA                                                             */
 8423:     POWERPC_DEF_SVR("MPC8349EA",
 8424:                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8349EA,    e300),
 8425: #if defined (TODO)
 8426:     /* MPC8358E                                                              */
 8427:     POWERPC_DEF_SVR("MPC8358E",
 8428:                     CPU_POWERPC_MPC835x,      POWERPC_SVR_8358E,     e300),
 8429: #endif
 8430: #if defined (TODO)
 8431:     /* MPC8360E                                                              */
 8432:     POWERPC_DEF_SVR("MPC8360E",
 8433:                     CPU_POWERPC_MPC836x,      POWERPC_SVR_8360E,     e300),
 8434: #endif
 8435:     /* MPC8377                                                               */
 8436:     POWERPC_DEF_SVR("MPC8377",
 8437:                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8377,      e300),
 8438:     /* MPC8377E                                                              */
 8439:     POWERPC_DEF_SVR("MPC8377E",
 8440:                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8377E,     e300),
 8441:     /* MPC8378                                                               */
 8442:     POWERPC_DEF_SVR("MPC8378",
 8443:                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8378,      e300),
 8444:     /* MPC8378E                                                              */
 8445:     POWERPC_DEF_SVR("MPC8378E",
 8446:                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8378E,     e300),
 8447:     /* MPC8379                                                               */
 8448:     POWERPC_DEF_SVR("MPC8379",
 8449:                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8379,      e300),
 8450:     /* MPC8379E                                                              */
 8451:     POWERPC_DEF_SVR("MPC8379E",
 8452:                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8379E,     e300),
 8453:     /* e500 family                                                           */
 8454:     /* PowerPC e500 core                                                     */
 8455:     POWERPC_DEF("e500",          CPU_POWERPC_e500v2_v22,             e500v2),
 8456:     /* PowerPC e500v1 core                                                   */
 8457:     POWERPC_DEF("e500v1",        CPU_POWERPC_e500v1,                 e500v1),
 8458:     /* PowerPC e500 v1.0 core                                                */
 8459:     POWERPC_DEF("e500_v10",      CPU_POWERPC_e500v1_v10,             e500v1),
 8460:     /* PowerPC e500 v2.0 core                                                */
 8461:     POWERPC_DEF("e500_v20",      CPU_POWERPC_e500v1_v20,             e500v1),
 8462:     /* PowerPC e500v2 core                                                   */
 8463:     POWERPC_DEF("e500v2",        CPU_POWERPC_e500v2,                 e500v2),
 8464:     /* PowerPC e500v2 v1.0 core                                              */
 8465:     POWERPC_DEF("e500v2_v10",    CPU_POWERPC_e500v2_v10,             e500v2),
 8466:     /* PowerPC e500v2 v2.0 core                                              */
 8467:     POWERPC_DEF("e500v2_v20",    CPU_POWERPC_e500v2_v20,             e500v2),
 8468:     /* PowerPC e500v2 v2.1 core                                              */
 8469:     POWERPC_DEF("e500v2_v21",    CPU_POWERPC_e500v2_v21,             e500v2),
 8470:     /* PowerPC e500v2 v2.2 core                                              */
 8471:     POWERPC_DEF("e500v2_v22",    CPU_POWERPC_e500v2_v22,             e500v2),
 8472:     /* PowerPC e500v2 v3.0 core                                              */
 8473:     POWERPC_DEF("e500v2_v30",    CPU_POWERPC_e500v2_v30,             e500v2),
 8474:     /* PowerPC e500 microcontrollers                                         */
 8475:     /* MPC8533                                                               */
 8476:     POWERPC_DEF_SVR("MPC8533",
 8477:                     CPU_POWERPC_MPC8533,      POWERPC_SVR_8533,      e500v2),
 8478:     /* MPC8533 v1.0                                                          */
 8479:     POWERPC_DEF_SVR("MPC8533_v10",
 8480:                     CPU_POWERPC_MPC8533_v10,  POWERPC_SVR_8533_v10,  e500v2),
 8481:     /* MPC8533 v1.1                                                          */
 8482:     POWERPC_DEF_SVR("MPC8533_v11",
 8483:                     CPU_POWERPC_MPC8533_v11,  POWERPC_SVR_8533_v11,  e500v2),
 8484:     /* MPC8533E                                                              */
 8485:     POWERPC_DEF_SVR("MPC8533E",
 8486:                     CPU_POWERPC_MPC8533E,     POWERPC_SVR_8533E,     e500v2),
 8487:     /* MPC8533E v1.0                                                         */
 8488:     POWERPC_DEF_SVR("MPC8533E_v10",
 8489:                     CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
 8490:     POWERPC_DEF_SVR("MPC8533E_v11",
 8491:                     CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
 8492:     /* MPC8540                                                               */
 8493:     POWERPC_DEF_SVR("MPC8540",
 8494:                     CPU_POWERPC_MPC8540,      POWERPC_SVR_8540,      e500v1),
 8495:     /* MPC8540 v1.0                                                          */
 8496:     POWERPC_DEF_SVR("MPC8540_v10",
 8497:                     CPU_POWERPC_MPC8540_v10,  POWERPC_SVR_8540_v10,  e500v1),
 8498:     /* MPC8540 v2.0                                                          */
 8499:     POWERPC_DEF_SVR("MPC8540_v20",
 8500:                     CPU_POWERPC_MPC8540_v20,  POWERPC_SVR_8540_v20,  e500v1),
 8501:     /* MPC8540 v2.1                                                          */
 8502:     POWERPC_DEF_SVR("MPC8540_v21",
 8503:                     CPU_POWERPC_MPC8540_v21,  POWERPC_SVR_8540_v21,  e500v1),
 8504:     /* MPC8541                                                               */
 8505:     POWERPC_DEF_SVR("MPC8541",
 8506:                     CPU_POWERPC_MPC8541,      POWERPC_SVR_8541,      e500v1),
 8507:     /* MPC8541 v1.0                                                          */
 8508:     POWERPC_DEF_SVR("MPC8541_v10",
 8509:                     CPU_POWERPC_MPC8541_v10,  POWERPC_SVR_8541_v10,  e500v1),
 8510:     /* MPC8541 v1.1                                                          */
 8511:     POWERPC_DEF_SVR("MPC8541_v11",
 8512:                     CPU_POWERPC_MPC8541_v11,  POWERPC_SVR_8541_v11,  e500v1),
 8513:     /* MPC8541E                                                              */
 8514:     POWERPC_DEF_SVR("MPC8541E",
 8515:                     CPU_POWERPC_MPC8541E,     POWERPC_SVR_8541E,     e500v1),
 8516:     /* MPC8541E v1.0                                                         */
 8517:     POWERPC_DEF_SVR("MPC8541E_v10",
 8518:                     CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
 8519:     /* MPC8541E v1.1                                                         */
 8520:     POWERPC_DEF_SVR("MPC8541E_v11",
 8521:                     CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
 8522:     /* MPC8543                                                               */
 8523:     POWERPC_DEF_SVR("MPC8543",
 8524:                     CPU_POWERPC_MPC8543,      POWERPC_SVR_8543,      e500v2),
 8525:     /* MPC8543 v1.0                                                          */
 8526:     POWERPC_DEF_SVR("MPC8543_v10",
 8527:                     CPU_POWERPC_MPC8543_v10,  POWERPC_SVR_8543_v10,  e500v2),
 8528:     /* MPC8543 v1.1                                                          */
 8529:     POWERPC_DEF_SVR("MPC8543_v11",
 8530:                     CPU_POWERPC_MPC8543_v11,  POWERPC_SVR_8543_v11,  e500v2),
 8531:     /* MPC8543 v2.0                                                          */
 8532:     POWERPC_DEF_SVR("MPC8543_v20",
 8533:                     CPU_POWERPC_MPC8543_v20,  POWERPC_SVR_8543_v20,  e500v2),
 8534:     /* MPC8543 v2.1                                                          */
 8535:     POWERPC_DEF_SVR("MPC8543_v21",
 8536:                     CPU_POWERPC_MPC8543_v21,  POWERPC_SVR_8543_v21,  e500v2),
 8537:     /* MPC8543E                                                              */
 8538:     POWERPC_DEF_SVR("MPC8543E",
 8539:                     CPU_POWERPC_MPC8543E,     POWERPC_SVR_8543E,     e500v2),
 8540:     /* MPC8543E v1.0                                                         */
 8541:     POWERPC_DEF_SVR("MPC8543E_v10",
 8542:                     CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
 8543:     /* MPC8543E v1.1                                                         */
 8544:     POWERPC_DEF_SVR("MPC8543E_v11",
 8545:                     CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
 8546:     /* MPC8543E v2.0                                                         */
 8547:     POWERPC_DEF_SVR("MPC8543E_v20",
 8548:                     CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
 8549:     /* MPC8543E v2.1                                                         */
 8550:     POWERPC_DEF_SVR("MPC8543E_v21",
 8551:                     CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
 8552:     /* MPC8544                                                               */
 8553:     POWERPC_DEF_SVR("MPC8544",
 8554:                     CPU_POWERPC_MPC8544,      POWERPC_SVR_8544,      e500v2),
 8555:     /* MPC8544 v1.0                                                          */
 8556:     POWERPC_DEF_SVR("MPC8544_v10",
 8557:                     CPU_POWERPC_MPC8544_v10,  POWERPC_SVR_8544_v10,  e500v2),
 8558:     /* MPC8544 v1.1                                                          */
 8559:     POWERPC_DEF_SVR("MPC8544_v11",
 8560:                     CPU_POWERPC_MPC8544_v11,  POWERPC_SVR_8544_v11,  e500v2),
 8561:     /* MPC8544E                                                              */
 8562:     POWERPC_DEF_SVR("MPC8544E",
 8563:                     CPU_POWERPC_MPC8544E,     POWERPC_SVR_8544E,     e500v2),
 8564:     /* MPC8544E v1.0                                                         */
 8565:     POWERPC_DEF_SVR("MPC8544E_v10",
 8566:                     CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
 8567:     /* MPC8544E v1.1                                                         */
 8568:     POWERPC_DEF_SVR("MPC8544E_v11",
 8569:                     CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
 8570:     /* MPC8545                                                               */
 8571:     POWERPC_DEF_SVR("MPC8545",
 8572:                     CPU_POWERPC_MPC8545,      POWERPC_SVR_8545,      e500v2),
 8573:     /* MPC8545 v2.0                                                          */
 8574:     POWERPC_DEF_SVR("MPC8545_v20",
 8575:                     CPU_POWERPC_MPC8545_v20,  POWERPC_SVR_8545_v20,  e500v2),
 8576:     /* MPC8545 v2.1                                                          */
 8577:     POWERPC_DEF_SVR("MPC8545_v21",
 8578:                     CPU_POWERPC_MPC8545_v21,  POWERPC_SVR_8545_v21,  e500v2),
 8579:     /* MPC8545E                                                              */
 8580:     POWERPC_DEF_SVR("MPC8545E",
 8581:                     CPU_POWERPC_MPC8545E,     POWERPC_SVR_8545E,     e500v2),
 8582:     /* MPC8545E v2.0                                                         */
 8583:     POWERPC_DEF_SVR("MPC8545E_v20",
 8584:                     CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
 8585:     /* MPC8545E v2.1                                                         */
 8586:     POWERPC_DEF_SVR("MPC8545E_v21",
 8587:                     CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
 8588:     /* MPC8547E                                                              */
 8589:     POWERPC_DEF_SVR("MPC8547E",
 8590:                     CPU_POWERPC_MPC8547E,     POWERPC_SVR_8547E,     e500v2),
 8591:     /* MPC8547E v2.0                                                         */
 8592:     POWERPC_DEF_SVR("MPC8547E_v20",
 8593:                     CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
 8594:     /* MPC8547E v2.1                                                         */
 8595:     POWERPC_DEF_SVR("MPC8547E_v21",
 8596:                     CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
 8597:     /* MPC8548                                                               */
 8598:     POWERPC_DEF_SVR("MPC8548",
 8599:                     CPU_POWERPC_MPC8548,      POWERPC_SVR_8548,      e500v2),
 8600:     /* MPC8548 v1.0                                                          */
 8601:     POWERPC_DEF_SVR("MPC8548_v10",
 8602:                     CPU_POWERPC_MPC8548_v10,  POWERPC_SVR_8548_v10,  e500v2),
 8603:     /* MPC8548 v1.1                                                          */
 8604:     POWERPC_DEF_SVR("MPC8548_v11",
 8605:                     CPU_POWERPC_MPC8548_v11,  POWERPC_SVR_8548_v11,  e500v2),
 8606:     /* MPC8548 v2.0                                                          */
 8607:     POWERPC_DEF_SVR("MPC8548_v20",
 8608:                     CPU_POWERPC_MPC8548_v20,  POWERPC_SVR_8548_v20,  e500v2),
 8609:     /* MPC8548 v2.1                                                          */
 8610:     POWERPC_DEF_SVR("MPC8548_v21",
 8611:                     CPU_POWERPC_MPC8548_v21,  POWERPC_SVR_8548_v21,  e500v2),
 8612:     /* MPC8548E                                                              */
 8613:     POWERPC_DEF_SVR("MPC8548E",
 8614:                     CPU_POWERPC_MPC8548E,     POWERPC_SVR_8548E,     e500v2),
 8615:     /* MPC8548E v1.0                                                         */
 8616:     POWERPC_DEF_SVR("MPC8548E_v10",
 8617:                     CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
 8618:     /* MPC8548E v1.1                                                         */
 8619:     POWERPC_DEF_SVR("MPC8548E_v11",
 8620:                     CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
 8621:     /* MPC8548E v2.0                                                         */
 8622:     POWERPC_DEF_SVR("MPC8548E_v20",
 8623:                     CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
 8624:     /* MPC8548E v2.1                                                         */
 8625:     POWERPC_DEF_SVR("MPC8548E_v21",
 8626:                     CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
 8627:     /* MPC8555                                                               */
 8628:     POWERPC_DEF_SVR("MPC8555",
 8629:                     CPU_POWERPC_MPC8555,      POWERPC_SVR_8555,      e500v2),
 8630:     /* MPC8555 v1.0                                                          */
 8631:     POWERPC_DEF_SVR("MPC8555_v10",
 8632:                     CPU_POWERPC_MPC8555_v10,  POWERPC_SVR_8555_v10,  e500v2),
 8633:     /* MPC8555 v1.1                                                          */
 8634:     POWERPC_DEF_SVR("MPC8555_v11",
 8635:                     CPU_POWERPC_MPC8555_v11,  POWERPC_SVR_8555_v11,  e500v2),
 8636:     /* MPC8555E                                                              */
 8637:     POWERPC_DEF_SVR("MPC8555E",
 8638:                     CPU_POWERPC_MPC8555E,     POWERPC_SVR_8555E,     e500v2),
 8639:     /* MPC8555E v1.0                                                         */
 8640:     POWERPC_DEF_SVR("MPC8555E_v10",
 8641:                     CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
 8642:     /* MPC8555E v1.1                                                         */
 8643:     POWERPC_DEF_SVR("MPC8555E_v11",
 8644:                     CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
 8645:     /* MPC8560                                                               */
 8646:     POWERPC_DEF_SVR("MPC8560",
 8647:                     CPU_POWERPC_MPC8560,      POWERPC_SVR_8560,      e500v2),
 8648:     /* MPC8560 v1.0                                                          */
 8649:     POWERPC_DEF_SVR("MPC8560_v10",
 8650:                     CPU_POWERPC_MPC8560_v10,  POWERPC_SVR_8560_v10,  e500v2),
 8651:     /* MPC8560 v2.0                                                          */
 8652:     POWERPC_DEF_SVR("MPC8560_v20",
 8653:                     CPU_POWERPC_MPC8560_v20,  POWERPC_SVR_8560_v20,  e500v2),
 8654:     /* MPC8560 v2.1                                                          */
 8655:     POWERPC_DEF_SVR("MPC8560_v21",
 8656:                     CPU_POWERPC_MPC8560_v21,  POWERPC_SVR_8560_v21,  e500v2),
 8657:     /* MPC8567                                                               */
 8658:     POWERPC_DEF_SVR("MPC8567",
 8659:                     CPU_POWERPC_MPC8567,      POWERPC_SVR_8567,      e500v2),
 8660:     /* MPC8567E                                                              */
 8661:     POWERPC_DEF_SVR("MPC8567E",
 8662:                     CPU_POWERPC_MPC8567E,     POWERPC_SVR_8567E,     e500v2),
 8663:     /* MPC8568                                                               */
 8664:     POWERPC_DEF_SVR("MPC8568",
 8665:                     CPU_POWERPC_MPC8568,      POWERPC_SVR_8568,      e500v2),
 8666:     /* MPC8568E                                                              */
 8667:     POWERPC_DEF_SVR("MPC8568E",
 8668:                     CPU_POWERPC_MPC8568E,     POWERPC_SVR_8568E,     e500v2),
 8669:     /* MPC8572                                                               */
 8670:     POWERPC_DEF_SVR("MPC8572",
 8671:                     CPU_POWERPC_MPC8572,      POWERPC_SVR_8572,      e500v2),
 8672:     /* MPC8572E                                                              */
 8673:     POWERPC_DEF_SVR("MPC8572E",
 8674:                     CPU_POWERPC_MPC8572E,     POWERPC_SVR_8572E,     e500v2),
 8675:     /* e600 family                                                           */
 8676:     /* PowerPC e600 core                                                     */
 8677:     POWERPC_DEF("e600",          CPU_POWERPC_e600,                   7400),
 8678:     /* PowerPC e600 microcontrollers                                         */
 8679: #if defined (TODO)
 8680:     /* MPC8610                                                               */
 8681:     POWERPC_DEF_SVR("MPC8610",
 8682:                     CPU_POWERPC_MPC8610,      POWERPC_SVR_8610,      7400),
 8683: #endif
 8684:     /* MPC8641                                                               */
 8685:     POWERPC_DEF_SVR("MPC8641",
 8686:                     CPU_POWERPC_MPC8641,      POWERPC_SVR_8641,      7400),
 8687:     /* MPC8641D                                                              */
 8688:     POWERPC_DEF_SVR("MPC8641D",
 8689:                     CPU_POWERPC_MPC8641D,     POWERPC_SVR_8641D,     7400),
 8690:     /* 32 bits "classic" PowerPC                                             */
 8691:     /* PowerPC 6xx family                                                    */
 8692:     /* PowerPC 601                                                           */
 8693:     POWERPC_DEF("601",           CPU_POWERPC_601,                    601v),
 8694:     /* PowerPC 601v0                                                         */
 8695:     POWERPC_DEF("601_v0",        CPU_POWERPC_601_v0,                 601),
 8696:     /* PowerPC 601v1                                                         */
 8697:     POWERPC_DEF("601_v1",        CPU_POWERPC_601_v1,                 601),
 8698:     /* PowerPC 601v                                                          */
 8699:     POWERPC_DEF("601v",          CPU_POWERPC_601v,                   601v),
 8700:     /* PowerPC 601v2                                                         */
 8701:     POWERPC_DEF("601_v2",        CPU_POWERPC_601_v2,                 601v),
 8702:     /* PowerPC 602                                                           */
 8703:     POWERPC_DEF("602",           CPU_POWERPC_602,                    602),
 8704:     /* PowerPC 603                                                           */
 8705:     POWERPC_DEF("603",           CPU_POWERPC_603,                    603),
 8706:     /* Code name for PowerPC 603                                             */
 8707:     POWERPC_DEF("Vanilla",       CPU_POWERPC_603,                    603),
 8708:     /* PowerPC 603e (aka PID6)                                               */
 8709:     POWERPC_DEF("603e",          CPU_POWERPC_603E,                   603E),
 8710:     /* Code name for PowerPC 603e                                            */
 8711:     POWERPC_DEF("Stretch",       CPU_POWERPC_603E,                   603E),
 8712:     /* PowerPC 603e v1.1                                                     */
 8713:     POWERPC_DEF("603e_v1.1",     CPU_POWERPC_603E_v11,               603E),
 8714:     /* PowerPC 603e v1.2                                                     */
 8715:     POWERPC_DEF("603e_v1.2",     CPU_POWERPC_603E_v12,               603E),
 8716:     /* PowerPC 603e v1.3                                                     */
 8717:     POWERPC_DEF("603e_v1.3",     CPU_POWERPC_603E_v13,               603E),
 8718:     /* PowerPC 603e v1.4                                                     */
 8719:     POWERPC_DEF("603e_v1.4",     CPU_POWERPC_603E_v14,               603E),
 8720:     /* PowerPC 603e v2.2                                                     */
 8721:     POWERPC_DEF("603e_v2.2",     CPU_POWERPC_603E_v22,               603E),
 8722:     /* PowerPC 603e v3                                                       */
 8723:     POWERPC_DEF("603e_v3",       CPU_POWERPC_603E_v3,                603E),
 8724:     /* PowerPC 603e v4                                                       */
 8725:     POWERPC_DEF("603e_v4",       CPU_POWERPC_603E_v4,                603E),
 8726:     /* PowerPC 603e v4.1                                                     */
 8727:     POWERPC_DEF("603e_v4.1",     CPU_POWERPC_603E_v41,               603E),
 8728:     /* PowerPC 603e (aka PID7)                                               */
 8729:     POWERPC_DEF("603e7",         CPU_POWERPC_603E7,                  603E),
 8730:     /* PowerPC 603e7t                                                        */
 8731:     POWERPC_DEF("603e7t",        CPU_POWERPC_603E7t,                 603E),
 8732:     /* PowerPC 603e7v                                                        */
 8733:     POWERPC_DEF("603e7v",        CPU_POWERPC_603E7v,                 603E),
 8734:     /* Code name for PowerPC 603ev                                           */
 8735:     POWERPC_DEF("Vaillant",      CPU_POWERPC_603E7v,                 603E),
 8736:     /* PowerPC 603e7v1                                                       */
 8737:     POWERPC_DEF("603e7v1",       CPU_POWERPC_603E7v1,                603E),
 8738:     /* PowerPC 603e7v2                                                       */
 8739:     POWERPC_DEF("603e7v2",       CPU_POWERPC_603E7v2,                603E),
 8740:     /* PowerPC 603p (aka PID7v)                                              */
 8741:     POWERPC_DEF("603p",          CPU_POWERPC_603P,                   603E),
 8742:     /* PowerPC 603r (aka PID7t)                                              */
 8743:     POWERPC_DEF("603r",          CPU_POWERPC_603R,                   603E),
 8744:     /* Code name for PowerPC 603r                                            */
 8745:     POWERPC_DEF("Goldeneye",     CPU_POWERPC_603R,                   603E),
 8746:     /* PowerPC 604                                                           */
 8747:     POWERPC_DEF("604",           CPU_POWERPC_604,                    604),
 8748:     /* PowerPC 604e (aka PID9)                                               */
 8749:     POWERPC_DEF("604e",          CPU_POWERPC_604E,                   604E),
 8750:     /* Code name for PowerPC 604e                                            */
 8751:     POWERPC_DEF("Sirocco",       CPU_POWERPC_604E,                   604E),
 8752:     /* PowerPC 604e v1.0                                                     */
 8753:     POWERPC_DEF("604e_v1.0",     CPU_POWERPC_604E_v10,               604E),
 8754:     /* PowerPC 604e v2.2                                                     */
 8755:     POWERPC_DEF("604e_v2.2",     CPU_POWERPC_604E_v22,               604E),
 8756:     /* PowerPC 604e v2.4                                                     */
 8757:     POWERPC_DEF("604e_v2.4",     CPU_POWERPC_604E_v24,               604E),
 8758:     /* PowerPC 604r (aka PIDA)                                               */
 8759:     POWERPC_DEF("604r",          CPU_POWERPC_604R,                   604E),
 8760:     /* Code name for PowerPC 604r                                            */
 8761:     POWERPC_DEF("Mach5",         CPU_POWERPC_604R,                   604E),
 8762: #if defined(TODO)
 8763:     /* PowerPC 604ev                                                         */
 8764:     POWERPC_DEF("604ev",         CPU_POWERPC_604EV,                  604E),
 8765: #endif
 8766:     /* PowerPC 7xx family                                                    */
 8767:     /* Generic PowerPC 740 (G3)                                              */
 8768:     POWERPC_DEF("740",           CPU_POWERPC_7x0,                    740),
 8769:     /* Code name for PowerPC 740                                             */
 8770:     POWERPC_DEF("Arthur",        CPU_POWERPC_7x0,                    740),
 8771:     /* Generic PowerPC 750 (G3)                                              */
 8772:     POWERPC_DEF("750",           CPU_POWERPC_7x0,                    750),
 8773:     /* Code name for PowerPC 750                                             */
 8774:     POWERPC_DEF("Typhoon",       CPU_POWERPC_7x0,                    750),
 8775:     /* PowerPC 740/750 is also known as G3                                   */
 8776:     POWERPC_DEF("G3",            CPU_POWERPC_7x0,                    750),
 8777:     /* PowerPC 740 v1.0 (G3)                                                 */
 8778:     POWERPC_DEF("740_v1.0",      CPU_POWERPC_7x0_v10,                740),
 8779:     /* PowerPC 750 v1.0 (G3)                                                 */
 8780:     POWERPC_DEF("750_v1.0",      CPU_POWERPC_7x0_v10,                750),
 8781:     /* PowerPC 740 v2.0 (G3)                                                 */
 8782:     POWERPC_DEF("740_v2.0",      CPU_POWERPC_7x0_v20,                740),
 8783:     /* PowerPC 750 v2.0 (G3)                                                 */
 8784:     POWERPC_DEF("750_v2.0",      CPU_POWERPC_7x0_v20,                750),
 8785:     /* PowerPC 740 v2.1 (G3)                                                 */
 8786:     POWERPC_DEF("740_v2.1",      CPU_POWERPC_7x0_v21,                740),
 8787:     /* PowerPC 750 v2.1 (G3)                                                 */
 8788:     POWERPC_DEF("750_v2.1",      CPU_POWERPC_7x0_v21,                750),
 8789:     /* PowerPC 740 v2.2 (G3)                                                 */
 8790:     POWERPC_DEF("740_v2.2",      CPU_POWERPC_7x0_v22,                740),
 8791:     /* PowerPC 750 v2.2 (G3)                                                 */
 8792:     POWERPC_DEF("750_v2.2",      CPU_POWERPC_7x0_v22,                750),
 8793:     /* PowerPC 740 v3.0 (G3)                                                 */
 8794:     POWERPC_DEF("740_v3.0",      CPU_POWERPC_7x0_v30,                740),
 8795:     /* PowerPC 750 v3.0 (G3)                                                 */
 8796:     POWERPC_DEF("750_v3.0",      CPU_POWERPC_7x0_v30,                750),
 8797:     /* PowerPC 740 v3.1 (G3)                                                 */
 8798:     POWERPC_DEF("740_v3.1",      CPU_POWERPC_7x0_v31,                740),
 8799:     /* PowerPC 750 v3.1 (G3)                                                 */
 8800:     POWERPC_DEF("750_v3.1",      CPU_POWERPC_7x0_v31,                750),
 8801:     /* PowerPC 740E (G3)                                                     */
 8802:     POWERPC_DEF("740e",          CPU_POWERPC_740E,                   740),
 8803:     /* PowerPC 750E (G3)                                                     */
 8804:     POWERPC_DEF("750e",          CPU_POWERPC_750E,                   750),
 8805:     /* PowerPC 740P (G3)                                                     */
 8806:     POWERPC_DEF("740p",          CPU_POWERPC_7x0P,                   740),
 8807:     /* PowerPC 750P (G3)                                                     */
 8808:     POWERPC_DEF("750p",          CPU_POWERPC_7x0P,                   750),
 8809:     /* Code name for PowerPC 740P/750P (G3)                                  */
 8810:     POWERPC_DEF("Conan/Doyle",   CPU_POWERPC_7x0P,                   750),
 8811:     /* PowerPC 750CL (G3 embedded)                                           */
 8812:     POWERPC_DEF("750cl",         CPU_POWERPC_750CL,                  750cl),
 8813:     /* PowerPC 750CL v1.0                                                    */
 8814:     POWERPC_DEF("750cl_v1.0",    CPU_POWERPC_750CL_v10,              750cl),
 8815:     /* PowerPC 750CL v2.0                                                    */
 8816:     POWERPC_DEF("750cl_v2.0",    CPU_POWERPC_750CL_v20,              750cl),
 8817:     /* PowerPC 750CX (G3 embedded)                                           */
 8818:     POWERPC_DEF("750cx",         CPU_POWERPC_750CX,                  750cx),
 8819:     /* PowerPC 750CX v1.0 (G3 embedded)                                      */
 8820:     POWERPC_DEF("750cx_v1.0",    CPU_POWERPC_750CX_v10,              750cx),
 8821:     /* PowerPC 750CX v2.1 (G3 embedded)                                      */
 8822:     POWERPC_DEF("750cx_v2.0",    CPU_POWERPC_750CX_v20,              750cx),
 8823:     /* PowerPC 750CX v2.1 (G3 embedded)                                      */
 8824:     POWERPC_DEF("750cx_v2.1",    CPU_POWERPC_750CX_v21,              750cx),
 8825:     /* PowerPC 750CX v2.2 (G3 embedded)                                      */
 8826:     POWERPC_DEF("750cx_v2.2",    CPU_POWERPC_750CX_v22,              750cx),
 8827:     /* PowerPC 750CXe (G3 embedded)                                          */
 8828:     POWERPC_DEF("750cxe",        CPU_POWERPC_750CXE,                 750cx),
 8829:     /* PowerPC 750CXe v2.1 (G3 embedded)                                     */
 8830:     POWERPC_DEF("750cxe_v2.1",   CPU_POWERPC_750CXE_v21,             750cx),
 8831:     /* PowerPC 750CXe v2.2 (G3 embedded)                                     */
 8832:     POWERPC_DEF("750cxe_v2.2",   CPU_POWERPC_750CXE_v22,             750cx),
 8833:     /* PowerPC 750CXe v2.3 (G3 embedded)                                     */
 8834:     POWERPC_DEF("750cxe_v2.3",   CPU_POWERPC_750CXE_v23,             750cx),
 8835:     /* PowerPC 750CXe v2.4 (G3 embedded)                                     */
 8836:     POWERPC_DEF("750cxe_v2.4",   CPU_POWERPC_750CXE_v24,             750cx),
 8837:     /* PowerPC 750CXe v2.4b (G3 embedded)                                    */
 8838:     POWERPC_DEF("750cxe_v2.4b",  CPU_POWERPC_750CXE_v24b,            750cx),
 8839:     /* PowerPC 750CXe v3.0 (G3 embedded)                                     */
 8840:     POWERPC_DEF("750cxe_v3.0",   CPU_POWERPC_750CXE_v30,             750cx),
 8841:     /* PowerPC 750CXe v3.1 (G3 embedded)                                     */
 8842:     POWERPC_DEF("750cxe_v3.1",   CPU_POWERPC_750CXE_v31,             750cx),
 8843:     /* PowerPC 750CXe v3.1b (G3 embedded)                                    */
 8844:     POWERPC_DEF("750cxe_v3.1b",  CPU_POWERPC_750CXE_v31b,            750cx),
 8845:     /* PowerPC 750CXr (G3 embedded)                                          */
 8846:     POWERPC_DEF("750cxr",        CPU_POWERPC_750CXR,                 750cx),
 8847:     /* PowerPC 750FL (G3 embedded)                                           */
 8848:     POWERPC_DEF("750fl",         CPU_POWERPC_750FL,                  750fx),
 8849:     /* PowerPC 750FX (G3 embedded)                                           */
 8850:     POWERPC_DEF("750fx",         CPU_POWERPC_750FX,                  750fx),
 8851:     /* PowerPC 750FX v1.0 (G3 embedded)                                      */
 8852:     POWERPC_DEF("750fx_v1.0",    CPU_POWERPC_750FX_v10,              750fx),
 8853:     /* PowerPC 750FX v2.0 (G3 embedded)                                      */
 8854:     POWERPC_DEF("750fx_v2.0",    CPU_POWERPC_750FX_v20,              750fx),
 8855:     /* PowerPC 750FX v2.1 (G3 embedded)                                      */
 8856:     POWERPC_DEF("750fx_v2.1",    CPU_POWERPC_750FX_v21,              750fx),
 8857:     /* PowerPC 750FX v2.2 (G3 embedded)                                      */
 8858:     POWERPC_DEF("750fx_v2.2",    CPU_POWERPC_750FX_v22,              750fx),
 8859:     /* PowerPC 750FX v2.3 (G3 embedded)                                      */
 8860:     POWERPC_DEF("750fx_v2.3",    CPU_POWERPC_750FX_v23,              750fx),
 8861:     /* PowerPC 750GL (G3 embedded)                                           */
 8862:     POWERPC_DEF("750gl",         CPU_POWERPC_750GL,                  750gx),
 8863:     /* PowerPC 750GX (G3 embedded)                                           */
 8864:     POWERPC_DEF("750gx",         CPU_POWERPC_750GX,                  750gx),
 8865:     /* PowerPC 750GX v1.0 (G3 embedded)                                      */
 8866:     POWERPC_DEF("750gx_v1.0",    CPU_POWERPC_750GX_v10,              750gx),
 8867:     /* PowerPC 750GX v1.1 (G3 embedded)                                      */
 8868:     POWERPC_DEF("750gx_v1.1",    CPU_POWERPC_750GX_v11,              750gx),
 8869:     /* PowerPC 750GX v1.2 (G3 embedded)                                      */
 8870:     POWERPC_DEF("750gx_v1.2",    CPU_POWERPC_750GX_v12,              750gx),
 8871:     /* PowerPC 750L (G3 embedded)                                            */
 8872:     POWERPC_DEF("750l",          CPU_POWERPC_750L,                   750),
 8873:     /* Code name for PowerPC 750L (G3 embedded)                              */
 8874:     POWERPC_DEF("LoneStar",      CPU_POWERPC_750L,                   750),
 8875:     /* PowerPC 750L v2.0 (G3 embedded)                                       */
 8876:     POWERPC_DEF("750l_v2.0",     CPU_POWERPC_750L_v20,               750),
 8877:     /* PowerPC 750L v2.1 (G3 embedded)                                       */
 8878:     POWERPC_DEF("750l_v2.1",     CPU_POWERPC_750L_v21,               750),
 8879:     /* PowerPC 750L v2.2 (G3 embedded)                                       */
 8880:     POWERPC_DEF("750l_v2.2",     CPU_POWERPC_750L_v22,               750),
 8881:     /* PowerPC 750L v3.0 (G3 embedded)                                       */
 8882:     POWERPC_DEF("750l_v3.0",     CPU_POWERPC_750L_v30,               750),
 8883:     /* PowerPC 750L v3.2 (G3 embedded)                                       */
 8884:     POWERPC_DEF("750l_v3.2",     CPU_POWERPC_750L_v32,               750),
 8885:     /* Generic PowerPC 745                                                   */
 8886:     POWERPC_DEF("745",           CPU_POWERPC_7x5,                    745),
 8887:     /* Generic PowerPC 755                                                   */
 8888:     POWERPC_DEF("755",           CPU_POWERPC_7x5,                    755),
 8889:     /* Code name for PowerPC 745/755                                         */
 8890:     POWERPC_DEF("Goldfinger",    CPU_POWERPC_7x5,                    755),
 8891:     /* PowerPC 745 v1.0                                                      */
 8892:     POWERPC_DEF("745_v1.0",      CPU_POWERPC_7x5_v10,                745),
 8893:     /* PowerPC 755 v1.0                                                      */
 8894:     POWERPC_DEF("755_v1.0",      CPU_POWERPC_7x5_v10,                755),
 8895:     /* PowerPC 745 v1.1                                                      */
 8896:     POWERPC_DEF("745_v1.1",      CPU_POWERPC_7x5_v11,                745),
 8897:     /* PowerPC 755 v1.1                                                      */
 8898:     POWERPC_DEF("755_v1.1",      CPU_POWERPC_7x5_v11,                755),
 8899:     /* PowerPC 745 v2.0                                                      */
 8900:     POWERPC_DEF("745_v2.0",      CPU_POWERPC_7x5_v20,                745),
 8901:     /* PowerPC 755 v2.0                                                      */
 8902:     POWERPC_DEF("755_v2.0",      CPU_POWERPC_7x5_v20,                755),
 8903:     /* PowerPC 745 v2.1                                                      */
 8904:     POWERPC_DEF("745_v2.1",      CPU_POWERPC_7x5_v21,                745),
 8905:     /* PowerPC 755 v2.1                                                      */
 8906:     POWERPC_DEF("755_v2.1",      CPU_POWERPC_7x5_v21,                755),
 8907:     /* PowerPC 745 v2.2                                                      */
 8908:     POWERPC_DEF("745_v2.2",      CPU_POWERPC_7x5_v22,                745),
 8909:     /* PowerPC 755 v2.2                                                      */
 8910:     POWERPC_DEF("755_v2.2",      CPU_POWERPC_7x5_v22,                755),
 8911:     /* PowerPC 745 v2.3                                                      */
 8912:     POWERPC_DEF("745_v2.3",      CPU_POWERPC_7x5_v23,                745),
 8913:     /* PowerPC 755 v2.3                                                      */
 8914:     POWERPC_DEF("755_v2.3",      CPU_POWERPC_7x5_v23,                755),
 8915:     /* PowerPC 745 v2.4                                                      */
 8916:     POWERPC_DEF("745_v2.4",      CPU_POWERPC_7x5_v24,                745),
 8917:     /* PowerPC 755 v2.4                                                      */
 8918:     POWERPC_DEF("755_v2.4",      CPU_POWERPC_7x5_v24,                755),
 8919:     /* PowerPC 745 v2.5                                                      */
 8920:     POWERPC_DEF("745_v2.5",      CPU_POWERPC_7x5_v25,                745),
 8921:     /* PowerPC 755 v2.5                                                      */
 8922:     POWERPC_DEF("755_v2.5",      CPU_POWERPC_7x5_v25,                755),
 8923:     /* PowerPC 745 v2.6                                                      */
 8924:     POWERPC_DEF("745_v2.6",      CPU_POWERPC_7x5_v26,                745),
 8925:     /* PowerPC 755 v2.6                                                      */
 8926:     POWERPC_DEF("755_v2.6",      CPU_POWERPC_7x5_v26,                755),
 8927:     /* PowerPC 745 v2.7                                                      */
 8928:     POWERPC_DEF("745_v2.7",      CPU_POWERPC_7x5_v27,                745),
 8929:     /* PowerPC 755 v2.7                                                      */
 8930:     POWERPC_DEF("755_v2.7",      CPU_POWERPC_7x5_v27,                755),
 8931:     /* PowerPC 745 v2.8                                                      */
 8932:     POWERPC_DEF("745_v2.8",      CPU_POWERPC_7x5_v28,                745),
 8933:     /* PowerPC 755 v2.8                                                      */
 8934:     POWERPC_DEF("755_v2.8",      CPU_POWERPC_7x5_v28,                755),
 8935: #if defined (TODO)
 8936:     /* PowerPC 745P (G3)                                                     */
 8937:     POWERPC_DEF("745p",          CPU_POWERPC_7x5P,                   745),
 8938:     /* PowerPC 755P (G3)                                                     */
 8939:     POWERPC_DEF("755p",          CPU_POWERPC_7x5P,                   755),
 8940: #endif
 8941:     /* PowerPC 74xx family                                                   */
 8942:     /* PowerPC 7400 (G4)                                                     */
 8943:     POWERPC_DEF("7400",          CPU_POWERPC_7400,                   7400),
 8944:     /* Code name for PowerPC 7400                                            */
 8945:     POWERPC_DEF("Max",           CPU_POWERPC_7400,                   7400),
 8946:     /* PowerPC 74xx is also well known as G4                                 */
 8947:     POWERPC_DEF("G4",            CPU_POWERPC_7400,                   7400),
 8948:     /* PowerPC 7400 v1.0 (G4)                                                */
 8949:     POWERPC_DEF("7400_v1.0",     CPU_POWERPC_7400_v10,               7400),
 8950:     /* PowerPC 7400 v1.1 (G4)                                                */
 8951:     POWERPC_DEF("7400_v1.1",     CPU_POWERPC_7400_v11,               7400),
 8952:     /* PowerPC 7400 v2.0 (G4)                                                */
 8953:     POWERPC_DEF("7400_v2.0",     CPU_POWERPC_7400_v20,               7400),
 8954:     /* PowerPC 7400 v2.1 (G4)                                                */
 8955:     POWERPC_DEF("7400_v2.1",     CPU_POWERPC_7400_v21,               7400),
 8956:     /* PowerPC 7400 v2.2 (G4)                                                */
 8957:     POWERPC_DEF("7400_v2.2",     CPU_POWERPC_7400_v22,               7400),
 8958:     /* PowerPC 7400 v2.6 (G4)                                                */
 8959:     POWERPC_DEF("7400_v2.6",     CPU_POWERPC_7400_v26,               7400),
 8960:     /* PowerPC 7400 v2.7 (G4)                                                */
 8961:     POWERPC_DEF("7400_v2.7",     CPU_POWERPC_7400_v27,               7400),
 8962:     /* PowerPC 7400 v2.8 (G4)                                                */
 8963:     POWERPC_DEF("7400_v2.8",     CPU_POWERPC_7400_v28,               7400),
 8964:     /* PowerPC 7400 v2.9 (G4)                                                */
 8965:     POWERPC_DEF("7400_v2.9",     CPU_POWERPC_7400_v29,               7400),
 8966:     /* PowerPC 7410 (G4)                                                     */
 8967:     POWERPC_DEF("7410",          CPU_POWERPC_7410,                   7410),
 8968:     /* Code name for PowerPC 7410                                            */
 8969:     POWERPC_DEF("Nitro",         CPU_POWERPC_7410,                   7410),
 8970:     /* PowerPC 7410 v1.0 (G4)                                                */
 8971:     POWERPC_DEF("7410_v1.0",     CPU_POWERPC_7410_v10,               7410),
 8972:     /* PowerPC 7410 v1.1 (G4)                                                */
 8973:     POWERPC_DEF("7410_v1.1",     CPU_POWERPC_7410_v11,               7410),
 8974:     /* PowerPC 7410 v1.2 (G4)                                                */
 8975:     POWERPC_DEF("7410_v1.2",     CPU_POWERPC_7410_v12,               7410),
 8976:     /* PowerPC 7410 v1.3 (G4)                                                */
 8977:     POWERPC_DEF("7410_v1.3",     CPU_POWERPC_7410_v13,               7410),
 8978:     /* PowerPC 7410 v1.4 (G4)                                                */
 8979:     POWERPC_DEF("7410_v1.4",     CPU_POWERPC_7410_v14,               7410),
 8980:     /* PowerPC 7448 (G4)                                                     */
 8981:     POWERPC_DEF("7448",          CPU_POWERPC_7448,                   7400),
 8982:     /* PowerPC 7448 v1.0 (G4)                                                */
 8983:     POWERPC_DEF("7448_v1.0",     CPU_POWERPC_7448_v10,               7400),
 8984:     /* PowerPC 7448 v1.1 (G4)                                                */
 8985:     POWERPC_DEF("7448_v1.1",     CPU_POWERPC_7448_v11,               7400),
 8986:     /* PowerPC 7448 v2.0 (G4)                                                */
 8987:     POWERPC_DEF("7448_v2.0",     CPU_POWERPC_7448_v20,               7400),
 8988:     /* PowerPC 7448 v2.1 (G4)                                                */
 8989:     POWERPC_DEF("7448_v2.1",     CPU_POWERPC_7448_v21,               7400),
 8990:     /* PowerPC 7450 (G4)                                                     */
 8991:     POWERPC_DEF("7450",          CPU_POWERPC_7450,                   7450),
 8992:     /* Code name for PowerPC 7450                                            */
 8993:     POWERPC_DEF("Vger",          CPU_POWERPC_7450,                   7450),
 8994:     /* PowerPC 7450 v1.0 (G4)                                                */
 8995:     POWERPC_DEF("7450_v1.0",     CPU_POWERPC_7450_v10,               7450),
 8996:     /* PowerPC 7450 v1.1 (G4)                                                */
 8997:     POWERPC_DEF("7450_v1.1",     CPU_POWERPC_7450_v11,               7450),
 8998:     /* PowerPC 7450 v1.2 (G4)                                                */
 8999:     POWERPC_DEF("7450_v1.2",     CPU_POWERPC_7450_v12,               7450),
 9000:     /* PowerPC 7450 v2.0 (G4)                                                */
 9001:     POWERPC_DEF("7450_v2.0",     CPU_POWERPC_7450_v20,               7450),
 9002:     /* PowerPC 7450 v2.1 (G4)                                                */
 9003:     POWERPC_DEF("7450_v2.1",     CPU_POWERPC_7450_v21,               7450),
 9004:     /* PowerPC 7441 (G4)                                                     */
 9005:     POWERPC_DEF("7441",          CPU_POWERPC_74x1,                   7440),
 9006:     /* PowerPC 7451 (G4)                                                     */
 9007:     POWERPC_DEF("7451",          CPU_POWERPC_74x1,                   7450),
 9008:     /* PowerPC 7441 v2.1 (G4)                                                */
 9009:     POWERPC_DEF("7441_v2.1",     CPU_POWERPC_7450_v21,               7440),
 9010:     /* PowerPC 7441 v2.3 (G4)                                                */
 9011:     POWERPC_DEF("7441_v2.3",     CPU_POWERPC_74x1_v23,               7440),
 9012:     /* PowerPC 7451 v2.3 (G4)                                                */
 9013:     POWERPC_DEF("7451_v2.3",     CPU_POWERPC_74x1_v23,               7450),
 9014:     /* PowerPC 7441 v2.10 (G4)                                                */
 9015:     POWERPC_DEF("7441_v2.10",    CPU_POWERPC_74x1_v210,              7440),
 9016:     /* PowerPC 7451 v2.10 (G4)                                               */
 9017:     POWERPC_DEF("7451_v2.10",    CPU_POWERPC_74x1_v210,              7450),
 9018:     /* PowerPC 7445 (G4)                                                     */
 9019:     POWERPC_DEF("7445",          CPU_POWERPC_74x5,                   7445),
 9020:     /* PowerPC 7455 (G4)                                                     */
 9021:     POWERPC_DEF("7455",          CPU_POWERPC_74x5,                   7455),
 9022:     /* Code name for PowerPC 7445/7455                                       */
 9023:     POWERPC_DEF("Apollo6",       CPU_POWERPC_74x5,                   7455),
 9024:     /* PowerPC 7445 v1.0 (G4)                                                */
 9025:     POWERPC_DEF("7445_v1.0",     CPU_POWERPC_74x5_v10,               7445),
 9026:     /* PowerPC 7455 v1.0 (G4)                                                */
 9027:     POWERPC_DEF("7455_v1.0",     CPU_POWERPC_74x5_v10,               7455),
 9028:     /* PowerPC 7445 v2.1 (G4)                                                */
 9029:     POWERPC_DEF("7445_v2.1",     CPU_POWERPC_74x5_v21,               7445),
 9030:     /* PowerPC 7455 v2.1 (G4)                                                */
 9031:     POWERPC_DEF("7455_v2.1",     CPU_POWERPC_74x5_v21,               7455),
 9032:     /* PowerPC 7445 v3.2 (G4)                                                */
 9033:     POWERPC_DEF("7445_v3.2",     CPU_POWERPC_74x5_v32,               7445),
 9034:     /* PowerPC 7455 v3.2 (G4)                                                */
 9035:     POWERPC_DEF("7455_v3.2",     CPU_POWERPC_74x5_v32,               7455),
 9036:     /* PowerPC 7445 v3.3 (G4)                                                */
 9037:     POWERPC_DEF("7445_v3.3",     CPU_POWERPC_74x5_v33,               7445),
 9038:     /* PowerPC 7455 v3.3 (G4)                                                */
 9039:     POWERPC_DEF("7455_v3.3",     CPU_POWERPC_74x5_v33,               7455),
 9040:     /* PowerPC 7445 v3.4 (G4)                                                */
 9041:     POWERPC_DEF("7445_v3.4",     CPU_POWERPC_74x5_v34,               7445),
 9042:     /* PowerPC 7455 v3.4 (G4)                                                */
 9043:     POWERPC_DEF("7455_v3.4",     CPU_POWERPC_74x5_v34,               7455),
 9044:     /* PowerPC 7447 (G4)                                                     */
 9045:     POWERPC_DEF("7447",          CPU_POWERPC_74x7,                   7445),
 9046:     /* PowerPC 7457 (G4)                                                     */
 9047:     POWERPC_DEF("7457",          CPU_POWERPC_74x7,                   7455),
 9048:     /* Code name for PowerPC 7447/7457                                       */
 9049:     POWERPC_DEF("Apollo7",       CPU_POWERPC_74x7,                   7455),
 9050:     /* PowerPC 7447 v1.0 (G4)                                                */
 9051:     POWERPC_DEF("7447_v1.0",     CPU_POWERPC_74x7_v10,               7445),
 9052:     /* PowerPC 7457 v1.0 (G4)                                                */
 9053:     POWERPC_DEF("7457_v1.0",     CPU_POWERPC_74x7_v10,               7455),
 9054:     /* PowerPC 7447 v1.1 (G4)                                                */
 9055:     POWERPC_DEF("7447_v1.1",     CPU_POWERPC_74x7_v11,               7445),
 9056:     /* PowerPC 7457 v1.1 (G4)                                                */
 9057:     POWERPC_DEF("7457_v1.1",     CPU_POWERPC_74x7_v11,               7455),
 9058:     /* PowerPC 7457 v1.2 (G4)                                                */
 9059:     POWERPC_DEF("7457_v1.2",     CPU_POWERPC_74x7_v12,               7455),
 9060:     /* PowerPC 7447A (G4)                                                    */
 9061:     POWERPC_DEF("7447A",         CPU_POWERPC_74x7A,                  7445),
 9062:     /* PowerPC 7457A (G4)                                                    */
 9063:     POWERPC_DEF("7457A",         CPU_POWERPC_74x7A,                  7455),
 9064:     /* PowerPC 7447A v1.0 (G4)                                               */
 9065:     POWERPC_DEF("7447A_v1.0",    CPU_POWERPC_74x7A_v10,              7445),
 9066:     /* PowerPC 7457A v1.0 (G4)                                               */
 9067:     POWERPC_DEF("7457A_v1.0",    CPU_POWERPC_74x7A_v10,              7455),
 9068:     /* Code name for PowerPC 7447A/7457A                                     */
 9069:     POWERPC_DEF("Apollo7PM",     CPU_POWERPC_74x7A_v10,              7455),
 9070:     /* PowerPC 7447A v1.1 (G4)                                               */
 9071:     POWERPC_DEF("7447A_v1.1",    CPU_POWERPC_74x7A_v11,              7445),
 9072:     /* PowerPC 7457A v1.1 (G4)                                               */
 9073:     POWERPC_DEF("7457A_v1.1",    CPU_POWERPC_74x7A_v11,              7455),
 9074:     /* PowerPC 7447A v1.2 (G4)                                               */
 9075:     POWERPC_DEF("7447A_v1.2",    CPU_POWERPC_74x7A_v12,              7445),
 9076:     /* PowerPC 7457A v1.2 (G4)                                               */
 9077:     POWERPC_DEF("7457A_v1.2",    CPU_POWERPC_74x7A_v12,              7455),
 9078:     /* 64 bits PowerPC                                                       */
 9079: #if defined (TARGET_PPC64)
 9080:     /* PowerPC 620                                                           */
 9081:     POWERPC_DEF("620",           CPU_POWERPC_620,                    620),
 9082:     /* Code name for PowerPC 620                                             */
 9083:     POWERPC_DEF("Trident",       CPU_POWERPC_620,                    620),
 9084: #if defined (TODO)
 9085:     /* PowerPC 630 (POWER3)                                                  */
 9086:     POWERPC_DEF("630",           CPU_POWERPC_630,                    630),
 9087:     POWERPC_DEF("POWER3",        CPU_POWERPC_630,                    630),
 9088:     /* Code names for POWER3                                                 */
 9089:     POWERPC_DEF("Boxer",         CPU_POWERPC_630,                    630),
 9090:     POWERPC_DEF("Dino",          CPU_POWERPC_630,                    630),
 9091: #endif
 9092: #if defined (TODO)
 9093:     /* PowerPC 631 (Power 3+)                                                */
 9094:     POWERPC_DEF("631",           CPU_POWERPC_631,                    631),
 9095:     POWERPC_DEF("POWER3+",       CPU_POWERPC_631,                    631),
 9096: #endif
 9097: #if defined (TODO)
 9098:     /* POWER4                                                                */
 9099:     POWERPC_DEF("POWER4",        CPU_POWERPC_POWER4,                 POWER4),
 9100: #endif
 9101: #if defined (TODO)
 9102:     /* POWER4p                                                               */
 9103:     POWERPC_DEF("POWER4+",       CPU_POWERPC_POWER4P,                POWER4P),
 9104: #endif
 9105: #if defined (TODO)
 9106:     /* POWER5                                                                */
 9107:     POWERPC_DEF("POWER5",        CPU_POWERPC_POWER5,                 POWER5),
 9108:     /* POWER5GR                                                              */
 9109:     POWERPC_DEF("POWER5gr",      CPU_POWERPC_POWER5GR,               POWER5),
 9110: #endif
 9111: #if defined (TODO)
 9112:     /* POWER5+                                                               */
 9113:     POWERPC_DEF("POWER5+",       CPU_POWERPC_POWER5P,                POWER5P),
 9114:     /* POWER5GS                                                              */
 9115:     POWERPC_DEF("POWER5gs",      CPU_POWERPC_POWER5GS,               POWER5P),
 9116: #endif
 9117: #if defined (TODO)
 9118:     /* POWER6                                                                */
 9119:     POWERPC_DEF("POWER6",        CPU_POWERPC_POWER6,                 POWER6),
 9120:     /* POWER6 running in POWER5 mode                                         */
 9121:     POWERPC_DEF("POWER6_5",      CPU_POWERPC_POWER6_5,               POWER5),
 9122:     /* POWER6A                                                               */
 9123:     POWERPC_DEF("POWER6A",       CPU_POWERPC_POWER6A,                POWER6),
 9124: #endif
 9125:     /* POWER7                                                                */
 9126:     POWERPC_DEF("POWER7",        CPU_POWERPC_POWER7,                 POWER7),
 9127:     POWERPC_DEF("POWER7_v2.0",   CPU_POWERPC_POWER7_v20,             POWER7),
 9128:     POWERPC_DEF("POWER7_v2.1",   CPU_POWERPC_POWER7_v21,             POWER7),
 9129:     POWERPC_DEF("POWER7_v2.3",   CPU_POWERPC_POWER7_v23,             POWER7),
 9130:     /* PowerPC 970                                                           */
 9131:     POWERPC_DEF("970",           CPU_POWERPC_970,                    970),
 9132:     /* PowerPC 970FX (G5)                                                    */
 9133:     POWERPC_DEF("970fx",         CPU_POWERPC_970FX,                  970FX),
 9134:     /* PowerPC 970FX v1.0 (G5)                                               */
 9135:     POWERPC_DEF("970fx_v1.0",    CPU_POWERPC_970FX_v10,              970FX),
 9136:     /* PowerPC 970FX v2.0 (G5)                                               */
 9137:     POWERPC_DEF("970fx_v2.0",    CPU_POWERPC_970FX_v20,              970FX),
 9138:     /* PowerPC 970FX v2.1 (G5)                                               */
 9139:     POWERPC_DEF("970fx_v2.1",    CPU_POWERPC_970FX_v21,              970FX),
 9140:     /* PowerPC 970FX v3.0 (G5)                                               */
 9141:     POWERPC_DEF("970fx_v3.0",    CPU_POWERPC_970FX_v30,              970FX),
 9142:     /* PowerPC 970FX v3.1 (G5)                                               */
 9143:     POWERPC_DEF("970fx_v3.1",    CPU_POWERPC_970FX_v31,              970FX),
 9144:     /* PowerPC 970GX (G5)                                                    */
 9145:     POWERPC_DEF("970gx",         CPU_POWERPC_970GX,                  970GX),
 9146:     /* PowerPC 970MP                                                         */
 9147:     POWERPC_DEF("970mp",         CPU_POWERPC_970MP,                  970MP),
 9148:     /* PowerPC 970MP v1.0                                                    */
 9149:     POWERPC_DEF("970mp_v1.0",    CPU_POWERPC_970MP_v10,              970MP),
 9150:     /* PowerPC 970MP v1.1                                                    */
 9151:     POWERPC_DEF("970mp_v1.1",    CPU_POWERPC_970MP_v11,              970MP),
 9152: #if defined (TODO)
 9153:     /* PowerPC Cell                                                          */
 9154:     POWERPC_DEF("Cell",          CPU_POWERPC_CELL,                   970),
 9155: #endif
 9156: #if defined (TODO)
 9157:     /* PowerPC Cell v1.0                                                     */
 9158:     POWERPC_DEF("Cell_v1.0",     CPU_POWERPC_CELL_v10,               970),
 9159: #endif
 9160: #if defined (TODO)
 9161:     /* PowerPC Cell v2.0                                                     */
 9162:     POWERPC_DEF("Cell_v2.0",     CPU_POWERPC_CELL_v20,               970),
 9163: #endif
 9164: #if defined (TODO)
 9165:     /* PowerPC Cell v3.0                                                     */
 9166:     POWERPC_DEF("Cell_v3.0",     CPU_POWERPC_CELL_v30,               970),
 9167: #endif
 9168: #if defined (TODO)
 9169:     /* PowerPC Cell v3.1                                                     */
 9170:     POWERPC_DEF("Cell_v3.1",     CPU_POWERPC_CELL_v31,               970),
 9171: #endif
 9172: #if defined (TODO)
 9173:     /* PowerPC Cell v3.2                                                     */
 9174:     POWERPC_DEF("Cell_v3.2",     CPU_POWERPC_CELL_v32,               970),
 9175: #endif
 9176: #if defined (TODO)
 9177:     /* RS64 (Apache/A35)                                                     */
 9178:     /* This one seems to support the whole POWER2 instruction set
 9179:      * and the PowerPC 64 one.
 9180:      */
 9181:     /* What about A10 & A30 ? */
 9182:     POWERPC_DEF("RS64",          CPU_POWERPC_RS64,                   RS64),
 9183:     POWERPC_DEF("Apache",        CPU_POWERPC_RS64,                   RS64),
 9184:     POWERPC_DEF("A35",           CPU_POWERPC_RS64,                   RS64),
 9185: #endif
 9186: #if defined (TODO)
 9187:     /* RS64-II (NorthStar/A50)                                               */
 9188:     POWERPC_DEF("RS64-II",       CPU_POWERPC_RS64II,                 RS64),
 9189:     POWERPC_DEF("NorthStar",     CPU_POWERPC_RS64II,                 RS64),
 9190:     POWERPC_DEF("A50",           CPU_POWERPC_RS64II,                 RS64),
 9191: #endif
 9192: #if defined (TODO)
 9193:     /* RS64-III (Pulsar)                                                     */
 9194:     POWERPC_DEF("RS64-III",      CPU_POWERPC_RS64III,                RS64),
 9195:     POWERPC_DEF("Pulsar",        CPU_POWERPC_RS64III,                RS64),
 9196: #endif
 9197: #if defined (TODO)
 9198:     /* RS64-IV (IceStar/IStar/SStar)                                         */
 9199:     POWERPC_DEF("RS64-IV",       CPU_POWERPC_RS64IV,                 RS64),
 9200:     POWERPC_DEF("IceStar",       CPU_POWERPC_RS64IV,                 RS64),
 9201:     POWERPC_DEF("IStar",         CPU_POWERPC_RS64IV,                 RS64),
 9202:     POWERPC_DEF("SStar",         CPU_POWERPC_RS64IV,                 RS64),
 9203: #endif
 9204: #endif /* defined (TARGET_PPC64) */
 9205:     /* POWER                                                                 */
 9206: #if defined (TODO)
 9207:     /* Original POWER                                                        */
 9208:     POWERPC_DEF("POWER",         CPU_POWERPC_POWER,                  POWER),
 9209:     POWERPC_DEF("RIOS",          CPU_POWERPC_POWER,                  POWER),
 9210:     POWERPC_DEF("RSC",           CPU_POWERPC_POWER,                  POWER),
 9211:     POWERPC_DEF("RSC3308",       CPU_POWERPC_POWER,                  POWER),
 9212:     POWERPC_DEF("RSC4608",       CPU_POWERPC_POWER,                  POWER),
 9213: #endif
 9214: #if defined (TODO)
 9215:     /* POWER2                                                                */
 9216:     POWERPC_DEF("POWER2",        CPU_POWERPC_POWER2,                 POWER),
 9217:     POWERPC_DEF("RSC2",          CPU_POWERPC_POWER2,                 POWER),
 9218:     POWERPC_DEF("P2SC",          CPU_POWERPC_POWER2,                 POWER),
 9219: #endif
 9220:     /* PA semi cores                                                         */
 9221: #if defined (TODO)
 9222:     /* PA PA6T */
 9223:     POWERPC_DEF("PA6T",          CPU_POWERPC_PA6T,                   PA6T),
 9224: #endif
 9225:     /* Generic PowerPCs                                                      */
 9226: #if defined (TARGET_PPC64)
 9227:     POWERPC_DEF("ppc64",         CPU_POWERPC_PPC64,                  PPC64),
 9228: #endif
 9229:     POWERPC_DEF("ppc32",         CPU_POWERPC_PPC32,                  PPC32),
 9230:     POWERPC_DEF("ppc",           CPU_POWERPC_DEFAULT,                DEFAULT),
 9231:     /* Fallback                                                              */
 9232:     POWERPC_DEF("default",       CPU_POWERPC_DEFAULT,                DEFAULT),
 9233: };
 9234: 
 9235: /*****************************************************************************/
 9236: /* Generic CPU instantiation routine                                         */
 9237: static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
 9238: {
 9239: #if !defined(CONFIG_USER_ONLY)
 9240:     int i;
 9241: 
 9242:     env->irq_inputs = NULL;
 9243:     /* Set all exception vectors to an invalid address */
 9244:     for (i = 0; i < POWERPC_EXCP_NB; i++)
 9245:         env->excp_vectors[i] = (target_ulong)(-1ULL);
 9246:     env->hreset_excp_prefix = 0x00000000;
 9247:     env->ivor_mask = 0x00000000;
 9248:     env->ivpr_mask = 0x00000000;
 9249:     /* Default MMU definitions */
 9250:     env->nb_BATs = 0;
 9251:     env->nb_tlb = 0;
 9252:     env->nb_ways = 0;
 9253:     env->tlb_type = TLB_NONE;
 9254: #endif
 9255:     /* Register SPR common to all PowerPC implementations */
 9256:     gen_spr_generic(env);
 9257:     spr_register(env, SPR_PVR, "PVR",
 9258:                  /* Linux permits userspace to read PVR */
 9259: #if defined(CONFIG_LINUX_USER)
 9260:                  &spr_read_generic,
 9261: #else
 9262:                  SPR_NOACCESS,
 9263: #endif
 9264:                  SPR_NOACCESS,
 9265:                  &spr_read_generic, SPR_NOACCESS,
 9266:                  def->pvr);
 9267:     /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
 9268:     if (def->svr != POWERPC_SVR_NONE) {
 9269:         if (def->svr & POWERPC_SVR_E500) {
 9270:             spr_register(env, SPR_E500_SVR, "SVR",
 9271:                          SPR_NOACCESS, SPR_NOACCESS,
 9272:                          &spr_read_generic, SPR_NOACCESS,
 9273:                          def->svr & ~POWERPC_SVR_E500);
 9274:         } else {
 9275:             spr_register(env, SPR_SVR, "SVR",
 9276:                          SPR_NOACCESS, SPR_NOACCESS,
 9277:                          &spr_read_generic, SPR_NOACCESS,
 9278:                          def->svr);
 9279:         }
 9280:     }
 9281:     /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
 9282:     (*def->init_proc)(env);
 9283: #if !defined(CONFIG_USER_ONLY)
 9284:     env->excp_prefix = env->hreset_excp_prefix;
 9285: #endif
 9286:     /* MSR bits & flags consistency checks */
 9287:     if (env->msr_mask & (1 << 25)) {
 9288:         switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
 9289:         case POWERPC_FLAG_SPE:
 9290:         case POWERPC_FLAG_VRE:
 9291:             break;
 9292:         default:
 9293:             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
 9294:                     "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
 9295:             exit(1);
 9296:         }
 9297:     } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
 9298:         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
 9299:                 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
 9300:         exit(1);
 9301:     }
 9302:     if (env->msr_mask & (1 << 17)) {
 9303:         switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
 9304:         case POWERPC_FLAG_TGPR:
 9305:         case POWERPC_FLAG_CE:
 9306:             break;
 9307:         default:
 9308:             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
 9309:                     "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
 9310:             exit(1);
 9311:         }
 9312:     } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
 9313:         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
 9314:                 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
 9315:         exit(1);
 9316:     }
 9317:     if (env->msr_mask & (1 << 10)) {
 9318:         switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
 9319:                               POWERPC_FLAG_UBLE)) {
 9320:         case POWERPC_FLAG_SE:
 9321:         case POWERPC_FLAG_DWE:
 9322:         case POWERPC_FLAG_UBLE:
 9323:             break;
 9324:         default:
 9325:             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
 9326:                     "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
 9327:                     "POWERPC_FLAG_UBLE\n");
 9328:             exit(1);
 9329:         }
 9330:     } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
 9331:                              POWERPC_FLAG_UBLE)) {
 9332:         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
 9333:                 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
 9334:                 "POWERPC_FLAG_UBLE\n");
 9335:             exit(1);
 9336:     }
 9337:     if (env->msr_mask & (1 << 9)) {
 9338:         switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
 9339:         case POWERPC_FLAG_BE:
 9340:         case POWERPC_FLAG_DE:
 9341:             break;
 9342:         default:
 9343:             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
 9344:                     "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
 9345:             exit(1);
 9346:         }
 9347:     } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
 9348:         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
 9349:                 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
 9350:         exit(1);
 9351:     }
 9352:     if (env->msr_mask & (1 << 2)) {
 9353:         switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
 9354:         case POWERPC_FLAG_PX:
 9355:         case POWERPC_FLAG_PMM:
 9356:             break;
 9357:         default:
 9358:             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
 9359:                     "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
 9360:             exit(1);
 9361:         }
 9362:     } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
 9363:         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
 9364:                 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
 9365:         exit(1);
 9366:     }
 9367:     if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
 9368:         fprintf(stderr, "PowerPC flags inconsistency\n"
 9369:                 "Should define the time-base and decrementer clock source\n");
 9370:         exit(1);
 9371:     }
 9372:     /* Allocate TLBs buffer when needed */
 9373: #if !defined(CONFIG_USER_ONLY)
 9374:     if (env->nb_tlb != 0) {
 9375:         int nb_tlb = env->nb_tlb;
 9376:         if (env->id_tlbs != 0)
 9377:             nb_tlb *= 2;
 9378:         switch (env->tlb_type) {
 9379:         case TLB_6XX:
 9380:             env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
 9381:             break;
 9382:         case TLB_EMB:
 9383:             env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
 9384:             break;
 9385:         case TLB_MAS:
 9386:             env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
 9387:             break;
 9388:         }
 9389:         /* Pre-compute some useful values */
 9390:         env->tlb_per_way = env->nb_tlb / env->nb_ways;
 9391:     }
 9392:     if (env->irq_inputs == NULL) {
 9393:         fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
 9394:                 " Attempt Qemu to crash very soon !\n");
 9395:     }
 9396: #endif
 9397:     if (env->check_pow == NULL) {
 9398:         fprintf(stderr, "WARNING: no power management check handler "
 9399:                 "registered.\n"
 9400:                 " Attempt Qemu to crash very soon !\n");
 9401:     }
 9402: }
 9403: 
 9404: #if defined(PPC_DUMP_CPU)
 9405: static void dump_ppc_sprs (CPUPPCState *env)
 9406: {
 9407:     ppc_spr_t *spr;
 9408: #if !defined(CONFIG_USER_ONLY)
 9409:     uint32_t sr, sw;
 9410: #endif
 9411:     uint32_t ur, uw;
 9412:     int i, j, n;
 9413: 
 9414:     printf("Special purpose registers:\n");
 9415:     for (i = 0; i < 32; i++) {
 9416:         for (j = 0; j < 32; j++) {
 9417:             n = (i << 5) | j;
 9418:             spr = &env->spr_cb[n];
 9419:             uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
 9420:             ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
 9421: #if !defined(CONFIG_USER_ONLY)
 9422:             sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
 9423:             sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
 9424:             if (sw || sr || uw || ur) {
 9425:                 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
 9426:                        (i << 5) | j, (i << 5) | j, spr->name,
 9427:                        sw ? 'w' : '-', sr ? 'r' : '-',
 9428:                        uw ? 'w' : '-', ur ? 'r' : '-');
 9429:             }
 9430: #else
 9431:             if (uw || ur) {
 9432:                 printf("SPR: %4d (%03x) %-8s u%c%c\n",
 9433:                        (i << 5) | j, (i << 5) | j, spr->name,
 9434:                        uw ? 'w' : '-', ur ? 'r' : '-');
 9435:             }
 9436: #endif
 9437:         }
 9438:     }
 9439:     fflush(stdout);
 9440:     fflush(stderr);
 9441: }
 9442: #endif
 9443: 
 9444: /*****************************************************************************/
 9445: #include <stdlib.h>
 9446: #include <string.h>
 9447: 
 9448: /* Opcode types */
 9449: enum {
 9450:     PPC_DIRECT   = 0, /* Opcode routine        */
 9451:     PPC_INDIRECT = 1, /* Indirect opcode table */
 9452: };
 9453: 
 9454: static inline int is_indirect_opcode (void *handler)
 9455: {
 9456:     return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
 9457: }
 9458: 
 9459: static inline opc_handler_t **ind_table(void *handler)
 9460: {
 9461:     return (opc_handler_t **)((unsigned long)handler & ~3);
 9462: }
 9463: 
 9464: /* Instruction table creation */
 9465: /* Opcodes tables creation */
 9466: static void fill_new_table (opc_handler_t **table, int len)
 9467: {
 9468:     int i;
 9469: 
 9470:     for (i = 0; i < len; i++)
 9471:         table[i] = &invalid_handler;
 9472: }
 9473: 
 9474: static int create_new_table (opc_handler_t **table, unsigned char idx)
 9475: {
 9476:     opc_handler_t **tmp;
 9477: 
 9478:     tmp = malloc(0x20 * sizeof(opc_handler_t));
 9479:     fill_new_table(tmp, 0x20);
 9480:     table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
 9481: 
 9482:     return 0;
 9483: }
 9484: 
 9485: static int insert_in_table (opc_handler_t **table, unsigned char idx,
 9486:                             opc_handler_t *handler)
 9487: {
 9488:     if (table[idx] != &invalid_handler)
 9489:         return -1;
 9490:     table[idx] = handler;
 9491: 
 9492:     return 0;
 9493: }
 9494: 
 9495: static int register_direct_insn (opc_handler_t **ppc_opcodes,
 9496:                                  unsigned char idx, opc_handler_t *handler)
 9497: {
 9498:     if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
 9499:         printf("*** ERROR: opcode %02x already assigned in main "
 9500:                "opcode table\n", idx);
 9501: #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
 9502:         printf("           Registered handler '%s' - new handler '%s'\n",
 9503:                ppc_opcodes[idx]->oname, handler->oname);
 9504: #endif
 9505:         return -1;
 9506:     }
 9507: 
 9508:     return 0;
 9509: }
 9510: 
 9511: static int register_ind_in_table (opc_handler_t **table,
 9512:                                   unsigned char idx1, unsigned char idx2,
 9513:                                   opc_handler_t *handler)
 9514: {
 9515:     if (table[idx1] == &invalid_handler) {
 9516:         if (create_new_table(table, idx1) < 0) {
 9517:             printf("*** ERROR: unable to create indirect table "
 9518:                    "idx=%02x\n", idx1);
 9519:             return -1;
 9520:         }
 9521:     } else {
 9522:         if (!is_indirect_opcode(table[idx1])) {
 9523:             printf("*** ERROR: idx %02x already assigned to a direct "
 9524:                    "opcode\n", idx1);
 9525: #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
 9526:             printf("           Registered handler '%s' - new handler '%s'\n",
 9527:                    ind_table(table[idx1])[idx2]->oname, handler->oname);
 9528: #endif
 9529:             return -1;
 9530:         }
 9531:     }
 9532:     if (handler != NULL &&
 9533:         insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
 9534:         printf("*** ERROR: opcode %02x already assigned in "
 9535:                "opcode table %02x\n", idx2, idx1);
 9536: #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
 9537:         printf("           Registered handler '%s' - new handler '%s'\n",
 9538:                ind_table(table[idx1])[idx2]->oname, handler->oname);
 9539: #endif
 9540:         return -1;
 9541:     }
 9542: 
 9543:     return 0;
 9544: }
 9545: 
 9546: static int register_ind_insn (opc_handler_t **ppc_opcodes,
 9547:                               unsigned char idx1, unsigned char idx2,
 9548:                               opc_handler_t *handler)
 9549: {
 9550:     int ret;
 9551: 
 9552:     ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
 9553: 
 9554:     return ret;
 9555: }
 9556: 
 9557: static int register_dblind_insn (opc_handler_t **ppc_opcodes,
 9558:                                  unsigned char idx1, unsigned char idx2,
 9559:                                  unsigned char idx3, opc_handler_t *handler)
 9560: {
 9561:     if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
 9562:         printf("*** ERROR: unable to join indirect table idx "
 9563:                "[%02x-%02x]\n", idx1, idx2);
 9564:         return -1;
 9565:     }
 9566:     if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
 9567:                               handler) < 0) {
 9568:         printf("*** ERROR: unable to insert opcode "
 9569:                "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
 9570:         return -1;
 9571:     }
 9572: 
 9573:     return 0;
 9574: }
 9575: 
 9576: static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
 9577: {
 9578:     if (insn->opc2 != 0xFF) {
 9579:         if (insn->opc3 != 0xFF) {
 9580:             if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
 9581:                                      insn->opc3, &insn->handler) < 0)
 9582:                 return -1;
 9583:         } else {
 9584:             if (register_ind_insn(ppc_opcodes, insn->opc1,
 9585:                                   insn->opc2, &insn->handler) < 0)
 9586:                 return -1;
 9587:         }
 9588:     } else {
 9589:         if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
 9590:             return -1;
 9591:     }
 9592: 
 9593:     return 0;
 9594: }
 9595: 
 9596: static int test_opcode_table (opc_handler_t **table, int len)
 9597: {
 9598:     int i, count, tmp;
 9599: 
 9600:     for (i = 0, count = 0; i < len; i++) {
 9601:         /* Consistency fixup */
 9602:         if (table[i] == NULL)
 9603:             table[i] = &invalid_handler;
 9604:         if (table[i] != &invalid_handler) {
 9605:             if (is_indirect_opcode(table[i])) {
 9606:                 tmp = test_opcode_table(ind_table(table[i]), 0x20);
 9607:                 if (tmp == 0) {
 9608:                     free(table[i]);
 9609:                     table[i] = &invalid_handler;
 9610:                 } else {
 9611:                     count++;
 9612:                 }
 9613:             } else {
 9614:                 count++;
 9615:             }
 9616:         }
 9617:     }
 9618: 
 9619:     return count;
 9620: }
 9621: 
 9622: static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
 9623: {
 9624:     if (test_opcode_table(ppc_opcodes, 0x40) == 0)
 9625:         printf("*** WARNING: no opcode defined !\n");
 9626: }
 9627: 
 9628: /*****************************************************************************/
 9629: static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
 9630: {
 9631:     opcode_t *opc;
 9632: 
 9633:     fill_new_table(env->opcodes, 0x40);
 9634:     for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
 9635:         if (((opc->handler.type & def->insns_flags) != 0) ||
 9636:             ((opc->handler.type2 & def->insns_flags2) != 0)) {
 9637:             if (register_insn(env->opcodes, opc) < 0) {
 9638:                 printf("*** ERROR initializing PowerPC instruction "
 9639:                        "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
 9640:                        opc->opc3);
 9641:                 return -1;
 9642:             }
 9643:         }
 9644:     }
 9645:     fix_opcode_tables(env->opcodes);
 9646:     fflush(stdout);
 9647:     fflush(stderr);
 9648: 
 9649:     return 0;
 9650: }
 9651: 
 9652: #if defined(PPC_DUMP_CPU)
 9653: static void dump_ppc_insns (CPUPPCState *env)
 9654: {
 9655:     opc_handler_t **table, *handler;
 9656:     const char *p, *q;
 9657:     uint8_t opc1, opc2, opc3;
 9658: 
 9659:     printf("Instructions set:\n");
 9660:     /* opc1 is 6 bits long */
 9661:     for (opc1 = 0x00; opc1 < 0x40; opc1++) {
 9662:         table = env->opcodes;
 9663:         handler = table[opc1];
 9664:         if (is_indirect_opcode(handler)) {
 9665:             /* opc2 is 5 bits long */
 9666:             for (opc2 = 0; opc2 < 0x20; opc2++) {
 9667:                 table = env->opcodes;
 9668:                 handler = env->opcodes[opc1];
 9669:                 table = ind_table(handler);
 9670:                 handler = table[opc2];
 9671:                 if (is_indirect_opcode(handler)) {
 9672:                     table = ind_table(handler);
 9673:                     /* opc3 is 5 bits long */
 9674:                     for (opc3 = 0; opc3 < 0x20; opc3++) {
 9675:                         handler = table[opc3];
 9676:                         if (handler->handler != &gen_invalid) {
 9677:                             /* Special hack to properly dump SPE insns */
 9678:                             p = strchr(handler->oname, '_');
 9679:                             if (p == NULL) {
 9680:                                 printf("INSN: %02x %02x %02x (%02d %04d) : "
 9681:                                        "%s\n",
 9682:                                        opc1, opc2, opc3, opc1,
 9683:                                        (opc3 << 5) | opc2,
 9684:                                        handler->oname);
 9685:                             } else {
 9686:                                 q = "speundef";
 9687:                                 if ((p - handler->oname) != strlen(q) ||
 9688:                                     memcmp(handler->oname, q, strlen(q)) != 0) {
 9689:                                     /* First instruction */
 9690:                                     printf("INSN: %02x %02x %02x (%02d %04d) : "
 9691:                                            "%.*s\n",
 9692:                                            opc1, opc2 << 1, opc3, opc1,
 9693:                                            (opc3 << 6) | (opc2 << 1),
 9694:                                            (int)(p - handler->oname),
 9695:                                            handler->oname);
 9696:                                 }
 9697:                                 if (strcmp(p + 1, q) != 0) {
 9698:                                     /* Second instruction */
 9699:                                     printf("INSN: %02x %02x %02x (%02d %04d) : "
 9700:                                            "%s\n",
 9701:                                            opc1, (opc2 << 1) | 1, opc3, opc1,
 9702:                                            (opc3 << 6) | (opc2 << 1) | 1,
 9703:                                            p + 1);
 9704:                                 }
 9705:                             }
 9706:                         }
 9707:                     }
 9708:                 } else {
 9709:                     if (handler->handler != &gen_invalid) {
 9710:                         printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
 9711:                                opc1, opc2, opc1, opc2, handler->oname);
 9712:                     }
 9713:                 }
 9714:             }
 9715:         } else {
 9716:             if (handler->handler != &gen_invalid) {
 9717:                 printf("INSN: %02x -- -- (%02d ----) : %s\n",
 9718:                        opc1, opc1, handler->oname);
 9719:             }
 9720:         }
 9721:     }
 9722: }
 9723: #endif
 9724: 
 9725: static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
 9726: {
 9727:     if (n < 32) {
 9728:         stfq_p(mem_buf, env->fpr[n]);
 9729:         return 8;
 9730:     }
 9731:     if (n == 32) {
 9732:         stl_p(mem_buf, env->fpscr);
 9733:         return 4;
 9734:     }
 9735:     return 0;
 9736: }
 9737: 
 9738: static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
 9739: {
 9740:     if (n < 32) {
 9741:         env->fpr[n] = ldfq_p(mem_buf);
 9742:         return 8;
 9743:     }
 9744:     if (n == 32) {
 9745:         /* FPSCR not implemented  */
 9746:         return 4;
 9747:     }
 9748:     return 0;
 9749: }
 9750: 
 9751: static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
 9752: {
 9753:     if (n < 32) {
 9754: #ifdef HOST_WORDS_BIGENDIAN
 9755:         stq_p(mem_buf, env->avr[n].u64[0]);
 9756:         stq_p(mem_buf+8, env->avr[n].u64[1]);
 9757: #else
 9758:         stq_p(mem_buf, env->avr[n].u64[1]);
 9759:         stq_p(mem_buf+8, env->avr[n].u64[0]);
 9760: #endif
 9761:         return 16;
 9762:     }
 9763:     if (n == 32) {
 9764:         stl_p(mem_buf, env->vscr);
 9765:         return 4;
 9766:     }
 9767:     if (n == 33) {
 9768:         stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
 9769:         return 4;
 9770:     }
 9771:     return 0;
 9772: }
 9773: 
 9774: static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
 9775: {
 9776:     if (n < 32) {
 9777: #ifdef HOST_WORDS_BIGENDIAN
 9778:         env->avr[n].u64[0] = ldq_p(mem_buf);
 9779:         env->avr[n].u64[1] = ldq_p(mem_buf+8);
 9780: #else
 9781:         env->avr[n].u64[1] = ldq_p(mem_buf);
 9782:         env->avr[n].u64[0] = ldq_p(mem_buf+8);
 9783: #endif
 9784:         return 16;
 9785:     }
 9786:     if (n == 32) {
 9787:         env->vscr = ldl_p(mem_buf);
 9788:         return 4;
 9789:     }
 9790:     if (n == 33) {
 9791:         env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
 9792:         return 4;
 9793:     }
 9794:     return 0;
 9795: }
 9796: 
 9797: static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
 9798: {
 9799:     if (n < 32) {
 9800: #if defined(TARGET_PPC64)
 9801:         stl_p(mem_buf, env->gpr[n] >> 32);
 9802: #else
 9803:         stl_p(mem_buf, env->gprh[n]);
 9804: #endif
 9805:         return 4;
 9806:     }
 9807:     if (n == 32) {
 9808:         stq_p(mem_buf, env->spe_acc);
 9809:         return 8;
 9810:     }
 9811:     if (n == 33) {
 9812:         stl_p(mem_buf, env->spe_fscr);
 9813:         return 4;
 9814:     }
 9815:     return 0;
 9816: }
 9817: 
 9818: static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
 9819: {
 9820:     if (n < 32) {
 9821: #if defined(TARGET_PPC64)
 9822:         target_ulong lo = (uint32_t)env->gpr[n];
 9823:         target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
 9824:         env->gpr[n] = lo | hi;
 9825: #else
 9826:         env->gprh[n] = ldl_p(mem_buf);
 9827: #endif
 9828:         return 4;
 9829:     }
 9830:     if (n == 32) {
 9831:         env->spe_acc = ldq_p(mem_buf);
 9832:         return 8;
 9833:     }
 9834:     if (n == 33) {
 9835:         env->spe_fscr = ldl_p(mem_buf);
 9836:         return 4;
 9837:     }
 9838:     return 0;
 9839: }
 9840: 
 9841: int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
 9842: {
 9843:     env->msr_mask = def->msr_mask;
 9844:     env->mmu_model = def->mmu_model;
 9845:     env->excp_model = def->excp_model;
 9846:     env->bus_model = def->bus_model;
 9847:     env->insns_flags = def->insns_flags;
 9848:     env->insns_flags2 = def->insns_flags2;
 9849:     if (!kvm_enabled()) {
 9850:         /* TCG doesn't (yet) emulate some groups of instructions that
 9851:          * are implemented on some otherwise supported CPUs (e.g. VSX
 9852:          * and decimal floating point instructions on POWER7).  We
 9853:          * remove unsupported instruction groups from the cpu state's
 9854:          * instruction masks and hope the guest can cope.  For at
 9855:          * least the pseries machine, the unavailability of these
 9856:          * instructions can be advertise to the guest via the device
 9857:          * tree.
 9858:          *
 9859:          * FIXME: we should have a similar masking for CPU features
 9860:          * not accessible under KVM, but so far, there aren't any of
 9861:          * those. */
 9862:         env->insns_flags &= PPC_TCG_INSNS;
 9863:         env->insns_flags2 &= PPC_TCG_INSNS2;
 9864:     }
 9865:     env->flags = def->flags;
 9866:     env->bfd_mach = def->bfd_mach;
 9867:     env->check_pow = def->check_pow;
 9868:     if (create_ppc_opcodes(env, def) < 0)
 9869:         return -1;
 9870:     init_ppc_proc(env, def);
 9871: 
 9872:     if (def->insns_flags & PPC_FLOAT) {
 9873:         gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
 9874:                                  33, "power-fpu.xml", 0);
 9875:     }
 9876:     if (def->insns_flags & PPC_ALTIVEC) {
 9877:         gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
 9878:                                  34, "power-altivec.xml", 0);
 9879:     }
 9880:     if (def->insns_flags & PPC_SPE) {
 9881:         gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
 9882:                                  34, "power-spe.xml", 0);
 9883:     }
 9884: 
 9885: #if defined(PPC_DUMP_CPU)
 9886:     {
 9887:         const char *mmu_model, *excp_model, *bus_model;
 9888:         switch (env->mmu_model) {
 9889:         case POWERPC_MMU_32B:
 9890:             mmu_model = "PowerPC 32";
 9891:             break;
 9892:         case POWERPC_MMU_SOFT_6xx:
 9893:             mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
 9894:             break;
 9895:         case POWERPC_MMU_SOFT_74xx:
 9896:             mmu_model = "PowerPC 74xx with software driven TLBs";
 9897:             break;
 9898:         case POWERPC_MMU_SOFT_4xx:
 9899:             mmu_model = "PowerPC 4xx with software driven TLBs";
 9900:             break;
 9901:         case POWERPC_MMU_SOFT_4xx_Z:
 9902:             mmu_model = "PowerPC 4xx with software driven TLBs "
 9903:                 "and zones protections";
 9904:             break;
 9905:         case POWERPC_MMU_REAL:
 9906:             mmu_model = "PowerPC real mode only";
 9907:             break;
 9908:         case POWERPC_MMU_MPC8xx:
 9909:             mmu_model = "PowerPC MPC8xx";
 9910:             break;
 9911:         case POWERPC_MMU_BOOKE:
 9912:             mmu_model = "PowerPC BookE";
 9913:             break;
 9914:         case POWERPC_MMU_BOOKE206:
 9915:             mmu_model = "PowerPC BookE 2.06";
 9916:             break;
 9917:         case POWERPC_MMU_601:
 9918:             mmu_model = "PowerPC 601";
 9919:             break;
 9920: #if defined (TARGET_PPC64)
 9921:         case POWERPC_MMU_64B:
 9922:             mmu_model = "PowerPC 64";
 9923:             break;
 9924:         case POWERPC_MMU_620:
 9925:             mmu_model = "PowerPC 620";
 9926:             break;
 9927: #endif
 9928:         default:
 9929:             mmu_model = "Unknown or invalid";
 9930:             break;
 9931:         }
 9932:         switch (env->excp_model) {
 9933:         case POWERPC_EXCP_STD:
 9934:             excp_model = "PowerPC";
 9935:             break;
 9936:         case POWERPC_EXCP_40x:
 9937:             excp_model = "PowerPC 40x";
 9938:             break;
 9939:         case POWERPC_EXCP_601:
 9940:             excp_model = "PowerPC 601";
 9941:             break;
 9942:         case POWERPC_EXCP_602:
 9943:             excp_model = "PowerPC 602";
 9944:             break;
 9945:         case POWERPC_EXCP_603:
 9946:             excp_model = "PowerPC 603";
 9947:             break;
 9948:         case POWERPC_EXCP_603E:
 9949:             excp_model = "PowerPC 603e";
 9950:             break;
 9951:         case POWERPC_EXCP_604:
 9952:             excp_model = "PowerPC 604";
 9953:             break;
 9954:         case POWERPC_EXCP_7x0:
 9955:             excp_model = "PowerPC 740/750";
 9956:             break;
 9957:         case POWERPC_EXCP_7x5:
 9958:             excp_model = "PowerPC 745/755";
 9959:             break;
 9960:         case POWERPC_EXCP_74xx:
 9961:             excp_model = "PowerPC 74xx";
 9962:             break;
 9963:         case POWERPC_EXCP_BOOKE:
 9964:             excp_model = "PowerPC BookE";
 9965:             break;
 9966: #if defined (TARGET_PPC64)
 9967:         case POWERPC_EXCP_970:
 9968:             excp_model = "PowerPC 970";
 9969:             break;
 9970: #endif
 9971:         default:
 9972:             excp_model = "Unknown or invalid";
 9973:             break;
 9974:         }
 9975:         switch (env->bus_model) {
 9976:         case PPC_FLAGS_INPUT_6xx:
 9977:             bus_model = "PowerPC 6xx";
 9978:             break;
 9979:         case PPC_FLAGS_INPUT_BookE:
 9980:             bus_model = "PowerPC BookE";
 9981:             break;
 9982:         case PPC_FLAGS_INPUT_405:
 9983:             bus_model = "PowerPC 405";
 9984:             break;
 9985:         case PPC_FLAGS_INPUT_401:
 9986:             bus_model = "PowerPC 401/403";
 9987:             break;
 9988:         case PPC_FLAGS_INPUT_RCPU:
 9989:             bus_model = "RCPU / MPC8xx";
 9990:             break;
 9991: #if defined (TARGET_PPC64)
 9992:         case PPC_FLAGS_INPUT_970:
 9993:             bus_model = "PowerPC 970";
 9994:             break;
 9995: #endif
 9996:         default:
 9997:             bus_model = "Unknown or invalid";
 9998:             break;
 9999:         }
10000:         printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
10001:                "    MMU model        : %s\n",
10002:                def->name, def->pvr, def->msr_mask, mmu_model);
10003: #if !defined(CONFIG_USER_ONLY)
10004:         if (env->tlb != NULL) {
10005:             printf("                       %d %s TLB in %d ways\n",
10006:                    env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
10007:                    env->nb_ways);
10008:         }
10009: #endif
10010:         printf("    Exceptions model : %s\n"
10011:                "    Bus model        : %s\n",
10012:                excp_model, bus_model);
10013:         printf("    MSR features     :\n");
10014:         if (env->flags & POWERPC_FLAG_SPE)
10015:             printf("                        signal processing engine enable"
10016:                    "\n");
10017:         else if (env->flags & POWERPC_FLAG_VRE)
10018:             printf("                        vector processor enable\n");
10019:         if (env->flags & POWERPC_FLAG_TGPR)
10020:             printf("                        temporary GPRs\n");
10021:         else if (env->flags & POWERPC_FLAG_CE)
10022:             printf("                        critical input enable\n");
10023:         if (env->flags & POWERPC_FLAG_SE)
10024:             printf("                        single-step trace mode\n");
10025:         else if (env->flags & POWERPC_FLAG_DWE)
10026:             printf("                        debug wait enable\n");
10027:         else if (env->flags & POWERPC_FLAG_UBLE)
10028:             printf("                        user BTB lock enable\n");
10029:         if (env->flags & POWERPC_FLAG_BE)
10030:             printf("                        branch-step trace mode\n");
10031:         else if (env->flags & POWERPC_FLAG_DE)
10032:             printf("                        debug interrupt enable\n");
10033:         if (env->flags & POWERPC_FLAG_PX)
10034:             printf("                        inclusive protection\n");
10035:         else if (env->flags & POWERPC_FLAG_PMM)
10036:             printf("                        performance monitor mark\n");
10037:         if (env->flags == POWERPC_FLAG_NONE)
10038:             printf("                        none\n");
10039:         printf("    Time-base/decrementer clock source: %s\n",
10040:                env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
10041:     }
10042:     dump_ppc_insns(env);
10043:     dump_ppc_sprs(env);
10044:     fflush(stdout);
10045: #endif
10046: 
10047:     return 0;
10048: }
10049: 
10050: static bool ppc_cpu_usable(const ppc_def_t *def)
10051: {
10052: #if defined(TARGET_PPCEMB)
10053:     /* When using the ppcemb target, we only support 440 style cores */
10054:     if (def->mmu_model != POWERPC_MMU_BOOKE) {
10055:         return false;
10056:     }
10057: #endif
10058: 
10059:     return true;
10060: }
10061: 
10062: const ppc_def_t *ppc_find_by_pvr(uint32_t pvr)
10063: {
10064:     int i;
10065: 
10066:     for (i = 0; i < ARRAY_SIZE(ppc_defs); i++) {
10067:         if (!ppc_cpu_usable(&ppc_defs[i])) {
10068:             continue;
10069:         }
10070: 
10071:         /* If we have an exact match, we're done */
10072:         if (pvr == ppc_defs[i].pvr) {
10073:             return &ppc_defs[i];
10074:         }
10075:     }
10076: 
10077:     return NULL;
10078: }
10079: 
10080: #include <ctype.h>
10081: 
10082: const ppc_def_t *cpu_ppc_find_by_name (const char *name)
10083: {
10084:     const ppc_def_t *ret;
10085:     const char *p;
10086:     int i, max, len;
10087: 
10088:     if (kvm_enabled() && (strcasecmp(name, "host") == 0)) {
10089:         return kvmppc_host_cpu_def();
10090:     }
10091: 
10092:     /* Check if the given name is a PVR */
10093:     len = strlen(name);
10094:     if (len == 10 && name[0] == '0' && name[1] == 'x') {
10095:         p = name + 2;
10096:         goto check_pvr;
10097:     } else if (len == 8) {
10098:         p = name;
10099:     check_pvr:
10100:         for (i = 0; i < 8; i++) {
10101:             if (!qemu_isxdigit(*p++))
10102:                 break;
10103:         }
10104:         if (i == 8)
10105:             return ppc_find_by_pvr(strtoul(name, NULL, 16));
10106:     }
10107:     ret = NULL;
10108:     max = ARRAY_SIZE(ppc_defs);
10109:     for (i = 0; i < max; i++) {
10110:         if (!ppc_cpu_usable(&ppc_defs[i])) {
10111:             continue;
10112:         }
10113: 
10114:         if (strcasecmp(name, ppc_defs[i].name) == 0) {
10115:             ret = &ppc_defs[i];
10116:             break;
10117:         }
10118:     }
10119: 
10120:     return ret;
10121: }
10122: 
10123: void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
10124: {
10125:     int i, max;
10126: 
10127:     max = ARRAY_SIZE(ppc_defs);
10128:     for (i = 0; i < max; i++) {
10129:         if (!ppc_cpu_usable(&ppc_defs[i])) {
10130:             continue;
10131:         }
10132: 
10133:         (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
10134:                        ppc_defs[i].name, ppc_defs[i].pvr);
10135:     }
10136: }

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