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1.1 root 1: /*
2: * SH4 emulation
3: *
4: * Copyright (c) 2005 Samuel Tardieu
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
17: * License along with this library; if not, write to the Free Software
18: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19: */
20: #ifndef _CPU_SH4_H
21: #define _CPU_SH4_H
22:
23: #include "config.h"
24:
25: #define TARGET_LONG_BITS 32
26: #define TARGET_HAS_ICE 1
27:
28: #include "cpu-defs.h"
29:
30: #define TARGET_PAGE_BITS 12 /* 4k XXXXX */
31:
32: #define SR_MD (1 << 30)
33: #define SR_RB (1 << 29)
34: #define SR_BL (1 << 28)
35: #define SR_FD (1 << 15)
36: #define SR_M (1 << 9)
37: #define SR_Q (1 << 8)
38: #define SR_S (1 << 1)
39: #define SR_T (1 << 0)
40:
41: #define FPSCR_FR (1 << 21)
42: #define FPSCR_SZ (1 << 20)
43: #define FPSCR_PR (1 << 19)
44: #define FPSCR_DN (1 << 18)
45:
46: #define DELAY_SLOT (1 << 0)
47: #define DELAY_SLOT_CONDITIONAL (1 << 1)
48: /* Those are used in contexts only */
49: #define BRANCH (1 << 2)
50: #define BRANCH_CONDITIONAL (1 << 3)
51: #define MODE_CHANGE (1 << 4) /* Potential MD|RB change */
52: #define BRANCH_EXCEPTION (1 << 5) /* Branch after exception */
53:
54: /* XXXXX The structure could be made more compact */
55: typedef struct tlb_t {
56: uint8_t asid; /* address space identifier */
57: uint32_t vpn; /* virtual page number */
58: uint8_t v; /* validity */
59: uint32_t ppn; /* physical page number */
60: uint8_t sz; /* page size */
61: uint32_t size; /* cached page size in bytes */
62: uint8_t sh; /* share status */
63: uint8_t c; /* cacheability */
64: uint8_t pr; /* protection key */
65: uint8_t d; /* dirty */
66: uint8_t wt; /* write through */
67: uint8_t sa; /* space attribute (PCMCIA) */
68: uint8_t tc; /* timing control */
69: } tlb_t;
70:
71: #define UTLB_SIZE 64
72: #define ITLB_SIZE 4
73:
74: typedef struct CPUSH4State {
75: uint32_t flags; /* general execution flags */
76: uint32_t gregs[24]; /* general registers */
77: uint32_t fregs[32]; /* floating point registers */
78: uint32_t sr; /* status register */
79: uint32_t ssr; /* saved status register */
80: uint32_t spc; /* saved program counter */
81: uint32_t gbr; /* global base register */
82: uint32_t vbr; /* vector base register */
83: uint32_t sgr; /* saved global register 15 */
84: uint32_t dbr; /* debug base register */
85: uint32_t pc; /* program counter */
86: uint32_t delayed_pc; /* target of delayed jump */
87: uint32_t mach; /* multiply and accumulate high */
88: uint32_t macl; /* multiply and accumulate low */
89: uint32_t pr; /* procedure register */
90: uint32_t fpscr; /* floating point status/control register */
91: uint32_t fpul; /* floating point communication register */
92:
93: /* Those belong to the specific unit (SH7750) but are handled here */
94: uint32_t mmucr; /* MMU control register */
95: uint32_t pteh; /* page table entry high register */
96: uint32_t ptel; /* page table entry low register */
97: uint32_t ptea; /* page table entry assistance register */
98: uint32_t ttb; /* tranlation table base register */
99: uint32_t tea; /* TLB exception address register */
100: uint32_t tra; /* TRAPA exception register */
101: uint32_t expevt; /* exception event register */
102: uint32_t intevt; /* interrupt event register */
103:
104: jmp_buf jmp_env;
105: int user_mode_only;
106: int interrupt_request;
107: int exception_index;
108: CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
109: tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
110: } CPUSH4State;
111:
112: CPUSH4State *cpu_sh4_init(void);
113: int cpu_sh4_exec(CPUSH4State * s);
114: struct siginfo;
115: int cpu_sh4_signal_handler(int hostsignum, struct siginfo *info,
116: void *puc);
117:
118: #include "softfloat.h"
119:
120: #include "cpu-all.h"
121:
122: /* Memory access type */
123: enum {
124: /* Privilege */
125: ACCESS_PRIV = 0x01,
126: /* Direction */
127: ACCESS_WRITE = 0x02,
128: /* Type of instruction */
129: ACCESS_CODE = 0x10,
130: ACCESS_INT = 0x20
131: };
132:
133: /* MMU control register */
134: #define MMUCR 0x1F000010
135: #define MMUCR_AT (1<<0)
136: #define MMUCR_SV (1<<8)
137:
138: #endif /* _CPU_SH4_H */
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