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1.1 root 1: /*
2: * SH4 emulation
1.1.1.4 root 3: *
1.1 root 4: * Copyright (c) 2005 Samuel Tardieu
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
1.1.1.6 root 17: * License along with this library; if not, see <http://www.gnu.org/licenses/>.
1.1 root 18: */
19: #ifndef _CPU_SH4_H
20: #define _CPU_SH4_H
21:
22: #include "config.h"
1.1.1.10 root 23: #include "qemu-common.h"
1.1 root 24:
25: #define TARGET_LONG_BITS 32
26: #define TARGET_HAS_ICE 1
27:
1.1.1.3 root 28: #define ELF_MACHINE EM_SH
29:
1.1.1.5 root 30: /* CPU Subtypes */
31: #define SH_CPU_SH7750 (1 << 0)
32: #define SH_CPU_SH7750S (1 << 1)
33: #define SH_CPU_SH7750R (1 << 2)
34: #define SH_CPU_SH7751 (1 << 3)
35: #define SH_CPU_SH7751R (1 << 4)
36: #define SH_CPU_SH7785 (1 << 5)
37: #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
38: #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
39:
1.1.1.13! root 40: #define CPUArchState struct CPUSH4State
1.1.1.6 root 41:
1.1 root 42: #include "cpu-defs.h"
43:
1.1.1.2 root 44: #include "softfloat.h"
45:
1.1 root 46: #define TARGET_PAGE_BITS 12 /* 4k XXXXX */
47:
1.1.1.9 root 48: #define TARGET_PHYS_ADDR_SPACE_BITS 32
49: #define TARGET_VIRT_ADDR_SPACE_BITS 32
50:
1.1 root 51: #define SR_MD (1 << 30)
52: #define SR_RB (1 << 29)
53: #define SR_BL (1 << 28)
54: #define SR_FD (1 << 15)
55: #define SR_M (1 << 9)
56: #define SR_Q (1 << 8)
1.1.1.5 root 57: #define SR_I3 (1 << 7)
58: #define SR_I2 (1 << 6)
59: #define SR_I1 (1 << 5)
60: #define SR_I0 (1 << 4)
1.1 root 61: #define SR_S (1 << 1)
62: #define SR_T (1 << 0)
63:
1.1.1.10 root 64: #define FPSCR_MASK (0x003fffff)
65: #define FPSCR_FR (1 << 21)
66: #define FPSCR_SZ (1 << 20)
67: #define FPSCR_PR (1 << 19)
68: #define FPSCR_DN (1 << 18)
69: #define FPSCR_CAUSE_MASK (0x3f << 12)
70: #define FPSCR_CAUSE_SHIFT (12)
71: #define FPSCR_CAUSE_E (1 << 17)
72: #define FPSCR_CAUSE_V (1 << 16)
73: #define FPSCR_CAUSE_Z (1 << 15)
74: #define FPSCR_CAUSE_O (1 << 14)
75: #define FPSCR_CAUSE_U (1 << 13)
76: #define FPSCR_CAUSE_I (1 << 12)
77: #define FPSCR_ENABLE_MASK (0x1f << 7)
78: #define FPSCR_ENABLE_SHIFT (7)
79: #define FPSCR_ENABLE_V (1 << 11)
80: #define FPSCR_ENABLE_Z (1 << 10)
81: #define FPSCR_ENABLE_O (1 << 9)
82: #define FPSCR_ENABLE_U (1 << 8)
83: #define FPSCR_ENABLE_I (1 << 7)
84: #define FPSCR_FLAG_MASK (0x1f << 2)
85: #define FPSCR_FLAG_SHIFT (2)
86: #define FPSCR_FLAG_V (1 << 6)
87: #define FPSCR_FLAG_Z (1 << 5)
88: #define FPSCR_FLAG_O (1 << 4)
89: #define FPSCR_FLAG_U (1 << 3)
90: #define FPSCR_FLAG_I (1 << 2)
91: #define FPSCR_RM_MASK (0x03 << 0)
92: #define FPSCR_RM_NEAREST (0 << 0)
93: #define FPSCR_RM_ZERO (1 << 0)
94:
1.1.1.4 root 95: #define DELAY_SLOT (1 << 0)
1.1 root 96: #define DELAY_SLOT_CONDITIONAL (1 << 1)
1.1.1.4 root 97: #define DELAY_SLOT_TRUE (1 << 2)
98: #define DELAY_SLOT_CLEARME (1 << 3)
99: /* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump
100: * after the delay slot should be taken or not. It is calculated from SR_T.
101: *
102: * It is unclear if it is permitted to modify the SR_T flag in a delay slot.
103: * The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification.
104: */
1.1 root 105:
106: typedef struct tlb_t {
107: uint32_t vpn; /* virtual page number */
108: uint32_t ppn; /* physical page number */
1.1.1.9 root 109: uint32_t size; /* mapped page size in bytes */
110: uint8_t asid; /* address space identifier */
111: uint8_t v:1; /* validity */
112: uint8_t sz:2; /* page size */
113: uint8_t sh:1; /* share status */
114: uint8_t c:1; /* cacheability */
115: uint8_t pr:2; /* protection key */
116: uint8_t d:1; /* dirty */
117: uint8_t wt:1; /* write through */
118: uint8_t sa:3; /* space attribute (PCMCIA) */
119: uint8_t tc:1; /* timing control */
1.1 root 120: } tlb_t;
121:
122: #define UTLB_SIZE 64
123: #define ITLB_SIZE 4
124:
1.1.1.4 root 125: #define NB_MMU_MODES 2
126:
1.1.1.5 root 127: enum sh_features {
128: SH_FEATURE_SH4A = 1,
129: SH_FEATURE_BCR3_AND_BCR4 = 2,
130: };
131:
1.1.1.6 root 132: typedef struct memory_content {
133: uint32_t address;
134: uint32_t value;
135: struct memory_content *next;
136: } memory_content;
137:
1.1 root 138: typedef struct CPUSH4State {
139: uint32_t flags; /* general execution flags */
140: uint32_t gregs[24]; /* general registers */
1.1.1.4 root 141: float32 fregs[32]; /* floating point registers */
1.1 root 142: uint32_t sr; /* status register */
143: uint32_t ssr; /* saved status register */
144: uint32_t spc; /* saved program counter */
145: uint32_t gbr; /* global base register */
146: uint32_t vbr; /* vector base register */
147: uint32_t sgr; /* saved global register 15 */
148: uint32_t dbr; /* debug base register */
149: uint32_t pc; /* program counter */
150: uint32_t delayed_pc; /* target of delayed jump */
151: uint32_t mach; /* multiply and accumulate high */
152: uint32_t macl; /* multiply and accumulate low */
153: uint32_t pr; /* procedure register */
154: uint32_t fpscr; /* floating point status/control register */
155: uint32_t fpul; /* floating point communication register */
156:
1.1.1.5 root 157: /* float point status register */
1.1.1.4 root 158: float_status fp_status;
1.1.1.2 root 159:
1.1.1.5 root 160: /* The features that we should emulate. See sh_features above. */
161: uint32_t features;
162:
1.1 root 163: /* Those belong to the specific unit (SH7750) but are handled here */
164: uint32_t mmucr; /* MMU control register */
165: uint32_t pteh; /* page table entry high register */
166: uint32_t ptel; /* page table entry low register */
167: uint32_t ptea; /* page table entry assistance register */
168: uint32_t ttb; /* tranlation table base register */
169: uint32_t tea; /* TLB exception address register */
170: uint32_t tra; /* TRAPA exception register */
171: uint32_t expevt; /* exception event register */
172: uint32_t intevt; /* interrupt event register */
173:
1.1.1.10 root 174: tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
175: tlb_t utlb[UTLB_SIZE]; /* unified translation table */
176:
177: uint32_t ldst;
178:
179: CPU_COMMON
180:
181: int id; /* CPU model */
1.1.1.5 root 182: uint32_t pvr; /* Processor Version Register */
183: uint32_t prr; /* Processor Revision Register */
184: uint32_t cvr; /* Cache Version Register */
185:
1.1.1.4 root 186: void *intc_handle;
1.1.1.11 root 187: int in_sleep; /* SR_BL ignored during sleep */
1.1.1.6 root 188: memory_content *movcal_backup;
189: memory_content **movcal_backup_tail;
1.1 root 190: } CPUSH4State;
191:
1.1.1.13! root 192: #include "cpu-qom.h"
! 193:
1.1.1.4 root 194: CPUSH4State *cpu_sh4_init(const char *cpu_model);
1.1 root 195: int cpu_sh4_exec(CPUSH4State * s);
1.1.1.4 root 196: int cpu_sh4_signal_handler(int host_signum, void *pinfo,
1.1.1.3 root 197: void *puc);
1.1.1.5 root 198: int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
1.1.1.12 root 199: int mmu_idx);
1.1.1.7 root 200: #define cpu_handle_mmu_fault cpu_sh4_handle_mmu_fault
1.1.1.5 root 201: void do_interrupt(CPUSH4State * env);
202:
1.1.1.10 root 203: void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1.1.1.9 root 204: #if !defined(CONFIG_USER_ONLY)
1.1.1.8 root 205: void cpu_sh4_invalidate_tlb(CPUSH4State *s);
1.1.1.10 root 206: uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
207: target_phys_addr_t addr);
208: void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, target_phys_addr_t addr,
209: uint32_t mem_value);
210: uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
211: target_phys_addr_t addr);
212: void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, target_phys_addr_t addr,
213: uint32_t mem_value);
214: uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
215: target_phys_addr_t addr);
1.1.1.5 root 216: void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
1.1.1.10 root 217: uint32_t mem_value);
218: uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
219: target_phys_addr_t addr);
220: void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, target_phys_addr_t addr,
221: uint32_t mem_value);
1.1.1.9 root 222: #endif
1.1.1.5 root 223:
1.1.1.6 root 224: int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
225:
1.1.1.5 root 226: static inline void cpu_set_tls(CPUSH4State *env, target_ulong newtls)
227: {
228: env->gbr = newtls;
229: }
230:
231: void cpu_load_tlb(CPUSH4State * env);
1.1 root 232:
233: #include "softfloat.h"
234:
1.1.1.4 root 235: #define cpu_init cpu_sh4_init
236: #define cpu_exec cpu_sh4_exec
237: #define cpu_gen_code cpu_sh4_gen_code
238: #define cpu_signal_handler cpu_sh4_signal_handler
1.1.1.5 root 239: #define cpu_list sh4_cpu_list
1.1.1.4 root 240:
241: /* MMU modes definitions */
242: #define MMU_MODE0_SUFFIX _kernel
243: #define MMU_MODE1_SUFFIX _user
244: #define MMU_USER_IDX 1
1.1.1.13! root 245: static inline int cpu_mmu_index (CPUSH4State *env)
1.1.1.4 root 246: {
247: return (env->sr & SR_MD) == 0 ? 1 : 0;
248: }
249:
1.1.1.5 root 250: #if defined(CONFIG_USER_ONLY)
1.1.1.13! root 251: static inline void cpu_clone_regs(CPUSH4State *env, target_ulong newsp)
1.1.1.5 root 252: {
253: if (newsp)
254: env->gregs[15] = newsp;
255: env->gregs[0] = 0;
256: }
257: #endif
258:
1.1 root 259: #include "cpu-all.h"
260:
261: /* Memory access type */
262: enum {
263: /* Privilege */
264: ACCESS_PRIV = 0x01,
265: /* Direction */
266: ACCESS_WRITE = 0x02,
267: /* Type of instruction */
268: ACCESS_CODE = 0x10,
269: ACCESS_INT = 0x20
270: };
271:
272: /* MMU control register */
273: #define MMUCR 0x1F000010
274: #define MMUCR_AT (1<<0)
1.1.1.8 root 275: #define MMUCR_TI (1<<2)
1.1 root 276: #define MMUCR_SV (1<<8)
1.1.1.5 root 277: #define MMUCR_URC_BITS (6)
278: #define MMUCR_URC_OFFSET (10)
279: #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
280: #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
281: static inline int cpu_mmucr_urc (uint32_t mmucr)
282: {
283: return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
284: }
285:
286: /* PTEH : Page Translation Entry High register */
287: #define PTEH_ASID_BITS (8)
288: #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
289: #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
290: #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
291: #define PTEH_VPN_BITS (22)
292: #define PTEH_VPN_OFFSET (10)
293: #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
294: #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
295: static inline int cpu_pteh_vpn (uint32_t pteh)
296: {
297: return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
298: }
299:
300: /* PTEL : Page Translation Entry Low register */
301: #define PTEL_V (1 << 8)
302: #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
303: #define PTEL_C (1 << 3)
304: #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
305: #define PTEL_D (1 << 2)
306: #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
307: #define PTEL_SH (1 << 1)
308: #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
309: #define PTEL_WT (1 << 0)
310: #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
311:
312: #define PTEL_SZ_HIGH_OFFSET (7)
313: #define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET)
314: #define PTEL_SZ_LOW_OFFSET (4)
315: #define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET)
316: static inline int cpu_ptel_sz (uint32_t ptel)
317: {
318: int sz;
319: sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
320: sz <<= 1;
321: sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
322: return sz;
323: }
324:
325: #define PTEL_PPN_BITS (19)
326: #define PTEL_PPN_OFFSET (10)
327: #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
328: #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
329: static inline int cpu_ptel_ppn (uint32_t ptel)
330: {
331: return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
332: }
333:
334: #define PTEL_PR_BITS (2)
335: #define PTEL_PR_OFFSET (5)
336: #define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
337: #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
338: static inline int cpu_ptel_pr (uint32_t ptel)
339: {
340: return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
341: }
342:
343: /* PTEA : Page Translation Entry Assistance register */
344: #define PTEA_SA_BITS (3)
345: #define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
346: #define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
347: #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
348: #define PTEA_TC (1 << 3)
349: #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
350:
1.1.1.6 root 351: #define TB_FLAG_PENDING_MOVCA (1 << 4)
352:
1.1.1.13! root 353: static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
1.1.1.5 root 354: target_ulong *cs_base, int *flags)
355: {
356: *pc = env->pc;
357: *cs_base = 0;
358: *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL
359: | DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME)) /* Bits 0- 3 */
360: | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */
361: | (env->sr & (SR_MD | SR_RB)) /* Bits 29-30 */
1.1.1.6 root 362: | (env->sr & SR_FD) /* Bit 15 */
363: | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
1.1.1.5 root 364: }
1.1 root 365:
1.1.1.13! root 366: static inline bool cpu_has_work(CPUSH4State *env)
1.1.1.11 root 367: {
368: return env->interrupt_request & CPU_INTERRUPT_HARD;
369: }
370:
371: #include "exec-all.h"
372:
1.1.1.13! root 373: static inline void cpu_pc_from_tb(CPUSH4State *env, TranslationBlock *tb)
1.1.1.11 root 374: {
375: env->pc = tb->pc;
376: env->flags = tb->flags;
377: }
378:
1.1 root 379: #endif /* _CPU_SH4_H */
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