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1.1 root 1: /*
2: * SH4 emulation
1.1.1.4 ! root 3: *
1.1 root 4: * Copyright (c) 2005 Samuel Tardieu
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
17: * License along with this library; if not, write to the Free Software
18: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19: */
20: #ifndef _CPU_SH4_H
21: #define _CPU_SH4_H
22:
23: #include "config.h"
24:
25: #define TARGET_LONG_BITS 32
26: #define TARGET_HAS_ICE 1
27:
1.1.1.3 root 28: #define ELF_MACHINE EM_SH
29:
1.1 root 30: #include "cpu-defs.h"
31:
1.1.1.2 root 32: #include "softfloat.h"
33:
1.1 root 34: #define TARGET_PAGE_BITS 12 /* 4k XXXXX */
35:
36: #define SR_MD (1 << 30)
37: #define SR_RB (1 << 29)
38: #define SR_BL (1 << 28)
39: #define SR_FD (1 << 15)
40: #define SR_M (1 << 9)
41: #define SR_Q (1 << 8)
42: #define SR_S (1 << 1)
43: #define SR_T (1 << 0)
44:
45: #define FPSCR_FR (1 << 21)
46: #define FPSCR_SZ (1 << 20)
47: #define FPSCR_PR (1 << 19)
48: #define FPSCR_DN (1 << 18)
1.1.1.4 ! root 49: #define DELAY_SLOT (1 << 0)
1.1 root 50: #define DELAY_SLOT_CONDITIONAL (1 << 1)
1.1.1.4 ! root 51: #define DELAY_SLOT_TRUE (1 << 2)
! 52: #define DELAY_SLOT_CLEARME (1 << 3)
! 53: /* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump
! 54: * after the delay slot should be taken or not. It is calculated from SR_T.
! 55: *
! 56: * It is unclear if it is permitted to modify the SR_T flag in a delay slot.
! 57: * The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification.
! 58: */
1.1 root 59:
60: /* XXXXX The structure could be made more compact */
61: typedef struct tlb_t {
62: uint8_t asid; /* address space identifier */
63: uint32_t vpn; /* virtual page number */
64: uint8_t v; /* validity */
65: uint32_t ppn; /* physical page number */
66: uint8_t sz; /* page size */
67: uint32_t size; /* cached page size in bytes */
68: uint8_t sh; /* share status */
69: uint8_t c; /* cacheability */
70: uint8_t pr; /* protection key */
71: uint8_t d; /* dirty */
72: uint8_t wt; /* write through */
73: uint8_t sa; /* space attribute (PCMCIA) */
74: uint8_t tc; /* timing control */
75: } tlb_t;
76:
77: #define UTLB_SIZE 64
78: #define ITLB_SIZE 4
79:
1.1.1.4 ! root 80: #define NB_MMU_MODES 2
! 81:
1.1 root 82: typedef struct CPUSH4State {
83: uint32_t flags; /* general execution flags */
84: uint32_t gregs[24]; /* general registers */
1.1.1.4 ! root 85: float32 fregs[32]; /* floating point registers */
1.1 root 86: uint32_t sr; /* status register */
87: uint32_t ssr; /* saved status register */
88: uint32_t spc; /* saved program counter */
89: uint32_t gbr; /* global base register */
90: uint32_t vbr; /* vector base register */
91: uint32_t sgr; /* saved global register 15 */
92: uint32_t dbr; /* debug base register */
93: uint32_t pc; /* program counter */
94: uint32_t delayed_pc; /* target of delayed jump */
95: uint32_t mach; /* multiply and accumulate high */
96: uint32_t macl; /* multiply and accumulate low */
97: uint32_t pr; /* procedure register */
98: uint32_t fpscr; /* floating point status/control register */
99: uint32_t fpul; /* floating point communication register */
100:
1.1.1.2 root 101: /* temporary float registers */
102: float32 ft0, ft1;
103: float64 dt0, dt1;
1.1.1.4 ! root 104: float_status fp_status;
1.1.1.2 root 105:
1.1 root 106: /* Those belong to the specific unit (SH7750) but are handled here */
107: uint32_t mmucr; /* MMU control register */
108: uint32_t pteh; /* page table entry high register */
109: uint32_t ptel; /* page table entry low register */
110: uint32_t ptea; /* page table entry assistance register */
111: uint32_t ttb; /* tranlation table base register */
112: uint32_t tea; /* TLB exception address register */
113: uint32_t tra; /* TRAPA exception register */
114: uint32_t expevt; /* exception event register */
115: uint32_t intevt; /* interrupt event register */
116:
117: jmp_buf jmp_env;
118: int user_mode_only;
119: int interrupt_request;
1.1.1.4 ! root 120: int halted;
1.1 root 121: int exception_index;
122: CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
123: tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
1.1.1.4 ! root 124: void *intc_handle;
1.1 root 125: } CPUSH4State;
126:
1.1.1.4 ! root 127: CPUSH4State *cpu_sh4_init(const char *cpu_model);
1.1 root 128: int cpu_sh4_exec(CPUSH4State * s);
1.1.1.4 ! root 129: int cpu_sh4_signal_handler(int host_signum, void *pinfo,
1.1.1.3 root 130: void *puc);
1.1 root 131:
132: #include "softfloat.h"
133:
1.1.1.4 ! root 134: #define CPUState CPUSH4State
! 135: #define cpu_init cpu_sh4_init
! 136: #define cpu_exec cpu_sh4_exec
! 137: #define cpu_gen_code cpu_sh4_gen_code
! 138: #define cpu_signal_handler cpu_sh4_signal_handler
! 139:
! 140: /* MMU modes definitions */
! 141: #define MMU_MODE0_SUFFIX _kernel
! 142: #define MMU_MODE1_SUFFIX _user
! 143: #define MMU_USER_IDX 1
! 144: static inline int cpu_mmu_index (CPUState *env)
! 145: {
! 146: return (env->sr & SR_MD) == 0 ? 1 : 0;
! 147: }
! 148:
1.1 root 149: #include "cpu-all.h"
150:
151: /* Memory access type */
152: enum {
153: /* Privilege */
154: ACCESS_PRIV = 0x01,
155: /* Direction */
156: ACCESS_WRITE = 0x02,
157: /* Type of instruction */
158: ACCESS_CODE = 0x10,
159: ACCESS_INT = 0x20
160: };
161:
162: /* MMU control register */
163: #define MMUCR 0x1F000010
164: #define MMUCR_AT (1<<0)
165: #define MMUCR_SV (1<<8)
166:
167: #endif /* _CPU_SH4_H */
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