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1.1 root 1: /*
2: * SH4 emulation
1.1.1.4 root 3: *
1.1 root 4: * Copyright (c) 2005 Samuel Tardieu
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
1.1.1.6 root 17: * License along with this library; if not, see <http://www.gnu.org/licenses/>.
1.1 root 18: */
19: #ifndef _CPU_SH4_H
20: #define _CPU_SH4_H
21:
22: #include "config.h"
23:
24: #define TARGET_LONG_BITS 32
25: #define TARGET_HAS_ICE 1
26:
1.1.1.3 root 27: #define ELF_MACHINE EM_SH
28:
1.1.1.5 root 29: /* CPU Subtypes */
30: #define SH_CPU_SH7750 (1 << 0)
31: #define SH_CPU_SH7750S (1 << 1)
32: #define SH_CPU_SH7750R (1 << 2)
33: #define SH_CPU_SH7751 (1 << 3)
34: #define SH_CPU_SH7751R (1 << 4)
35: #define SH_CPU_SH7785 (1 << 5)
36: #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
37: #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
38:
1.1.1.6 root 39: #define CPUState struct CPUSH4State
40:
1.1 root 41: #include "cpu-defs.h"
42:
1.1.1.2 root 43: #include "softfloat.h"
44:
1.1 root 45: #define TARGET_PAGE_BITS 12 /* 4k XXXXX */
46:
1.1.1.9 ! root 47: #define TARGET_PHYS_ADDR_SPACE_BITS 32
! 48: #define TARGET_VIRT_ADDR_SPACE_BITS 32
! 49:
1.1 root 50: #define SR_MD (1 << 30)
51: #define SR_RB (1 << 29)
52: #define SR_BL (1 << 28)
53: #define SR_FD (1 << 15)
54: #define SR_M (1 << 9)
55: #define SR_Q (1 << 8)
1.1.1.5 root 56: #define SR_I3 (1 << 7)
57: #define SR_I2 (1 << 6)
58: #define SR_I1 (1 << 5)
59: #define SR_I0 (1 << 4)
1.1 root 60: #define SR_S (1 << 1)
61: #define SR_T (1 << 0)
62:
63: #define FPSCR_FR (1 << 21)
64: #define FPSCR_SZ (1 << 20)
65: #define FPSCR_PR (1 << 19)
66: #define FPSCR_DN (1 << 18)
1.1.1.4 root 67: #define DELAY_SLOT (1 << 0)
1.1 root 68: #define DELAY_SLOT_CONDITIONAL (1 << 1)
1.1.1.4 root 69: #define DELAY_SLOT_TRUE (1 << 2)
70: #define DELAY_SLOT_CLEARME (1 << 3)
71: /* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump
72: * after the delay slot should be taken or not. It is calculated from SR_T.
73: *
74: * It is unclear if it is permitted to modify the SR_T flag in a delay slot.
75: * The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification.
76: */
1.1 root 77:
78: typedef struct tlb_t {
79: uint32_t vpn; /* virtual page number */
80: uint32_t ppn; /* physical page number */
1.1.1.9 ! root 81: uint32_t size; /* mapped page size in bytes */
! 82: uint8_t asid; /* address space identifier */
! 83: uint8_t v:1; /* validity */
! 84: uint8_t sz:2; /* page size */
! 85: uint8_t sh:1; /* share status */
! 86: uint8_t c:1; /* cacheability */
! 87: uint8_t pr:2; /* protection key */
! 88: uint8_t d:1; /* dirty */
! 89: uint8_t wt:1; /* write through */
! 90: uint8_t sa:3; /* space attribute (PCMCIA) */
! 91: uint8_t tc:1; /* timing control */
1.1 root 92: } tlb_t;
93:
94: #define UTLB_SIZE 64
95: #define ITLB_SIZE 4
96:
1.1.1.4 root 97: #define NB_MMU_MODES 2
98:
1.1.1.5 root 99: enum sh_features {
100: SH_FEATURE_SH4A = 1,
101: SH_FEATURE_BCR3_AND_BCR4 = 2,
102: };
103:
1.1.1.6 root 104: typedef struct memory_content {
105: uint32_t address;
106: uint32_t value;
107: struct memory_content *next;
108: } memory_content;
109:
1.1 root 110: typedef struct CPUSH4State {
1.1.1.5 root 111: int id; /* CPU model */
112:
1.1 root 113: uint32_t flags; /* general execution flags */
114: uint32_t gregs[24]; /* general registers */
1.1.1.4 root 115: float32 fregs[32]; /* floating point registers */
1.1 root 116: uint32_t sr; /* status register */
117: uint32_t ssr; /* saved status register */
118: uint32_t spc; /* saved program counter */
119: uint32_t gbr; /* global base register */
120: uint32_t vbr; /* vector base register */
121: uint32_t sgr; /* saved global register 15 */
122: uint32_t dbr; /* debug base register */
123: uint32_t pc; /* program counter */
124: uint32_t delayed_pc; /* target of delayed jump */
125: uint32_t mach; /* multiply and accumulate high */
126: uint32_t macl; /* multiply and accumulate low */
127: uint32_t pr; /* procedure register */
128: uint32_t fpscr; /* floating point status/control register */
129: uint32_t fpul; /* floating point communication register */
130:
1.1.1.5 root 131: /* float point status register */
1.1.1.4 root 132: float_status fp_status;
1.1.1.2 root 133:
1.1.1.5 root 134: /* The features that we should emulate. See sh_features above. */
135: uint32_t features;
136:
1.1 root 137: /* Those belong to the specific unit (SH7750) but are handled here */
138: uint32_t mmucr; /* MMU control register */
139: uint32_t pteh; /* page table entry high register */
140: uint32_t ptel; /* page table entry low register */
141: uint32_t ptea; /* page table entry assistance register */
142: uint32_t ttb; /* tranlation table base register */
143: uint32_t tea; /* TLB exception address register */
144: uint32_t tra; /* TRAPA exception register */
145: uint32_t expevt; /* exception event register */
146: uint32_t intevt; /* interrupt event register */
147:
1.1.1.5 root 148: uint32_t pvr; /* Processor Version Register */
149: uint32_t prr; /* Processor Revision Register */
150: uint32_t cvr; /* Cache Version Register */
151:
152: uint32_t ldst;
153:
1.1 root 154: CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
155: tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
1.1.1.4 root 156: void *intc_handle;
1.1.1.5 root 157: int intr_at_halt; /* SR_BL ignored during sleep */
1.1.1.6 root 158: memory_content *movcal_backup;
159: memory_content **movcal_backup_tail;
1.1 root 160: } CPUSH4State;
161:
1.1.1.4 root 162: CPUSH4State *cpu_sh4_init(const char *cpu_model);
1.1 root 163: int cpu_sh4_exec(CPUSH4State * s);
1.1.1.4 root 164: int cpu_sh4_signal_handler(int host_signum, void *pinfo,
1.1.1.3 root 165: void *puc);
1.1.1.5 root 166: int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
167: int mmu_idx, int is_softmmu);
1.1.1.7 root 168: #define cpu_handle_mmu_fault cpu_sh4_handle_mmu_fault
1.1.1.5 root 169: void do_interrupt(CPUSH4State * env);
170:
171: void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
1.1.1.9 ! root 172: #if !defined(CONFIG_USER_ONLY)
1.1.1.8 root 173: void cpu_sh4_invalidate_tlb(CPUSH4State *s);
1.1.1.5 root 174: void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
175: uint32_t mem_value);
1.1.1.9 ! root 176: #endif
1.1.1.5 root 177:
1.1.1.6 root 178: int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
179:
1.1.1.5 root 180: static inline void cpu_set_tls(CPUSH4State *env, target_ulong newtls)
181: {
182: env->gbr = newtls;
183: }
184:
185: void cpu_load_tlb(CPUSH4State * env);
1.1 root 186:
187: #include "softfloat.h"
188:
1.1.1.4 root 189: #define cpu_init cpu_sh4_init
190: #define cpu_exec cpu_sh4_exec
191: #define cpu_gen_code cpu_sh4_gen_code
192: #define cpu_signal_handler cpu_sh4_signal_handler
1.1.1.5 root 193: #define cpu_list sh4_cpu_list
1.1.1.4 root 194:
195: /* MMU modes definitions */
196: #define MMU_MODE0_SUFFIX _kernel
197: #define MMU_MODE1_SUFFIX _user
198: #define MMU_USER_IDX 1
199: static inline int cpu_mmu_index (CPUState *env)
200: {
201: return (env->sr & SR_MD) == 0 ? 1 : 0;
202: }
203:
1.1.1.5 root 204: #if defined(CONFIG_USER_ONLY)
205: static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
206: {
207: if (newsp)
208: env->gregs[15] = newsp;
209: env->gregs[0] = 0;
210: }
211: #endif
212:
1.1 root 213: #include "cpu-all.h"
214:
215: /* Memory access type */
216: enum {
217: /* Privilege */
218: ACCESS_PRIV = 0x01,
219: /* Direction */
220: ACCESS_WRITE = 0x02,
221: /* Type of instruction */
222: ACCESS_CODE = 0x10,
223: ACCESS_INT = 0x20
224: };
225:
226: /* MMU control register */
227: #define MMUCR 0x1F000010
228: #define MMUCR_AT (1<<0)
1.1.1.8 root 229: #define MMUCR_TI (1<<2)
1.1 root 230: #define MMUCR_SV (1<<8)
1.1.1.5 root 231: #define MMUCR_URC_BITS (6)
232: #define MMUCR_URC_OFFSET (10)
233: #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
234: #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
235: static inline int cpu_mmucr_urc (uint32_t mmucr)
236: {
237: return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
238: }
239:
240: /* PTEH : Page Translation Entry High register */
241: #define PTEH_ASID_BITS (8)
242: #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
243: #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
244: #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
245: #define PTEH_VPN_BITS (22)
246: #define PTEH_VPN_OFFSET (10)
247: #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
248: #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
249: static inline int cpu_pteh_vpn (uint32_t pteh)
250: {
251: return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
252: }
253:
254: /* PTEL : Page Translation Entry Low register */
255: #define PTEL_V (1 << 8)
256: #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
257: #define PTEL_C (1 << 3)
258: #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
259: #define PTEL_D (1 << 2)
260: #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
261: #define PTEL_SH (1 << 1)
262: #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
263: #define PTEL_WT (1 << 0)
264: #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
265:
266: #define PTEL_SZ_HIGH_OFFSET (7)
267: #define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET)
268: #define PTEL_SZ_LOW_OFFSET (4)
269: #define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET)
270: static inline int cpu_ptel_sz (uint32_t ptel)
271: {
272: int sz;
273: sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
274: sz <<= 1;
275: sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
276: return sz;
277: }
278:
279: #define PTEL_PPN_BITS (19)
280: #define PTEL_PPN_OFFSET (10)
281: #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
282: #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
283: static inline int cpu_ptel_ppn (uint32_t ptel)
284: {
285: return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
286: }
287:
288: #define PTEL_PR_BITS (2)
289: #define PTEL_PR_OFFSET (5)
290: #define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
291: #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
292: static inline int cpu_ptel_pr (uint32_t ptel)
293: {
294: return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
295: }
296:
297: /* PTEA : Page Translation Entry Assistance register */
298: #define PTEA_SA_BITS (3)
299: #define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
300: #define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
301: #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
302: #define PTEA_TC (1 << 3)
303: #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
304:
1.1.1.6 root 305: #define TB_FLAG_PENDING_MOVCA (1 << 4)
306:
1.1.1.5 root 307: static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
308: target_ulong *cs_base, int *flags)
309: {
310: *pc = env->pc;
311: *cs_base = 0;
312: *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL
313: | DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME)) /* Bits 0- 3 */
314: | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */
315: | (env->sr & (SR_MD | SR_RB)) /* Bits 29-30 */
1.1.1.6 root 316: | (env->sr & SR_FD) /* Bit 15 */
317: | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
1.1.1.5 root 318: }
1.1 root 319:
320: #endif /* _CPU_SH4_H */
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