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1.1 root 1: /*
2: * SH4 emulation
1.1.1.3 root 3: *
1.1 root 4: * Copyright (c) 2005 Samuel Tardieu
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License as published by the Free Software Foundation; either
9: * version 2 of the License, or (at your option) any later version.
10: *
11: * This library is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14: * Lesser General Public License for more details.
15: *
16: * You should have received a copy of the GNU Lesser General Public
1.1.1.5 root 17: * License along with this library; if not, see <http://www.gnu.org/licenses/>.
1.1 root 18: */
19: #include <stdarg.h>
20: #include <stdlib.h>
21: #include <stdio.h>
22: #include <string.h>
23: #include <inttypes.h>
24: #include <signal.h>
25:
26: #include "cpu.h"
1.1.1.3 root 27: #include "hw/sh_intc.h"
1.1 root 28:
1.1.1.2 root 29: #if defined(CONFIG_USER_ONLY)
30:
31: void do_interrupt (CPUState *env)
32: {
33: env->exception_index = -1;
34: }
35:
36: int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
1.1.1.3 root 37: int mmu_idx, int is_softmmu)
1.1.1.2 root 38: {
39: env->tea = address;
1.1.1.7 root 40: env->exception_index = -1;
1.1.1.2 root 41: switch (rw) {
42: case 0:
43: env->exception_index = 0x0a0;
44: break;
45: case 1:
46: env->exception_index = 0x0c0;
47: break;
1.1.1.4 root 48: case 2:
49: env->exception_index = 0x0a0;
50: break;
1.1.1.2 root 51: }
52: return 1;
53: }
54:
1.1.1.5 root 55: int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
56: {
57: /* For user mode, only U0 area is cachable. */
58: return !(addr & 0x80000000);
59: }
60:
1.1.1.2 root 61: #else /* !CONFIG_USER_ONLY */
62:
1.1 root 63: #define MMU_OK 0
64: #define MMU_ITLB_MISS (-1)
65: #define MMU_ITLB_MULTIPLE (-2)
66: #define MMU_ITLB_VIOLATION (-3)
67: #define MMU_DTLB_MISS_READ (-4)
68: #define MMU_DTLB_MISS_WRITE (-5)
69: #define MMU_DTLB_INITIAL_WRITE (-6)
70: #define MMU_DTLB_VIOLATION_READ (-7)
71: #define MMU_DTLB_VIOLATION_WRITE (-8)
72: #define MMU_DTLB_MULTIPLE (-9)
73: #define MMU_DTLB_MISS (-10)
1.1.1.4 root 74: #define MMU_IADDR_ERROR (-11)
75: #define MMU_DADDR_ERROR_READ (-12)
76: #define MMU_DADDR_ERROR_WRITE (-13)
1.1 root 77:
78: void do_interrupt(CPUState * env)
79: {
1.1.1.3 root 80: int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
81: int do_exp, irq_vector = env->exception_index;
82:
83: /* prioritize exceptions over interrupts */
84:
85: do_exp = env->exception_index != -1;
86: do_irq = do_irq && (env->exception_index == -1);
87:
88: if (env->sr & SR_BL) {
89: if (do_exp && env->exception_index != 0x1e0) {
90: env->exception_index = 0x000; /* masked exception -> reset */
91: }
1.1.1.9 ! root 92: if (do_irq && !env->in_sleep) {
1.1.1.3 root 93: return; /* masked */
94: }
95: }
1.1.1.9 ! root 96: env->in_sleep = 0;
1.1.1.3 root 97:
98: if (do_irq) {
99: irq_vector = sh_intc_get_pending_vector(env->intc_handle,
100: (env->sr >> 4) & 0xf);
101: if (irq_vector == -1) {
102: return; /* masked */
103: }
104: }
105:
1.1.1.4 root 106: if (qemu_loglevel_mask(CPU_LOG_INT)) {
1.1 root 107: const char *expname;
108: switch (env->exception_index) {
109: case 0x0e0:
110: expname = "addr_error";
111: break;
112: case 0x040:
113: expname = "tlb_miss";
114: break;
115: case 0x0a0:
116: expname = "tlb_violation";
117: break;
118: case 0x180:
119: expname = "illegal_instruction";
120: break;
121: case 0x1a0:
122: expname = "slot_illegal_instruction";
123: break;
124: case 0x800:
125: expname = "fpu_disable";
126: break;
127: case 0x820:
128: expname = "slot_fpu";
129: break;
130: case 0x100:
131: expname = "data_write";
132: break;
133: case 0x060:
134: expname = "dtlb_miss_write";
135: break;
136: case 0x0c0:
137: expname = "dtlb_violation_write";
138: break;
139: case 0x120:
140: expname = "fpu_exception";
141: break;
142: case 0x080:
143: expname = "initial_page_write";
144: break;
145: case 0x160:
146: expname = "trapa";
147: break;
148: default:
1.1.1.3 root 149: expname = do_irq ? "interrupt" : "???";
150: break;
1.1 root 151: }
1.1.1.4 root 152: qemu_log("exception 0x%03x [%s] raised\n",
153: irq_vector, expname);
154: log_cpu_state(env, 0);
1.1 root 155: }
156:
157: env->ssr = env->sr;
1.1.1.3 root 158: env->spc = env->pc;
1.1 root 159: env->sgr = env->gregs[15];
160: env->sr |= SR_BL | SR_MD | SR_RB;
161:
1.1.1.4 root 162: if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
163: /* Branch instruction should be executed again before delay slot. */
164: env->spc -= 2;
165: /* Clear flags for exception/interrupt routine. */
166: env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);
167: }
168: if (env->flags & DELAY_SLOT_CLEARME)
169: env->flags = 0;
170:
1.1.1.3 root 171: if (do_exp) {
172: env->expevt = env->exception_index;
173: switch (env->exception_index) {
174: case 0x000:
175: case 0x020:
176: case 0x140:
177: env->sr &= ~SR_FD;
178: env->sr |= 0xf << 4; /* IMASK */
179: env->pc = 0xa0000000;
180: break;
181: case 0x040:
182: case 0x060:
183: env->pc = env->vbr + 0x400;
184: break;
185: case 0x160:
186: env->spc += 2; /* special case for TRAPA */
187: /* fall through */
188: default:
189: env->pc = env->vbr + 0x100;
190: break;
191: }
192: return;
193: }
194:
195: if (do_irq) {
196: env->intevt = irq_vector;
197: env->pc = env->vbr + 0x600;
198: return;
1.1 root 199: }
200: }
201:
202: static void update_itlb_use(CPUState * env, int itlbnb)
203: {
204: uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
205:
206: switch (itlbnb) {
207: case 0:
1.1.1.4 root 208: and_mask = 0x1f;
1.1 root 209: break;
210: case 1:
211: and_mask = 0xe7;
212: or_mask = 0x80;
213: break;
214: case 2:
215: and_mask = 0xfb;
216: or_mask = 0x50;
217: break;
218: case 3:
219: or_mask = 0x2c;
220: break;
221: }
222:
1.1.1.4 root 223: env->mmucr &= (and_mask << 24) | 0x00ffffff;
1.1 root 224: env->mmucr |= (or_mask << 24);
225: }
226:
227: static int itlb_replacement(CPUState * env)
228: {
229: if ((env->mmucr & 0xe0000000) == 0xe0000000)
230: return 0;
1.1.1.4 root 231: if ((env->mmucr & 0x98000000) == 0x18000000)
1.1 root 232: return 1;
233: if ((env->mmucr & 0x54000000) == 0x04000000)
234: return 2;
235: if ((env->mmucr & 0x2c000000) == 0x00000000)
236: return 3;
1.1.1.7 root 237: cpu_abort(env, "Unhandled itlb_replacement");
1.1 root 238: }
239:
240: /* Find the corresponding entry in the right TLB
241: Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
242: */
243: static int find_tlb_entry(CPUState * env, target_ulong address,
244: tlb_t * entries, uint8_t nbtlb, int use_asid)
245: {
246: int match = MMU_DTLB_MISS;
247: uint32_t start, end;
248: uint8_t asid;
249: int i;
250:
251: asid = env->pteh & 0xff;
252:
253: for (i = 0; i < nbtlb; i++) {
254: if (!entries[i].v)
255: continue; /* Invalid entry */
1.1.1.4 root 256: if (!entries[i].sh && use_asid && entries[i].asid != asid)
1.1 root 257: continue; /* Bad ASID */
258: start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
259: end = start + entries[i].size - 1;
260: if (address >= start && address <= end) { /* Match */
1.1.1.4 root 261: if (match != MMU_DTLB_MISS)
1.1 root 262: return MMU_DTLB_MULTIPLE; /* Multiple match */
263: match = i;
264: }
265: }
266: return match;
267: }
268:
1.1.1.4 root 269: static void increment_urc(CPUState * env)
270: {
271: uint8_t urb, urc;
272:
273: /* Increment URC */
274: urb = ((env->mmucr) >> 18) & 0x3f;
275: urc = ((env->mmucr) >> 10) & 0x3f;
276: urc++;
277: if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
278: urc = 0;
279: env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
280: }
281:
1.1.1.8 root 282: /* Copy and utlb entry into itlb
283: Return entry
284: */
285: static int copy_utlb_entry_itlb(CPUState *env, int utlb)
286: {
287: int itlb;
288:
289: tlb_t * ientry;
290: itlb = itlb_replacement(env);
291: ientry = &env->itlb[itlb];
292: if (ientry->v) {
293: tlb_flush_page(env, ientry->vpn << 10);
294: }
295: *ientry = env->utlb[utlb];
296: update_itlb_use(env, itlb);
297: return itlb;
298: }
299:
300: /* Find itlb entry
1.1 root 301: Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
302: */
1.1.1.4 root 303: static int find_itlb_entry(CPUState * env, target_ulong address,
1.1.1.8 root 304: int use_asid)
1.1 root 305: {
1.1.1.8 root 306: int e;
1.1 root 307:
308: e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
1.1.1.8 root 309: if (e == MMU_DTLB_MULTIPLE) {
1.1 root 310: e = MMU_ITLB_MULTIPLE;
1.1.1.8 root 311: } else if (e == MMU_DTLB_MISS) {
1.1.1.4 root 312: e = MMU_ITLB_MISS;
1.1.1.8 root 313: } else if (e >= 0) {
1.1 root 314: update_itlb_use(env, e);
1.1.1.8 root 315: }
1.1 root 316: return e;
317: }
318:
319: /* Find utlb entry
320: Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
1.1.1.4 root 321: static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
1.1 root 322: {
1.1.1.4 root 323: /* per utlb access */
324: increment_urc(env);
1.1 root 325:
326: /* Return entry */
327: return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
328: }
329:
330: /* Match address against MMU
331: Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
332: MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
333: MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
1.1.1.4 root 334: MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
335: MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
1.1 root 336: */
337: static int get_mmu_address(CPUState * env, target_ulong * physical,
338: int *prot, target_ulong address,
339: int rw, int access_type)
340: {
1.1.1.4 root 341: int use_asid, n;
1.1 root 342: tlb_t *matching = NULL;
343:
1.1.1.4 root 344: use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
1.1 root 345:
1.1.1.4 root 346: if (rw == 2) {
1.1.1.8 root 347: n = find_itlb_entry(env, address, use_asid);
1.1 root 348: if (n >= 0) {
349: matching = &env->itlb[n];
1.1.1.6 root 350: if (!(env->sr & SR_MD) && !(matching->pr & 2))
1.1 root 351: n = MMU_ITLB_VIOLATION;
352: else
1.1.1.7 root 353: *prot = PAGE_EXEC;
1.1.1.8 root 354: } else {
355: n = find_utlb_entry(env, address, use_asid);
356: if (n >= 0) {
357: n = copy_utlb_entry_itlb(env, n);
358: matching = &env->itlb[n];
359: if (!(env->sr & SR_MD) && !(matching->pr & 2)) {
360: n = MMU_ITLB_VIOLATION;
361: } else {
362: *prot = PAGE_READ | PAGE_EXEC;
363: if ((matching->pr & 1) && matching->d) {
364: *prot |= PAGE_WRITE;
365: }
366: }
367: } else if (n == MMU_DTLB_MULTIPLE) {
368: n = MMU_ITLB_MULTIPLE;
369: } else if (n == MMU_DTLB_MISS) {
370: n = MMU_ITLB_MISS;
371: }
1.1 root 372: }
373: } else {
374: n = find_utlb_entry(env, address, use_asid);
375: if (n >= 0) {
376: matching = &env->utlb[n];
1.1.1.7 root 377: if (!(env->sr & SR_MD) && !(matching->pr & 2)) {
378: n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
379: MMU_DTLB_VIOLATION_READ;
380: } else if ((rw == 1) && !(matching->pr & 1)) {
381: n = MMU_DTLB_VIOLATION_WRITE;
1.1.1.8 root 382: } else if ((rw == 1) && !matching->d) {
1.1.1.7 root 383: n = MMU_DTLB_INITIAL_WRITE;
384: } else {
385: *prot = PAGE_READ;
386: if ((matching->pr & 1) && matching->d) {
387: *prot |= PAGE_WRITE;
388: }
389: }
1.1 root 390: } else if (n == MMU_DTLB_MISS) {
1.1.1.4 root 391: n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
1.1 root 392: MMU_DTLB_MISS_READ;
393: }
394: }
395: if (n >= 0) {
1.1.1.7 root 396: n = MMU_OK;
1.1 root 397: *physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
398: (address & (matching->size - 1));
399: }
400: return n;
401: }
402:
1.1.1.4 root 403: static int get_physical_address(CPUState * env, target_ulong * physical,
404: int *prot, target_ulong address,
405: int rw, int access_type)
1.1 root 406: {
407: /* P1, P2 and P4 areas do not use translation */
408: if ((address >= 0x80000000 && address < 0xc0000000) ||
409: address >= 0xe0000000) {
410: if (!(env->sr & SR_MD)
1.1.1.6 root 411: && (address < 0xe0000000 || address >= 0xe4000000)) {
1.1 root 412: /* Unauthorized access in user mode (only store queues are available) */
413: fprintf(stderr, "Unauthorized access\n");
1.1.1.4 root 414: if (rw == 0)
415: return MMU_DADDR_ERROR_READ;
416: else if (rw == 1)
417: return MMU_DADDR_ERROR_WRITE;
418: else
419: return MMU_IADDR_ERROR;
420: }
421: if (address >= 0x80000000 && address < 0xc0000000) {
422: /* Mask upper 3 bits for P1 and P2 areas */
423: *physical = address & 0x1fffffff;
424: } else {
425: *physical = address;
1.1 root 426: }
1.1.1.7 root 427: *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1.1 root 428: return MMU_OK;
429: }
430:
431: /* If MMU is disabled, return the corresponding physical page */
1.1.1.8 root 432: if (!(env->mmucr & MMUCR_AT)) {
1.1 root 433: *physical = address & 0x1FFFFFFF;
1.1.1.7 root 434: *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1.1 root 435: return MMU_OK;
436: }
437:
438: /* We need to resort to the MMU */
439: return get_mmu_address(env, physical, prot, address, rw, access_type);
440: }
441:
442: int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
1.1.1.3 root 443: int mmu_idx, int is_softmmu)
1.1 root 444: {
1.1.1.7 root 445: target_ulong physical;
1.1 root 446: int prot, ret, access_type;
447:
448: access_type = ACCESS_INT;
449: ret =
450: get_physical_address(env, &physical, &prot, address, rw,
451: access_type);
452:
453: if (ret != MMU_OK) {
454: env->tea = address;
1.1.1.8 root 455: if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) {
456: env->pteh = (env->pteh & PTEH_ASID_MASK) |
457: (address & PTEH_VPN_MASK);
458: }
1.1 root 459: switch (ret) {
460: case MMU_ITLB_MISS:
461: case MMU_DTLB_MISS_READ:
462: env->exception_index = 0x040;
463: break;
464: case MMU_DTLB_MULTIPLE:
465: case MMU_ITLB_MULTIPLE:
466: env->exception_index = 0x140;
467: break;
468: case MMU_ITLB_VIOLATION:
469: env->exception_index = 0x0a0;
470: break;
471: case MMU_DTLB_MISS_WRITE:
472: env->exception_index = 0x060;
473: break;
474: case MMU_DTLB_INITIAL_WRITE:
475: env->exception_index = 0x080;
476: break;
477: case MMU_DTLB_VIOLATION_READ:
478: env->exception_index = 0x0a0;
479: break;
480: case MMU_DTLB_VIOLATION_WRITE:
481: env->exception_index = 0x0c0;
482: break;
1.1.1.4 root 483: case MMU_IADDR_ERROR:
484: case MMU_DADDR_ERROR_READ:
1.1.1.8 root 485: env->exception_index = 0x0e0;
1.1.1.4 root 486: break;
487: case MMU_DADDR_ERROR_WRITE:
488: env->exception_index = 0x100;
489: break;
1.1 root 490: default:
1.1.1.7 root 491: cpu_abort(env, "Unhandled MMU fault");
1.1 root 492: }
493: return 1;
494: }
495:
1.1.1.7 root 496: address &= TARGET_PAGE_MASK;
497: physical &= TARGET_PAGE_MASK;
1.1 root 498:
1.1.1.7 root 499: tlb_set_page(env, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
500: return 0;
1.1 root 501: }
1.1.1.2 root 502:
1.1.1.3 root 503: target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
1.1.1.2 root 504: {
505: target_ulong physical;
506: int prot;
507:
1.1.1.4 root 508: get_physical_address(env, &physical, &prot, addr, 0, 0);
1.1.1.2 root 509: return physical;
510: }
511:
1.1.1.4 root 512: void cpu_load_tlb(CPUSH4State * env)
513: {
514: int n = cpu_mmucr_urc(env->mmucr);
515: tlb_t * entry = &env->utlb[n];
516:
517: if (entry->v) {
518: /* Overwriting valid entry in utlb. */
519: target_ulong address = entry->vpn << 10;
1.1.1.7 root 520: tlb_flush_page(env, address);
1.1.1.4 root 521: }
522:
523: /* Take values into cpu status from registers. */
524: entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
525: entry->vpn = cpu_pteh_vpn(env->pteh);
526: entry->v = (uint8_t)cpu_ptel_v(env->ptel);
527: entry->ppn = cpu_ptel_ppn(env->ptel);
528: entry->sz = (uint8_t)cpu_ptel_sz(env->ptel);
529: switch (entry->sz) {
530: case 0: /* 00 */
531: entry->size = 1024; /* 1K */
532: break;
533: case 1: /* 01 */
534: entry->size = 1024 * 4; /* 4K */
535: break;
536: case 2: /* 10 */
537: entry->size = 1024 * 64; /* 64K */
538: break;
539: case 3: /* 11 */
540: entry->size = 1024 * 1024; /* 1M */
541: break;
542: default:
1.1.1.7 root 543: cpu_abort(env, "Unhandled load_tlb");
1.1.1.4 root 544: break;
545: }
546: entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
547: entry->c = (uint8_t)cpu_ptel_c(env->ptel);
548: entry->pr = (uint8_t)cpu_ptel_pr(env->ptel);
549: entry->d = (uint8_t)cpu_ptel_d(env->ptel);
550: entry->wt = (uint8_t)cpu_ptel_wt(env->ptel);
551: entry->sa = (uint8_t)cpu_ptea_sa(env->ptea);
552: entry->tc = (uint8_t)cpu_ptea_tc(env->ptea);
553: }
554:
1.1.1.6 root 555: void cpu_sh4_invalidate_tlb(CPUSH4State *s)
556: {
557: int i;
558:
559: /* UTLB */
560: for (i = 0; i < UTLB_SIZE; i++) {
561: tlb_t * entry = &s->utlb[i];
562: entry->v = 0;
563: }
564: /* ITLB */
1.1.1.8 root 565: for (i = 0; i < ITLB_SIZE; i++) {
566: tlb_t * entry = &s->itlb[i];
1.1.1.6 root 567: entry->v = 0;
568: }
569:
570: tlb_flush(s, 1);
571: }
572:
1.1.1.8 root 573: uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
574: target_phys_addr_t addr)
575: {
576: int index = (addr & 0x00000300) >> 8;
577: tlb_t * entry = &s->itlb[index];
578:
579: return (entry->vpn << 10) |
580: (entry->v << 8) |
581: (entry->asid);
582: }
583:
584: void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, target_phys_addr_t addr,
585: uint32_t mem_value)
586: {
587: uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
588: uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
589: uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
590:
591: int index = (addr & 0x00000300) >> 8;
592: tlb_t * entry = &s->itlb[index];
593: if (entry->v) {
594: /* Overwriting valid entry in itlb. */
595: target_ulong address = entry->vpn << 10;
596: tlb_flush_page(s, address);
597: }
598: entry->asid = asid;
599: entry->vpn = vpn;
600: entry->v = v;
601: }
602:
603: uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
604: target_phys_addr_t addr)
605: {
606: int array = (addr & 0x00800000) >> 23;
607: int index = (addr & 0x00000300) >> 8;
608: tlb_t * entry = &s->itlb[index];
609:
610: if (array == 0) {
611: /* ITLB Data Array 1 */
612: return (entry->ppn << 10) |
613: (entry->v << 8) |
614: (entry->pr << 5) |
615: ((entry->sz & 1) << 6) |
616: ((entry->sz & 2) << 4) |
617: (entry->c << 3) |
618: (entry->sh << 1);
619: } else {
620: /* ITLB Data Array 2 */
621: return (entry->tc << 1) |
622: (entry->sa);
623: }
624: }
625:
626: void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, target_phys_addr_t addr,
627: uint32_t mem_value)
628: {
629: int array = (addr & 0x00800000) >> 23;
630: int index = (addr & 0x00000300) >> 8;
631: tlb_t * entry = &s->itlb[index];
632:
633: if (array == 0) {
634: /* ITLB Data Array 1 */
635: if (entry->v) {
636: /* Overwriting valid entry in utlb. */
637: target_ulong address = entry->vpn << 10;
638: tlb_flush_page(s, address);
639: }
640: entry->ppn = (mem_value & 0x1ffffc00) >> 10;
641: entry->v = (mem_value & 0x00000100) >> 8;
642: entry->sz = (mem_value & 0x00000080) >> 6 |
643: (mem_value & 0x00000010) >> 4;
644: entry->pr = (mem_value & 0x00000040) >> 5;
645: entry->c = (mem_value & 0x00000008) >> 3;
646: entry->sh = (mem_value & 0x00000002) >> 1;
647: } else {
648: /* ITLB Data Array 2 */
649: entry->tc = (mem_value & 0x00000008) >> 3;
650: entry->sa = (mem_value & 0x00000007);
651: }
652: }
653:
654: uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
655: target_phys_addr_t addr)
656: {
657: int index = (addr & 0x00003f00) >> 8;
658: tlb_t * entry = &s->utlb[index];
659:
660: increment_urc(s); /* per utlb access */
661:
662: return (entry->vpn << 10) |
663: (entry->v << 8) |
664: (entry->asid);
665: }
666:
1.1.1.4 root 667: void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
668: uint32_t mem_value)
669: {
670: int associate = addr & 0x0000080;
671: uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
672: uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
673: uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
674: uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
675: int use_asid = (s->mmucr & MMUCR_SV) == 0 || (s->sr & SR_MD) == 0;
676:
677: if (associate) {
678: int i;
679: tlb_t * utlb_match_entry = NULL;
680: int needs_tlb_flush = 0;
681:
682: /* search UTLB */
683: for (i = 0; i < UTLB_SIZE; i++) {
684: tlb_t * entry = &s->utlb[i];
685: if (!entry->v)
686: continue;
687:
688: if (entry->vpn == vpn
689: && (!use_asid || entry->asid == asid || entry->sh)) {
690: if (utlb_match_entry) {
691: /* Multiple TLB Exception */
692: s->exception_index = 0x140;
693: s->tea = addr;
694: break;
695: }
696: if (entry->v && !v)
697: needs_tlb_flush = 1;
698: entry->v = v;
699: entry->d = d;
700: utlb_match_entry = entry;
701: }
702: increment_urc(s); /* per utlb access */
703: }
704:
705: /* search ITLB */
706: for (i = 0; i < ITLB_SIZE; i++) {
707: tlb_t * entry = &s->itlb[i];
708: if (entry->vpn == vpn
709: && (!use_asid || entry->asid == asid || entry->sh)) {
710: if (entry->v && !v)
711: needs_tlb_flush = 1;
712: if (utlb_match_entry)
713: *entry = *utlb_match_entry;
714: else
715: entry->v = v;
716: break;
717: }
718: }
719:
720: if (needs_tlb_flush)
721: tlb_flush_page(s, vpn << 10);
722:
723: } else {
724: int index = (addr & 0x00003f00) >> 8;
725: tlb_t * entry = &s->utlb[index];
726: if (entry->v) {
727: /* Overwriting valid entry in utlb. */
728: target_ulong address = entry->vpn << 10;
1.1.1.7 root 729: tlb_flush_page(s, address);
1.1.1.4 root 730: }
731: entry->asid = asid;
732: entry->vpn = vpn;
733: entry->d = d;
734: entry->v = v;
735: increment_urc(s);
736: }
737: }
738:
1.1.1.8 root 739: uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
740: target_phys_addr_t addr)
741: {
742: int array = (addr & 0x00800000) >> 23;
743: int index = (addr & 0x00003f00) >> 8;
744: tlb_t * entry = &s->utlb[index];
745:
746: increment_urc(s); /* per utlb access */
747:
748: if (array == 0) {
749: /* ITLB Data Array 1 */
750: return (entry->ppn << 10) |
751: (entry->v << 8) |
752: (entry->pr << 5) |
753: ((entry->sz & 1) << 6) |
754: ((entry->sz & 2) << 4) |
755: (entry->c << 3) |
756: (entry->d << 2) |
757: (entry->sh << 1) |
758: (entry->wt);
759: } else {
760: /* ITLB Data Array 2 */
761: return (entry->tc << 1) |
762: (entry->sa);
763: }
764: }
765:
766: void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, target_phys_addr_t addr,
767: uint32_t mem_value)
768: {
769: int array = (addr & 0x00800000) >> 23;
770: int index = (addr & 0x00003f00) >> 8;
771: tlb_t * entry = &s->utlb[index];
772:
773: increment_urc(s); /* per utlb access */
774:
775: if (array == 0) {
776: /* UTLB Data Array 1 */
777: if (entry->v) {
778: /* Overwriting valid entry in utlb. */
779: target_ulong address = entry->vpn << 10;
780: tlb_flush_page(s, address);
781: }
782: entry->ppn = (mem_value & 0x1ffffc00) >> 10;
783: entry->v = (mem_value & 0x00000100) >> 8;
784: entry->sz = (mem_value & 0x00000080) >> 6 |
785: (mem_value & 0x00000010) >> 4;
786: entry->pr = (mem_value & 0x00000060) >> 5;
787: entry->c = (mem_value & 0x00000008) >> 3;
788: entry->d = (mem_value & 0x00000004) >> 2;
789: entry->sh = (mem_value & 0x00000002) >> 1;
790: entry->wt = (mem_value & 0x00000001);
791: } else {
792: /* UTLB Data Array 2 */
793: entry->tc = (mem_value & 0x00000008) >> 3;
794: entry->sa = (mem_value & 0x00000007);
795: }
796: }
797:
1.1.1.5 root 798: int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
799: {
800: int n;
801: int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
802:
803: /* check area */
804: if (env->sr & SR_MD) {
805: /* For previledged mode, P2 and P4 area is not cachable. */
806: if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
807: return 0;
808: } else {
809: /* For user mode, only U0 area is cachable. */
810: if (0x80000000 <= addr)
811: return 0;
812: }
813:
814: /*
815: * TODO : Evaluate CCR and check if the cache is on or off.
816: * Now CCR is not in CPUSH4State, but in SH7750State.
817: * When you move the ccr inot CPUSH4State, the code will be
818: * as follows.
819: */
820: #if 0
821: /* check if operand cache is enabled or not. */
822: if (!(env->ccr & 1))
823: return 0;
824: #endif
825:
826: /* if MMU is off, no check for TLB. */
827: if (env->mmucr & MMUCR_AT)
828: return 1;
829:
830: /* check TLB */
831: n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
832: if (n >= 0)
833: return env->itlb[n].c;
834:
835: n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
836: if (n >= 0)
837: return env->utlb[n].c;
838:
839: return 0;
840: }
841:
1.1.1.2 root 842: #endif
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