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Annotation of qemu/target-sparc/cpu.h, revision 1.1

1.1     ! root        1: #ifndef CPU_SPARC_H
        !             2: #define CPU_SPARC_H
        !             3: 
        !             4: #include "config.h"
        !             5: 
        !             6: #if !defined(TARGET_SPARC64)
        !             7: #define TARGET_LONG_BITS 32
        !             8: #define TARGET_FPREGS 32
        !             9: #define TARGET_PAGE_BITS 12 /* 4k */
        !            10: #else
        !            11: #define TARGET_LONG_BITS 64
        !            12: #define TARGET_FPREGS 64
        !            13: #define TARGET_PAGE_BITS 12 /* XXX */
        !            14: #endif
        !            15: #define TARGET_FPREG_T float
        !            16: 
        !            17: #include "cpu-defs.h"
        !            18: 
        !            19: #include "softfloat.h"
        !            20: 
        !            21: #define TARGET_HAS_ICE 1
        !            22: 
        !            23: /*#define EXCP_INTERRUPT 0x100*/
        !            24: 
        !            25: /* trap definitions */
        !            26: #ifndef TARGET_SPARC64
        !            27: #define TT_TFAULT   0x01
        !            28: #define TT_ILL_INSN 0x02
        !            29: #define TT_PRIV_INSN 0x03
        !            30: #define TT_NFPU_INSN 0x04
        !            31: #define TT_WIN_OVF  0x05
        !            32: #define TT_WIN_UNF  0x06 
        !            33: #define TT_FP_EXCP  0x08
        !            34: #define TT_DFAULT   0x09
        !            35: #define TT_EXTINT   0x10
        !            36: #define TT_DIV_ZERO 0x2a
        !            37: #define TT_TRAP     0x80
        !            38: #else
        !            39: #define TT_TFAULT   0x08
        !            40: #define TT_TMISS    0x09
        !            41: #define TT_ILL_INSN 0x10
        !            42: #define TT_PRIV_INSN 0x11
        !            43: #define TT_NFPU_INSN 0x20
        !            44: #define TT_FP_EXCP  0x21
        !            45: #define TT_CLRWIN   0x24
        !            46: #define TT_DIV_ZERO 0x28
        !            47: #define TT_DFAULT   0x30
        !            48: #define TT_DMISS    0x31
        !            49: #define TT_DPROT    0x32
        !            50: #define TT_PRIV_ACT 0x37
        !            51: #define TT_EXTINT   0x40
        !            52: #define TT_SPILL    0x80
        !            53: #define TT_FILL     0xc0
        !            54: #define TT_WOTHER   0x10
        !            55: #define TT_TRAP     0x100
        !            56: #endif
        !            57: 
        !            58: #define PSR_NEG   (1<<23)
        !            59: #define PSR_ZERO  (1<<22)
        !            60: #define PSR_OVF   (1<<21)
        !            61: #define PSR_CARRY (1<<20)
        !            62: #define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
        !            63: #define PSR_EF    (1<<12)
        !            64: #define PSR_PIL   0xf00
        !            65: #define PSR_S     (1<<7)
        !            66: #define PSR_PS    (1<<6)
        !            67: #define PSR_ET    (1<<5)
        !            68: #define PSR_CWP   0x1f
        !            69: 
        !            70: /* Trap base register */
        !            71: #define TBR_BASE_MASK 0xfffff000
        !            72: 
        !            73: #if defined(TARGET_SPARC64)
        !            74: #define PS_IG    (1<<11)
        !            75: #define PS_MG    (1<<10)
        !            76: #define PS_RED   (1<<5)
        !            77: #define PS_PEF   (1<<4)
        !            78: #define PS_AM    (1<<3)
        !            79: #define PS_PRIV  (1<<2)
        !            80: #define PS_IE    (1<<1)
        !            81: #define PS_AG    (1<<0)
        !            82: #endif
        !            83: 
        !            84: /* Fcc */
        !            85: #define FSR_RD1        (1<<31)
        !            86: #define FSR_RD0        (1<<30)
        !            87: #define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
        !            88: #define FSR_RD_NEAREST 0
        !            89: #define FSR_RD_ZERO    FSR_RD0
        !            90: #define FSR_RD_POS     FSR_RD1
        !            91: #define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)
        !            92: 
        !            93: #define FSR_NVM   (1<<27)
        !            94: #define FSR_OFM   (1<<26)
        !            95: #define FSR_UFM   (1<<25)
        !            96: #define FSR_DZM   (1<<24)
        !            97: #define FSR_NXM   (1<<23)
        !            98: #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
        !            99: 
        !           100: #define FSR_NVA   (1<<9)
        !           101: #define FSR_OFA   (1<<8)
        !           102: #define FSR_UFA   (1<<7)
        !           103: #define FSR_DZA   (1<<6)
        !           104: #define FSR_NXA   (1<<5)
        !           105: #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
        !           106: 
        !           107: #define FSR_NVC   (1<<4)
        !           108: #define FSR_OFC   (1<<3)
        !           109: #define FSR_UFC   (1<<2)
        !           110: #define FSR_DZC   (1<<1)
        !           111: #define FSR_NXC   (1<<0)
        !           112: #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
        !           113: 
        !           114: #define FSR_FTT2   (1<<16)
        !           115: #define FSR_FTT1   (1<<15)
        !           116: #define FSR_FTT0   (1<<14)
        !           117: #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
        !           118: #define FSR_FTT_IEEE_EXCP (1 << 14)
        !           119: #define FSR_FTT_UNIMPFPOP (3 << 14)
        !           120: #define FSR_FTT_INVAL_FPR (6 << 14)
        !           121: 
        !           122: #define FSR_FCC1  (1<<11)
        !           123: #define FSR_FCC0  (1<<10)
        !           124: 
        !           125: /* MMU */
        !           126: #define MMU_E    (1<<0)
        !           127: #define MMU_NF   (1<<1)
        !           128: 
        !           129: #define PTE_ENTRYTYPE_MASK 3
        !           130: #define PTE_ACCESS_MASK    0x1c
        !           131: #define PTE_ACCESS_SHIFT   2
        !           132: #define PTE_PPN_SHIFT      7
        !           133: #define PTE_ADDR_MASK      0xffffff00
        !           134: 
        !           135: #define PG_ACCESSED_BIT        5
        !           136: #define PG_MODIFIED_BIT        6
        !           137: #define PG_CACHE_BIT    7
        !           138: 
        !           139: #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
        !           140: #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
        !           141: #define PG_CACHE_MASK    (1 << PG_CACHE_BIT)
        !           142: 
        !           143: /* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
        !           144: #define NWINDOWS  8
        !           145: 
        !           146: typedef struct CPUSPARCState {
        !           147:     target_ulong gregs[8]; /* general registers */
        !           148:     target_ulong *regwptr; /* pointer to current register window */
        !           149:     TARGET_FPREG_T    fpr[TARGET_FPREGS];  /* floating point registers */
        !           150:     target_ulong pc;       /* program counter */
        !           151:     target_ulong npc;      /* next program counter */
        !           152:     target_ulong y;        /* multiply/divide register */
        !           153:     uint32_t psr;      /* processor state register */
        !           154:     target_ulong fsr;      /* FPU state register */
        !           155:     uint32_t cwp;      /* index of current register window (extracted
        !           156:                           from PSR) */
        !           157:     uint32_t wim;      /* window invalid mask */
        !           158:     target_ulong tbr;  /* trap base register */
        !           159:     int      psrs;     /* supervisor mode (extracted from PSR) */
        !           160:     int      psrps;    /* previous supervisor mode */
        !           161:     int      psret;    /* enable traps */
        !           162:     uint32_t psrpil;   /* interrupt level */
        !           163:     int      psref;    /* enable fpu */
        !           164:     jmp_buf  jmp_env;
        !           165:     int user_mode_only;
        !           166:     int exception_index;
        !           167:     int interrupt_index;
        !           168:     int interrupt_request;
        !           169:     struct TranslationBlock *current_tb;
        !           170:     void *opaque;
        !           171:     /* NOTE: we allow 8 more registers to handle wrapping */
        !           172:     target_ulong regbase[NWINDOWS * 16 + 8];
        !           173: 
        !           174:     /* in order to avoid passing too many arguments to the memory
        !           175:        write helpers, we store some rarely used information in the CPU
        !           176:        context) */
        !           177:     unsigned long mem_write_pc; /* host pc at which the memory was
        !           178:                                    written */
        !           179:     target_ulong mem_write_vaddr; /* target virtual addr at which the
        !           180:                                       memory was written */
        !           181:     /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
        !           182:     CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
        !           183:     CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
        !           184:     /* MMU regs */
        !           185: #if defined(TARGET_SPARC64)
        !           186:     uint64_t lsu;
        !           187: #define DMMU_E 0x8
        !           188: #define IMMU_E 0x4
        !           189:     uint64_t immuregs[16];
        !           190:     uint64_t dmmuregs[16];
        !           191:     uint64_t itlb_tag[64];
        !           192:     uint64_t itlb_tte[64];
        !           193:     uint64_t dtlb_tag[64];
        !           194:     uint64_t dtlb_tte[64];
        !           195: #else
        !           196:     uint32_t mmuregs[16];
        !           197: #endif
        !           198:     /* temporary float registers */
        !           199:     float ft0, ft1;
        !           200:     double dt0, dt1;
        !           201:     float_status fp_status;
        !           202: #if defined(TARGET_SPARC64)
        !           203: #define MAXTL 4
        !           204:     uint64_t t0, t1, t2;
        !           205:     uint64_t tpc[MAXTL];
        !           206:     uint64_t tnpc[MAXTL];
        !           207:     uint64_t tstate[MAXTL];
        !           208:     uint32_t tt[MAXTL];
        !           209:     uint32_t xcc;              /* Extended integer condition codes */
        !           210:     uint32_t asi;
        !           211:     uint32_t pstate;
        !           212:     uint32_t tl;
        !           213:     uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
        !           214:     uint64_t agregs[8]; /* alternate general registers */
        !           215:     uint64_t bgregs[8]; /* backup for normal global registers */
        !           216:     uint64_t igregs[8]; /* interrupt general registers */
        !           217:     uint64_t mgregs[8]; /* mmu general registers */
        !           218:     uint64_t version;
        !           219:     uint64_t fprs;
        !           220:     uint64_t tick_cmpr, stick_cmpr;
        !           221: #endif
        !           222: #if !defined(TARGET_SPARC64) && !defined(reg_T2)
        !           223:     target_ulong t2;
        !           224: #endif
        !           225: 
        !           226:     /* ice debug support */
        !           227:     target_ulong breakpoints[MAX_BREAKPOINTS];
        !           228:     int nb_breakpoints;
        !           229:     int singlestep_enabled; /* XXX: should use CPU single step mode instead */
        !           230: 
        !           231: } CPUSPARCState;
        !           232: #if defined(TARGET_SPARC64)
        !           233: #define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
        !           234: #define PUT_FSR32(env, val) do { uint32_t _tmp = val;                  \
        !           235:        env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL);  \
        !           236:     } while (0)
        !           237: #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
        !           238: #define PUT_FSR64(env, val) do { uint64_t _tmp = val;  \
        !           239:        env->fsr = _tmp & 0x3fcfc1c3ffULL;              \
        !           240:     } while (0)
        !           241: // Manuf 0x17, version 0x11, mask 0 (UltraSparc-II)
        !           242: #define GET_VER(env) ((0x17ULL << 48) | (0x11ULL << 32) |              \
        !           243:                      (0 << 24) | (MAXTL << 8) | (NWINDOWS - 1))
        !           244: #else
        !           245: #define GET_FSR32(env) (env->fsr)
        !           246: #define PUT_FSR32(env, val) do { uint32_t _tmp = val;  \
        !           247:        env->fsr = _tmp & 0xcfc1ffff;                   \
        !           248:     } while (0)
        !           249: #endif
        !           250: 
        !           251: CPUSPARCState *cpu_sparc_init(void);
        !           252: int cpu_sparc_exec(CPUSPARCState *s);
        !           253: int cpu_sparc_close(CPUSPARCState *s);
        !           254: void cpu_get_fp64(uint64_t *pmant, uint16_t *pexp, double f);
        !           255: double cpu_put_fp64(uint64_t mant, uint16_t exp);
        !           256: 
        !           257: /* Fake impl 0, version 4 */
        !           258: #define GET_PSR(env) ((0 << 28) | (4 << 24) | (env->psr & PSR_ICC) |   \
        !           259:                      (env->psref? PSR_EF : 0) |                        \
        !           260:                      (env->psrpil << 8) |                              \
        !           261:                      (env->psrs? PSR_S : 0) |                          \
        !           262:                      (env->psrps? PSR_PS : 0) |                        \
        !           263:                      (env->psret? PSR_ET : 0) | env->cwp)
        !           264: 
        !           265: #ifndef NO_CPU_IO_DEFS
        !           266: void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
        !           267: #endif
        !           268: 
        !           269: #define PUT_PSR(env, val) do { int _tmp = val;                         \
        !           270:        env->psr = _tmp & PSR_ICC;                                      \
        !           271:        env->psref = (_tmp & PSR_EF)? 1 : 0;                            \
        !           272:        env->psrpil = (_tmp & PSR_PIL) >> 8;                            \
        !           273:        env->psrs = (_tmp & PSR_S)? 1 : 0;                              \
        !           274:        env->psrps = (_tmp & PSR_PS)? 1 : 0;                            \
        !           275:        env->psret = (_tmp & PSR_ET)? 1 : 0;                            \
        !           276:        cpu_set_cwp(env, _tmp & PSR_CWP & (NWINDOWS - 1));              \
        !           277:     } while (0)
        !           278: 
        !           279: #ifdef TARGET_SPARC64
        !           280: #define GET_CCR(env) ((env->xcc << 4) | (env->psr & PSR_ICC))
        !           281: #define PUT_CCR(env, val) do { int _tmp = val;                         \
        !           282:        env->xcc = _tmp >> 4;                                           \
        !           283:        env->psr = (_tmp & 0xf) << 20;                                  \
        !           284:     } while (0)
        !           285: #endif
        !           286: 
        !           287: struct siginfo;
        !           288: int cpu_sparc_signal_handler(int hostsignum, struct siginfo *info, void *puc);
        !           289: 
        !           290: #include "cpu-all.h"
        !           291: 
        !           292: #endif

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