![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to cpu.h CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Qemu by Fabrice Bellard] / qemu / target-sparc|
Return to cpu.h CVS log | Up to [Qemu by Fabrice Bellard] / qemu / target-sparc |
1.1 root 1: #ifndef CPU_SPARC_H
2: #define CPU_SPARC_H
3:
4: #include "config.h"
1.1.1.10! root 5: #include "qemu-common.h"
1.1 root 6:
7: #if !defined(TARGET_SPARC64)
8: #define TARGET_LONG_BITS 32
9: #define TARGET_FPREGS 32
10: #define TARGET_PAGE_BITS 12 /* 4k */
1.1.1.9 root 11: #define TARGET_PHYS_ADDR_SPACE_BITS 36
12: #define TARGET_VIRT_ADDR_SPACE_BITS 32
1.1 root 13: #else
14: #define TARGET_LONG_BITS 64
15: #define TARGET_FPREGS 64
1.1.1.5 root 16: #define TARGET_PAGE_BITS 13 /* 8k */
1.1.1.9 root 17: #define TARGET_PHYS_ADDR_SPACE_BITS 41
18: # ifdef TARGET_ABI32
19: # define TARGET_VIRT_ADDR_SPACE_BITS 32
20: # else
21: # define TARGET_VIRT_ADDR_SPACE_BITS 44
22: # endif
1.1 root 23: #endif
24:
1.1.1.7 root 25: #define CPUState struct CPUSPARCState
1.1.1.5 root 26:
1.1 root 27: #include "cpu-defs.h"
28:
29: #include "softfloat.h"
30:
31: #define TARGET_HAS_ICE 1
32:
1.1.1.4 root 33: #if !defined(TARGET_SPARC64)
1.1.1.5 root 34: #define ELF_MACHINE EM_SPARC
1.1.1.4 root 35: #else
1.1.1.5 root 36: #define ELF_MACHINE EM_SPARCV9
1.1.1.4 root 37: #endif
38:
1.1 root 39: /*#define EXCP_INTERRUPT 0x100*/
40:
41: /* trap definitions */
42: #ifndef TARGET_SPARC64
43: #define TT_TFAULT 0x01
44: #define TT_ILL_INSN 0x02
45: #define TT_PRIV_INSN 0x03
46: #define TT_NFPU_INSN 0x04
47: #define TT_WIN_OVF 0x05
1.1.1.5 root 48: #define TT_WIN_UNF 0x06
49: #define TT_UNALIGNED 0x07
1.1 root 50: #define TT_FP_EXCP 0x08
51: #define TT_DFAULT 0x09
1.1.1.5 root 52: #define TT_TOVF 0x0a
1.1 root 53: #define TT_EXTINT 0x10
1.1.1.5 root 54: #define TT_CODE_ACCESS 0x21
1.1.1.6 root 55: #define TT_UNIMP_FLUSH 0x25
1.1.1.5 root 56: #define TT_DATA_ACCESS 0x29
1.1 root 57: #define TT_DIV_ZERO 0x2a
1.1.1.5 root 58: #define TT_NCP_INSN 0x24
1.1 root 59: #define TT_TRAP 0x80
60: #else
1.1.1.8 root 61: #define TT_POWER_ON_RESET 0x01
1.1 root 62: #define TT_TFAULT 0x08
1.1.1.5 root 63: #define TT_CODE_ACCESS 0x0a
1.1 root 64: #define TT_ILL_INSN 0x10
1.1.1.6 root 65: #define TT_UNIMP_FLUSH TT_ILL_INSN
1.1 root 66: #define TT_PRIV_INSN 0x11
67: #define TT_NFPU_INSN 0x20
68: #define TT_FP_EXCP 0x21
1.1.1.5 root 69: #define TT_TOVF 0x23
1.1 root 70: #define TT_CLRWIN 0x24
71: #define TT_DIV_ZERO 0x28
72: #define TT_DFAULT 0x30
1.1.1.5 root 73: #define TT_DATA_ACCESS 0x32
74: #define TT_UNALIGNED 0x34
1.1 root 75: #define TT_PRIV_ACT 0x37
76: #define TT_EXTINT 0x40
1.1.1.6 root 77: #define TT_IVEC 0x60
78: #define TT_TMISS 0x64
79: #define TT_DMISS 0x68
80: #define TT_DPROT 0x6c
1.1 root 81: #define TT_SPILL 0x80
82: #define TT_FILL 0xc0
1.1.1.9 root 83: #define TT_WOTHER (1 << 5)
1.1 root 84: #define TT_TRAP 0x100
85: #endif
86:
1.1.1.6 root 87: #define PSR_NEG_SHIFT 23
88: #define PSR_NEG (1 << PSR_NEG_SHIFT)
89: #define PSR_ZERO_SHIFT 22
90: #define PSR_ZERO (1 << PSR_ZERO_SHIFT)
91: #define PSR_OVF_SHIFT 21
92: #define PSR_OVF (1 << PSR_OVF_SHIFT)
93: #define PSR_CARRY_SHIFT 20
94: #define PSR_CARRY (1 << PSR_CARRY_SHIFT)
1.1 root 95: #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
1.1.1.9 root 96: #if !defined(TARGET_SPARC64)
1.1 root 97: #define PSR_EF (1<<12)
98: #define PSR_PIL 0xf00
99: #define PSR_S (1<<7)
100: #define PSR_PS (1<<6)
101: #define PSR_ET (1<<5)
102: #define PSR_CWP 0x1f
1.1.1.9 root 103: #endif
1.1 root 104:
1.1.1.7 root 105: #define CC_SRC (env->cc_src)
106: #define CC_SRC2 (env->cc_src2)
107: #define CC_DST (env->cc_dst)
108: #define CC_OP (env->cc_op)
109:
110: enum {
111: CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
112: CC_OP_FLAGS, /* all cc are back in status register */
113: CC_OP_DIV, /* modify N, Z and V, C = 0*/
114: CC_OP_ADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
115: CC_OP_ADDX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
116: CC_OP_TADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
117: CC_OP_TADDTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
118: CC_OP_SUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
119: CC_OP_SUBX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
120: CC_OP_TSUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
121: CC_OP_TSUBTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
122: CC_OP_LOGIC, /* modify N and Z, C = V = 0, CC_DST = res */
123: CC_OP_NB,
124: };
125:
1.1 root 126: /* Trap base register */
127: #define TBR_BASE_MASK 0xfffff000
128:
129: #if defined(TARGET_SPARC64)
1.1.1.7 root 130: #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */
131: #define PS_IG (1<<11) /* v9, zero on UA2007 */
132: #define PS_MG (1<<10) /* v9, zero on UA2007 */
133: #define PS_CLE (1<<9) /* UA2007 */
134: #define PS_TLE (1<<8) /* UA2007 */
1.1.1.5 root 135: #define PS_RMO (1<<7)
1.1.1.7 root 136: #define PS_RED (1<<5) /* v9, zero on UA2007 */
137: #define PS_PEF (1<<4) /* enable fpu */
138: #define PS_AM (1<<3) /* address mask */
1.1 root 139: #define PS_PRIV (1<<2)
140: #define PS_IE (1<<1)
1.1.1.7 root 141: #define PS_AG (1<<0) /* v9, zero on UA2007 */
1.1.1.3 root 142:
143: #define FPRS_FEF (1<<2)
1.1.1.5 root 144:
145: #define HS_PRIV (1<<2)
1.1 root 146: #endif
147:
148: /* Fcc */
1.1.1.6 root 149: #define FSR_RD1 (1ULL << 31)
150: #define FSR_RD0 (1ULL << 30)
1.1 root 151: #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
152: #define FSR_RD_NEAREST 0
153: #define FSR_RD_ZERO FSR_RD0
154: #define FSR_RD_POS FSR_RD1
155: #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
156:
1.1.1.6 root 157: #define FSR_NVM (1ULL << 27)
158: #define FSR_OFM (1ULL << 26)
159: #define FSR_UFM (1ULL << 25)
160: #define FSR_DZM (1ULL << 24)
161: #define FSR_NXM (1ULL << 23)
1.1 root 162: #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
163:
1.1.1.6 root 164: #define FSR_NVA (1ULL << 9)
165: #define FSR_OFA (1ULL << 8)
166: #define FSR_UFA (1ULL << 7)
167: #define FSR_DZA (1ULL << 6)
168: #define FSR_NXA (1ULL << 5)
1.1 root 169: #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
170:
1.1.1.6 root 171: #define FSR_NVC (1ULL << 4)
172: #define FSR_OFC (1ULL << 3)
173: #define FSR_UFC (1ULL << 2)
174: #define FSR_DZC (1ULL << 1)
175: #define FSR_NXC (1ULL << 0)
1.1 root 176: #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
177:
1.1.1.6 root 178: #define FSR_FTT2 (1ULL << 16)
179: #define FSR_FTT1 (1ULL << 15)
180: #define FSR_FTT0 (1ULL << 14)
181: //gcc warns about constant overflow for ~FSR_FTT_MASK
182: //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
183: #ifdef TARGET_SPARC64
184: #define FSR_FTT_NMASK 0xfffffffffffe3fffULL
185: #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
186: #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL
187: #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL
188: #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
189: #else
190: #define FSR_FTT_NMASK 0xfffe3fffULL
191: #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
192: #define FSR_LDFSR_OLDMASK 0x000fc000ULL
193: #endif
194: #define FSR_LDFSR_MASK 0xcfc00fffULL
195: #define FSR_FTT_IEEE_EXCP (1ULL << 14)
196: #define FSR_FTT_UNIMPFPOP (3ULL << 14)
197: #define FSR_FTT_SEQ_ERROR (4ULL << 14)
198: #define FSR_FTT_INVAL_FPR (6ULL << 14)
199:
200: #define FSR_FCC1_SHIFT 11
201: #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT)
202: #define FSR_FCC0_SHIFT 10
203: #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT)
1.1 root 204:
205: /* MMU */
1.1.1.5 root 206: #define MMU_E (1<<0)
207: #define MMU_NF (1<<1)
1.1 root 208:
209: #define PTE_ENTRYTYPE_MASK 3
210: #define PTE_ACCESS_MASK 0x1c
211: #define PTE_ACCESS_SHIFT 2
212: #define PTE_PPN_SHIFT 7
213: #define PTE_ADDR_MASK 0xffffff00
214:
1.1.1.5 root 215: #define PG_ACCESSED_BIT 5
216: #define PG_MODIFIED_BIT 6
1.1 root 217: #define PG_CACHE_BIT 7
218:
219: #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
220: #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
221: #define PG_CACHE_MASK (1 << PG_CACHE_BIT)
222:
1.1.1.6 root 223: /* 3 <= NWINDOWS <= 32. */
224: #define MIN_NWINDOWS 3
225: #define MAX_NWINDOWS 32
1.1 root 226:
1.1.1.5 root 227: #if !defined(TARGET_SPARC64)
228: #define NB_MMU_MODES 2
229: #else
1.1.1.9 root 230: #define NB_MMU_MODES 6
1.1.1.6 root 231: typedef struct trap_state {
232: uint64_t tpc;
233: uint64_t tnpc;
234: uint64_t tstate;
235: uint32_t tt;
236: } trap_state;
237: #endif
238:
239: typedef struct sparc_def_t {
240: const char *name;
241: target_ulong iu_version;
242: uint32_t fpu_version;
243: uint32_t mmu_version;
244: uint32_t mmu_bm;
245: uint32_t mmu_ctpr_mask;
246: uint32_t mmu_cxr_mask;
247: uint32_t mmu_sfsr_mask;
248: uint32_t mmu_trcr_mask;
249: uint32_t mxcc_version;
250: uint32_t features;
251: uint32_t nwindows;
252: uint32_t maxtl;
253: } sparc_def_t;
254:
1.1.1.10! root 255: #define CPU_FEATURE_FLOAT (1 << 0)
! 256: #define CPU_FEATURE_FLOAT128 (1 << 1)
! 257: #define CPU_FEATURE_SWAP (1 << 2)
! 258: #define CPU_FEATURE_MUL (1 << 3)
! 259: #define CPU_FEATURE_DIV (1 << 4)
! 260: #define CPU_FEATURE_FLUSH (1 << 5)
! 261: #define CPU_FEATURE_FSQRT (1 << 6)
! 262: #define CPU_FEATURE_FMUL (1 << 7)
! 263: #define CPU_FEATURE_VIS1 (1 << 8)
! 264: #define CPU_FEATURE_VIS2 (1 << 9)
! 265: #define CPU_FEATURE_FSMULD (1 << 10)
! 266: #define CPU_FEATURE_HYPV (1 << 11)
! 267: #define CPU_FEATURE_CMT (1 << 12)
! 268: #define CPU_FEATURE_GL (1 << 13)
! 269: #define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */
! 270: #define CPU_FEATURE_ASR17 (1 << 15)
! 271: #define CPU_FEATURE_CACHE_CTRL (1 << 16)
! 272:
1.1.1.6 root 273: #ifndef TARGET_SPARC64
274: #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
275: CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
276: CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
277: CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
278: #else
279: #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
280: CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
281: CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
282: CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \
283: CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD)
284: enum {
285: mmu_us_12, // Ultrasparc < III (64 entry TLB)
286: mmu_us_3, // Ultrasparc III (512 entry TLB)
287: mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages)
288: mmu_sun4v, // T1, T2
289: };
1.1.1.5 root 290: #endif
291:
1.1.1.8 root 292: #define TTE_VALID_BIT (1ULL << 63)
293: #define TTE_USED_BIT (1ULL << 41)
294: #define TTE_LOCKED_BIT (1ULL << 6)
295: #define TTE_GLOBAL_BIT (1ULL << 0)
296:
297: #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT)
298: #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT)
299: #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT)
300: #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT)
301:
302: #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT)
303: #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
304:
305: typedef struct SparcTLBEntry {
306: uint64_t tag;
307: uint64_t tte;
308: } SparcTLBEntry;
309:
1.1.1.9 root 310: struct CPUTimer
311: {
312: const char *name;
313: uint32_t frequency;
314: uint32_t disabled;
315: uint64_t disabled_mask;
316: int64_t clock_offset;
317: struct QEMUTimer *qtimer;
318: };
319:
320: typedef struct CPUTimer CPUTimer;
321:
322: struct QEMUFile;
323: void cpu_put_timer(struct QEMUFile *f, CPUTimer *s);
324: void cpu_get_timer(struct QEMUFile *f, CPUTimer *s);
325:
1.1 root 326: typedef struct CPUSPARCState {
327: target_ulong gregs[8]; /* general registers */
328: target_ulong *regwptr; /* pointer to current register window */
329: target_ulong pc; /* program counter */
330: target_ulong npc; /* next program counter */
331: target_ulong y; /* multiply/divide register */
1.1.1.6 root 332:
333: /* emulator internal flags handling */
334: target_ulong cc_src, cc_src2;
335: target_ulong cc_dst;
1.1.1.7 root 336: uint32_t cc_op;
1.1.1.6 root 337:
338: target_ulong t0, t1; /* temporaries live across basic blocks */
339: target_ulong cond; /* conditional branch result (XXX: save it in a
340: temporary register when possible) */
341:
1.1 root 342: uint32_t psr; /* processor state register */
343: target_ulong fsr; /* FPU state register */
1.1.1.6 root 344: float32 fpr[TARGET_FPREGS]; /* floating point registers */
1.1 root 345: uint32_t cwp; /* index of current register window (extracted
346: from PSR) */
1.1.1.7 root 347: #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
1.1 root 348: uint32_t wim; /* window invalid mask */
1.1.1.7 root 349: #endif
1.1 root 350: target_ulong tbr; /* trap base register */
1.1.1.9 root 351: #if !defined(TARGET_SPARC64)
1.1 root 352: int psrs; /* supervisor mode (extracted from PSR) */
353: int psrps; /* previous supervisor mode */
354: int psret; /* enable traps */
1.1.1.7 root 355: #endif
1.1.1.5 root 356: uint32_t psrpil; /* interrupt blocking level */
357: uint32_t pil_in; /* incoming interrupt level bitmap */
1.1.1.9 root 358: #if !defined(TARGET_SPARC64)
1.1 root 359: int psref; /* enable fpu */
1.1.1.9 root 360: #endif
1.1.1.5 root 361: target_ulong version;
1.1 root 362: int interrupt_index;
1.1.1.6 root 363: uint32_t nwindows;
1.1 root 364: /* NOTE: we allow 8 more registers to handle wrapping */
1.1.1.6 root 365: target_ulong regbase[MAX_NWINDOWS * 16 + 8];
1.1 root 366:
1.1.1.2 root 367: CPU_COMMON
368:
1.1 root 369: /* MMU regs */
370: #if defined(TARGET_SPARC64)
371: uint64_t lsu;
372: #define DMMU_E 0x8
373: #define IMMU_E 0x4
1.1.1.8 root 374: //typedef struct SparcMMU
375: union {
376: uint64_t immuregs[16];
377: struct {
378: uint64_t tsb_tag_target;
379: uint64_t unused_mmu_primary_context; // use DMMU
380: uint64_t unused_mmu_secondary_context; // use DMMU
381: uint64_t sfsr;
382: uint64_t sfar;
383: uint64_t tsb;
384: uint64_t tag_access;
385: } immu;
386: };
387: union {
388: uint64_t dmmuregs[16];
389: struct {
390: uint64_t tsb_tag_target;
391: uint64_t mmu_primary_context;
392: uint64_t mmu_secondary_context;
393: uint64_t sfsr;
394: uint64_t sfar;
395: uint64_t tsb;
396: uint64_t tag_access;
397: } dmmu;
398: };
399: SparcTLBEntry itlb[64];
400: SparcTLBEntry dtlb[64];
1.1.1.6 root 401: uint32_t mmu_version;
1.1 root 402: #else
1.1.1.5 root 403: uint32_t mmuregs[32];
404: uint64_t mxccdata[4];
405: uint64_t mxccregs[8];
1.1.1.6 root 406: uint64_t mmubpregs[4];
1.1.1.5 root 407: uint64_t prom_addr;
1.1 root 408: #endif
409: /* temporary float registers */
1.1.1.3 root 410: float64 dt0, dt1;
1.1.1.5 root 411: float128 qt0, qt1;
1.1 root 412: float_status fp_status;
413: #if defined(TARGET_SPARC64)
1.1.1.6 root 414: #define MAXTL_MAX 8
415: #define MAXTL_MASK (MAXTL_MAX - 1)
416: trap_state ts[MAXTL_MAX];
1.1.1.5 root 417: uint32_t xcc; /* Extended integer condition codes */
1.1 root 418: uint32_t asi;
419: uint32_t pstate;
420: uint32_t tl;
1.1.1.6 root 421: uint32_t maxtl;
1.1 root 422: uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
423: uint64_t agregs[8]; /* alternate general registers */
424: uint64_t bgregs[8]; /* backup for normal global registers */
425: uint64_t igregs[8]; /* interrupt general registers */
426: uint64_t mgregs[8]; /* mmu general registers */
427: uint64_t fprs;
428: uint64_t tick_cmpr, stick_cmpr;
1.1.1.9 root 429: CPUTimer *tick, *stick;
430: #define TICK_NPT_MASK 0x8000000000000000ULL
431: #define TICK_INT_DIS 0x8000000000000000ULL
1.1.1.3 root 432: uint64_t gsr;
1.1.1.5 root 433: uint32_t gl; // UA2005
434: /* UA 2005 hyperprivileged registers */
1.1.1.6 root 435: uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
1.1.1.9 root 436: CPUTimer *hstick; // UA 2005
1.1.1.6 root 437: uint32_t softint;
438: #define SOFTINT_TIMER 1
439: #define SOFTINT_STIMER (1 << 16)
1.1.1.9 root 440: #define SOFTINT_INTRMASK (0xFFFE)
441: #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
1.1 root 442: #endif
1.1.1.6 root 443: sparc_def_t *def;
1.1.1.10! root 444:
! 445: void *irq_manager;
! 446: void (*qemu_irq_ack) (void *irq_manager, int intno);
! 447:
! 448: /* Leon3 cache control */
! 449: uint32_t cache_control;
1.1 root 450: } CPUSPARCState;
451:
1.1.1.9 root 452: #ifndef NO_CPU_IO_DEFS
1.1.1.6 root 453: /* helper.c */
1.1.1.5 root 454: CPUSPARCState *cpu_sparc_init(const char *cpu_model);
1.1.1.6 root 455: void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
1.1.1.10! root 456: void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1.1.1.6 root 457: int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
458: int mmu_idx, int is_softmmu);
1.1.1.8 root 459: #define cpu_handle_mmu_fault cpu_sparc_handle_mmu_fault
1.1.1.6 root 460: target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
1.1.1.10! root 461: void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env);
1.1.1.6 root 462:
463: /* translate.c */
464: void gen_intermediate_code_init(CPUSPARCState *env);
465:
466: /* cpu-exec.c */
467: int cpu_sparc_exec(CPUSPARCState *s);
1.1.1.5 root 468:
1.1.1.9 root 469: /* op_helper.c */
470: target_ulong cpu_get_psr(CPUState *env1);
471: void cpu_put_psr(CPUState *env1, target_ulong val);
472: #ifdef TARGET_SPARC64
473: target_ulong cpu_get_ccr(CPUState *env1);
474: void cpu_put_ccr(CPUState *env1, target_ulong val);
475: target_ulong cpu_get_cwp64(CPUState *env1);
476: void cpu_put_cwp64(CPUState *env1, int cwp);
477: #endif
478: int cpu_cwp_inc(CPUState *env1, int cwp);
479: int cpu_cwp_dec(CPUState *env1, int cwp);
480: void cpu_set_cwp(CPUState *env1, int new_cwp);
1.1.1.10! root 481: void leon3_irq_manager(void *irq_manager, int intno);
1.1.1.6 root 482:
1.1.1.8 root 483: /* sun4m.c, sun4u.c */
484: void cpu_check_irqs(CPUSPARCState *env);
1.1.1.6 root 485:
1.1.1.10! root 486: /* leon3.c */
! 487: void leon3_irq_ack(void *irq_manager, int intno);
! 488:
1.1.1.9 root 489: #if defined (TARGET_SPARC64)
490:
491: static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
1.1.1.6 root 492: {
1.1.1.9 root 493: return (x & mask) == (y & mask);
1.1.1.8 root 494: }
1.1 root 495:
1.1.1.9 root 496: #define MMU_CONTEXT_BITS 13
497: #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1)
1.1.1.5 root 498:
1.1.1.9 root 499: static inline int tlb_compare_context(const SparcTLBEntry *tlb,
500: uint64_t context)
1.1.1.6 root 501: {
1.1.1.9 root 502: return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK);
1.1.1.6 root 503: }
1.1.1.9 root 504:
1.1.1.6 root 505: #endif
1.1 root 506: #endif
507:
1.1.1.6 root 508: /* cpu-exec.c */
1.1.1.9 root 509: #if !defined(CONFIG_USER_ONLY)
1.1.1.5 root 510: void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1.1.1.6 root 511: int is_asi, int size);
1.1.1.9 root 512: target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
513: int mmu_idx);
514:
515: #endif
1.1.1.6 root 516: int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
1.1.1.5 root 517:
518: #define cpu_init cpu_sparc_init
519: #define cpu_exec cpu_sparc_exec
520: #define cpu_gen_code cpu_sparc_gen_code
521: #define cpu_signal_handler cpu_sparc_signal_handler
522: #define cpu_list sparc_cpu_list
523:
1.1.1.9 root 524: #define CPU_SAVE_VERSION 6
1.1.1.6 root 525:
1.1.1.5 root 526: /* MMU modes definitions */
1.1.1.9 root 527: #if defined (TARGET_SPARC64)
528: #define MMU_USER_IDX 0
1.1.1.5 root 529: #define MMU_MODE0_SUFFIX _user
1.1.1.9 root 530: #define MMU_USER_SECONDARY_IDX 1
531: #define MMU_MODE1_SUFFIX _user_secondary
532: #define MMU_KERNEL_IDX 2
533: #define MMU_MODE2_SUFFIX _kernel
534: #define MMU_KERNEL_SECONDARY_IDX 3
535: #define MMU_MODE3_SUFFIX _kernel_secondary
536: #define MMU_NUCLEUS_IDX 4
537: #define MMU_MODE4_SUFFIX _nucleus
538: #define MMU_HYPV_IDX 5
539: #define MMU_MODE5_SUFFIX _hypv
540: #else
1.1.1.6 root 541: #define MMU_USER_IDX 0
1.1.1.9 root 542: #define MMU_MODE0_SUFFIX _user
1.1.1.6 root 543: #define MMU_KERNEL_IDX 1
1.1.1.9 root 544: #define MMU_MODE1_SUFFIX _kernel
545: #endif
546:
547: #if defined (TARGET_SPARC64)
548: static inline int cpu_has_hypervisor(CPUState *env1)
549: {
550: return env1->def->features & CPU_FEATURE_HYPV;
551: }
552:
553: static inline int cpu_hypervisor_mode(CPUState *env1)
554: {
555: return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
556: }
557:
558: static inline int cpu_supervisor_mode(CPUState *env1)
559: {
560: return env1->pstate & PS_PRIV;
561: }
562: #endif
1.1.1.6 root 563:
564: static inline int cpu_mmu_index(CPUState *env1)
1.1.1.5 root 565: {
566: #if defined(CONFIG_USER_ONLY)
1.1.1.6 root 567: return MMU_USER_IDX;
1.1.1.5 root 568: #elif !defined(TARGET_SPARC64)
1.1.1.6 root 569: return env1->psrs;
1.1.1.5 root 570: #else
1.1.1.9 root 571: if (env1->tl > 0) {
572: return MMU_NUCLEUS_IDX;
573: } else if (cpu_hypervisor_mode(env1)) {
1.1.1.6 root 574: return MMU_HYPV_IDX;
1.1.1.9 root 575: } else if (cpu_supervisor_mode(env1)) {
576: return MMU_KERNEL_IDX;
577: } else {
578: return MMU_USER_IDX;
579: }
580: #endif
581: }
582:
583: static inline int cpu_interrupts_enabled(CPUState *env1)
584: {
585: #if !defined (TARGET_SPARC64)
586: if (env1->psret != 0)
587: return 1;
588: #else
589: if (env1->pstate & PS_IE)
590: return 1;
591: #endif
592:
593: return 0;
594: }
595:
596: static inline int cpu_pil_allowed(CPUState *env1, int pil)
597: {
598: #if !defined(TARGET_SPARC64)
599: /* level 15 is non-maskable on sparc v8 */
600: return pil == 15 || pil > env1->psrpil;
601: #else
602: return pil > env1->psrpil;
1.1.1.5 root 603: #endif
604: }
605:
1.1.1.6 root 606: static inline int cpu_fpu_enabled(CPUState *env1)
1.1.1.5 root 607: {
608: #if defined(CONFIG_USER_ONLY)
609: return 1;
610: #elif !defined(TARGET_SPARC64)
1.1.1.6 root 611: return env1->psref;
1.1.1.5 root 612: #else
1.1.1.6 root 613: return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0);
1.1.1.5 root 614: #endif
615: }
1.1 root 616:
1.1.1.6 root 617: #if defined(CONFIG_USER_ONLY)
618: static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
619: {
620: if (newsp)
621: env->regwptr[22] = newsp;
622: env->regwptr[0] = 0;
623: /* FIXME: Do we also need to clear CF? */
624: /* XXXXX */
625: printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
626: }
627: #endif
628:
1.1 root 629: #include "cpu-all.h"
1.1.1.6 root 630:
631: #ifdef TARGET_SPARC64
632: /* sun4u.c */
1.1.1.9 root 633: void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
634: uint64_t cpu_tick_get_count(CPUTimer *timer);
635: void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
1.1.1.8 root 636: trap_state* cpu_tsptr(CPUState* env);
1.1.1.6 root 637: #endif
638:
639: static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
640: target_ulong *cs_base, int *flags)
641: {
642: *pc = env->pc;
643: *cs_base = env->npc;
644: #ifdef TARGET_SPARC64
645: // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
1.1.1.9 root 646: *flags = ((env->pstate & PS_AM) << 2) /* 5 */
647: | (((env->pstate & PS_PEF) >> 1) /* 3 */
648: | ((env->fprs & FPRS_FEF) << 2)) /* 4 */
649: | (env->pstate & PS_PRIV) /* 2 */
650: | ((env->lsu & (DMMU_E | IMMU_E)) >> 2) /* 1, 0 */
651: | ((env->tl & 0xff) << 8)
652: | (env->dmmu.mmu_primary_context << 16); /* 16... */
1.1.1.6 root 653: #else
654: // FPU enable . Supervisor
655: *flags = (env->psref << 4) | env->psrs;
656: #endif
657: }
1.1 root 658:
659: #endif
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.