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1.1 root 1: #ifndef CPU_SPARC_H
2: #define CPU_SPARC_H
3:
4: #include "config.h"
1.1.1.10 root 5: #include "qemu-common.h"
1.1 root 6:
7: #if !defined(TARGET_SPARC64)
8: #define TARGET_LONG_BITS 32
9: #define TARGET_FPREGS 32
10: #define TARGET_PAGE_BITS 12 /* 4k */
1.1.1.9 root 11: #define TARGET_PHYS_ADDR_SPACE_BITS 36
12: #define TARGET_VIRT_ADDR_SPACE_BITS 32
1.1 root 13: #else
14: #define TARGET_LONG_BITS 64
15: #define TARGET_FPREGS 64
1.1.1.5 root 16: #define TARGET_PAGE_BITS 13 /* 8k */
1.1.1.9 root 17: #define TARGET_PHYS_ADDR_SPACE_BITS 41
18: # ifdef TARGET_ABI32
19: # define TARGET_VIRT_ADDR_SPACE_BITS 32
20: # else
21: # define TARGET_VIRT_ADDR_SPACE_BITS 44
22: # endif
1.1 root 23: #endif
24:
1.1.1.7 root 25: #define CPUState struct CPUSPARCState
1.1.1.5 root 26:
1.1 root 27: #include "cpu-defs.h"
28:
29: #include "softfloat.h"
30:
31: #define TARGET_HAS_ICE 1
32:
1.1.1.4 root 33: #if !defined(TARGET_SPARC64)
1.1.1.5 root 34: #define ELF_MACHINE EM_SPARC
1.1.1.4 root 35: #else
1.1.1.5 root 36: #define ELF_MACHINE EM_SPARCV9
1.1.1.4 root 37: #endif
38:
1.1 root 39: /*#define EXCP_INTERRUPT 0x100*/
40:
41: /* trap definitions */
42: #ifndef TARGET_SPARC64
43: #define TT_TFAULT 0x01
44: #define TT_ILL_INSN 0x02
45: #define TT_PRIV_INSN 0x03
46: #define TT_NFPU_INSN 0x04
47: #define TT_WIN_OVF 0x05
1.1.1.5 root 48: #define TT_WIN_UNF 0x06
49: #define TT_UNALIGNED 0x07
1.1 root 50: #define TT_FP_EXCP 0x08
51: #define TT_DFAULT 0x09
1.1.1.5 root 52: #define TT_TOVF 0x0a
1.1 root 53: #define TT_EXTINT 0x10
1.1.1.5 root 54: #define TT_CODE_ACCESS 0x21
1.1.1.6 root 55: #define TT_UNIMP_FLUSH 0x25
1.1.1.5 root 56: #define TT_DATA_ACCESS 0x29
1.1 root 57: #define TT_DIV_ZERO 0x2a
1.1.1.5 root 58: #define TT_NCP_INSN 0x24
1.1 root 59: #define TT_TRAP 0x80
60: #else
1.1.1.8 root 61: #define TT_POWER_ON_RESET 0x01
1.1 root 62: #define TT_TFAULT 0x08
1.1.1.5 root 63: #define TT_CODE_ACCESS 0x0a
1.1 root 64: #define TT_ILL_INSN 0x10
1.1.1.6 root 65: #define TT_UNIMP_FLUSH TT_ILL_INSN
1.1 root 66: #define TT_PRIV_INSN 0x11
67: #define TT_NFPU_INSN 0x20
68: #define TT_FP_EXCP 0x21
1.1.1.5 root 69: #define TT_TOVF 0x23
1.1 root 70: #define TT_CLRWIN 0x24
71: #define TT_DIV_ZERO 0x28
72: #define TT_DFAULT 0x30
1.1.1.5 root 73: #define TT_DATA_ACCESS 0x32
74: #define TT_UNALIGNED 0x34
1.1 root 75: #define TT_PRIV_ACT 0x37
76: #define TT_EXTINT 0x40
1.1.1.6 root 77: #define TT_IVEC 0x60
78: #define TT_TMISS 0x64
79: #define TT_DMISS 0x68
80: #define TT_DPROT 0x6c
1.1 root 81: #define TT_SPILL 0x80
82: #define TT_FILL 0xc0
1.1.1.9 root 83: #define TT_WOTHER (1 << 5)
1.1 root 84: #define TT_TRAP 0x100
85: #endif
86:
1.1.1.6 root 87: #define PSR_NEG_SHIFT 23
88: #define PSR_NEG (1 << PSR_NEG_SHIFT)
89: #define PSR_ZERO_SHIFT 22
90: #define PSR_ZERO (1 << PSR_ZERO_SHIFT)
91: #define PSR_OVF_SHIFT 21
92: #define PSR_OVF (1 << PSR_OVF_SHIFT)
93: #define PSR_CARRY_SHIFT 20
94: #define PSR_CARRY (1 << PSR_CARRY_SHIFT)
1.1 root 95: #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
1.1.1.9 root 96: #if !defined(TARGET_SPARC64)
1.1 root 97: #define PSR_EF (1<<12)
98: #define PSR_PIL 0xf00
99: #define PSR_S (1<<7)
100: #define PSR_PS (1<<6)
101: #define PSR_ET (1<<5)
102: #define PSR_CWP 0x1f
1.1.1.9 root 103: #endif
1.1 root 104:
1.1.1.7 root 105: #define CC_SRC (env->cc_src)
106: #define CC_SRC2 (env->cc_src2)
107: #define CC_DST (env->cc_dst)
108: #define CC_OP (env->cc_op)
109:
110: enum {
111: CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
112: CC_OP_FLAGS, /* all cc are back in status register */
113: CC_OP_DIV, /* modify N, Z and V, C = 0*/
114: CC_OP_ADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
115: CC_OP_ADDX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
116: CC_OP_TADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
117: CC_OP_TADDTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
118: CC_OP_SUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
119: CC_OP_SUBX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
120: CC_OP_TSUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
121: CC_OP_TSUBTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
122: CC_OP_LOGIC, /* modify N and Z, C = V = 0, CC_DST = res */
123: CC_OP_NB,
124: };
125:
1.1 root 126: /* Trap base register */
127: #define TBR_BASE_MASK 0xfffff000
128:
129: #if defined(TARGET_SPARC64)
1.1.1.7 root 130: #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */
131: #define PS_IG (1<<11) /* v9, zero on UA2007 */
132: #define PS_MG (1<<10) /* v9, zero on UA2007 */
133: #define PS_CLE (1<<9) /* UA2007 */
134: #define PS_TLE (1<<8) /* UA2007 */
1.1.1.5 root 135: #define PS_RMO (1<<7)
1.1.1.7 root 136: #define PS_RED (1<<5) /* v9, zero on UA2007 */
137: #define PS_PEF (1<<4) /* enable fpu */
138: #define PS_AM (1<<3) /* address mask */
1.1 root 139: #define PS_PRIV (1<<2)
140: #define PS_IE (1<<1)
1.1.1.7 root 141: #define PS_AG (1<<0) /* v9, zero on UA2007 */
1.1.1.3 root 142:
143: #define FPRS_FEF (1<<2)
1.1.1.5 root 144:
145: #define HS_PRIV (1<<2)
1.1 root 146: #endif
147:
148: /* Fcc */
1.1.1.6 root 149: #define FSR_RD1 (1ULL << 31)
150: #define FSR_RD0 (1ULL << 30)
1.1 root 151: #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
152: #define FSR_RD_NEAREST 0
153: #define FSR_RD_ZERO FSR_RD0
154: #define FSR_RD_POS FSR_RD1
155: #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
156:
1.1.1.6 root 157: #define FSR_NVM (1ULL << 27)
158: #define FSR_OFM (1ULL << 26)
159: #define FSR_UFM (1ULL << 25)
160: #define FSR_DZM (1ULL << 24)
161: #define FSR_NXM (1ULL << 23)
1.1 root 162: #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
163:
1.1.1.6 root 164: #define FSR_NVA (1ULL << 9)
165: #define FSR_OFA (1ULL << 8)
166: #define FSR_UFA (1ULL << 7)
167: #define FSR_DZA (1ULL << 6)
168: #define FSR_NXA (1ULL << 5)
1.1 root 169: #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
170:
1.1.1.6 root 171: #define FSR_NVC (1ULL << 4)
172: #define FSR_OFC (1ULL << 3)
173: #define FSR_UFC (1ULL << 2)
174: #define FSR_DZC (1ULL << 1)
175: #define FSR_NXC (1ULL << 0)
1.1 root 176: #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
177:
1.1.1.6 root 178: #define FSR_FTT2 (1ULL << 16)
179: #define FSR_FTT1 (1ULL << 15)
180: #define FSR_FTT0 (1ULL << 14)
181: //gcc warns about constant overflow for ~FSR_FTT_MASK
182: //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
183: #ifdef TARGET_SPARC64
184: #define FSR_FTT_NMASK 0xfffffffffffe3fffULL
185: #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
186: #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL
187: #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL
188: #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
189: #else
190: #define FSR_FTT_NMASK 0xfffe3fffULL
191: #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
192: #define FSR_LDFSR_OLDMASK 0x000fc000ULL
193: #endif
194: #define FSR_LDFSR_MASK 0xcfc00fffULL
195: #define FSR_FTT_IEEE_EXCP (1ULL << 14)
196: #define FSR_FTT_UNIMPFPOP (3ULL << 14)
197: #define FSR_FTT_SEQ_ERROR (4ULL << 14)
198: #define FSR_FTT_INVAL_FPR (6ULL << 14)
199:
200: #define FSR_FCC1_SHIFT 11
201: #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT)
202: #define FSR_FCC0_SHIFT 10
203: #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT)
1.1 root 204:
205: /* MMU */
1.1.1.5 root 206: #define MMU_E (1<<0)
207: #define MMU_NF (1<<1)
1.1 root 208:
209: #define PTE_ENTRYTYPE_MASK 3
210: #define PTE_ACCESS_MASK 0x1c
211: #define PTE_ACCESS_SHIFT 2
212: #define PTE_PPN_SHIFT 7
213: #define PTE_ADDR_MASK 0xffffff00
214:
1.1.1.5 root 215: #define PG_ACCESSED_BIT 5
216: #define PG_MODIFIED_BIT 6
1.1 root 217: #define PG_CACHE_BIT 7
218:
219: #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
220: #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
221: #define PG_CACHE_MASK (1 << PG_CACHE_BIT)
222:
1.1.1.6 root 223: /* 3 <= NWINDOWS <= 32. */
224: #define MIN_NWINDOWS 3
225: #define MAX_NWINDOWS 32
1.1 root 226:
1.1.1.5 root 227: #if !defined(TARGET_SPARC64)
228: #define NB_MMU_MODES 2
229: #else
1.1.1.9 root 230: #define NB_MMU_MODES 6
1.1.1.6 root 231: typedef struct trap_state {
232: uint64_t tpc;
233: uint64_t tnpc;
234: uint64_t tstate;
235: uint32_t tt;
236: } trap_state;
237: #endif
238:
239: typedef struct sparc_def_t {
240: const char *name;
241: target_ulong iu_version;
242: uint32_t fpu_version;
243: uint32_t mmu_version;
244: uint32_t mmu_bm;
245: uint32_t mmu_ctpr_mask;
246: uint32_t mmu_cxr_mask;
247: uint32_t mmu_sfsr_mask;
248: uint32_t mmu_trcr_mask;
249: uint32_t mxcc_version;
250: uint32_t features;
251: uint32_t nwindows;
252: uint32_t maxtl;
253: } sparc_def_t;
254:
1.1.1.10 root 255: #define CPU_FEATURE_FLOAT (1 << 0)
256: #define CPU_FEATURE_FLOAT128 (1 << 1)
257: #define CPU_FEATURE_SWAP (1 << 2)
258: #define CPU_FEATURE_MUL (1 << 3)
259: #define CPU_FEATURE_DIV (1 << 4)
260: #define CPU_FEATURE_FLUSH (1 << 5)
261: #define CPU_FEATURE_FSQRT (1 << 6)
262: #define CPU_FEATURE_FMUL (1 << 7)
263: #define CPU_FEATURE_VIS1 (1 << 8)
264: #define CPU_FEATURE_VIS2 (1 << 9)
265: #define CPU_FEATURE_FSMULD (1 << 10)
266: #define CPU_FEATURE_HYPV (1 << 11)
267: #define CPU_FEATURE_CMT (1 << 12)
268: #define CPU_FEATURE_GL (1 << 13)
269: #define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */
270: #define CPU_FEATURE_ASR17 (1 << 15)
271: #define CPU_FEATURE_CACHE_CTRL (1 << 16)
272:
1.1.1.6 root 273: #ifndef TARGET_SPARC64
274: #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
275: CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
276: CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
277: CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
278: #else
279: #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
280: CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
281: CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
282: CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \
283: CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD)
284: enum {
285: mmu_us_12, // Ultrasparc < III (64 entry TLB)
286: mmu_us_3, // Ultrasparc III (512 entry TLB)
287: mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages)
288: mmu_sun4v, // T1, T2
289: };
1.1.1.5 root 290: #endif
291:
1.1.1.8 root 292: #define TTE_VALID_BIT (1ULL << 63)
1.1.1.11! root 293: #define TTE_NFO_BIT (1ULL << 60)
1.1.1.8 root 294: #define TTE_USED_BIT (1ULL << 41)
295: #define TTE_LOCKED_BIT (1ULL << 6)
1.1.1.11! root 296: #define TTE_SIDEEFFECT_BIT (1ULL << 3)
! 297: #define TTE_PRIV_BIT (1ULL << 2)
! 298: #define TTE_W_OK_BIT (1ULL << 1)
1.1.1.8 root 299: #define TTE_GLOBAL_BIT (1ULL << 0)
300:
301: #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT)
1.1.1.11! root 302: #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT)
1.1.1.8 root 303: #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT)
304: #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT)
1.1.1.11! root 305: #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)
! 306: #define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT)
! 307: #define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT)
1.1.1.8 root 308: #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT)
309:
310: #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT)
311: #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
312:
1.1.1.11! root 313: #define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL)
! 314: #define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL)
! 315:
! 316: #define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */
! 317: #define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */
! 318: #define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */
! 319: #define SFSR_FT_VA_DMMU_BIT (1ULL << 12) /* USIIi VA out of range (DMMU) */
! 320: #define SFSR_FT_NFO_BIT (1ULL << 11) /* NFO page access */
! 321: #define SFSR_FT_ILL_BIT (1ULL << 10) /* illegal LDA/STA ASI */
! 322: #define SFSR_FT_ATOMIC_BIT (1ULL << 9) /* atomic op on noncacheable area */
! 323: #define SFSR_FT_NF_E_BIT (1ULL << 8) /* NF access on side effect area */
! 324: #define SFSR_FT_PRIV_BIT (1ULL << 7) /* privilege violation */
! 325: #define SFSR_PR_BIT (1ULL << 3) /* privilege mode */
! 326: #define SFSR_WRITE_BIT (1ULL << 2) /* write access mode */
! 327: #define SFSR_OW_BIT (1ULL << 1) /* status overwritten */
! 328: #define SFSR_VALID_BIT (1ULL << 0) /* status valid */
! 329:
! 330: #define SFSR_ASI_SHIFT 16 /* 23:16 ASI value */
! 331: #define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT)
! 332: #define SFSR_CT_PRIMARY (0ULL << 4) /* 5:4 context type */
! 333: #define SFSR_CT_SECONDARY (1ULL << 4)
! 334: #define SFSR_CT_NUCLEUS (2ULL << 4)
! 335: #define SFSR_CT_NOTRANS (3ULL << 4)
! 336: #define SFSR_CT_MASK (3ULL << 4)
! 337:
1.1.1.8 root 338: typedef struct SparcTLBEntry {
339: uint64_t tag;
340: uint64_t tte;
341: } SparcTLBEntry;
342:
1.1.1.9 root 343: struct CPUTimer
344: {
345: const char *name;
346: uint32_t frequency;
347: uint32_t disabled;
348: uint64_t disabled_mask;
349: int64_t clock_offset;
350: struct QEMUTimer *qtimer;
351: };
352:
353: typedef struct CPUTimer CPUTimer;
354:
355: struct QEMUFile;
356: void cpu_put_timer(struct QEMUFile *f, CPUTimer *s);
357: void cpu_get_timer(struct QEMUFile *f, CPUTimer *s);
358:
1.1 root 359: typedef struct CPUSPARCState {
360: target_ulong gregs[8]; /* general registers */
361: target_ulong *regwptr; /* pointer to current register window */
362: target_ulong pc; /* program counter */
363: target_ulong npc; /* next program counter */
364: target_ulong y; /* multiply/divide register */
1.1.1.6 root 365:
366: /* emulator internal flags handling */
367: target_ulong cc_src, cc_src2;
368: target_ulong cc_dst;
1.1.1.7 root 369: uint32_t cc_op;
1.1.1.6 root 370:
371: target_ulong t0, t1; /* temporaries live across basic blocks */
372: target_ulong cond; /* conditional branch result (XXX: save it in a
373: temporary register when possible) */
374:
1.1 root 375: uint32_t psr; /* processor state register */
376: target_ulong fsr; /* FPU state register */
1.1.1.6 root 377: float32 fpr[TARGET_FPREGS]; /* floating point registers */
1.1 root 378: uint32_t cwp; /* index of current register window (extracted
379: from PSR) */
1.1.1.7 root 380: #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
1.1 root 381: uint32_t wim; /* window invalid mask */
1.1.1.7 root 382: #endif
1.1 root 383: target_ulong tbr; /* trap base register */
1.1.1.9 root 384: #if !defined(TARGET_SPARC64)
1.1 root 385: int psrs; /* supervisor mode (extracted from PSR) */
386: int psrps; /* previous supervisor mode */
387: int psret; /* enable traps */
1.1.1.7 root 388: #endif
1.1.1.5 root 389: uint32_t psrpil; /* interrupt blocking level */
390: uint32_t pil_in; /* incoming interrupt level bitmap */
1.1.1.9 root 391: #if !defined(TARGET_SPARC64)
1.1 root 392: int psref; /* enable fpu */
1.1.1.9 root 393: #endif
1.1.1.5 root 394: target_ulong version;
1.1 root 395: int interrupt_index;
1.1.1.6 root 396: uint32_t nwindows;
1.1 root 397: /* NOTE: we allow 8 more registers to handle wrapping */
1.1.1.6 root 398: target_ulong regbase[MAX_NWINDOWS * 16 + 8];
1.1 root 399:
1.1.1.2 root 400: CPU_COMMON
401:
1.1 root 402: /* MMU regs */
403: #if defined(TARGET_SPARC64)
404: uint64_t lsu;
405: #define DMMU_E 0x8
406: #define IMMU_E 0x4
1.1.1.8 root 407: //typedef struct SparcMMU
408: union {
409: uint64_t immuregs[16];
410: struct {
411: uint64_t tsb_tag_target;
412: uint64_t unused_mmu_primary_context; // use DMMU
413: uint64_t unused_mmu_secondary_context; // use DMMU
414: uint64_t sfsr;
415: uint64_t sfar;
416: uint64_t tsb;
417: uint64_t tag_access;
418: } immu;
419: };
420: union {
421: uint64_t dmmuregs[16];
422: struct {
423: uint64_t tsb_tag_target;
424: uint64_t mmu_primary_context;
425: uint64_t mmu_secondary_context;
426: uint64_t sfsr;
427: uint64_t sfar;
428: uint64_t tsb;
429: uint64_t tag_access;
430: } dmmu;
431: };
432: SparcTLBEntry itlb[64];
433: SparcTLBEntry dtlb[64];
1.1.1.6 root 434: uint32_t mmu_version;
1.1 root 435: #else
1.1.1.5 root 436: uint32_t mmuregs[32];
437: uint64_t mxccdata[4];
438: uint64_t mxccregs[8];
1.1.1.11! root 439: uint32_t mmubpctrv, mmubpctrc, mmubpctrs;
! 440: uint64_t mmubpaction;
1.1.1.6 root 441: uint64_t mmubpregs[4];
1.1.1.5 root 442: uint64_t prom_addr;
1.1 root 443: #endif
444: /* temporary float registers */
1.1.1.3 root 445: float64 dt0, dt1;
1.1.1.5 root 446: float128 qt0, qt1;
1.1 root 447: float_status fp_status;
448: #if defined(TARGET_SPARC64)
1.1.1.6 root 449: #define MAXTL_MAX 8
450: #define MAXTL_MASK (MAXTL_MAX - 1)
451: trap_state ts[MAXTL_MAX];
1.1.1.5 root 452: uint32_t xcc; /* Extended integer condition codes */
1.1 root 453: uint32_t asi;
454: uint32_t pstate;
455: uint32_t tl;
1.1.1.6 root 456: uint32_t maxtl;
1.1 root 457: uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
458: uint64_t agregs[8]; /* alternate general registers */
459: uint64_t bgregs[8]; /* backup for normal global registers */
460: uint64_t igregs[8]; /* interrupt general registers */
461: uint64_t mgregs[8]; /* mmu general registers */
462: uint64_t fprs;
463: uint64_t tick_cmpr, stick_cmpr;
1.1.1.9 root 464: CPUTimer *tick, *stick;
465: #define TICK_NPT_MASK 0x8000000000000000ULL
466: #define TICK_INT_DIS 0x8000000000000000ULL
1.1.1.3 root 467: uint64_t gsr;
1.1.1.5 root 468: uint32_t gl; // UA2005
469: /* UA 2005 hyperprivileged registers */
1.1.1.6 root 470: uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
1.1.1.9 root 471: CPUTimer *hstick; // UA 2005
1.1.1.6 root 472: uint32_t softint;
473: #define SOFTINT_TIMER 1
474: #define SOFTINT_STIMER (1 << 16)
1.1.1.9 root 475: #define SOFTINT_INTRMASK (0xFFFE)
476: #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
1.1 root 477: #endif
1.1.1.6 root 478: sparc_def_t *def;
1.1.1.10 root 479:
480: void *irq_manager;
481: void (*qemu_irq_ack) (void *irq_manager, int intno);
482:
483: /* Leon3 cache control */
484: uint32_t cache_control;
1.1 root 485: } CPUSPARCState;
486:
1.1.1.9 root 487: #ifndef NO_CPU_IO_DEFS
1.1.1.6 root 488: /* helper.c */
1.1.1.5 root 489: CPUSPARCState *cpu_sparc_init(const char *cpu_model);
1.1.1.6 root 490: void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
1.1.1.10 root 491: void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1.1.1.6 root 492: int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
493: int mmu_idx, int is_softmmu);
1.1.1.8 root 494: #define cpu_handle_mmu_fault cpu_sparc_handle_mmu_fault
1.1.1.6 root 495: target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
1.1.1.10 root 496: void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env);
1.1.1.6 root 497:
498: /* translate.c */
499: void gen_intermediate_code_init(CPUSPARCState *env);
500:
501: /* cpu-exec.c */
502: int cpu_sparc_exec(CPUSPARCState *s);
1.1.1.5 root 503:
1.1.1.9 root 504: /* op_helper.c */
505: target_ulong cpu_get_psr(CPUState *env1);
506: void cpu_put_psr(CPUState *env1, target_ulong val);
507: #ifdef TARGET_SPARC64
508: target_ulong cpu_get_ccr(CPUState *env1);
509: void cpu_put_ccr(CPUState *env1, target_ulong val);
510: target_ulong cpu_get_cwp64(CPUState *env1);
511: void cpu_put_cwp64(CPUState *env1, int cwp);
1.1.1.11! root 512: void cpu_change_pstate(CPUState *env1, uint32_t new_pstate);
1.1.1.9 root 513: #endif
514: int cpu_cwp_inc(CPUState *env1, int cwp);
515: int cpu_cwp_dec(CPUState *env1, int cwp);
516: void cpu_set_cwp(CPUState *env1, int new_cwp);
1.1.1.10 root 517: void leon3_irq_manager(void *irq_manager, int intno);
1.1.1.6 root 518:
1.1.1.8 root 519: /* sun4m.c, sun4u.c */
520: void cpu_check_irqs(CPUSPARCState *env);
1.1.1.6 root 521:
1.1.1.10 root 522: /* leon3.c */
523: void leon3_irq_ack(void *irq_manager, int intno);
524:
1.1.1.9 root 525: #if defined (TARGET_SPARC64)
526:
527: static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
1.1.1.6 root 528: {
1.1.1.9 root 529: return (x & mask) == (y & mask);
1.1.1.8 root 530: }
1.1 root 531:
1.1.1.9 root 532: #define MMU_CONTEXT_BITS 13
533: #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1)
1.1.1.5 root 534:
1.1.1.9 root 535: static inline int tlb_compare_context(const SparcTLBEntry *tlb,
536: uint64_t context)
1.1.1.6 root 537: {
1.1.1.9 root 538: return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK);
1.1.1.6 root 539: }
1.1.1.9 root 540:
1.1.1.6 root 541: #endif
1.1 root 542: #endif
543:
1.1.1.6 root 544: /* cpu-exec.c */
1.1.1.9 root 545: #if !defined(CONFIG_USER_ONLY)
1.1.1.11! root 546: void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
! 547: int is_write, int is_exec, int is_asi, int size);
! 548: #if defined(TARGET_SPARC64)
1.1.1.9 root 549: target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
550: int mmu_idx);
551:
552: #endif
1.1.1.11! root 553: #endif
1.1.1.6 root 554: int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
1.1.1.5 root 555:
556: #define cpu_init cpu_sparc_init
557: #define cpu_exec cpu_sparc_exec
558: #define cpu_gen_code cpu_sparc_gen_code
559: #define cpu_signal_handler cpu_sparc_signal_handler
560: #define cpu_list sparc_cpu_list
561:
1.1.1.11! root 562: #define CPU_SAVE_VERSION 7
1.1.1.6 root 563:
1.1.1.5 root 564: /* MMU modes definitions */
1.1.1.9 root 565: #if defined (TARGET_SPARC64)
566: #define MMU_USER_IDX 0
1.1.1.5 root 567: #define MMU_MODE0_SUFFIX _user
1.1.1.9 root 568: #define MMU_USER_SECONDARY_IDX 1
569: #define MMU_MODE1_SUFFIX _user_secondary
570: #define MMU_KERNEL_IDX 2
571: #define MMU_MODE2_SUFFIX _kernel
572: #define MMU_KERNEL_SECONDARY_IDX 3
573: #define MMU_MODE3_SUFFIX _kernel_secondary
574: #define MMU_NUCLEUS_IDX 4
575: #define MMU_MODE4_SUFFIX _nucleus
576: #define MMU_HYPV_IDX 5
577: #define MMU_MODE5_SUFFIX _hypv
578: #else
1.1.1.6 root 579: #define MMU_USER_IDX 0
1.1.1.9 root 580: #define MMU_MODE0_SUFFIX _user
1.1.1.6 root 581: #define MMU_KERNEL_IDX 1
1.1.1.9 root 582: #define MMU_MODE1_SUFFIX _kernel
583: #endif
584:
585: #if defined (TARGET_SPARC64)
586: static inline int cpu_has_hypervisor(CPUState *env1)
587: {
588: return env1->def->features & CPU_FEATURE_HYPV;
589: }
590:
591: static inline int cpu_hypervisor_mode(CPUState *env1)
592: {
593: return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
594: }
595:
596: static inline int cpu_supervisor_mode(CPUState *env1)
597: {
598: return env1->pstate & PS_PRIV;
599: }
600: #endif
1.1.1.6 root 601:
602: static inline int cpu_mmu_index(CPUState *env1)
1.1.1.5 root 603: {
604: #if defined(CONFIG_USER_ONLY)
1.1.1.6 root 605: return MMU_USER_IDX;
1.1.1.5 root 606: #elif !defined(TARGET_SPARC64)
1.1.1.6 root 607: return env1->psrs;
1.1.1.5 root 608: #else
1.1.1.9 root 609: if (env1->tl > 0) {
610: return MMU_NUCLEUS_IDX;
611: } else if (cpu_hypervisor_mode(env1)) {
1.1.1.6 root 612: return MMU_HYPV_IDX;
1.1.1.9 root 613: } else if (cpu_supervisor_mode(env1)) {
614: return MMU_KERNEL_IDX;
615: } else {
616: return MMU_USER_IDX;
617: }
618: #endif
619: }
620:
621: static inline int cpu_interrupts_enabled(CPUState *env1)
622: {
623: #if !defined (TARGET_SPARC64)
624: if (env1->psret != 0)
625: return 1;
626: #else
627: if (env1->pstate & PS_IE)
628: return 1;
629: #endif
630:
631: return 0;
632: }
633:
634: static inline int cpu_pil_allowed(CPUState *env1, int pil)
635: {
636: #if !defined(TARGET_SPARC64)
637: /* level 15 is non-maskable on sparc v8 */
638: return pil == 15 || pil > env1->psrpil;
639: #else
640: return pil > env1->psrpil;
1.1.1.5 root 641: #endif
642: }
643:
1.1.1.6 root 644: #if defined(CONFIG_USER_ONLY)
645: static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
646: {
647: if (newsp)
648: env->regwptr[22] = newsp;
649: env->regwptr[0] = 0;
650: /* FIXME: Do we also need to clear CF? */
651: /* XXXXX */
652: printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
653: }
654: #endif
655:
1.1 root 656: #include "cpu-all.h"
1.1.1.6 root 657:
658: #ifdef TARGET_SPARC64
659: /* sun4u.c */
1.1.1.9 root 660: void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
661: uint64_t cpu_tick_get_count(CPUTimer *timer);
662: void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
1.1.1.8 root 663: trap_state* cpu_tsptr(CPUState* env);
1.1.1.6 root 664: #endif
665:
1.1.1.11! root 666: #define TB_FLAG_FPU_ENABLED (1 << 4)
! 667: #define TB_FLAG_AM_ENABLED (1 << 5)
! 668:
1.1.1.6 root 669: static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
670: target_ulong *cs_base, int *flags)
671: {
672: *pc = env->pc;
673: *cs_base = env->npc;
674: #ifdef TARGET_SPARC64
675: // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
1.1.1.11! root 676: *flags = (env->pstate & PS_PRIV) /* 2 */
1.1.1.9 root 677: | ((env->lsu & (DMMU_E | IMMU_E)) >> 2) /* 1, 0 */
678: | ((env->tl & 0xff) << 8)
679: | (env->dmmu.mmu_primary_context << 16); /* 16... */
1.1.1.11! root 680: if (env->pstate & PS_AM) {
! 681: *flags |= TB_FLAG_AM_ENABLED;
! 682: }
! 683: if ((env->def->features & CPU_FEATURE_FLOAT) && (env->pstate & PS_PEF)
! 684: && (env->fprs & FPRS_FEF)) {
! 685: *flags |= TB_FLAG_FPU_ENABLED;
! 686: }
1.1.1.6 root 687: #else
688: // FPU enable . Supervisor
1.1.1.11! root 689: *flags = env->psrs;
! 690: if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) {
! 691: *flags |= TB_FLAG_FPU_ENABLED;
! 692: }
1.1.1.6 root 693: #endif
694: }
1.1 root 695:
1.1.1.11! root 696: static inline bool tb_fpu_enabled(int tb_flags)
! 697: {
! 698: #if defined(CONFIG_USER_ONLY)
! 699: return true;
! 700: #else
! 701: return tb_flags & TB_FLAG_FPU_ENABLED;
! 702: #endif
! 703: }
! 704:
! 705: static inline bool tb_am_enabled(int tb_flags)
! 706: {
! 707: #ifndef TARGET_SPARC64
! 708: return false;
! 709: #else
! 710: return tb_flags & TB_FLAG_AM_ENABLED;
! 711: #endif
! 712: }
! 713:
! 714: /* helper.c */
! 715: void do_interrupt(CPUState *env);
! 716:
! 717: static inline bool cpu_has_work(CPUState *env1)
! 718: {
! 719: return (env1->interrupt_request & CPU_INTERRUPT_HARD) &&
! 720: cpu_interrupts_enabled(env1);
! 721: }
! 722:
! 723: #include "exec-all.h"
! 724:
! 725: static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
! 726: {
! 727: env->pc = tb->pc;
! 728: env->npc = tb->cs_base;
! 729: }
! 730:
1.1 root 731: #endif
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