![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to cpu.h CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Qemu by Fabrice Bellard] / qemu / target-sparc|
Return to cpu.h CVS log | Up to [Qemu by Fabrice Bellard] / qemu / target-sparc |
1.1 root 1: #ifndef CPU_SPARC_H
2: #define CPU_SPARC_H
3:
4: #include "config.h"
5:
6: #if !defined(TARGET_SPARC64)
7: #define TARGET_LONG_BITS 32
8: #define TARGET_FPREGS 32
9: #define TARGET_PAGE_BITS 12 /* 4k */
10: #else
11: #define TARGET_LONG_BITS 64
12: #define TARGET_FPREGS 64
13: #define TARGET_PAGE_BITS 12 /* XXX */
14: #endif
15:
16: #include "cpu-defs.h"
17:
18: #include "softfloat.h"
19:
20: #define TARGET_HAS_ICE 1
21:
22: /*#define EXCP_INTERRUPT 0x100*/
23:
24: /* trap definitions */
25: #ifndef TARGET_SPARC64
26: #define TT_TFAULT 0x01
27: #define TT_ILL_INSN 0x02
28: #define TT_PRIV_INSN 0x03
29: #define TT_NFPU_INSN 0x04
30: #define TT_WIN_OVF 0x05
31: #define TT_WIN_UNF 0x06
32: #define TT_FP_EXCP 0x08
33: #define TT_DFAULT 0x09
34: #define TT_EXTINT 0x10
35: #define TT_DIV_ZERO 0x2a
36: #define TT_TRAP 0x80
37: #else
38: #define TT_TFAULT 0x08
39: #define TT_TMISS 0x09
40: #define TT_ILL_INSN 0x10
41: #define TT_PRIV_INSN 0x11
42: #define TT_NFPU_INSN 0x20
43: #define TT_FP_EXCP 0x21
44: #define TT_CLRWIN 0x24
45: #define TT_DIV_ZERO 0x28
46: #define TT_DFAULT 0x30
47: #define TT_DMISS 0x31
48: #define TT_DPROT 0x32
49: #define TT_PRIV_ACT 0x37
50: #define TT_EXTINT 0x40
51: #define TT_SPILL 0x80
52: #define TT_FILL 0xc0
53: #define TT_WOTHER 0x10
54: #define TT_TRAP 0x100
55: #endif
56:
57: #define PSR_NEG (1<<23)
58: #define PSR_ZERO (1<<22)
59: #define PSR_OVF (1<<21)
60: #define PSR_CARRY (1<<20)
61: #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
62: #define PSR_EF (1<<12)
63: #define PSR_PIL 0xf00
64: #define PSR_S (1<<7)
65: #define PSR_PS (1<<6)
66: #define PSR_ET (1<<5)
67: #define PSR_CWP 0x1f
68:
69: /* Trap base register */
70: #define TBR_BASE_MASK 0xfffff000
71:
72: #if defined(TARGET_SPARC64)
73: #define PS_IG (1<<11)
74: #define PS_MG (1<<10)
75: #define PS_RED (1<<5)
76: #define PS_PEF (1<<4)
77: #define PS_AM (1<<3)
78: #define PS_PRIV (1<<2)
79: #define PS_IE (1<<1)
80: #define PS_AG (1<<0)
1.1.1.3 ! root 81:
! 82: #define FPRS_FEF (1<<2)
1.1 root 83: #endif
84:
85: /* Fcc */
86: #define FSR_RD1 (1<<31)
87: #define FSR_RD0 (1<<30)
88: #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
89: #define FSR_RD_NEAREST 0
90: #define FSR_RD_ZERO FSR_RD0
91: #define FSR_RD_POS FSR_RD1
92: #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
93:
94: #define FSR_NVM (1<<27)
95: #define FSR_OFM (1<<26)
96: #define FSR_UFM (1<<25)
97: #define FSR_DZM (1<<24)
98: #define FSR_NXM (1<<23)
99: #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
100:
101: #define FSR_NVA (1<<9)
102: #define FSR_OFA (1<<8)
103: #define FSR_UFA (1<<7)
104: #define FSR_DZA (1<<6)
105: #define FSR_NXA (1<<5)
106: #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
107:
108: #define FSR_NVC (1<<4)
109: #define FSR_OFC (1<<3)
110: #define FSR_UFC (1<<2)
111: #define FSR_DZC (1<<1)
112: #define FSR_NXC (1<<0)
113: #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
114:
115: #define FSR_FTT2 (1<<16)
116: #define FSR_FTT1 (1<<15)
117: #define FSR_FTT0 (1<<14)
118: #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
119: #define FSR_FTT_IEEE_EXCP (1 << 14)
120: #define FSR_FTT_UNIMPFPOP (3 << 14)
121: #define FSR_FTT_INVAL_FPR (6 << 14)
122:
123: #define FSR_FCC1 (1<<11)
124: #define FSR_FCC0 (1<<10)
125:
126: /* MMU */
127: #define MMU_E (1<<0)
128: #define MMU_NF (1<<1)
129:
130: #define PTE_ENTRYTYPE_MASK 3
131: #define PTE_ACCESS_MASK 0x1c
132: #define PTE_ACCESS_SHIFT 2
133: #define PTE_PPN_SHIFT 7
134: #define PTE_ADDR_MASK 0xffffff00
135:
136: #define PG_ACCESSED_BIT 5
137: #define PG_MODIFIED_BIT 6
138: #define PG_CACHE_BIT 7
139:
140: #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
141: #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
142: #define PG_CACHE_MASK (1 << PG_CACHE_BIT)
143:
144: /* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
145: #define NWINDOWS 8
146:
147: typedef struct CPUSPARCState {
148: target_ulong gregs[8]; /* general registers */
149: target_ulong *regwptr; /* pointer to current register window */
1.1.1.3 ! root 150: float32 fpr[TARGET_FPREGS]; /* floating point registers */
1.1 root 151: target_ulong pc; /* program counter */
152: target_ulong npc; /* next program counter */
153: target_ulong y; /* multiply/divide register */
154: uint32_t psr; /* processor state register */
155: target_ulong fsr; /* FPU state register */
156: uint32_t cwp; /* index of current register window (extracted
157: from PSR) */
158: uint32_t wim; /* window invalid mask */
159: target_ulong tbr; /* trap base register */
160: int psrs; /* supervisor mode (extracted from PSR) */
161: int psrps; /* previous supervisor mode */
162: int psret; /* enable traps */
163: uint32_t psrpil; /* interrupt level */
164: int psref; /* enable fpu */
165: jmp_buf jmp_env;
166: int user_mode_only;
167: int exception_index;
168: int interrupt_index;
169: int interrupt_request;
1.1.1.2 root 170: int halted;
1.1 root 171: /* NOTE: we allow 8 more registers to handle wrapping */
172: target_ulong regbase[NWINDOWS * 16 + 8];
173:
1.1.1.2 root 174: CPU_COMMON
175:
1.1 root 176: /* MMU regs */
177: #if defined(TARGET_SPARC64)
178: uint64_t lsu;
179: #define DMMU_E 0x8
180: #define IMMU_E 0x4
181: uint64_t immuregs[16];
182: uint64_t dmmuregs[16];
183: uint64_t itlb_tag[64];
184: uint64_t itlb_tte[64];
185: uint64_t dtlb_tag[64];
186: uint64_t dtlb_tte[64];
187: #else
188: uint32_t mmuregs[16];
189: #endif
190: /* temporary float registers */
1.1.1.3 ! root 191: float32 ft0, ft1;
! 192: float64 dt0, dt1;
1.1 root 193: float_status fp_status;
194: #if defined(TARGET_SPARC64)
195: #define MAXTL 4
196: uint64_t t0, t1, t2;
197: uint64_t tpc[MAXTL];
198: uint64_t tnpc[MAXTL];
199: uint64_t tstate[MAXTL];
200: uint32_t tt[MAXTL];
201: uint32_t xcc; /* Extended integer condition codes */
202: uint32_t asi;
203: uint32_t pstate;
204: uint32_t tl;
205: uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
206: uint64_t agregs[8]; /* alternate general registers */
207: uint64_t bgregs[8]; /* backup for normal global registers */
208: uint64_t igregs[8]; /* interrupt general registers */
209: uint64_t mgregs[8]; /* mmu general registers */
210: uint64_t version;
211: uint64_t fprs;
212: uint64_t tick_cmpr, stick_cmpr;
1.1.1.3 ! root 213: uint64_t gsr;
1.1 root 214: #endif
215: #if !defined(TARGET_SPARC64) && !defined(reg_T2)
216: target_ulong t2;
217: #endif
218: } CPUSPARCState;
219: #if defined(TARGET_SPARC64)
220: #define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
221: #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
222: env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \
223: } while (0)
224: #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
225: #define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
226: env->fsr = _tmp & 0x3fcfc1c3ffULL; \
227: } while (0)
228: // Manuf 0x17, version 0x11, mask 0 (UltraSparc-II)
229: #define GET_VER(env) ((0x17ULL << 48) | (0x11ULL << 32) | \
230: (0 << 24) | (MAXTL << 8) | (NWINDOWS - 1))
231: #else
232: #define GET_FSR32(env) (env->fsr)
233: #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
234: env->fsr = _tmp & 0xcfc1ffff; \
235: } while (0)
236: #endif
237:
238: CPUSPARCState *cpu_sparc_init(void);
239: int cpu_sparc_exec(CPUSPARCState *s);
240: int cpu_sparc_close(CPUSPARCState *s);
241:
242: /* Fake impl 0, version 4 */
243: #define GET_PSR(env) ((0 << 28) | (4 << 24) | (env->psr & PSR_ICC) | \
244: (env->psref? PSR_EF : 0) | \
245: (env->psrpil << 8) | \
246: (env->psrs? PSR_S : 0) | \
247: (env->psrps? PSR_PS : 0) | \
248: (env->psret? PSR_ET : 0) | env->cwp)
249:
250: #ifndef NO_CPU_IO_DEFS
251: void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
252: #endif
253:
254: #define PUT_PSR(env, val) do { int _tmp = val; \
255: env->psr = _tmp & PSR_ICC; \
256: env->psref = (_tmp & PSR_EF)? 1 : 0; \
257: env->psrpil = (_tmp & PSR_PIL) >> 8; \
258: env->psrs = (_tmp & PSR_S)? 1 : 0; \
259: env->psrps = (_tmp & PSR_PS)? 1 : 0; \
260: env->psret = (_tmp & PSR_ET)? 1 : 0; \
261: cpu_set_cwp(env, _tmp & PSR_CWP & (NWINDOWS - 1)); \
262: } while (0)
263:
264: #ifdef TARGET_SPARC64
265: #define GET_CCR(env) ((env->xcc << 4) | (env->psr & PSR_ICC))
266: #define PUT_CCR(env, val) do { int _tmp = val; \
267: env->xcc = _tmp >> 4; \
268: env->psr = (_tmp & 0xf) << 20; \
269: } while (0)
270: #endif
271:
272: struct siginfo;
273: int cpu_sparc_signal_handler(int hostsignum, struct siginfo *info, void *puc);
274:
275: #include "cpu-all.h"
276:
277: #endif
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.