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1.1 root 1: #ifndef CPU_SPARC_H
2: #define CPU_SPARC_H
3:
4: #include "config.h"
5:
6: #if !defined(TARGET_SPARC64)
7: #define TARGET_LONG_BITS 32
8: #define TARGET_FPREGS 32
9: #define TARGET_PAGE_BITS 12 /* 4k */
10: #else
11: #define TARGET_LONG_BITS 64
12: #define TARGET_FPREGS 64
13: #define TARGET_PAGE_BITS 12 /* XXX */
14: #endif
15:
16: #include "cpu-defs.h"
17:
18: #include "softfloat.h"
19:
20: #define TARGET_HAS_ICE 1
21:
1.1.1.4 ! root 22: #if !defined(TARGET_SPARC64)
! 23: #define ELF_MACHINE EM_SPARC
! 24: #else
! 25: #define ELF_MACHINE EM_SPARCV9
! 26: #endif
! 27:
1.1 root 28: /*#define EXCP_INTERRUPT 0x100*/
29:
30: /* trap definitions */
31: #ifndef TARGET_SPARC64
32: #define TT_TFAULT 0x01
33: #define TT_ILL_INSN 0x02
34: #define TT_PRIV_INSN 0x03
35: #define TT_NFPU_INSN 0x04
36: #define TT_WIN_OVF 0x05
37: #define TT_WIN_UNF 0x06
38: #define TT_FP_EXCP 0x08
39: #define TT_DFAULT 0x09
40: #define TT_EXTINT 0x10
41: #define TT_DIV_ZERO 0x2a
42: #define TT_TRAP 0x80
43: #else
44: #define TT_TFAULT 0x08
45: #define TT_TMISS 0x09
46: #define TT_ILL_INSN 0x10
47: #define TT_PRIV_INSN 0x11
48: #define TT_NFPU_INSN 0x20
49: #define TT_FP_EXCP 0x21
50: #define TT_CLRWIN 0x24
51: #define TT_DIV_ZERO 0x28
52: #define TT_DFAULT 0x30
53: #define TT_DMISS 0x31
54: #define TT_DPROT 0x32
55: #define TT_PRIV_ACT 0x37
56: #define TT_EXTINT 0x40
57: #define TT_SPILL 0x80
58: #define TT_FILL 0xc0
59: #define TT_WOTHER 0x10
60: #define TT_TRAP 0x100
61: #endif
62:
63: #define PSR_NEG (1<<23)
64: #define PSR_ZERO (1<<22)
65: #define PSR_OVF (1<<21)
66: #define PSR_CARRY (1<<20)
67: #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
68: #define PSR_EF (1<<12)
69: #define PSR_PIL 0xf00
70: #define PSR_S (1<<7)
71: #define PSR_PS (1<<6)
72: #define PSR_ET (1<<5)
73: #define PSR_CWP 0x1f
74:
75: /* Trap base register */
76: #define TBR_BASE_MASK 0xfffff000
77:
78: #if defined(TARGET_SPARC64)
79: #define PS_IG (1<<11)
80: #define PS_MG (1<<10)
81: #define PS_RED (1<<5)
82: #define PS_PEF (1<<4)
83: #define PS_AM (1<<3)
84: #define PS_PRIV (1<<2)
85: #define PS_IE (1<<1)
86: #define PS_AG (1<<0)
1.1.1.3 root 87:
88: #define FPRS_FEF (1<<2)
1.1 root 89: #endif
90:
91: /* Fcc */
92: #define FSR_RD1 (1<<31)
93: #define FSR_RD0 (1<<30)
94: #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
95: #define FSR_RD_NEAREST 0
96: #define FSR_RD_ZERO FSR_RD0
97: #define FSR_RD_POS FSR_RD1
98: #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
99:
100: #define FSR_NVM (1<<27)
101: #define FSR_OFM (1<<26)
102: #define FSR_UFM (1<<25)
103: #define FSR_DZM (1<<24)
104: #define FSR_NXM (1<<23)
105: #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
106:
107: #define FSR_NVA (1<<9)
108: #define FSR_OFA (1<<8)
109: #define FSR_UFA (1<<7)
110: #define FSR_DZA (1<<6)
111: #define FSR_NXA (1<<5)
112: #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
113:
114: #define FSR_NVC (1<<4)
115: #define FSR_OFC (1<<3)
116: #define FSR_UFC (1<<2)
117: #define FSR_DZC (1<<1)
118: #define FSR_NXC (1<<0)
119: #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
120:
121: #define FSR_FTT2 (1<<16)
122: #define FSR_FTT1 (1<<15)
123: #define FSR_FTT0 (1<<14)
124: #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
125: #define FSR_FTT_IEEE_EXCP (1 << 14)
126: #define FSR_FTT_UNIMPFPOP (3 << 14)
127: #define FSR_FTT_INVAL_FPR (6 << 14)
128:
129: #define FSR_FCC1 (1<<11)
130: #define FSR_FCC0 (1<<10)
131:
132: /* MMU */
133: #define MMU_E (1<<0)
134: #define MMU_NF (1<<1)
135:
136: #define PTE_ENTRYTYPE_MASK 3
137: #define PTE_ACCESS_MASK 0x1c
138: #define PTE_ACCESS_SHIFT 2
139: #define PTE_PPN_SHIFT 7
140: #define PTE_ADDR_MASK 0xffffff00
141:
142: #define PG_ACCESSED_BIT 5
143: #define PG_MODIFIED_BIT 6
144: #define PG_CACHE_BIT 7
145:
146: #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
147: #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
148: #define PG_CACHE_MASK (1 << PG_CACHE_BIT)
149:
150: /* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
151: #define NWINDOWS 8
152:
153: typedef struct CPUSPARCState {
154: target_ulong gregs[8]; /* general registers */
155: target_ulong *regwptr; /* pointer to current register window */
1.1.1.3 root 156: float32 fpr[TARGET_FPREGS]; /* floating point registers */
1.1 root 157: target_ulong pc; /* program counter */
158: target_ulong npc; /* next program counter */
159: target_ulong y; /* multiply/divide register */
160: uint32_t psr; /* processor state register */
161: target_ulong fsr; /* FPU state register */
162: uint32_t cwp; /* index of current register window (extracted
163: from PSR) */
164: uint32_t wim; /* window invalid mask */
165: target_ulong tbr; /* trap base register */
166: int psrs; /* supervisor mode (extracted from PSR) */
167: int psrps; /* previous supervisor mode */
168: int psret; /* enable traps */
169: uint32_t psrpil; /* interrupt level */
170: int psref; /* enable fpu */
171: jmp_buf jmp_env;
172: int user_mode_only;
173: int exception_index;
174: int interrupt_index;
175: int interrupt_request;
1.1.1.2 root 176: int halted;
1.1 root 177: /* NOTE: we allow 8 more registers to handle wrapping */
178: target_ulong regbase[NWINDOWS * 16 + 8];
179:
1.1.1.2 root 180: CPU_COMMON
181:
1.1 root 182: /* MMU regs */
183: #if defined(TARGET_SPARC64)
184: uint64_t lsu;
185: #define DMMU_E 0x8
186: #define IMMU_E 0x4
187: uint64_t immuregs[16];
188: uint64_t dmmuregs[16];
189: uint64_t itlb_tag[64];
190: uint64_t itlb_tte[64];
191: uint64_t dtlb_tag[64];
192: uint64_t dtlb_tte[64];
193: #else
194: uint32_t mmuregs[16];
195: #endif
196: /* temporary float registers */
1.1.1.3 root 197: float32 ft0, ft1;
198: float64 dt0, dt1;
1.1 root 199: float_status fp_status;
200: #if defined(TARGET_SPARC64)
201: #define MAXTL 4
202: uint64_t t0, t1, t2;
203: uint64_t tpc[MAXTL];
204: uint64_t tnpc[MAXTL];
205: uint64_t tstate[MAXTL];
206: uint32_t tt[MAXTL];
207: uint32_t xcc; /* Extended integer condition codes */
208: uint32_t asi;
209: uint32_t pstate;
210: uint32_t tl;
211: uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
212: uint64_t agregs[8]; /* alternate general registers */
213: uint64_t bgregs[8]; /* backup for normal global registers */
214: uint64_t igregs[8]; /* interrupt general registers */
215: uint64_t mgregs[8]; /* mmu general registers */
216: uint64_t version;
217: uint64_t fprs;
218: uint64_t tick_cmpr, stick_cmpr;
1.1.1.3 root 219: uint64_t gsr;
1.1 root 220: #endif
221: #if !defined(TARGET_SPARC64) && !defined(reg_T2)
222: target_ulong t2;
223: #endif
224: } CPUSPARCState;
225: #if defined(TARGET_SPARC64)
226: #define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
227: #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
228: env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \
229: } while (0)
230: #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
231: #define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
232: env->fsr = _tmp & 0x3fcfc1c3ffULL; \
233: } while (0)
234: // Manuf 0x17, version 0x11, mask 0 (UltraSparc-II)
235: #define GET_VER(env) ((0x17ULL << 48) | (0x11ULL << 32) | \
236: (0 << 24) | (MAXTL << 8) | (NWINDOWS - 1))
237: #else
238: #define GET_FSR32(env) (env->fsr)
239: #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
240: env->fsr = _tmp & 0xcfc1ffff; \
241: } while (0)
242: #endif
243:
244: CPUSPARCState *cpu_sparc_init(void);
245: int cpu_sparc_exec(CPUSPARCState *s);
246: int cpu_sparc_close(CPUSPARCState *s);
247:
248: /* Fake impl 0, version 4 */
249: #define GET_PSR(env) ((0 << 28) | (4 << 24) | (env->psr & PSR_ICC) | \
250: (env->psref? PSR_EF : 0) | \
251: (env->psrpil << 8) | \
252: (env->psrs? PSR_S : 0) | \
253: (env->psrps? PSR_PS : 0) | \
254: (env->psret? PSR_ET : 0) | env->cwp)
255:
256: #ifndef NO_CPU_IO_DEFS
257: void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
258: #endif
259:
260: #define PUT_PSR(env, val) do { int _tmp = val; \
261: env->psr = _tmp & PSR_ICC; \
262: env->psref = (_tmp & PSR_EF)? 1 : 0; \
263: env->psrpil = (_tmp & PSR_PIL) >> 8; \
264: env->psrs = (_tmp & PSR_S)? 1 : 0; \
265: env->psrps = (_tmp & PSR_PS)? 1 : 0; \
266: env->psret = (_tmp & PSR_ET)? 1 : 0; \
267: cpu_set_cwp(env, _tmp & PSR_CWP & (NWINDOWS - 1)); \
268: } while (0)
269:
270: #ifdef TARGET_SPARC64
271: #define GET_CCR(env) ((env->xcc << 4) | (env->psr & PSR_ICC))
272: #define PUT_CCR(env, val) do { int _tmp = val; \
273: env->xcc = _tmp >> 4; \
274: env->psr = (_tmp & 0xf) << 20; \
275: } while (0)
276: #endif
277:
1.1.1.4 ! root 278: int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
1.1 root 279:
280: #include "cpu-all.h"
281:
282: #endif
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