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1.1 root 1: #ifndef CPU_SPARC_H
2: #define CPU_SPARC_H
3:
4: #include "config.h"
5:
6: #if !defined(TARGET_SPARC64)
7: #define TARGET_LONG_BITS 32
8: #define TARGET_FPREGS 32
9: #define TARGET_PAGE_BITS 12 /* 4k */
10: #else
11: #define TARGET_LONG_BITS 64
12: #define TARGET_FPREGS 64
1.1.1.5 ! root 13: #define TARGET_PAGE_BITS 13 /* 8k */
1.1 root 14: #endif
15:
1.1.1.5 ! root 16: #define TARGET_PHYS_ADDR_BITS 64
! 17:
1.1 root 18: #include "cpu-defs.h"
19:
20: #include "softfloat.h"
21:
22: #define TARGET_HAS_ICE 1
23:
1.1.1.4 root 24: #if !defined(TARGET_SPARC64)
1.1.1.5 ! root 25: #define ELF_MACHINE EM_SPARC
1.1.1.4 root 26: #else
1.1.1.5 ! root 27: #define ELF_MACHINE EM_SPARCV9
1.1.1.4 root 28: #endif
29:
1.1 root 30: /*#define EXCP_INTERRUPT 0x100*/
31:
32: /* trap definitions */
33: #ifndef TARGET_SPARC64
34: #define TT_TFAULT 0x01
35: #define TT_ILL_INSN 0x02
36: #define TT_PRIV_INSN 0x03
37: #define TT_NFPU_INSN 0x04
38: #define TT_WIN_OVF 0x05
1.1.1.5 ! root 39: #define TT_WIN_UNF 0x06
! 40: #define TT_UNALIGNED 0x07
1.1 root 41: #define TT_FP_EXCP 0x08
42: #define TT_DFAULT 0x09
1.1.1.5 ! root 43: #define TT_TOVF 0x0a
1.1 root 44: #define TT_EXTINT 0x10
1.1.1.5 ! root 45: #define TT_CODE_ACCESS 0x21
! 46: #define TT_DATA_ACCESS 0x29
1.1 root 47: #define TT_DIV_ZERO 0x2a
1.1.1.5 ! root 48: #define TT_NCP_INSN 0x24
1.1 root 49: #define TT_TRAP 0x80
50: #else
51: #define TT_TFAULT 0x08
52: #define TT_TMISS 0x09
1.1.1.5 ! root 53: #define TT_CODE_ACCESS 0x0a
1.1 root 54: #define TT_ILL_INSN 0x10
55: #define TT_PRIV_INSN 0x11
56: #define TT_NFPU_INSN 0x20
57: #define TT_FP_EXCP 0x21
1.1.1.5 ! root 58: #define TT_TOVF 0x23
1.1 root 59: #define TT_CLRWIN 0x24
60: #define TT_DIV_ZERO 0x28
61: #define TT_DFAULT 0x30
62: #define TT_DMISS 0x31
1.1.1.5 ! root 63: #define TT_DATA_ACCESS 0x32
! 64: #define TT_DPROT 0x33
! 65: #define TT_UNALIGNED 0x34
1.1 root 66: #define TT_PRIV_ACT 0x37
67: #define TT_EXTINT 0x40
68: #define TT_SPILL 0x80
69: #define TT_FILL 0xc0
70: #define TT_WOTHER 0x10
71: #define TT_TRAP 0x100
72: #endif
73:
74: #define PSR_NEG (1<<23)
75: #define PSR_ZERO (1<<22)
76: #define PSR_OVF (1<<21)
77: #define PSR_CARRY (1<<20)
78: #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
79: #define PSR_EF (1<<12)
80: #define PSR_PIL 0xf00
81: #define PSR_S (1<<7)
82: #define PSR_PS (1<<6)
83: #define PSR_ET (1<<5)
84: #define PSR_CWP 0x1f
85:
86: /* Trap base register */
87: #define TBR_BASE_MASK 0xfffff000
88:
89: #if defined(TARGET_SPARC64)
90: #define PS_IG (1<<11)
91: #define PS_MG (1<<10)
1.1.1.5 ! root 92: #define PS_RMO (1<<7)
1.1 root 93: #define PS_RED (1<<5)
94: #define PS_PEF (1<<4)
95: #define PS_AM (1<<3)
96: #define PS_PRIV (1<<2)
97: #define PS_IE (1<<1)
98: #define PS_AG (1<<0)
1.1.1.3 root 99:
100: #define FPRS_FEF (1<<2)
1.1.1.5 ! root 101:
! 102: #define HS_PRIV (1<<2)
1.1 root 103: #endif
104:
105: /* Fcc */
106: #define FSR_RD1 (1<<31)
107: #define FSR_RD0 (1<<30)
108: #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
109: #define FSR_RD_NEAREST 0
110: #define FSR_RD_ZERO FSR_RD0
111: #define FSR_RD_POS FSR_RD1
112: #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
113:
114: #define FSR_NVM (1<<27)
115: #define FSR_OFM (1<<26)
116: #define FSR_UFM (1<<25)
117: #define FSR_DZM (1<<24)
118: #define FSR_NXM (1<<23)
119: #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
120:
121: #define FSR_NVA (1<<9)
122: #define FSR_OFA (1<<8)
123: #define FSR_UFA (1<<7)
124: #define FSR_DZA (1<<6)
125: #define FSR_NXA (1<<5)
126: #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
127:
128: #define FSR_NVC (1<<4)
129: #define FSR_OFC (1<<3)
130: #define FSR_UFC (1<<2)
131: #define FSR_DZC (1<<1)
132: #define FSR_NXC (1<<0)
133: #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
134:
135: #define FSR_FTT2 (1<<16)
136: #define FSR_FTT1 (1<<15)
137: #define FSR_FTT0 (1<<14)
138: #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
139: #define FSR_FTT_IEEE_EXCP (1 << 14)
140: #define FSR_FTT_UNIMPFPOP (3 << 14)
1.1.1.5 ! root 141: #define FSR_FTT_SEQ_ERROR (4 << 14)
1.1 root 142: #define FSR_FTT_INVAL_FPR (6 << 14)
143:
144: #define FSR_FCC1 (1<<11)
145: #define FSR_FCC0 (1<<10)
146:
147: /* MMU */
1.1.1.5 ! root 148: #define MMU_E (1<<0)
! 149: #define MMU_NF (1<<1)
1.1 root 150:
151: #define PTE_ENTRYTYPE_MASK 3
152: #define PTE_ACCESS_MASK 0x1c
153: #define PTE_ACCESS_SHIFT 2
154: #define PTE_PPN_SHIFT 7
155: #define PTE_ADDR_MASK 0xffffff00
156:
1.1.1.5 ! root 157: #define PG_ACCESSED_BIT 5
! 158: #define PG_MODIFIED_BIT 6
1.1 root 159: #define PG_CACHE_BIT 7
160:
161: #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
162: #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
163: #define PG_CACHE_MASK (1 << PG_CACHE_BIT)
164:
165: /* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
166: #define NWINDOWS 8
167:
1.1.1.5 ! root 168: #if !defined(TARGET_SPARC64)
! 169: #define NB_MMU_MODES 2
! 170: #else
! 171: #define NB_MMU_MODES 3
! 172: #endif
! 173:
1.1 root 174: typedef struct CPUSPARCState {
175: target_ulong gregs[8]; /* general registers */
176: target_ulong *regwptr; /* pointer to current register window */
1.1.1.3 root 177: float32 fpr[TARGET_FPREGS]; /* floating point registers */
1.1 root 178: target_ulong pc; /* program counter */
179: target_ulong npc; /* next program counter */
180: target_ulong y; /* multiply/divide register */
181: uint32_t psr; /* processor state register */
182: target_ulong fsr; /* FPU state register */
183: uint32_t cwp; /* index of current register window (extracted
184: from PSR) */
185: uint32_t wim; /* window invalid mask */
186: target_ulong tbr; /* trap base register */
187: int psrs; /* supervisor mode (extracted from PSR) */
188: int psrps; /* previous supervisor mode */
189: int psret; /* enable traps */
1.1.1.5 ! root 190: uint32_t psrpil; /* interrupt blocking level */
! 191: uint32_t pil_in; /* incoming interrupt level bitmap */
1.1 root 192: int psref; /* enable fpu */
1.1.1.5 ! root 193: target_ulong version;
1.1 root 194: jmp_buf jmp_env;
195: int user_mode_only;
196: int exception_index;
197: int interrupt_index;
198: int interrupt_request;
1.1.1.2 root 199: int halted;
1.1.1.5 ! root 200: uint32_t mmu_bm;
1.1 root 201: /* NOTE: we allow 8 more registers to handle wrapping */
202: target_ulong regbase[NWINDOWS * 16 + 8];
203:
1.1.1.2 root 204: CPU_COMMON
205:
1.1 root 206: /* MMU regs */
207: #if defined(TARGET_SPARC64)
208: uint64_t lsu;
209: #define DMMU_E 0x8
210: #define IMMU_E 0x4
211: uint64_t immuregs[16];
212: uint64_t dmmuregs[16];
213: uint64_t itlb_tag[64];
214: uint64_t itlb_tte[64];
215: uint64_t dtlb_tag[64];
216: uint64_t dtlb_tte[64];
217: #else
1.1.1.5 ! root 218: uint32_t mmuregs[32];
! 219: uint64_t mxccdata[4];
! 220: uint64_t mxccregs[8];
! 221: uint64_t prom_addr;
1.1 root 222: #endif
223: /* temporary float registers */
1.1.1.3 root 224: float32 ft0, ft1;
225: float64 dt0, dt1;
1.1.1.5 ! root 226: #if defined(CONFIG_USER_ONLY)
! 227: float128 qt0, qt1;
! 228: #endif
1.1 root 229: float_status fp_status;
230: #if defined(TARGET_SPARC64)
231: #define MAXTL 4
232: uint64_t t0, t1, t2;
233: uint64_t tpc[MAXTL];
234: uint64_t tnpc[MAXTL];
235: uint64_t tstate[MAXTL];
236: uint32_t tt[MAXTL];
1.1.1.5 ! root 237: uint32_t xcc; /* Extended integer condition codes */
1.1 root 238: uint32_t asi;
239: uint32_t pstate;
240: uint32_t tl;
241: uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
242: uint64_t agregs[8]; /* alternate general registers */
243: uint64_t bgregs[8]; /* backup for normal global registers */
244: uint64_t igregs[8]; /* interrupt general registers */
245: uint64_t mgregs[8]; /* mmu general registers */
246: uint64_t fprs;
247: uint64_t tick_cmpr, stick_cmpr;
1.1.1.5 ! root 248: void *tick, *stick;
1.1.1.3 root 249: uint64_t gsr;
1.1.1.5 ! root 250: uint32_t gl; // UA2005
! 251: /* UA 2005 hyperprivileged registers */
! 252: uint64_t hpstate, htstate[MAXTL], hintp, htba, hver, hstick_cmpr, ssr;
! 253: void *hstick; // UA 2005
1.1 root 254: #endif
255: #if !defined(TARGET_SPARC64) && !defined(reg_T2)
256: target_ulong t2;
257: #endif
258: } CPUSPARCState;
259: #if defined(TARGET_SPARC64)
260: #define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
1.1.1.5 ! root 261: #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
! 262: env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \
1.1 root 263: } while (0)
264: #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
1.1.1.5 ! root 265: #define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
! 266: env->fsr = _tmp & 0x3fcfc1c3ffULL; \
1.1 root 267: } while (0)
268: #else
269: #define GET_FSR32(env) (env->fsr)
1.1.1.5 ! root 270: #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
! 271: env->fsr = (_tmp & 0xcfc1dfff) | (env->fsr & 0x000e0000); \
1.1 root 272: } while (0)
273: #endif
274:
1.1.1.5 ! root 275: CPUSPARCState *cpu_sparc_init(const char *cpu_model);
1.1 root 276: int cpu_sparc_exec(CPUSPARCState *s);
277: int cpu_sparc_close(CPUSPARCState *s);
1.1.1.5 ! root 278: void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
! 279: ...));
! 280: void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
! 281:
! 282: #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \
! 283: (env->psref? PSR_EF : 0) | \
! 284: (env->psrpil << 8) | \
! 285: (env->psrs? PSR_S : 0) | \
! 286: (env->psrps? PSR_PS : 0) | \
! 287: (env->psret? PSR_ET : 0) | env->cwp)
1.1 root 288:
289: #ifndef NO_CPU_IO_DEFS
290: void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
291: #endif
292:
1.1.1.5 ! root 293: #define PUT_PSR(env, val) do { int _tmp = val; \
! 294: env->psr = _tmp & PSR_ICC; \
! 295: env->psref = (_tmp & PSR_EF)? 1 : 0; \
! 296: env->psrpil = (_tmp & PSR_PIL) >> 8; \
! 297: env->psrs = (_tmp & PSR_S)? 1 : 0; \
! 298: env->psrps = (_tmp & PSR_PS)? 1 : 0; \
! 299: env->psret = (_tmp & PSR_ET)? 1 : 0; \
! 300: cpu_set_cwp(env, _tmp & PSR_CWP); \
1.1 root 301: } while (0)
302:
303: #ifdef TARGET_SPARC64
1.1.1.5 ! root 304: #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
! 305: #define PUT_CCR(env, val) do { int _tmp = val; \
! 306: env->xcc = (_tmp >> 4) << 20; \
! 307: env->psr = (_tmp & 0xf) << 20; \
1.1 root 308: } while (0)
1.1.1.5 ! root 309: #define GET_CWP64(env) (NWINDOWS - 1 - (env)->cwp)
! 310: #define PUT_CWP64(env, val) \
! 311: cpu_set_cwp(env, NWINDOWS - 1 - ((val) & (NWINDOWS - 1)))
! 312:
1.1 root 313: #endif
314:
1.1.1.4 root 315: int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
1.1.1.5 ! root 316: void raise_exception(int tt);
! 317: void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
! 318: int is_asi);
! 319: void do_tick_set_count(void *opaque, uint64_t count);
! 320: uint64_t do_tick_get_count(void *opaque);
! 321: void do_tick_set_limit(void *opaque, uint64_t limit);
! 322: void cpu_check_irqs(CPUSPARCState *env);
! 323:
! 324: #define CPUState CPUSPARCState
! 325: #define cpu_init cpu_sparc_init
! 326: #define cpu_exec cpu_sparc_exec
! 327: #define cpu_gen_code cpu_sparc_gen_code
! 328: #define cpu_signal_handler cpu_sparc_signal_handler
! 329: #define cpu_list sparc_cpu_list
! 330:
! 331: /* MMU modes definitions */
! 332: #define MMU_MODE0_SUFFIX _user
! 333: #define MMU_MODE1_SUFFIX _kernel
! 334: #ifdef TARGET_SPARC64
! 335: #define MMU_MODE2_SUFFIX _hypv
! 336: #endif
! 337: #define MMU_USER_IDX 0
! 338: static inline int cpu_mmu_index (CPUState *env)
! 339: {
! 340: #if defined(CONFIG_USER_ONLY)
! 341: return 0;
! 342: #elif !defined(TARGET_SPARC64)
! 343: return env->psrs;
! 344: #else
! 345: if (!env->psrs)
! 346: return 0;
! 347: else if ((env->hpstate & HS_PRIV) == 0)
! 348: return 1;
! 349: else
! 350: return 2;
! 351: #endif
! 352: }
! 353:
! 354: static inline int cpu_fpu_enabled(CPUState *env)
! 355: {
! 356: #if defined(CONFIG_USER_ONLY)
! 357: return 1;
! 358: #elif !defined(TARGET_SPARC64)
! 359: return env->psref;
! 360: #else
! 361: return ((env->pstate & PS_PEF) != 0) && ((env->fprs & FPRS_FEF) != 0);
! 362: #endif
! 363: }
1.1 root 364:
365: #include "cpu-all.h"
366:
367: #endif
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