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1.1 root 1: #ifndef CPU_SPARC_H
2: #define CPU_SPARC_H
3:
4: #include "config.h"
5:
6: #if !defined(TARGET_SPARC64)
7: #define TARGET_LONG_BITS 32
8: #define TARGET_FPREGS 32
9: #define TARGET_PAGE_BITS 12 /* 4k */
10: #else
11: #define TARGET_LONG_BITS 64
12: #define TARGET_FPREGS 64
1.1.1.5 root 13: #define TARGET_PAGE_BITS 13 /* 8k */
1.1 root 14: #endif
15:
1.1.1.5 root 16: #define TARGET_PHYS_ADDR_BITS 64
17:
1.1 root 18: #include "cpu-defs.h"
19:
20: #include "softfloat.h"
21:
22: #define TARGET_HAS_ICE 1
23:
1.1.1.4 root 24: #if !defined(TARGET_SPARC64)
1.1.1.5 root 25: #define ELF_MACHINE EM_SPARC
1.1.1.4 root 26: #else
1.1.1.5 root 27: #define ELF_MACHINE EM_SPARCV9
1.1.1.4 root 28: #endif
29:
1.1 root 30: /*#define EXCP_INTERRUPT 0x100*/
31:
32: /* trap definitions */
33: #ifndef TARGET_SPARC64
34: #define TT_TFAULT 0x01
35: #define TT_ILL_INSN 0x02
36: #define TT_PRIV_INSN 0x03
37: #define TT_NFPU_INSN 0x04
38: #define TT_WIN_OVF 0x05
1.1.1.5 root 39: #define TT_WIN_UNF 0x06
40: #define TT_UNALIGNED 0x07
1.1 root 41: #define TT_FP_EXCP 0x08
42: #define TT_DFAULT 0x09
1.1.1.5 root 43: #define TT_TOVF 0x0a
1.1 root 44: #define TT_EXTINT 0x10
1.1.1.5 root 45: #define TT_CODE_ACCESS 0x21
1.1.1.6 ! root 46: #define TT_UNIMP_FLUSH 0x25
1.1.1.5 root 47: #define TT_DATA_ACCESS 0x29
1.1 root 48: #define TT_DIV_ZERO 0x2a
1.1.1.5 root 49: #define TT_NCP_INSN 0x24
1.1 root 50: #define TT_TRAP 0x80
51: #else
52: #define TT_TFAULT 0x08
1.1.1.5 root 53: #define TT_CODE_ACCESS 0x0a
1.1 root 54: #define TT_ILL_INSN 0x10
1.1.1.6 ! root 55: #define TT_UNIMP_FLUSH TT_ILL_INSN
1.1 root 56: #define TT_PRIV_INSN 0x11
57: #define TT_NFPU_INSN 0x20
58: #define TT_FP_EXCP 0x21
1.1.1.5 root 59: #define TT_TOVF 0x23
1.1 root 60: #define TT_CLRWIN 0x24
61: #define TT_DIV_ZERO 0x28
62: #define TT_DFAULT 0x30
1.1.1.5 root 63: #define TT_DATA_ACCESS 0x32
64: #define TT_UNALIGNED 0x34
1.1 root 65: #define TT_PRIV_ACT 0x37
66: #define TT_EXTINT 0x40
1.1.1.6 ! root 67: #define TT_IVEC 0x60
! 68: #define TT_TMISS 0x64
! 69: #define TT_DMISS 0x68
! 70: #define TT_DPROT 0x6c
1.1 root 71: #define TT_SPILL 0x80
72: #define TT_FILL 0xc0
73: #define TT_WOTHER 0x10
74: #define TT_TRAP 0x100
75: #endif
76:
1.1.1.6 ! root 77: #define PSR_NEG_SHIFT 23
! 78: #define PSR_NEG (1 << PSR_NEG_SHIFT)
! 79: #define PSR_ZERO_SHIFT 22
! 80: #define PSR_ZERO (1 << PSR_ZERO_SHIFT)
! 81: #define PSR_OVF_SHIFT 21
! 82: #define PSR_OVF (1 << PSR_OVF_SHIFT)
! 83: #define PSR_CARRY_SHIFT 20
! 84: #define PSR_CARRY (1 << PSR_CARRY_SHIFT)
1.1 root 85: #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
86: #define PSR_EF (1<<12)
87: #define PSR_PIL 0xf00
88: #define PSR_S (1<<7)
89: #define PSR_PS (1<<6)
90: #define PSR_ET (1<<5)
91: #define PSR_CWP 0x1f
92:
93: /* Trap base register */
94: #define TBR_BASE_MASK 0xfffff000
95:
96: #if defined(TARGET_SPARC64)
97: #define PS_IG (1<<11)
98: #define PS_MG (1<<10)
1.1.1.5 root 99: #define PS_RMO (1<<7)
1.1 root 100: #define PS_RED (1<<5)
101: #define PS_PEF (1<<4)
102: #define PS_AM (1<<3)
103: #define PS_PRIV (1<<2)
104: #define PS_IE (1<<1)
105: #define PS_AG (1<<0)
1.1.1.3 root 106:
107: #define FPRS_FEF (1<<2)
1.1.1.5 root 108:
109: #define HS_PRIV (1<<2)
1.1 root 110: #endif
111:
112: /* Fcc */
1.1.1.6 ! root 113: #define FSR_RD1 (1ULL << 31)
! 114: #define FSR_RD0 (1ULL << 30)
1.1 root 115: #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
116: #define FSR_RD_NEAREST 0
117: #define FSR_RD_ZERO FSR_RD0
118: #define FSR_RD_POS FSR_RD1
119: #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
120:
1.1.1.6 ! root 121: #define FSR_NVM (1ULL << 27)
! 122: #define FSR_OFM (1ULL << 26)
! 123: #define FSR_UFM (1ULL << 25)
! 124: #define FSR_DZM (1ULL << 24)
! 125: #define FSR_NXM (1ULL << 23)
1.1 root 126: #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
127:
1.1.1.6 ! root 128: #define FSR_NVA (1ULL << 9)
! 129: #define FSR_OFA (1ULL << 8)
! 130: #define FSR_UFA (1ULL << 7)
! 131: #define FSR_DZA (1ULL << 6)
! 132: #define FSR_NXA (1ULL << 5)
1.1 root 133: #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
134:
1.1.1.6 ! root 135: #define FSR_NVC (1ULL << 4)
! 136: #define FSR_OFC (1ULL << 3)
! 137: #define FSR_UFC (1ULL << 2)
! 138: #define FSR_DZC (1ULL << 1)
! 139: #define FSR_NXC (1ULL << 0)
1.1 root 140: #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
141:
1.1.1.6 ! root 142: #define FSR_FTT2 (1ULL << 16)
! 143: #define FSR_FTT1 (1ULL << 15)
! 144: #define FSR_FTT0 (1ULL << 14)
! 145: //gcc warns about constant overflow for ~FSR_FTT_MASK
! 146: //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
! 147: #ifdef TARGET_SPARC64
! 148: #define FSR_FTT_NMASK 0xfffffffffffe3fffULL
! 149: #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
! 150: #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL
! 151: #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL
! 152: #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
! 153: #else
! 154: #define FSR_FTT_NMASK 0xfffe3fffULL
! 155: #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
! 156: #define FSR_LDFSR_OLDMASK 0x000fc000ULL
! 157: #endif
! 158: #define FSR_LDFSR_MASK 0xcfc00fffULL
! 159: #define FSR_FTT_IEEE_EXCP (1ULL << 14)
! 160: #define FSR_FTT_UNIMPFPOP (3ULL << 14)
! 161: #define FSR_FTT_SEQ_ERROR (4ULL << 14)
! 162: #define FSR_FTT_INVAL_FPR (6ULL << 14)
! 163:
! 164: #define FSR_FCC1_SHIFT 11
! 165: #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT)
! 166: #define FSR_FCC0_SHIFT 10
! 167: #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT)
1.1 root 168:
169: /* MMU */
1.1.1.5 root 170: #define MMU_E (1<<0)
171: #define MMU_NF (1<<1)
1.1 root 172:
173: #define PTE_ENTRYTYPE_MASK 3
174: #define PTE_ACCESS_MASK 0x1c
175: #define PTE_ACCESS_SHIFT 2
176: #define PTE_PPN_SHIFT 7
177: #define PTE_ADDR_MASK 0xffffff00
178:
1.1.1.5 root 179: #define PG_ACCESSED_BIT 5
180: #define PG_MODIFIED_BIT 6
1.1 root 181: #define PG_CACHE_BIT 7
182:
183: #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
184: #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
185: #define PG_CACHE_MASK (1 << PG_CACHE_BIT)
186:
1.1.1.6 ! root 187: /* 3 <= NWINDOWS <= 32. */
! 188: #define MIN_NWINDOWS 3
! 189: #define MAX_NWINDOWS 32
1.1 root 190:
1.1.1.5 root 191: #if !defined(TARGET_SPARC64)
192: #define NB_MMU_MODES 2
193: #else
194: #define NB_MMU_MODES 3
1.1.1.6 ! root 195: typedef struct trap_state {
! 196: uint64_t tpc;
! 197: uint64_t tnpc;
! 198: uint64_t tstate;
! 199: uint32_t tt;
! 200: } trap_state;
! 201: #endif
! 202:
! 203: typedef struct sparc_def_t {
! 204: const char *name;
! 205: target_ulong iu_version;
! 206: uint32_t fpu_version;
! 207: uint32_t mmu_version;
! 208: uint32_t mmu_bm;
! 209: uint32_t mmu_ctpr_mask;
! 210: uint32_t mmu_cxr_mask;
! 211: uint32_t mmu_sfsr_mask;
! 212: uint32_t mmu_trcr_mask;
! 213: uint32_t mxcc_version;
! 214: uint32_t features;
! 215: uint32_t nwindows;
! 216: uint32_t maxtl;
! 217: } sparc_def_t;
! 218:
! 219: #define CPU_FEATURE_FLOAT (1 << 0)
! 220: #define CPU_FEATURE_FLOAT128 (1 << 1)
! 221: #define CPU_FEATURE_SWAP (1 << 2)
! 222: #define CPU_FEATURE_MUL (1 << 3)
! 223: #define CPU_FEATURE_DIV (1 << 4)
! 224: #define CPU_FEATURE_FLUSH (1 << 5)
! 225: #define CPU_FEATURE_FSQRT (1 << 6)
! 226: #define CPU_FEATURE_FMUL (1 << 7)
! 227: #define CPU_FEATURE_VIS1 (1 << 8)
! 228: #define CPU_FEATURE_VIS2 (1 << 9)
! 229: #define CPU_FEATURE_FSMULD (1 << 10)
! 230: #define CPU_FEATURE_HYPV (1 << 11)
! 231: #define CPU_FEATURE_CMT (1 << 12)
! 232: #define CPU_FEATURE_GL (1 << 13)
! 233: #ifndef TARGET_SPARC64
! 234: #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
! 235: CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
! 236: CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
! 237: CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
! 238: #else
! 239: #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
! 240: CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
! 241: CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
! 242: CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \
! 243: CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD)
! 244: enum {
! 245: mmu_us_12, // Ultrasparc < III (64 entry TLB)
! 246: mmu_us_3, // Ultrasparc III (512 entry TLB)
! 247: mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages)
! 248: mmu_sun4v, // T1, T2
! 249: };
1.1.1.5 root 250: #endif
251:
1.1 root 252: typedef struct CPUSPARCState {
253: target_ulong gregs[8]; /* general registers */
254: target_ulong *regwptr; /* pointer to current register window */
255: target_ulong pc; /* program counter */
256: target_ulong npc; /* next program counter */
257: target_ulong y; /* multiply/divide register */
1.1.1.6 ! root 258:
! 259: /* emulator internal flags handling */
! 260: target_ulong cc_src, cc_src2;
! 261: target_ulong cc_dst;
! 262:
! 263: target_ulong t0, t1; /* temporaries live across basic blocks */
! 264: target_ulong cond; /* conditional branch result (XXX: save it in a
! 265: temporary register when possible) */
! 266:
1.1 root 267: uint32_t psr; /* processor state register */
268: target_ulong fsr; /* FPU state register */
1.1.1.6 ! root 269: float32 fpr[TARGET_FPREGS]; /* floating point registers */
1.1 root 270: uint32_t cwp; /* index of current register window (extracted
271: from PSR) */
272: uint32_t wim; /* window invalid mask */
273: target_ulong tbr; /* trap base register */
274: int psrs; /* supervisor mode (extracted from PSR) */
275: int psrps; /* previous supervisor mode */
276: int psret; /* enable traps */
1.1.1.5 root 277: uint32_t psrpil; /* interrupt blocking level */
278: uint32_t pil_in; /* incoming interrupt level bitmap */
1.1 root 279: int psref; /* enable fpu */
1.1.1.5 root 280: target_ulong version;
1.1 root 281: int interrupt_index;
1.1.1.6 ! root 282: uint32_t nwindows;
1.1 root 283: /* NOTE: we allow 8 more registers to handle wrapping */
1.1.1.6 ! root 284: target_ulong regbase[MAX_NWINDOWS * 16 + 8];
1.1 root 285:
1.1.1.2 root 286: CPU_COMMON
287:
1.1 root 288: /* MMU regs */
289: #if defined(TARGET_SPARC64)
290: uint64_t lsu;
291: #define DMMU_E 0x8
292: #define IMMU_E 0x4
293: uint64_t immuregs[16];
294: uint64_t dmmuregs[16];
295: uint64_t itlb_tag[64];
296: uint64_t itlb_tte[64];
297: uint64_t dtlb_tag[64];
298: uint64_t dtlb_tte[64];
1.1.1.6 ! root 299: uint32_t mmu_version;
1.1 root 300: #else
1.1.1.5 root 301: uint32_t mmuregs[32];
302: uint64_t mxccdata[4];
303: uint64_t mxccregs[8];
1.1.1.6 ! root 304: uint64_t mmubpregs[4];
1.1.1.5 root 305: uint64_t prom_addr;
1.1 root 306: #endif
307: /* temporary float registers */
1.1.1.3 root 308: float64 dt0, dt1;
1.1.1.5 root 309: float128 qt0, qt1;
1.1 root 310: float_status fp_status;
311: #if defined(TARGET_SPARC64)
1.1.1.6 ! root 312: #define MAXTL_MAX 8
! 313: #define MAXTL_MASK (MAXTL_MAX - 1)
! 314: trap_state *tsptr;
! 315: trap_state ts[MAXTL_MAX];
1.1.1.5 root 316: uint32_t xcc; /* Extended integer condition codes */
1.1 root 317: uint32_t asi;
318: uint32_t pstate;
319: uint32_t tl;
1.1.1.6 ! root 320: uint32_t maxtl;
1.1 root 321: uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
322: uint64_t agregs[8]; /* alternate general registers */
323: uint64_t bgregs[8]; /* backup for normal global registers */
324: uint64_t igregs[8]; /* interrupt general registers */
325: uint64_t mgregs[8]; /* mmu general registers */
326: uint64_t fprs;
327: uint64_t tick_cmpr, stick_cmpr;
1.1.1.5 root 328: void *tick, *stick;
1.1.1.3 root 329: uint64_t gsr;
1.1.1.5 root 330: uint32_t gl; // UA2005
331: /* UA 2005 hyperprivileged registers */
1.1.1.6 ! root 332: uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
1.1.1.5 root 333: void *hstick; // UA 2005
1.1.1.6 ! root 334: uint32_t softint;
! 335: #define SOFTINT_TIMER 1
! 336: #define SOFTINT_STIMER (1 << 16)
1.1 root 337: #endif
1.1.1.6 ! root 338: sparc_def_t *def;
1.1 root 339: } CPUSPARCState;
340:
1.1.1.6 ! root 341: /* helper.c */
1.1.1.5 root 342: CPUSPARCState *cpu_sparc_init(const char *cpu_model);
1.1.1.6 ! root 343: void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
1.1.1.5 root 344: void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
345: ...));
1.1.1.6 ! root 346: void cpu_lock(void);
! 347: void cpu_unlock(void);
! 348: int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
! 349: int mmu_idx, int is_softmmu);
! 350: target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
! 351: void dump_mmu(CPUSPARCState *env);
! 352:
! 353: /* translate.c */
! 354: void gen_intermediate_code_init(CPUSPARCState *env);
! 355:
! 356: /* cpu-exec.c */
! 357: int cpu_sparc_exec(CPUSPARCState *s);
1.1.1.5 root 358:
359: #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \
360: (env->psref? PSR_EF : 0) | \
361: (env->psrpil << 8) | \
362: (env->psrs? PSR_S : 0) | \
363: (env->psrps? PSR_PS : 0) | \
364: (env->psret? PSR_ET : 0) | env->cwp)
1.1 root 365:
366: #ifndef NO_CPU_IO_DEFS
1.1.1.6 ! root 367: static inline void memcpy32(target_ulong *dst, const target_ulong *src)
! 368: {
! 369: dst[0] = src[0];
! 370: dst[1] = src[1];
! 371: dst[2] = src[2];
! 372: dst[3] = src[3];
! 373: dst[4] = src[4];
! 374: dst[5] = src[5];
! 375: dst[6] = src[6];
! 376: dst[7] = src[7];
! 377: }
! 378:
! 379: static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp)
! 380: {
! 381: /* put the modified wrap registers at their proper location */
! 382: if (env1->cwp == env1->nwindows - 1)
! 383: memcpy32(env1->regbase, env1->regbase + env1->nwindows * 16);
! 384: env1->cwp = new_cwp;
! 385: /* put the wrap registers at their temporary location */
! 386: if (new_cwp == env1->nwindows - 1)
! 387: memcpy32(env1->regbase + env1->nwindows * 16, env1->regbase);
! 388: env1->regwptr = env1->regbase + (new_cwp * 16);
! 389: }
! 390:
! 391: static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
! 392: {
! 393: if (unlikely(cwp >= env1->nwindows))
! 394: cwp -= env1->nwindows;
! 395: return cwp;
! 396: }
! 397:
! 398: static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
! 399: {
! 400: if (unlikely(cwp < 0))
! 401: cwp += env1->nwindows;
! 402: return cwp;
! 403: }
1.1 root 404: #endif
405:
1.1.1.5 root 406: #define PUT_PSR(env, val) do { int _tmp = val; \
407: env->psr = _tmp & PSR_ICC; \
408: env->psref = (_tmp & PSR_EF)? 1 : 0; \
409: env->psrpil = (_tmp & PSR_PIL) >> 8; \
410: env->psrs = (_tmp & PSR_S)? 1 : 0; \
411: env->psrps = (_tmp & PSR_PS)? 1 : 0; \
412: env->psret = (_tmp & PSR_ET)? 1 : 0; \
413: cpu_set_cwp(env, _tmp & PSR_CWP); \
1.1 root 414: } while (0)
415:
416: #ifdef TARGET_SPARC64
1.1.1.5 root 417: #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
418: #define PUT_CCR(env, val) do { int _tmp = val; \
1.1.1.6 ! root 419: env->xcc = (_tmp >> 4) << 20; \
1.1.1.5 root 420: env->psr = (_tmp & 0xf) << 20; \
1.1 root 421: } while (0)
1.1.1.6 ! root 422: #define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp)
1.1.1.5 root 423:
1.1.1.6 ! root 424: #ifndef NO_CPU_IO_DEFS
! 425: static inline void PUT_CWP64(CPUSPARCState *env1, int cwp)
! 426: {
! 427: if (unlikely(cwp >= env1->nwindows || cwp < 0))
! 428: cwp = 0;
! 429: cpu_set_cwp(env1, env1->nwindows - 1 - cwp);
! 430: }
! 431: #endif
1.1 root 432: #endif
433:
1.1.1.6 ! root 434: /* cpu-exec.c */
1.1.1.5 root 435: void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1.1.1.6 ! root 436: int is_asi, int size);
! 437: int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
1.1.1.5 root 438:
439: #define CPUState CPUSPARCState
440: #define cpu_init cpu_sparc_init
441: #define cpu_exec cpu_sparc_exec
442: #define cpu_gen_code cpu_sparc_gen_code
443: #define cpu_signal_handler cpu_sparc_signal_handler
444: #define cpu_list sparc_cpu_list
445:
1.1.1.6 ! root 446: #define CPU_SAVE_VERSION 5
! 447:
1.1.1.5 root 448: /* MMU modes definitions */
449: #define MMU_MODE0_SUFFIX _user
450: #define MMU_MODE1_SUFFIX _kernel
451: #ifdef TARGET_SPARC64
452: #define MMU_MODE2_SUFFIX _hypv
453: #endif
1.1.1.6 ! root 454: #define MMU_USER_IDX 0
! 455: #define MMU_KERNEL_IDX 1
! 456: #define MMU_HYPV_IDX 2
! 457:
! 458: static inline int cpu_mmu_index(CPUState *env1)
1.1.1.5 root 459: {
460: #if defined(CONFIG_USER_ONLY)
1.1.1.6 ! root 461: return MMU_USER_IDX;
1.1.1.5 root 462: #elif !defined(TARGET_SPARC64)
1.1.1.6 ! root 463: return env1->psrs;
1.1.1.5 root 464: #else
1.1.1.6 ! root 465: if (!env1->psrs)
! 466: return MMU_USER_IDX;
! 467: else if ((env1->hpstate & HS_PRIV) == 0)
! 468: return MMU_KERNEL_IDX;
1.1.1.5 root 469: else
1.1.1.6 ! root 470: return MMU_HYPV_IDX;
1.1.1.5 root 471: #endif
472: }
473:
1.1.1.6 ! root 474: static inline int cpu_fpu_enabled(CPUState *env1)
1.1.1.5 root 475: {
476: #if defined(CONFIG_USER_ONLY)
477: return 1;
478: #elif !defined(TARGET_SPARC64)
1.1.1.6 ! root 479: return env1->psref;
1.1.1.5 root 480: #else
1.1.1.6 ! root 481: return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0);
1.1.1.5 root 482: #endif
483: }
1.1 root 484:
1.1.1.6 ! root 485: #if defined(CONFIG_USER_ONLY)
! 486: static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
! 487: {
! 488: if (newsp)
! 489: env->regwptr[22] = newsp;
! 490: env->regwptr[0] = 0;
! 491: /* FIXME: Do we also need to clear CF? */
! 492: /* XXXXX */
! 493: printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
! 494: }
! 495: #endif
! 496:
1.1 root 497: #include "cpu-all.h"
1.1.1.6 ! root 498: #include "exec-all.h"
! 499:
! 500: /* sum4m.c, sun4u.c */
! 501: void cpu_check_irqs(CPUSPARCState *env);
! 502:
! 503: #ifdef TARGET_SPARC64
! 504: /* sun4u.c */
! 505: void cpu_tick_set_count(void *opaque, uint64_t count);
! 506: uint64_t cpu_tick_get_count(void *opaque);
! 507: void cpu_tick_set_limit(void *opaque, uint64_t limit);
! 508: #endif
! 509:
! 510: static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
! 511: {
! 512: env->pc = tb->pc;
! 513: env->npc = tb->cs_base;
! 514: }
! 515:
! 516: static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
! 517: target_ulong *cs_base, int *flags)
! 518: {
! 519: *pc = env->pc;
! 520: *cs_base = env->npc;
! 521: #ifdef TARGET_SPARC64
! 522: // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
! 523: *flags = ((env->pstate & PS_AM) << 2)
! 524: | (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
! 525: | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
! 526: #else
! 527: // FPU enable . Supervisor
! 528: *flags = (env->psref << 4) | env->psrs;
! 529: #endif
! 530: }
1.1 root 531:
532: #endif
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