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1.1 root 1: #ifndef CPU_SPARC_H
2: #define CPU_SPARC_H
3:
4: #include "config.h"
5:
6: #if !defined(TARGET_SPARC64)
7: #define TARGET_LONG_BITS 32
8: #define TARGET_FPREGS 32
9: #define TARGET_PAGE_BITS 12 /* 4k */
10: #else
11: #define TARGET_LONG_BITS 64
12: #define TARGET_FPREGS 64
1.1.1.5 root 13: #define TARGET_PAGE_BITS 13 /* 8k */
1.1 root 14: #endif
15:
1.1.1.7 ! root 16: #define CPUState struct CPUSPARCState
1.1.1.5 root 17:
1.1 root 18: #include "cpu-defs.h"
19:
20: #include "softfloat.h"
21:
22: #define TARGET_HAS_ICE 1
23:
1.1.1.4 root 24: #if !defined(TARGET_SPARC64)
1.1.1.5 root 25: #define ELF_MACHINE EM_SPARC
1.1.1.4 root 26: #else
1.1.1.5 root 27: #define ELF_MACHINE EM_SPARCV9
1.1.1.4 root 28: #endif
29:
1.1 root 30: /*#define EXCP_INTERRUPT 0x100*/
31:
32: /* trap definitions */
33: #ifndef TARGET_SPARC64
34: #define TT_TFAULT 0x01
35: #define TT_ILL_INSN 0x02
36: #define TT_PRIV_INSN 0x03
37: #define TT_NFPU_INSN 0x04
38: #define TT_WIN_OVF 0x05
1.1.1.5 root 39: #define TT_WIN_UNF 0x06
40: #define TT_UNALIGNED 0x07
1.1 root 41: #define TT_FP_EXCP 0x08
42: #define TT_DFAULT 0x09
1.1.1.5 root 43: #define TT_TOVF 0x0a
1.1 root 44: #define TT_EXTINT 0x10
1.1.1.5 root 45: #define TT_CODE_ACCESS 0x21
1.1.1.6 root 46: #define TT_UNIMP_FLUSH 0x25
1.1.1.5 root 47: #define TT_DATA_ACCESS 0x29
1.1 root 48: #define TT_DIV_ZERO 0x2a
1.1.1.5 root 49: #define TT_NCP_INSN 0x24
1.1 root 50: #define TT_TRAP 0x80
51: #else
52: #define TT_TFAULT 0x08
1.1.1.5 root 53: #define TT_CODE_ACCESS 0x0a
1.1 root 54: #define TT_ILL_INSN 0x10
1.1.1.6 root 55: #define TT_UNIMP_FLUSH TT_ILL_INSN
1.1 root 56: #define TT_PRIV_INSN 0x11
57: #define TT_NFPU_INSN 0x20
58: #define TT_FP_EXCP 0x21
1.1.1.5 root 59: #define TT_TOVF 0x23
1.1 root 60: #define TT_CLRWIN 0x24
61: #define TT_DIV_ZERO 0x28
62: #define TT_DFAULT 0x30
1.1.1.5 root 63: #define TT_DATA_ACCESS 0x32
64: #define TT_UNALIGNED 0x34
1.1 root 65: #define TT_PRIV_ACT 0x37
66: #define TT_EXTINT 0x40
1.1.1.6 root 67: #define TT_IVEC 0x60
68: #define TT_TMISS 0x64
69: #define TT_DMISS 0x68
70: #define TT_DPROT 0x6c
1.1 root 71: #define TT_SPILL 0x80
72: #define TT_FILL 0xc0
73: #define TT_WOTHER 0x10
74: #define TT_TRAP 0x100
75: #endif
76:
1.1.1.6 root 77: #define PSR_NEG_SHIFT 23
78: #define PSR_NEG (1 << PSR_NEG_SHIFT)
79: #define PSR_ZERO_SHIFT 22
80: #define PSR_ZERO (1 << PSR_ZERO_SHIFT)
81: #define PSR_OVF_SHIFT 21
82: #define PSR_OVF (1 << PSR_OVF_SHIFT)
83: #define PSR_CARRY_SHIFT 20
84: #define PSR_CARRY (1 << PSR_CARRY_SHIFT)
1.1 root 85: #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
86: #define PSR_EF (1<<12)
87: #define PSR_PIL 0xf00
88: #define PSR_S (1<<7)
89: #define PSR_PS (1<<6)
90: #define PSR_ET (1<<5)
91: #define PSR_CWP 0x1f
92:
1.1.1.7 ! root 93: #define CC_SRC (env->cc_src)
! 94: #define CC_SRC2 (env->cc_src2)
! 95: #define CC_DST (env->cc_dst)
! 96: #define CC_OP (env->cc_op)
! 97:
! 98: enum {
! 99: CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
! 100: CC_OP_FLAGS, /* all cc are back in status register */
! 101: CC_OP_DIV, /* modify N, Z and V, C = 0*/
! 102: CC_OP_ADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
! 103: CC_OP_ADDX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
! 104: CC_OP_TADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
! 105: CC_OP_TADDTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
! 106: CC_OP_SUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
! 107: CC_OP_SUBX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
! 108: CC_OP_TSUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
! 109: CC_OP_TSUBTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
! 110: CC_OP_LOGIC, /* modify N and Z, C = V = 0, CC_DST = res */
! 111: CC_OP_NB,
! 112: };
! 113:
1.1 root 114: /* Trap base register */
115: #define TBR_BASE_MASK 0xfffff000
116:
117: #if defined(TARGET_SPARC64)
1.1.1.7 ! root 118: #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */
! 119: #define PS_IG (1<<11) /* v9, zero on UA2007 */
! 120: #define PS_MG (1<<10) /* v9, zero on UA2007 */
! 121: #define PS_CLE (1<<9) /* UA2007 */
! 122: #define PS_TLE (1<<8) /* UA2007 */
1.1.1.5 root 123: #define PS_RMO (1<<7)
1.1.1.7 ! root 124: #define PS_RED (1<<5) /* v9, zero on UA2007 */
! 125: #define PS_PEF (1<<4) /* enable fpu */
! 126: #define PS_AM (1<<3) /* address mask */
1.1 root 127: #define PS_PRIV (1<<2)
128: #define PS_IE (1<<1)
1.1.1.7 ! root 129: #define PS_AG (1<<0) /* v9, zero on UA2007 */
1.1.1.3 root 130:
131: #define FPRS_FEF (1<<2)
1.1.1.5 root 132:
133: #define HS_PRIV (1<<2)
1.1 root 134: #endif
135:
136: /* Fcc */
1.1.1.6 root 137: #define FSR_RD1 (1ULL << 31)
138: #define FSR_RD0 (1ULL << 30)
1.1 root 139: #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
140: #define FSR_RD_NEAREST 0
141: #define FSR_RD_ZERO FSR_RD0
142: #define FSR_RD_POS FSR_RD1
143: #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
144:
1.1.1.6 root 145: #define FSR_NVM (1ULL << 27)
146: #define FSR_OFM (1ULL << 26)
147: #define FSR_UFM (1ULL << 25)
148: #define FSR_DZM (1ULL << 24)
149: #define FSR_NXM (1ULL << 23)
1.1 root 150: #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
151:
1.1.1.6 root 152: #define FSR_NVA (1ULL << 9)
153: #define FSR_OFA (1ULL << 8)
154: #define FSR_UFA (1ULL << 7)
155: #define FSR_DZA (1ULL << 6)
156: #define FSR_NXA (1ULL << 5)
1.1 root 157: #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
158:
1.1.1.6 root 159: #define FSR_NVC (1ULL << 4)
160: #define FSR_OFC (1ULL << 3)
161: #define FSR_UFC (1ULL << 2)
162: #define FSR_DZC (1ULL << 1)
163: #define FSR_NXC (1ULL << 0)
1.1 root 164: #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
165:
1.1.1.6 root 166: #define FSR_FTT2 (1ULL << 16)
167: #define FSR_FTT1 (1ULL << 15)
168: #define FSR_FTT0 (1ULL << 14)
169: //gcc warns about constant overflow for ~FSR_FTT_MASK
170: //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
171: #ifdef TARGET_SPARC64
172: #define FSR_FTT_NMASK 0xfffffffffffe3fffULL
173: #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
174: #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL
175: #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL
176: #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
177: #else
178: #define FSR_FTT_NMASK 0xfffe3fffULL
179: #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
180: #define FSR_LDFSR_OLDMASK 0x000fc000ULL
181: #endif
182: #define FSR_LDFSR_MASK 0xcfc00fffULL
183: #define FSR_FTT_IEEE_EXCP (1ULL << 14)
184: #define FSR_FTT_UNIMPFPOP (3ULL << 14)
185: #define FSR_FTT_SEQ_ERROR (4ULL << 14)
186: #define FSR_FTT_INVAL_FPR (6ULL << 14)
187:
188: #define FSR_FCC1_SHIFT 11
189: #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT)
190: #define FSR_FCC0_SHIFT 10
191: #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT)
1.1 root 192:
193: /* MMU */
1.1.1.5 root 194: #define MMU_E (1<<0)
195: #define MMU_NF (1<<1)
1.1 root 196:
197: #define PTE_ENTRYTYPE_MASK 3
198: #define PTE_ACCESS_MASK 0x1c
199: #define PTE_ACCESS_SHIFT 2
200: #define PTE_PPN_SHIFT 7
201: #define PTE_ADDR_MASK 0xffffff00
202:
1.1.1.5 root 203: #define PG_ACCESSED_BIT 5
204: #define PG_MODIFIED_BIT 6
1.1 root 205: #define PG_CACHE_BIT 7
206:
207: #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
208: #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
209: #define PG_CACHE_MASK (1 << PG_CACHE_BIT)
210:
1.1.1.6 root 211: /* 3 <= NWINDOWS <= 32. */
212: #define MIN_NWINDOWS 3
213: #define MAX_NWINDOWS 32
1.1 root 214:
1.1.1.5 root 215: #if !defined(TARGET_SPARC64)
216: #define NB_MMU_MODES 2
217: #else
218: #define NB_MMU_MODES 3
1.1.1.6 root 219: typedef struct trap_state {
220: uint64_t tpc;
221: uint64_t tnpc;
222: uint64_t tstate;
223: uint32_t tt;
224: } trap_state;
225: #endif
226:
227: typedef struct sparc_def_t {
228: const char *name;
229: target_ulong iu_version;
230: uint32_t fpu_version;
231: uint32_t mmu_version;
232: uint32_t mmu_bm;
233: uint32_t mmu_ctpr_mask;
234: uint32_t mmu_cxr_mask;
235: uint32_t mmu_sfsr_mask;
236: uint32_t mmu_trcr_mask;
237: uint32_t mxcc_version;
238: uint32_t features;
239: uint32_t nwindows;
240: uint32_t maxtl;
241: } sparc_def_t;
242:
243: #define CPU_FEATURE_FLOAT (1 << 0)
244: #define CPU_FEATURE_FLOAT128 (1 << 1)
245: #define CPU_FEATURE_SWAP (1 << 2)
246: #define CPU_FEATURE_MUL (1 << 3)
247: #define CPU_FEATURE_DIV (1 << 4)
248: #define CPU_FEATURE_FLUSH (1 << 5)
249: #define CPU_FEATURE_FSQRT (1 << 6)
250: #define CPU_FEATURE_FMUL (1 << 7)
251: #define CPU_FEATURE_VIS1 (1 << 8)
252: #define CPU_FEATURE_VIS2 (1 << 9)
253: #define CPU_FEATURE_FSMULD (1 << 10)
254: #define CPU_FEATURE_HYPV (1 << 11)
255: #define CPU_FEATURE_CMT (1 << 12)
256: #define CPU_FEATURE_GL (1 << 13)
257: #ifndef TARGET_SPARC64
258: #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
259: CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
260: CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
261: CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
262: #else
263: #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
264: CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
265: CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
266: CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \
267: CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD)
268: enum {
269: mmu_us_12, // Ultrasparc < III (64 entry TLB)
270: mmu_us_3, // Ultrasparc III (512 entry TLB)
271: mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages)
272: mmu_sun4v, // T1, T2
273: };
1.1.1.5 root 274: #endif
275:
1.1 root 276: typedef struct CPUSPARCState {
277: target_ulong gregs[8]; /* general registers */
278: target_ulong *regwptr; /* pointer to current register window */
279: target_ulong pc; /* program counter */
280: target_ulong npc; /* next program counter */
281: target_ulong y; /* multiply/divide register */
1.1.1.6 root 282:
283: /* emulator internal flags handling */
284: target_ulong cc_src, cc_src2;
285: target_ulong cc_dst;
1.1.1.7 ! root 286: uint32_t cc_op;
1.1.1.6 root 287:
288: target_ulong t0, t1; /* temporaries live across basic blocks */
289: target_ulong cond; /* conditional branch result (XXX: save it in a
290: temporary register when possible) */
291:
1.1 root 292: uint32_t psr; /* processor state register */
293: target_ulong fsr; /* FPU state register */
1.1.1.6 root 294: float32 fpr[TARGET_FPREGS]; /* floating point registers */
1.1 root 295: uint32_t cwp; /* index of current register window (extracted
296: from PSR) */
1.1.1.7 ! root 297: #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
1.1 root 298: uint32_t wim; /* window invalid mask */
1.1.1.7 ! root 299: #endif
1.1 root 300: target_ulong tbr; /* trap base register */
301: int psrs; /* supervisor mode (extracted from PSR) */
302: int psrps; /* previous supervisor mode */
1.1.1.7 ! root 303: #if !defined(TARGET_SPARC64)
1.1 root 304: int psret; /* enable traps */
1.1.1.7 ! root 305: #endif
1.1.1.5 root 306: uint32_t psrpil; /* interrupt blocking level */
307: uint32_t pil_in; /* incoming interrupt level bitmap */
1.1 root 308: int psref; /* enable fpu */
1.1.1.5 root 309: target_ulong version;
1.1 root 310: int interrupt_index;
1.1.1.6 root 311: uint32_t nwindows;
1.1 root 312: /* NOTE: we allow 8 more registers to handle wrapping */
1.1.1.6 root 313: target_ulong regbase[MAX_NWINDOWS * 16 + 8];
1.1 root 314:
1.1.1.2 root 315: CPU_COMMON
316:
1.1 root 317: /* MMU regs */
318: #if defined(TARGET_SPARC64)
319: uint64_t lsu;
320: #define DMMU_E 0x8
321: #define IMMU_E 0x4
322: uint64_t immuregs[16];
323: uint64_t dmmuregs[16];
324: uint64_t itlb_tag[64];
325: uint64_t itlb_tte[64];
326: uint64_t dtlb_tag[64];
327: uint64_t dtlb_tte[64];
1.1.1.6 root 328: uint32_t mmu_version;
1.1 root 329: #else
1.1.1.5 root 330: uint32_t mmuregs[32];
331: uint64_t mxccdata[4];
332: uint64_t mxccregs[8];
1.1.1.6 root 333: uint64_t mmubpregs[4];
1.1.1.5 root 334: uint64_t prom_addr;
1.1 root 335: #endif
336: /* temporary float registers */
1.1.1.3 root 337: float64 dt0, dt1;
1.1.1.5 root 338: float128 qt0, qt1;
1.1 root 339: float_status fp_status;
340: #if defined(TARGET_SPARC64)
1.1.1.6 root 341: #define MAXTL_MAX 8
342: #define MAXTL_MASK (MAXTL_MAX - 1)
343: trap_state *tsptr;
344: trap_state ts[MAXTL_MAX];
1.1.1.5 root 345: uint32_t xcc; /* Extended integer condition codes */
1.1 root 346: uint32_t asi;
347: uint32_t pstate;
348: uint32_t tl;
1.1.1.6 root 349: uint32_t maxtl;
1.1 root 350: uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
351: uint64_t agregs[8]; /* alternate general registers */
352: uint64_t bgregs[8]; /* backup for normal global registers */
353: uint64_t igregs[8]; /* interrupt general registers */
354: uint64_t mgregs[8]; /* mmu general registers */
355: uint64_t fprs;
356: uint64_t tick_cmpr, stick_cmpr;
1.1.1.5 root 357: void *tick, *stick;
1.1.1.3 root 358: uint64_t gsr;
1.1.1.5 root 359: uint32_t gl; // UA2005
360: /* UA 2005 hyperprivileged registers */
1.1.1.6 root 361: uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
1.1.1.5 root 362: void *hstick; // UA 2005
1.1.1.6 root 363: uint32_t softint;
364: #define SOFTINT_TIMER 1
365: #define SOFTINT_STIMER (1 << 16)
1.1 root 366: #endif
1.1.1.6 root 367: sparc_def_t *def;
1.1 root 368: } CPUSPARCState;
369:
1.1.1.6 root 370: /* helper.c */
1.1.1.5 root 371: CPUSPARCState *cpu_sparc_init(const char *cpu_model);
1.1.1.6 root 372: void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
1.1.1.5 root 373: void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
374: ...));
1.1.1.6 root 375: void cpu_lock(void);
376: void cpu_unlock(void);
377: int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
378: int mmu_idx, int is_softmmu);
379: target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
380: void dump_mmu(CPUSPARCState *env);
381:
382: /* translate.c */
383: void gen_intermediate_code_init(CPUSPARCState *env);
384:
385: /* cpu-exec.c */
386: int cpu_sparc_exec(CPUSPARCState *s);
1.1.1.5 root 387:
1.1.1.7 ! root 388: #if !defined (TARGET_SPARC64)
1.1.1.5 root 389: #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \
390: (env->psref? PSR_EF : 0) | \
391: (env->psrpil << 8) | \
392: (env->psrs? PSR_S : 0) | \
393: (env->psrps? PSR_PS : 0) | \
394: (env->psret? PSR_ET : 0) | env->cwp)
1.1.1.7 ! root 395: #else
! 396: #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \
! 397: (env->psref? PSR_EF : 0) | \
! 398: (env->psrpil << 8) | \
! 399: (env->psrs? PSR_S : 0) | \
! 400: (env->psrps? PSR_PS : 0) | \
! 401: env->cwp)
! 402: #endif
1.1 root 403:
404: #ifndef NO_CPU_IO_DEFS
1.1.1.6 root 405: static inline void memcpy32(target_ulong *dst, const target_ulong *src)
406: {
407: dst[0] = src[0];
408: dst[1] = src[1];
409: dst[2] = src[2];
410: dst[3] = src[3];
411: dst[4] = src[4];
412: dst[5] = src[5];
413: dst[6] = src[6];
414: dst[7] = src[7];
415: }
416:
417: static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp)
418: {
419: /* put the modified wrap registers at their proper location */
420: if (env1->cwp == env1->nwindows - 1)
421: memcpy32(env1->regbase, env1->regbase + env1->nwindows * 16);
422: env1->cwp = new_cwp;
423: /* put the wrap registers at their temporary location */
424: if (new_cwp == env1->nwindows - 1)
425: memcpy32(env1->regbase + env1->nwindows * 16, env1->regbase);
426: env1->regwptr = env1->regbase + (new_cwp * 16);
427: }
428:
429: static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
430: {
431: if (unlikely(cwp >= env1->nwindows))
432: cwp -= env1->nwindows;
433: return cwp;
434: }
435:
436: static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
437: {
438: if (unlikely(cwp < 0))
439: cwp += env1->nwindows;
440: return cwp;
441: }
1.1 root 442: #endif
443:
1.1.1.7 ! root 444: #if !defined (TARGET_SPARC64)
1.1.1.5 root 445: #define PUT_PSR(env, val) do { int _tmp = val; \
446: env->psr = _tmp & PSR_ICC; \
447: env->psref = (_tmp & PSR_EF)? 1 : 0; \
448: env->psrpil = (_tmp & PSR_PIL) >> 8; \
449: env->psrs = (_tmp & PSR_S)? 1 : 0; \
450: env->psrps = (_tmp & PSR_PS)? 1 : 0; \
451: env->psret = (_tmp & PSR_ET)? 1 : 0; \
452: cpu_set_cwp(env, _tmp & PSR_CWP); \
1.1.1.7 ! root 453: CC_OP = CC_OP_FLAGS; \
! 454: } while (0)
! 455: #else
! 456: #define PUT_PSR(env, val) do { int _tmp = val; \
! 457: env->psr = _tmp & PSR_ICC; \
! 458: env->psref = (_tmp & PSR_EF)? 1 : 0; \
! 459: env->psrpil = (_tmp & PSR_PIL) >> 8; \
! 460: env->psrs = (_tmp & PSR_S)? 1 : 0; \
! 461: env->psrps = (_tmp & PSR_PS)? 1 : 0; \
! 462: cpu_set_cwp(env, _tmp & PSR_CWP); \
! 463: CC_OP = CC_OP_FLAGS; \
1.1 root 464: } while (0)
1.1.1.7 ! root 465: #endif
1.1 root 466:
467: #ifdef TARGET_SPARC64
1.1.1.5 root 468: #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
469: #define PUT_CCR(env, val) do { int _tmp = val; \
1.1.1.6 root 470: env->xcc = (_tmp >> 4) << 20; \
1.1.1.5 root 471: env->psr = (_tmp & 0xf) << 20; \
1.1.1.7 ! root 472: CC_OP = CC_OP_FLAGS; \
1.1 root 473: } while (0)
1.1.1.6 root 474: #define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp)
1.1.1.5 root 475:
1.1.1.6 root 476: #ifndef NO_CPU_IO_DEFS
477: static inline void PUT_CWP64(CPUSPARCState *env1, int cwp)
478: {
479: if (unlikely(cwp >= env1->nwindows || cwp < 0))
480: cwp = 0;
481: cpu_set_cwp(env1, env1->nwindows - 1 - cwp);
482: }
483: #endif
1.1 root 484: #endif
485:
1.1.1.6 root 486: /* cpu-exec.c */
1.1.1.5 root 487: void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1.1.1.6 root 488: int is_asi, int size);
489: int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
1.1.1.5 root 490:
491: #define cpu_init cpu_sparc_init
492: #define cpu_exec cpu_sparc_exec
493: #define cpu_gen_code cpu_sparc_gen_code
494: #define cpu_signal_handler cpu_sparc_signal_handler
495: #define cpu_list sparc_cpu_list
496:
1.1.1.6 root 497: #define CPU_SAVE_VERSION 5
498:
1.1.1.5 root 499: /* MMU modes definitions */
500: #define MMU_MODE0_SUFFIX _user
501: #define MMU_MODE1_SUFFIX _kernel
502: #ifdef TARGET_SPARC64
503: #define MMU_MODE2_SUFFIX _hypv
504: #endif
1.1.1.6 root 505: #define MMU_USER_IDX 0
506: #define MMU_KERNEL_IDX 1
507: #define MMU_HYPV_IDX 2
508:
509: static inline int cpu_mmu_index(CPUState *env1)
1.1.1.5 root 510: {
511: #if defined(CONFIG_USER_ONLY)
1.1.1.6 root 512: return MMU_USER_IDX;
1.1.1.5 root 513: #elif !defined(TARGET_SPARC64)
1.1.1.6 root 514: return env1->psrs;
1.1.1.5 root 515: #else
1.1.1.6 root 516: if (!env1->psrs)
517: return MMU_USER_IDX;
518: else if ((env1->hpstate & HS_PRIV) == 0)
519: return MMU_KERNEL_IDX;
1.1.1.5 root 520: else
1.1.1.6 root 521: return MMU_HYPV_IDX;
1.1.1.5 root 522: #endif
523: }
524:
1.1.1.6 root 525: static inline int cpu_fpu_enabled(CPUState *env1)
1.1.1.5 root 526: {
527: #if defined(CONFIG_USER_ONLY)
528: return 1;
529: #elif !defined(TARGET_SPARC64)
1.1.1.6 root 530: return env1->psref;
1.1.1.5 root 531: #else
1.1.1.6 root 532: return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0);
1.1.1.5 root 533: #endif
534: }
1.1 root 535:
1.1.1.6 root 536: #if defined(CONFIG_USER_ONLY)
537: static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
538: {
539: if (newsp)
540: env->regwptr[22] = newsp;
541: env->regwptr[0] = 0;
542: /* FIXME: Do we also need to clear CF? */
543: /* XXXXX */
544: printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
545: }
546: #endif
547:
1.1 root 548: #include "cpu-all.h"
1.1.1.6 root 549: #include "exec-all.h"
550:
551: /* sum4m.c, sun4u.c */
552: void cpu_check_irqs(CPUSPARCState *env);
553:
554: #ifdef TARGET_SPARC64
555: /* sun4u.c */
556: void cpu_tick_set_count(void *opaque, uint64_t count);
557: uint64_t cpu_tick_get_count(void *opaque);
558: void cpu_tick_set_limit(void *opaque, uint64_t limit);
559: #endif
560:
561: static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
562: {
563: env->pc = tb->pc;
564: env->npc = tb->cs_base;
565: }
566:
567: static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
568: target_ulong *cs_base, int *flags)
569: {
570: *pc = env->pc;
571: *cs_base = env->npc;
572: #ifdef TARGET_SPARC64
573: // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
574: *flags = ((env->pstate & PS_AM) << 2)
575: | (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
576: | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
577: #else
578: // FPU enable . Supervisor
579: *flags = (env->psref << 4) | env->psrs;
580: #endif
581: }
1.1 root 582:
583: #endif
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