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1.1 root 1: #ifndef CPU_SPARC_H
2: #define CPU_SPARC_H
3:
4: #include "config.h"
5:
6: #if !defined(TARGET_SPARC64)
7: #define TARGET_LONG_BITS 32
8: #define TARGET_FPREGS 32
9: #define TARGET_PAGE_BITS 12 /* 4k */
1.1.1.9 ! root 10: #define TARGET_PHYS_ADDR_SPACE_BITS 36
! 11: #define TARGET_VIRT_ADDR_SPACE_BITS 32
1.1 root 12: #else
13: #define TARGET_LONG_BITS 64
14: #define TARGET_FPREGS 64
1.1.1.5 root 15: #define TARGET_PAGE_BITS 13 /* 8k */
1.1.1.9 ! root 16: #define TARGET_PHYS_ADDR_SPACE_BITS 41
! 17: # ifdef TARGET_ABI32
! 18: # define TARGET_VIRT_ADDR_SPACE_BITS 32
! 19: # else
! 20: # define TARGET_VIRT_ADDR_SPACE_BITS 44
! 21: # endif
1.1 root 22: #endif
23:
1.1.1.7 root 24: #define CPUState struct CPUSPARCState
1.1.1.5 root 25:
1.1 root 26: #include "cpu-defs.h"
27:
28: #include "softfloat.h"
29:
30: #define TARGET_HAS_ICE 1
31:
1.1.1.4 root 32: #if !defined(TARGET_SPARC64)
1.1.1.5 root 33: #define ELF_MACHINE EM_SPARC
1.1.1.4 root 34: #else
1.1.1.5 root 35: #define ELF_MACHINE EM_SPARCV9
1.1.1.4 root 36: #endif
37:
1.1 root 38: /*#define EXCP_INTERRUPT 0x100*/
39:
40: /* trap definitions */
41: #ifndef TARGET_SPARC64
42: #define TT_TFAULT 0x01
43: #define TT_ILL_INSN 0x02
44: #define TT_PRIV_INSN 0x03
45: #define TT_NFPU_INSN 0x04
46: #define TT_WIN_OVF 0x05
1.1.1.5 root 47: #define TT_WIN_UNF 0x06
48: #define TT_UNALIGNED 0x07
1.1 root 49: #define TT_FP_EXCP 0x08
50: #define TT_DFAULT 0x09
1.1.1.5 root 51: #define TT_TOVF 0x0a
1.1 root 52: #define TT_EXTINT 0x10
1.1.1.5 root 53: #define TT_CODE_ACCESS 0x21
1.1.1.6 root 54: #define TT_UNIMP_FLUSH 0x25
1.1.1.5 root 55: #define TT_DATA_ACCESS 0x29
1.1 root 56: #define TT_DIV_ZERO 0x2a
1.1.1.5 root 57: #define TT_NCP_INSN 0x24
1.1 root 58: #define TT_TRAP 0x80
59: #else
1.1.1.8 root 60: #define TT_POWER_ON_RESET 0x01
1.1 root 61: #define TT_TFAULT 0x08
1.1.1.5 root 62: #define TT_CODE_ACCESS 0x0a
1.1 root 63: #define TT_ILL_INSN 0x10
1.1.1.6 root 64: #define TT_UNIMP_FLUSH TT_ILL_INSN
1.1 root 65: #define TT_PRIV_INSN 0x11
66: #define TT_NFPU_INSN 0x20
67: #define TT_FP_EXCP 0x21
1.1.1.5 root 68: #define TT_TOVF 0x23
1.1 root 69: #define TT_CLRWIN 0x24
70: #define TT_DIV_ZERO 0x28
71: #define TT_DFAULT 0x30
1.1.1.5 root 72: #define TT_DATA_ACCESS 0x32
73: #define TT_UNALIGNED 0x34
1.1 root 74: #define TT_PRIV_ACT 0x37
75: #define TT_EXTINT 0x40
1.1.1.6 root 76: #define TT_IVEC 0x60
77: #define TT_TMISS 0x64
78: #define TT_DMISS 0x68
79: #define TT_DPROT 0x6c
1.1 root 80: #define TT_SPILL 0x80
81: #define TT_FILL 0xc0
1.1.1.9 ! root 82: #define TT_WOTHER (1 << 5)
1.1 root 83: #define TT_TRAP 0x100
84: #endif
85:
1.1.1.6 root 86: #define PSR_NEG_SHIFT 23
87: #define PSR_NEG (1 << PSR_NEG_SHIFT)
88: #define PSR_ZERO_SHIFT 22
89: #define PSR_ZERO (1 << PSR_ZERO_SHIFT)
90: #define PSR_OVF_SHIFT 21
91: #define PSR_OVF (1 << PSR_OVF_SHIFT)
92: #define PSR_CARRY_SHIFT 20
93: #define PSR_CARRY (1 << PSR_CARRY_SHIFT)
1.1 root 94: #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
1.1.1.9 ! root 95: #if !defined(TARGET_SPARC64)
1.1 root 96: #define PSR_EF (1<<12)
97: #define PSR_PIL 0xf00
98: #define PSR_S (1<<7)
99: #define PSR_PS (1<<6)
100: #define PSR_ET (1<<5)
101: #define PSR_CWP 0x1f
1.1.1.9 ! root 102: #endif
1.1 root 103:
1.1.1.7 root 104: #define CC_SRC (env->cc_src)
105: #define CC_SRC2 (env->cc_src2)
106: #define CC_DST (env->cc_dst)
107: #define CC_OP (env->cc_op)
108:
109: enum {
110: CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
111: CC_OP_FLAGS, /* all cc are back in status register */
112: CC_OP_DIV, /* modify N, Z and V, C = 0*/
113: CC_OP_ADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
114: CC_OP_ADDX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
115: CC_OP_TADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
116: CC_OP_TADDTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
117: CC_OP_SUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
118: CC_OP_SUBX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
119: CC_OP_TSUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
120: CC_OP_TSUBTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
121: CC_OP_LOGIC, /* modify N and Z, C = V = 0, CC_DST = res */
122: CC_OP_NB,
123: };
124:
1.1 root 125: /* Trap base register */
126: #define TBR_BASE_MASK 0xfffff000
127:
128: #if defined(TARGET_SPARC64)
1.1.1.7 root 129: #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */
130: #define PS_IG (1<<11) /* v9, zero on UA2007 */
131: #define PS_MG (1<<10) /* v9, zero on UA2007 */
132: #define PS_CLE (1<<9) /* UA2007 */
133: #define PS_TLE (1<<8) /* UA2007 */
1.1.1.5 root 134: #define PS_RMO (1<<7)
1.1.1.7 root 135: #define PS_RED (1<<5) /* v9, zero on UA2007 */
136: #define PS_PEF (1<<4) /* enable fpu */
137: #define PS_AM (1<<3) /* address mask */
1.1 root 138: #define PS_PRIV (1<<2)
139: #define PS_IE (1<<1)
1.1.1.7 root 140: #define PS_AG (1<<0) /* v9, zero on UA2007 */
1.1.1.3 root 141:
142: #define FPRS_FEF (1<<2)
1.1.1.5 root 143:
144: #define HS_PRIV (1<<2)
1.1 root 145: #endif
146:
147: /* Fcc */
1.1.1.6 root 148: #define FSR_RD1 (1ULL << 31)
149: #define FSR_RD0 (1ULL << 30)
1.1 root 150: #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
151: #define FSR_RD_NEAREST 0
152: #define FSR_RD_ZERO FSR_RD0
153: #define FSR_RD_POS FSR_RD1
154: #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
155:
1.1.1.6 root 156: #define FSR_NVM (1ULL << 27)
157: #define FSR_OFM (1ULL << 26)
158: #define FSR_UFM (1ULL << 25)
159: #define FSR_DZM (1ULL << 24)
160: #define FSR_NXM (1ULL << 23)
1.1 root 161: #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
162:
1.1.1.6 root 163: #define FSR_NVA (1ULL << 9)
164: #define FSR_OFA (1ULL << 8)
165: #define FSR_UFA (1ULL << 7)
166: #define FSR_DZA (1ULL << 6)
167: #define FSR_NXA (1ULL << 5)
1.1 root 168: #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
169:
1.1.1.6 root 170: #define FSR_NVC (1ULL << 4)
171: #define FSR_OFC (1ULL << 3)
172: #define FSR_UFC (1ULL << 2)
173: #define FSR_DZC (1ULL << 1)
174: #define FSR_NXC (1ULL << 0)
1.1 root 175: #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
176:
1.1.1.6 root 177: #define FSR_FTT2 (1ULL << 16)
178: #define FSR_FTT1 (1ULL << 15)
179: #define FSR_FTT0 (1ULL << 14)
180: //gcc warns about constant overflow for ~FSR_FTT_MASK
181: //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
182: #ifdef TARGET_SPARC64
183: #define FSR_FTT_NMASK 0xfffffffffffe3fffULL
184: #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
185: #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL
186: #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL
187: #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
188: #else
189: #define FSR_FTT_NMASK 0xfffe3fffULL
190: #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
191: #define FSR_LDFSR_OLDMASK 0x000fc000ULL
192: #endif
193: #define FSR_LDFSR_MASK 0xcfc00fffULL
194: #define FSR_FTT_IEEE_EXCP (1ULL << 14)
195: #define FSR_FTT_UNIMPFPOP (3ULL << 14)
196: #define FSR_FTT_SEQ_ERROR (4ULL << 14)
197: #define FSR_FTT_INVAL_FPR (6ULL << 14)
198:
199: #define FSR_FCC1_SHIFT 11
200: #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT)
201: #define FSR_FCC0_SHIFT 10
202: #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT)
1.1 root 203:
204: /* MMU */
1.1.1.5 root 205: #define MMU_E (1<<0)
206: #define MMU_NF (1<<1)
1.1 root 207:
208: #define PTE_ENTRYTYPE_MASK 3
209: #define PTE_ACCESS_MASK 0x1c
210: #define PTE_ACCESS_SHIFT 2
211: #define PTE_PPN_SHIFT 7
212: #define PTE_ADDR_MASK 0xffffff00
213:
1.1.1.5 root 214: #define PG_ACCESSED_BIT 5
215: #define PG_MODIFIED_BIT 6
1.1 root 216: #define PG_CACHE_BIT 7
217:
218: #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
219: #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
220: #define PG_CACHE_MASK (1 << PG_CACHE_BIT)
221:
1.1.1.6 root 222: /* 3 <= NWINDOWS <= 32. */
223: #define MIN_NWINDOWS 3
224: #define MAX_NWINDOWS 32
1.1 root 225:
1.1.1.5 root 226: #if !defined(TARGET_SPARC64)
227: #define NB_MMU_MODES 2
228: #else
1.1.1.9 ! root 229: #define NB_MMU_MODES 6
1.1.1.6 root 230: typedef struct trap_state {
231: uint64_t tpc;
232: uint64_t tnpc;
233: uint64_t tstate;
234: uint32_t tt;
235: } trap_state;
236: #endif
237:
238: typedef struct sparc_def_t {
239: const char *name;
240: target_ulong iu_version;
241: uint32_t fpu_version;
242: uint32_t mmu_version;
243: uint32_t mmu_bm;
244: uint32_t mmu_ctpr_mask;
245: uint32_t mmu_cxr_mask;
246: uint32_t mmu_sfsr_mask;
247: uint32_t mmu_trcr_mask;
248: uint32_t mxcc_version;
249: uint32_t features;
250: uint32_t nwindows;
251: uint32_t maxtl;
252: } sparc_def_t;
253:
254: #define CPU_FEATURE_FLOAT (1 << 0)
255: #define CPU_FEATURE_FLOAT128 (1 << 1)
256: #define CPU_FEATURE_SWAP (1 << 2)
257: #define CPU_FEATURE_MUL (1 << 3)
258: #define CPU_FEATURE_DIV (1 << 4)
259: #define CPU_FEATURE_FLUSH (1 << 5)
260: #define CPU_FEATURE_FSQRT (1 << 6)
261: #define CPU_FEATURE_FMUL (1 << 7)
262: #define CPU_FEATURE_VIS1 (1 << 8)
263: #define CPU_FEATURE_VIS2 (1 << 9)
264: #define CPU_FEATURE_FSMULD (1 << 10)
265: #define CPU_FEATURE_HYPV (1 << 11)
266: #define CPU_FEATURE_CMT (1 << 12)
267: #define CPU_FEATURE_GL (1 << 13)
268: #ifndef TARGET_SPARC64
269: #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
270: CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
271: CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
272: CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
273: #else
274: #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
275: CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
276: CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
277: CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \
278: CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD)
279: enum {
280: mmu_us_12, // Ultrasparc < III (64 entry TLB)
281: mmu_us_3, // Ultrasparc III (512 entry TLB)
282: mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages)
283: mmu_sun4v, // T1, T2
284: };
1.1.1.5 root 285: #endif
286:
1.1.1.8 root 287: #define TTE_VALID_BIT (1ULL << 63)
288: #define TTE_USED_BIT (1ULL << 41)
289: #define TTE_LOCKED_BIT (1ULL << 6)
290: #define TTE_GLOBAL_BIT (1ULL << 0)
291:
292: #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT)
293: #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT)
294: #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT)
295: #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT)
296:
297: #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT)
298: #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
299:
300: typedef struct SparcTLBEntry {
301: uint64_t tag;
302: uint64_t tte;
303: } SparcTLBEntry;
304:
1.1.1.9 ! root 305: struct CPUTimer
! 306: {
! 307: const char *name;
! 308: uint32_t frequency;
! 309: uint32_t disabled;
! 310: uint64_t disabled_mask;
! 311: int64_t clock_offset;
! 312: struct QEMUTimer *qtimer;
! 313: };
! 314:
! 315: typedef struct CPUTimer CPUTimer;
! 316:
! 317: struct QEMUFile;
! 318: void cpu_put_timer(struct QEMUFile *f, CPUTimer *s);
! 319: void cpu_get_timer(struct QEMUFile *f, CPUTimer *s);
! 320:
1.1 root 321: typedef struct CPUSPARCState {
322: target_ulong gregs[8]; /* general registers */
323: target_ulong *regwptr; /* pointer to current register window */
324: target_ulong pc; /* program counter */
325: target_ulong npc; /* next program counter */
326: target_ulong y; /* multiply/divide register */
1.1.1.6 root 327:
328: /* emulator internal flags handling */
329: target_ulong cc_src, cc_src2;
330: target_ulong cc_dst;
1.1.1.7 root 331: uint32_t cc_op;
1.1.1.6 root 332:
333: target_ulong t0, t1; /* temporaries live across basic blocks */
334: target_ulong cond; /* conditional branch result (XXX: save it in a
335: temporary register when possible) */
336:
1.1 root 337: uint32_t psr; /* processor state register */
338: target_ulong fsr; /* FPU state register */
1.1.1.6 root 339: float32 fpr[TARGET_FPREGS]; /* floating point registers */
1.1 root 340: uint32_t cwp; /* index of current register window (extracted
341: from PSR) */
1.1.1.7 root 342: #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
1.1 root 343: uint32_t wim; /* window invalid mask */
1.1.1.7 root 344: #endif
1.1 root 345: target_ulong tbr; /* trap base register */
1.1.1.9 ! root 346: #if !defined(TARGET_SPARC64)
1.1 root 347: int psrs; /* supervisor mode (extracted from PSR) */
348: int psrps; /* previous supervisor mode */
349: int psret; /* enable traps */
1.1.1.7 root 350: #endif
1.1.1.5 root 351: uint32_t psrpil; /* interrupt blocking level */
352: uint32_t pil_in; /* incoming interrupt level bitmap */
1.1.1.9 ! root 353: #if !defined(TARGET_SPARC64)
1.1 root 354: int psref; /* enable fpu */
1.1.1.9 ! root 355: #endif
1.1.1.5 root 356: target_ulong version;
1.1 root 357: int interrupt_index;
1.1.1.6 root 358: uint32_t nwindows;
1.1 root 359: /* NOTE: we allow 8 more registers to handle wrapping */
1.1.1.6 root 360: target_ulong regbase[MAX_NWINDOWS * 16 + 8];
1.1 root 361:
1.1.1.2 root 362: CPU_COMMON
363:
1.1 root 364: /* MMU regs */
365: #if defined(TARGET_SPARC64)
366: uint64_t lsu;
367: #define DMMU_E 0x8
368: #define IMMU_E 0x4
1.1.1.8 root 369: //typedef struct SparcMMU
370: union {
371: uint64_t immuregs[16];
372: struct {
373: uint64_t tsb_tag_target;
374: uint64_t unused_mmu_primary_context; // use DMMU
375: uint64_t unused_mmu_secondary_context; // use DMMU
376: uint64_t sfsr;
377: uint64_t sfar;
378: uint64_t tsb;
379: uint64_t tag_access;
380: } immu;
381: };
382: union {
383: uint64_t dmmuregs[16];
384: struct {
385: uint64_t tsb_tag_target;
386: uint64_t mmu_primary_context;
387: uint64_t mmu_secondary_context;
388: uint64_t sfsr;
389: uint64_t sfar;
390: uint64_t tsb;
391: uint64_t tag_access;
392: } dmmu;
393: };
394: SparcTLBEntry itlb[64];
395: SparcTLBEntry dtlb[64];
1.1.1.6 root 396: uint32_t mmu_version;
1.1 root 397: #else
1.1.1.5 root 398: uint32_t mmuregs[32];
399: uint64_t mxccdata[4];
400: uint64_t mxccregs[8];
1.1.1.6 root 401: uint64_t mmubpregs[4];
1.1.1.5 root 402: uint64_t prom_addr;
1.1 root 403: #endif
404: /* temporary float registers */
1.1.1.3 root 405: float64 dt0, dt1;
1.1.1.5 root 406: float128 qt0, qt1;
1.1 root 407: float_status fp_status;
408: #if defined(TARGET_SPARC64)
1.1.1.6 root 409: #define MAXTL_MAX 8
410: #define MAXTL_MASK (MAXTL_MAX - 1)
411: trap_state ts[MAXTL_MAX];
1.1.1.5 root 412: uint32_t xcc; /* Extended integer condition codes */
1.1 root 413: uint32_t asi;
414: uint32_t pstate;
415: uint32_t tl;
1.1.1.6 root 416: uint32_t maxtl;
1.1 root 417: uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
418: uint64_t agregs[8]; /* alternate general registers */
419: uint64_t bgregs[8]; /* backup for normal global registers */
420: uint64_t igregs[8]; /* interrupt general registers */
421: uint64_t mgregs[8]; /* mmu general registers */
422: uint64_t fprs;
423: uint64_t tick_cmpr, stick_cmpr;
1.1.1.9 ! root 424: CPUTimer *tick, *stick;
! 425: #define TICK_NPT_MASK 0x8000000000000000ULL
! 426: #define TICK_INT_DIS 0x8000000000000000ULL
1.1.1.3 root 427: uint64_t gsr;
1.1.1.5 root 428: uint32_t gl; // UA2005
429: /* UA 2005 hyperprivileged registers */
1.1.1.6 root 430: uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
1.1.1.9 ! root 431: CPUTimer *hstick; // UA 2005
1.1.1.6 root 432: uint32_t softint;
433: #define SOFTINT_TIMER 1
434: #define SOFTINT_STIMER (1 << 16)
1.1.1.9 ! root 435: #define SOFTINT_INTRMASK (0xFFFE)
! 436: #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
1.1 root 437: #endif
1.1.1.6 root 438: sparc_def_t *def;
1.1 root 439: } CPUSPARCState;
440:
1.1.1.9 ! root 441: #ifndef NO_CPU_IO_DEFS
1.1.1.6 root 442: /* helper.c */
1.1.1.5 root 443: CPUSPARCState *cpu_sparc_init(const char *cpu_model);
1.1.1.6 root 444: void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
1.1.1.5 root 445: void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
446: ...));
1.1.1.6 root 447: void cpu_lock(void);
448: void cpu_unlock(void);
449: int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
450: int mmu_idx, int is_softmmu);
1.1.1.8 root 451: #define cpu_handle_mmu_fault cpu_sparc_handle_mmu_fault
1.1.1.6 root 452: target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
453: void dump_mmu(CPUSPARCState *env);
454:
455: /* translate.c */
456: void gen_intermediate_code_init(CPUSPARCState *env);
457:
458: /* cpu-exec.c */
459: int cpu_sparc_exec(CPUSPARCState *s);
1.1.1.5 root 460:
1.1.1.9 ! root 461: /* op_helper.c */
! 462: target_ulong cpu_get_psr(CPUState *env1);
! 463: void cpu_put_psr(CPUState *env1, target_ulong val);
! 464: #ifdef TARGET_SPARC64
! 465: target_ulong cpu_get_ccr(CPUState *env1);
! 466: void cpu_put_ccr(CPUState *env1, target_ulong val);
! 467: target_ulong cpu_get_cwp64(CPUState *env1);
! 468: void cpu_put_cwp64(CPUState *env1, int cwp);
! 469: #endif
! 470: int cpu_cwp_inc(CPUState *env1, int cwp);
! 471: int cpu_cwp_dec(CPUState *env1, int cwp);
! 472: void cpu_set_cwp(CPUState *env1, int new_cwp);
1.1.1.6 root 473:
1.1.1.8 root 474: /* sun4m.c, sun4u.c */
475: void cpu_check_irqs(CPUSPARCState *env);
1.1.1.6 root 476:
1.1.1.9 ! root 477: #if defined (TARGET_SPARC64)
! 478:
! 479: static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
1.1.1.6 root 480: {
1.1.1.9 ! root 481: return (x & mask) == (y & mask);
1.1.1.8 root 482: }
1.1 root 483:
1.1.1.9 ! root 484: #define MMU_CONTEXT_BITS 13
! 485: #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1)
1.1.1.5 root 486:
1.1.1.9 ! root 487: static inline int tlb_compare_context(const SparcTLBEntry *tlb,
! 488: uint64_t context)
1.1.1.6 root 489: {
1.1.1.9 ! root 490: return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK);
1.1.1.6 root 491: }
1.1.1.9 ! root 492:
1.1.1.6 root 493: #endif
1.1 root 494: #endif
495:
1.1.1.6 root 496: /* cpu-exec.c */
1.1.1.9 ! root 497: #if !defined(CONFIG_USER_ONLY)
1.1.1.5 root 498: void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1.1.1.6 root 499: int is_asi, int size);
1.1.1.9 ! root 500: target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
! 501: int mmu_idx);
! 502:
! 503: #endif
1.1.1.6 root 504: int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
1.1.1.5 root 505:
506: #define cpu_init cpu_sparc_init
507: #define cpu_exec cpu_sparc_exec
508: #define cpu_gen_code cpu_sparc_gen_code
509: #define cpu_signal_handler cpu_sparc_signal_handler
510: #define cpu_list sparc_cpu_list
511:
1.1.1.9 ! root 512: #define CPU_SAVE_VERSION 6
1.1.1.6 root 513:
1.1.1.5 root 514: /* MMU modes definitions */
1.1.1.9 ! root 515: #if defined (TARGET_SPARC64)
! 516: #define MMU_USER_IDX 0
1.1.1.5 root 517: #define MMU_MODE0_SUFFIX _user
1.1.1.9 ! root 518: #define MMU_USER_SECONDARY_IDX 1
! 519: #define MMU_MODE1_SUFFIX _user_secondary
! 520: #define MMU_KERNEL_IDX 2
! 521: #define MMU_MODE2_SUFFIX _kernel
! 522: #define MMU_KERNEL_SECONDARY_IDX 3
! 523: #define MMU_MODE3_SUFFIX _kernel_secondary
! 524: #define MMU_NUCLEUS_IDX 4
! 525: #define MMU_MODE4_SUFFIX _nucleus
! 526: #define MMU_HYPV_IDX 5
! 527: #define MMU_MODE5_SUFFIX _hypv
! 528: #else
1.1.1.6 root 529: #define MMU_USER_IDX 0
1.1.1.9 ! root 530: #define MMU_MODE0_SUFFIX _user
1.1.1.6 root 531: #define MMU_KERNEL_IDX 1
1.1.1.9 ! root 532: #define MMU_MODE1_SUFFIX _kernel
! 533: #endif
! 534:
! 535: #if defined (TARGET_SPARC64)
! 536: static inline int cpu_has_hypervisor(CPUState *env1)
! 537: {
! 538: return env1->def->features & CPU_FEATURE_HYPV;
! 539: }
! 540:
! 541: static inline int cpu_hypervisor_mode(CPUState *env1)
! 542: {
! 543: return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
! 544: }
! 545:
! 546: static inline int cpu_supervisor_mode(CPUState *env1)
! 547: {
! 548: return env1->pstate & PS_PRIV;
! 549: }
! 550: #endif
1.1.1.6 root 551:
552: static inline int cpu_mmu_index(CPUState *env1)
1.1.1.5 root 553: {
554: #if defined(CONFIG_USER_ONLY)
1.1.1.6 root 555: return MMU_USER_IDX;
1.1.1.5 root 556: #elif !defined(TARGET_SPARC64)
1.1.1.6 root 557: return env1->psrs;
1.1.1.5 root 558: #else
1.1.1.9 ! root 559: if (env1->tl > 0) {
! 560: return MMU_NUCLEUS_IDX;
! 561: } else if (cpu_hypervisor_mode(env1)) {
1.1.1.6 root 562: return MMU_HYPV_IDX;
1.1.1.9 ! root 563: } else if (cpu_supervisor_mode(env1)) {
! 564: return MMU_KERNEL_IDX;
! 565: } else {
! 566: return MMU_USER_IDX;
! 567: }
! 568: #endif
! 569: }
! 570:
! 571: static inline int cpu_interrupts_enabled(CPUState *env1)
! 572: {
! 573: #if !defined (TARGET_SPARC64)
! 574: if (env1->psret != 0)
! 575: return 1;
! 576: #else
! 577: if (env1->pstate & PS_IE)
! 578: return 1;
! 579: #endif
! 580:
! 581: return 0;
! 582: }
! 583:
! 584: static inline int cpu_pil_allowed(CPUState *env1, int pil)
! 585: {
! 586: #if !defined(TARGET_SPARC64)
! 587: /* level 15 is non-maskable on sparc v8 */
! 588: return pil == 15 || pil > env1->psrpil;
! 589: #else
! 590: return pil > env1->psrpil;
1.1.1.5 root 591: #endif
592: }
593:
1.1.1.6 root 594: static inline int cpu_fpu_enabled(CPUState *env1)
1.1.1.5 root 595: {
596: #if defined(CONFIG_USER_ONLY)
597: return 1;
598: #elif !defined(TARGET_SPARC64)
1.1.1.6 root 599: return env1->psref;
1.1.1.5 root 600: #else
1.1.1.6 root 601: return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0);
1.1.1.5 root 602: #endif
603: }
1.1 root 604:
1.1.1.6 root 605: #if defined(CONFIG_USER_ONLY)
606: static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
607: {
608: if (newsp)
609: env->regwptr[22] = newsp;
610: env->regwptr[0] = 0;
611: /* FIXME: Do we also need to clear CF? */
612: /* XXXXX */
613: printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
614: }
615: #endif
616:
1.1 root 617: #include "cpu-all.h"
1.1.1.6 root 618:
619: #ifdef TARGET_SPARC64
620: /* sun4u.c */
1.1.1.9 ! root 621: void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
! 622: uint64_t cpu_tick_get_count(CPUTimer *timer);
! 623: void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
1.1.1.8 root 624: trap_state* cpu_tsptr(CPUState* env);
1.1.1.6 root 625: #endif
626:
627: static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
628: target_ulong *cs_base, int *flags)
629: {
630: *pc = env->pc;
631: *cs_base = env->npc;
632: #ifdef TARGET_SPARC64
633: // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
1.1.1.9 ! root 634: *flags = ((env->pstate & PS_AM) << 2) /* 5 */
! 635: | (((env->pstate & PS_PEF) >> 1) /* 3 */
! 636: | ((env->fprs & FPRS_FEF) << 2)) /* 4 */
! 637: | (env->pstate & PS_PRIV) /* 2 */
! 638: | ((env->lsu & (DMMU_E | IMMU_E)) >> 2) /* 1, 0 */
! 639: | ((env->tl & 0xff) << 8)
! 640: | (env->dmmu.mmu_primary_context << 16); /* 16... */
1.1.1.6 root 641: #else
642: // FPU enable . Supervisor
643: *flags = (env->psref << 4) | env->psrs;
644: #endif
645: }
1.1 root 646:
647: #endif
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