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1.1 ! root 1: #include "hw/hw.h" ! 2: #include "hw/boards.h" ! 3: #include "qemu-timer.h" ! 4: ! 5: #include "exec-all.h" ! 6: ! 7: void register_machines(void) ! 8: { ! 9: #ifdef TARGET_SPARC64 ! 10: qemu_register_machine(&sun4u_machine); ! 11: qemu_register_machine(&sun4v_machine); ! 12: qemu_register_machine(&niagara_machine); ! 13: #else ! 14: qemu_register_machine(&ss5_machine); ! 15: qemu_register_machine(&ss10_machine); ! 16: qemu_register_machine(&ss600mp_machine); ! 17: qemu_register_machine(&ss20_machine); ! 18: qemu_register_machine(&ss2_machine); ! 19: qemu_register_machine(&voyager_machine); ! 20: qemu_register_machine(&ss_lx_machine); ! 21: qemu_register_machine(&ss4_machine); ! 22: qemu_register_machine(&scls_machine); ! 23: qemu_register_machine(&sbook_machine); ! 24: qemu_register_machine(&ss1000_machine); ! 25: qemu_register_machine(&ss2000_machine); ! 26: #endif ! 27: } ! 28: ! 29: void cpu_save(QEMUFile *f, void *opaque) ! 30: { ! 31: CPUState *env = opaque; ! 32: int i; ! 33: uint32_t tmp; ! 34: ! 35: // if env->cwp == env->nwindows - 1, this will set the ins of the last ! 36: // window as the outs of the first window ! 37: cpu_set_cwp(env, env->cwp); ! 38: ! 39: for(i = 0; i < 8; i++) ! 40: qemu_put_betls(f, &env->gregs[i]); ! 41: qemu_put_be32s(f, &env->nwindows); ! 42: for(i = 0; i < env->nwindows * 16; i++) ! 43: qemu_put_betls(f, &env->regbase[i]); ! 44: ! 45: /* FPU */ ! 46: for(i = 0; i < TARGET_FPREGS; i++) { ! 47: union { ! 48: float32 f; ! 49: uint32_t i; ! 50: } u; ! 51: u.f = env->fpr[i]; ! 52: qemu_put_be32(f, u.i); ! 53: } ! 54: ! 55: qemu_put_betls(f, &env->pc); ! 56: qemu_put_betls(f, &env->npc); ! 57: qemu_put_betls(f, &env->y); ! 58: tmp = GET_PSR(env); ! 59: qemu_put_be32(f, tmp); ! 60: qemu_put_betls(f, &env->fsr); ! 61: qemu_put_betls(f, &env->tbr); ! 62: tmp = env->interrupt_index; ! 63: qemu_put_be32(f, tmp); ! 64: qemu_put_be32s(f, &env->pil_in); ! 65: #ifndef TARGET_SPARC64 ! 66: qemu_put_be32s(f, &env->wim); ! 67: /* MMU */ ! 68: for (i = 0; i < 32; i++) ! 69: qemu_put_be32s(f, &env->mmuregs[i]); ! 70: #else ! 71: qemu_put_be64s(f, &env->lsu); ! 72: for (i = 0; i < 16; i++) { ! 73: qemu_put_be64s(f, &env->immuregs[i]); ! 74: qemu_put_be64s(f, &env->dmmuregs[i]); ! 75: } ! 76: for (i = 0; i < 64; i++) { ! 77: qemu_put_be64s(f, &env->itlb_tag[i]); ! 78: qemu_put_be64s(f, &env->itlb_tte[i]); ! 79: qemu_put_be64s(f, &env->dtlb_tag[i]); ! 80: qemu_put_be64s(f, &env->dtlb_tte[i]); ! 81: } ! 82: qemu_put_be32s(f, &env->mmu_version); ! 83: for (i = 0; i < MAXTL_MAX; i++) { ! 84: qemu_put_be64s(f, &env->ts[i].tpc); ! 85: qemu_put_be64s(f, &env->ts[i].tnpc); ! 86: qemu_put_be64s(f, &env->ts[i].tstate); ! 87: qemu_put_be32s(f, &env->ts[i].tt); ! 88: } ! 89: qemu_put_be32s(f, &env->xcc); ! 90: qemu_put_be32s(f, &env->asi); ! 91: qemu_put_be32s(f, &env->pstate); ! 92: qemu_put_be32s(f, &env->tl); ! 93: qemu_put_be32s(f, &env->cansave); ! 94: qemu_put_be32s(f, &env->canrestore); ! 95: qemu_put_be32s(f, &env->otherwin); ! 96: qemu_put_be32s(f, &env->wstate); ! 97: qemu_put_be32s(f, &env->cleanwin); ! 98: for (i = 0; i < 8; i++) ! 99: qemu_put_be64s(f, &env->agregs[i]); ! 100: for (i = 0; i < 8; i++) ! 101: qemu_put_be64s(f, &env->bgregs[i]); ! 102: for (i = 0; i < 8; i++) ! 103: qemu_put_be64s(f, &env->igregs[i]); ! 104: for (i = 0; i < 8; i++) ! 105: qemu_put_be64s(f, &env->mgregs[i]); ! 106: qemu_put_be64s(f, &env->fprs); ! 107: qemu_put_be64s(f, &env->tick_cmpr); ! 108: qemu_put_be64s(f, &env->stick_cmpr); ! 109: qemu_put_ptimer(f, env->tick); ! 110: qemu_put_ptimer(f, env->stick); ! 111: qemu_put_be64s(f, &env->gsr); ! 112: qemu_put_be32s(f, &env->gl); ! 113: qemu_put_be64s(f, &env->hpstate); ! 114: for (i = 0; i < MAXTL_MAX; i++) ! 115: qemu_put_be64s(f, &env->htstate[i]); ! 116: qemu_put_be64s(f, &env->hintp); ! 117: qemu_put_be64s(f, &env->htba); ! 118: qemu_put_be64s(f, &env->hver); ! 119: qemu_put_be64s(f, &env->hstick_cmpr); ! 120: qemu_put_be64s(f, &env->ssr); ! 121: qemu_put_ptimer(f, env->hstick); ! 122: #endif ! 123: } ! 124: ! 125: int cpu_load(QEMUFile *f, void *opaque, int version_id) ! 126: { ! 127: CPUState *env = opaque; ! 128: int i; ! 129: uint32_t tmp; ! 130: ! 131: if (version_id != 5) ! 132: return -EINVAL; ! 133: for(i = 0; i < 8; i++) ! 134: qemu_get_betls(f, &env->gregs[i]); ! 135: qemu_get_be32s(f, &env->nwindows); ! 136: for(i = 0; i < env->nwindows * 16; i++) ! 137: qemu_get_betls(f, &env->regbase[i]); ! 138: ! 139: /* FPU */ ! 140: for(i = 0; i < TARGET_FPREGS; i++) { ! 141: union { ! 142: float32 f; ! 143: uint32_t i; ! 144: } u; ! 145: u.i = qemu_get_be32(f); ! 146: env->fpr[i] = u.f; ! 147: } ! 148: ! 149: qemu_get_betls(f, &env->pc); ! 150: qemu_get_betls(f, &env->npc); ! 151: qemu_get_betls(f, &env->y); ! 152: tmp = qemu_get_be32(f); ! 153: env->cwp = 0; /* needed to ensure that the wrapping registers are ! 154: correctly updated */ ! 155: PUT_PSR(env, tmp); ! 156: qemu_get_betls(f, &env->fsr); ! 157: qemu_get_betls(f, &env->tbr); ! 158: tmp = qemu_get_be32(f); ! 159: env->interrupt_index = tmp; ! 160: qemu_get_be32s(f, &env->pil_in); ! 161: #ifndef TARGET_SPARC64 ! 162: qemu_get_be32s(f, &env->wim); ! 163: /* MMU */ ! 164: for (i = 0; i < 32; i++) ! 165: qemu_get_be32s(f, &env->mmuregs[i]); ! 166: #else ! 167: qemu_get_be64s(f, &env->lsu); ! 168: for (i = 0; i < 16; i++) { ! 169: qemu_get_be64s(f, &env->immuregs[i]); ! 170: qemu_get_be64s(f, &env->dmmuregs[i]); ! 171: } ! 172: for (i = 0; i < 64; i++) { ! 173: qemu_get_be64s(f, &env->itlb_tag[i]); ! 174: qemu_get_be64s(f, &env->itlb_tte[i]); ! 175: qemu_get_be64s(f, &env->dtlb_tag[i]); ! 176: qemu_get_be64s(f, &env->dtlb_tte[i]); ! 177: } ! 178: qemu_get_be32s(f, &env->mmu_version); ! 179: for (i = 0; i < MAXTL_MAX; i++) { ! 180: qemu_get_be64s(f, &env->ts[i].tpc); ! 181: qemu_get_be64s(f, &env->ts[i].tnpc); ! 182: qemu_get_be64s(f, &env->ts[i].tstate); ! 183: qemu_get_be32s(f, &env->ts[i].tt); ! 184: } ! 185: qemu_get_be32s(f, &env->xcc); ! 186: qemu_get_be32s(f, &env->asi); ! 187: qemu_get_be32s(f, &env->pstate); ! 188: qemu_get_be32s(f, &env->tl); ! 189: env->tsptr = &env->ts[env->tl & MAXTL_MASK]; ! 190: qemu_get_be32s(f, &env->cansave); ! 191: qemu_get_be32s(f, &env->canrestore); ! 192: qemu_get_be32s(f, &env->otherwin); ! 193: qemu_get_be32s(f, &env->wstate); ! 194: qemu_get_be32s(f, &env->cleanwin); ! 195: for (i = 0; i < 8; i++) ! 196: qemu_get_be64s(f, &env->agregs[i]); ! 197: for (i = 0; i < 8; i++) ! 198: qemu_get_be64s(f, &env->bgregs[i]); ! 199: for (i = 0; i < 8; i++) ! 200: qemu_get_be64s(f, &env->igregs[i]); ! 201: for (i = 0; i < 8; i++) ! 202: qemu_get_be64s(f, &env->mgregs[i]); ! 203: qemu_get_be64s(f, &env->fprs); ! 204: qemu_get_be64s(f, &env->tick_cmpr); ! 205: qemu_get_be64s(f, &env->stick_cmpr); ! 206: qemu_get_ptimer(f, env->tick); ! 207: qemu_get_ptimer(f, env->stick); ! 208: qemu_get_be64s(f, &env->gsr); ! 209: qemu_get_be32s(f, &env->gl); ! 210: qemu_get_be64s(f, &env->hpstate); ! 211: for (i = 0; i < MAXTL_MAX; i++) ! 212: qemu_get_be64s(f, &env->htstate[i]); ! 213: qemu_get_be64s(f, &env->hintp); ! 214: qemu_get_be64s(f, &env->htba); ! 215: qemu_get_be64s(f, &env->hver); ! 216: qemu_get_be64s(f, &env->hstick_cmpr); ! 217: qemu_get_be64s(f, &env->ssr); ! 218: qemu_get_ptimer(f, env->hstick); ! 219: #endif ! 220: tlb_flush(env, 1); ! 221: return 0; ! 222: }
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