Diff for /qemu/target-xtensa/cpu.h between versions 1.1.1.1 and 1.1.1.2

version 1.1.1.1, 2018/04/24 19:33:13 version 1.1.1.2, 2018/04/24 19:54:04
Line 31 Line 31
 #define TARGET_LONG_BITS 32  #define TARGET_LONG_BITS 32
 #define ELF_MACHINE EM_XTENSA  #define ELF_MACHINE EM_XTENSA
   
 #define CPUState struct CPUXtensaState  #define CPUArchState struct CPUXtensaState
   
 #include "config.h"  #include "config.h"
 #include "qemu-common.h"  #include "qemu-common.h"
Line 126  enum { Line 126  enum {
     RASID = 90,      RASID = 90,
     ITLBCFG = 91,      ITLBCFG = 91,
     DTLBCFG = 92,      DTLBCFG = 92,
       IBREAKENABLE = 96,
       IBREAKA = 128,
       DBREAKA = 144,
       DBREAKC = 160,
     EPC1 = 177,      EPC1 = 177,
     DEPC = 192,      DEPC = 192,
     EPS2 = 194,      EPS2 = 194,
Line 137  enum { Line 141  enum {
     PS = 230,      PS = 230,
     VECBASE = 231,      VECBASE = 231,
     EXCCAUSE = 232,      EXCCAUSE = 232,
       DEBUGCAUSE = 233,
     CCOUNT = 234,      CCOUNT = 234,
     PRID = 235,      PRID = 235,
       ICOUNT = 236,
       ICOUNTLEVEL = 237,
     EXCVADDR = 238,      EXCVADDR = 238,
     CCOMPARE = 240,      CCOMPARE = 240,
 };  };
Line 161  enum { Line 168  enum {
   
 #define PS_WOE 0x40000  #define PS_WOE 0x40000
   
   #define DEBUGCAUSE_IC 0x1
   #define DEBUGCAUSE_IB 0x2
   #define DEBUGCAUSE_DB 0x4
   #define DEBUGCAUSE_BI 0x8
   #define DEBUGCAUSE_BN 0x10
   #define DEBUGCAUSE_DI 0x20
   #define DEBUGCAUSE_DBNUM 0xf00
   #define DEBUGCAUSE_DBNUM_SHIFT 8
   
   #define DBREAKC_SB 0x80000000
   #define DBREAKC_LB 0x40000000
   #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
   #define DBREAKC_MASK 0x3f
   
 #define MAX_NAREG 64  #define MAX_NAREG 64
 #define MAX_NINTERRUPT 32  #define MAX_NINTERRUPT 32
 #define MAX_NLEVEL 6  #define MAX_NLEVEL 6
 #define MAX_NNMI 1  #define MAX_NNMI 1
 #define MAX_NCCOMPARE 3  #define MAX_NCCOMPARE 3
 #define MAX_TLB_WAY_SIZE 8  #define MAX_TLB_WAY_SIZE 8
   #define MAX_NDBREAK 2
   
 #define REGION_PAGE_MASK 0xe0000000  #define REGION_PAGE_MASK 0xe0000000
   
Line 186  enum { Line 208  enum {
     EXC_KERNEL,      EXC_KERNEL,
     EXC_USER,      EXC_USER,
     EXC_DOUBLE,      EXC_DOUBLE,
       EXC_DEBUG,
     EXC_MAX      EXC_MAX
 };  };
   
Line 279  typedef struct XtensaConfig { Line 302  typedef struct XtensaConfig {
     uint32_t timerint[MAX_NCCOMPARE];      uint32_t timerint[MAX_NCCOMPARE];
     unsigned nextint;      unsigned nextint;
     unsigned extint[MAX_NINTERRUPT];      unsigned extint[MAX_NINTERRUPT];
   
       unsigned debug_level;
       unsigned nibreak;
       unsigned ndbreak;
   
     uint32_t clock_freq_khz;      uint32_t clock_freq_khz;
   
     xtensa_tlb itlb;      xtensa_tlb itlb;
Line 310  typedef struct CPUXtensaState { Line 338  typedef struct CPUXtensaState {
   
     int exception_taken;      int exception_taken;
   
       /* Watchpoints for DBREAK registers */
       CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
   
     CPU_COMMON      CPU_COMMON
 } CPUXtensaState;  } CPUXtensaState;
   
Line 325  int cpu_xtensa_exec(CPUXtensaState *s); Line 356  int cpu_xtensa_exec(CPUXtensaState *s);
 void xtensa_register_core(XtensaConfigList *node);  void xtensa_register_core(XtensaConfigList *node);
 void do_interrupt(CPUXtensaState *s);  void do_interrupt(CPUXtensaState *s);
 void check_interrupts(CPUXtensaState *s);  void check_interrupts(CPUXtensaState *s);
 void xtensa_irq_init(CPUState *env);  void xtensa_irq_init(CPUXtensaState *env);
 void *xtensa_get_extint(CPUState *env, unsigned extint);  void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
 void xtensa_advance_ccount(CPUState *env, uint32_t d);  void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d);
 void xtensa_timer_irq(CPUState *env, uint32_t id, uint32_t active);  void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
 void xtensa_rearm_ccompare_timer(CPUState *env);  void xtensa_rearm_ccompare_timer(CPUXtensaState *env);
 int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);  int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);  void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 void xtensa_sync_window_from_phys(CPUState *env);  void xtensa_sync_window_from_phys(CPUXtensaState *env);
 void xtensa_sync_phys_from_window(CPUState *env);  void xtensa_sync_phys_from_window(CPUXtensaState *env);
 uint32_t xtensa_tlb_get_addr_mask(const CPUState *env, bool dtlb, uint32_t way);  uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
 void split_tlb_entry_spec_way(const CPUState *env, uint32_t v, bool dtlb,  void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
         uint32_t *vpn, uint32_t wi, uint32_t *ei);          uint32_t *vpn, uint32_t wi, uint32_t *ei);
 int xtensa_tlb_lookup(const CPUState *env, uint32_t addr, bool dtlb,  int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
         uint32_t *pwi, uint32_t *pei, uint8_t *pring);          uint32_t *pwi, uint32_t *pei, uint8_t *pring);
 void xtensa_tlb_set_entry(CPUState *env, bool dtlb,  void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
           xtensa_tlb_entry *entry, bool dtlb,
           unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
   void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);          unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
 int xtensa_get_physical_addr(CPUState *env,  int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
         uint32_t vaddr, int is_write, int mmu_idx,          uint32_t vaddr, int is_write, int mmu_idx,
         uint32_t *paddr, uint32_t *page_size, unsigned *access);          uint32_t *paddr, uint32_t *page_size, unsigned *access);
   void reset_mmu(CPUXtensaState *env);
   void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
   void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
   
   
 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))  #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
Line 359  static inline bool xtensa_option_enabled Line 396  static inline bool xtensa_option_enabled
     return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));      return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
 }  }
   
 static inline int xtensa_get_cintlevel(const CPUState *env)  static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
 {  {
     int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;      int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
     if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {      if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
Line 368  static inline int xtensa_get_cintlevel(c Line 405  static inline int xtensa_get_cintlevel(c
     return level;      return level;
 }  }
   
 static inline int xtensa_get_ring(const CPUState *env)  static inline int xtensa_get_ring(const CPUXtensaState *env)
 {  {
     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {      if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;          return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
Line 377  static inline int xtensa_get_ring(const  Line 414  static inline int xtensa_get_ring(const 
     }      }
 }  }
   
 static inline int xtensa_get_cring(const CPUState *env)  static inline int xtensa_get_cring(const CPUXtensaState *env)
 {  {
     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&      if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
             (env->sregs[PS] & PS_EXCM) == 0) {              (env->sregs[PS] & PS_EXCM) == 0) {
Line 387  static inline int xtensa_get_cring(const Line 424  static inline int xtensa_get_cring(const
     }      }
 }  }
   
 static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUState *env,  static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
         bool dtlb, unsigned wi, unsigned ei)          bool dtlb, unsigned wi, unsigned ei)
 {  {
     return dtlb ?      return dtlb ?
Line 401  static inline xtensa_tlb_entry *xtensa_t Line 438  static inline xtensa_tlb_entry *xtensa_t
 #define MMU_MODE2_SUFFIX _ring2  #define MMU_MODE2_SUFFIX _ring2
 #define MMU_MODE3_SUFFIX _ring3  #define MMU_MODE3_SUFFIX _ring3
   
 static inline int cpu_mmu_index(CPUState *env)  static inline int cpu_mmu_index(CPUXtensaState *env)
 {  {
     return xtensa_get_cring(env);      return xtensa_get_cring(env);
 }  }
Line 409  static inline int cpu_mmu_index(CPUState Line 446  static inline int cpu_mmu_index(CPUState
 #define XTENSA_TBFLAG_RING_MASK 0x3  #define XTENSA_TBFLAG_RING_MASK 0x3
 #define XTENSA_TBFLAG_EXCM 0x4  #define XTENSA_TBFLAG_EXCM 0x4
 #define XTENSA_TBFLAG_LITBASE 0x8  #define XTENSA_TBFLAG_LITBASE 0x8
   #define XTENSA_TBFLAG_DEBUG 0x10
   #define XTENSA_TBFLAG_ICOUNT 0x20
   
 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,  static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
         target_ulong *cs_base, int *flags)          target_ulong *cs_base, int *flags)
 {  {
     *pc = env->pc;      *pc = env->pc;
Line 424  static inline void cpu_get_tb_cpu_state( Line 463  static inline void cpu_get_tb_cpu_state(
             (env->sregs[LITBASE] & 1)) {              (env->sregs[LITBASE] & 1)) {
         *flags |= XTENSA_TBFLAG_LITBASE;          *flags |= XTENSA_TBFLAG_LITBASE;
     }      }
       if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
           if (xtensa_get_cintlevel(env) < env->config->debug_level) {
               *flags |= XTENSA_TBFLAG_DEBUG;
           }
           if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
               *flags |= XTENSA_TBFLAG_ICOUNT;
           }
       }
 }  }
   
 #include "cpu-all.h"  #include "cpu-all.h"
   #include "cpu-qom.h"
 #include "exec-all.h"  #include "exec-all.h"
   
 static inline int cpu_has_work(CPUState *env)  static inline int cpu_has_work(CPUXtensaState *env)
 {  {
     return env->pending_irq_level;      return env->pending_irq_level;
 }  }
   
 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)  static inline void cpu_pc_from_tb(CPUXtensaState *env, TranslationBlock *tb)
 {  {
     env->pc = tb->pc;      env->pc = tb->pc;
 }  }

Removed from v.1.1.1.1  
changed lines
  Added in v.1.1.1.2


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