--- qemu/tcg/i386/tcg-target.c 2018/04/24 18:57:12 1.1.1.5 +++ qemu/tcg/i386/tcg-target.c 2018/04/24 19:35:51 1.1.1.7 @@ -63,10 +63,15 @@ static const int tcg_target_reg_alloc_or static const int tcg_target_call_iarg_regs[] = { #if TCG_TARGET_REG_BITS == 64 +#if defined(_WIN64) + TCG_REG_RCX, + TCG_REG_RDX, +#else TCG_REG_RDI, TCG_REG_RSI, TCG_REG_RDX, TCG_REG_RCX, +#endif TCG_REG_R8, TCG_REG_R9, #else @@ -76,9 +81,11 @@ static const int tcg_target_call_iarg_re #endif }; -static const int tcg_target_call_oarg_regs[2] = { +static const int tcg_target_call_oarg_regs[] = { TCG_REG_EAX, +#if TCG_TARGET_REG_BITS == 32 TCG_REG_EDX +#endif }; static uint8_t *tb_ret_addr; @@ -114,17 +121,7 @@ static inline int tcg_target_get_call_ia return 6; } - flags &= TCG_CALL_TYPE_MASK; - switch(flags) { - case TCG_CALL_TYPE_STD: - return 0; - case TCG_CALL_TYPE_REGPARM_1: - case TCG_CALL_TYPE_REGPARM_2: - case TCG_CALL_TYPE_REGPARM: - return flags - TCG_CALL_TYPE_REGPARM_1 + 1; - default: - tcg_abort(); - } + return 0; } /* parse target specific constraints */ @@ -166,6 +163,10 @@ static int target_parse_constraint(TCGAr tcg_regset_set32(ct->u.regs, 0, 0xf); } break; + case 'Q': + ct->ct |= TCG_CT_REG; + tcg_regset_set32(ct->u.regs, 0, 0xf); + break; case 'r': ct->ct |= TCG_CT_REG; if (TCG_TARGET_REG_BITS == 64) { @@ -180,8 +181,11 @@ static int target_parse_constraint(TCGAr ct->ct |= TCG_CT_REG; if (TCG_TARGET_REG_BITS == 64) { tcg_regset_set32(ct->u.regs, 0, 0xffff); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI); - tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI); + tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]); + tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]); +#ifdef CONFIG_TCG_PASS_AREG0 + tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]); +#endif } else { tcg_regset_set32(ct->u.regs, 0, 0xff); tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX); @@ -512,7 +516,8 @@ static inline void tgen_arithr(TCGContex tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src); } -static inline void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg) +static inline void tcg_out_mov(TCGContext *s, TCGType type, + TCGReg ret, TCGReg arg) { if (arg != ret) { int opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0); @@ -521,7 +526,7 @@ static inline void tcg_out_mov(TCGContex } static void tcg_out_movi(TCGContext *s, TCGType type, - int ret, tcg_target_long arg) + TCGReg ret, tcg_target_long arg) { if (arg == 0) { tgen_arithr(s, ARITH_XOR, ret, ret); @@ -562,15 +567,15 @@ static inline void tcg_out_pop(TCGContex tcg_out_opc(s, OPC_POP_r32 + LOWREGMASK(reg), 0, reg, 0); } -static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret, - int arg1, tcg_target_long arg2) +static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, + TCGReg arg1, tcg_target_long arg2) { int opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0); tcg_out_modrm_offset(s, opc, ret, arg1, arg2); } -static inline void tcg_out_st(TCGContext *s, TCGType type, int arg, - int arg1, tcg_target_long arg2) +static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, tcg_target_long arg2) { int opc = OPC_MOVL_EvGv + (type == TCG_TYPE_I64 ? P_REXW : 0); tcg_out_modrm_offset(s, opc, arg, arg1, arg2); @@ -868,7 +873,7 @@ static void tcg_out_brcond2(TCGContext * default: tcg_abort(); } - tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr); + tcg_out_label(s, label_next, s->code_ptr); } #endif @@ -910,10 +915,10 @@ static void tcg_out_setcond2(TCGContext tcg_out_movi(s, TCG_TYPE_I32, args[0], 0); tcg_out_jxx(s, JCC_JMP, label_over, 1); - tcg_out_label(s, label_true, (tcg_target_long)s->code_ptr); + tcg_out_label(s, label_true, s->code_ptr); tcg_out_movi(s, TCG_TYPE_I32, args[0], 1); - tcg_out_label(s, label_over, (tcg_target_long)s->code_ptr); + tcg_out_label(s, label_over, s->code_ptr); } else { /* When the destination does not overlap one of the arguments, clear the destination first, jump if cond false, and emit an @@ -927,7 +932,7 @@ static void tcg_out_setcond2(TCGContext tcg_out_brcond2(s, new_args, const_args+1, 1); tgen_arithi(s, ARITH_ADD, args[0], 1, 0); - tcg_out_label(s, label_over, (tcg_target_long)s->code_ptr); + tcg_out_label(s, label_over, s->code_ptr); } } #endif @@ -960,6 +965,27 @@ static void tcg_out_jmp(TCGContext *s, t #include "../../softmmu_defs.h" +#ifdef CONFIG_TCG_PASS_AREG0 +/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, + int mmu_idx) */ +static const void *qemu_ld_helpers[4] = { + helper_ldb_mmu, + helper_ldw_mmu, + helper_ldl_mmu, + helper_ldq_mmu, +}; + +/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr, + uintxx_t val, int mmu_idx) */ +static const void *qemu_st_helpers[4] = { + helper_stb_mmu, + helper_stw_mmu, + helper_stl_mmu, + helper_stq_mmu, +}; +#else +/* legacy helper signature: __ld_mmu(target_ulong addr, int + mmu_idx) */ static void *qemu_ld_helpers[4] = { __ldb_mmu, __ldw_mmu, @@ -967,12 +993,15 @@ static void *qemu_ld_helpers[4] = { __ldq_mmu, }; +/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val, + int mmu_idx) */ static void *qemu_st_helpers[4] = { __stb_mmu, __stw_mmu, __stl_mmu, __stq_mmu, }; +#endif /* Perform the TLB load and compare. @@ -1024,7 +1053,7 @@ static inline void tcg_out_tlb_load(TCGC (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS, 0); tcg_out_modrm_sib_offset(s, OPC_LEA + P_REXW, r1, TCG_AREG0, r1, 0, - offsetof(CPUState, tlb_table[mem_index][0]) + offsetof(CPUArchState, tlb_table[mem_index][0]) + which); /* cmp 0(r1), r0 */ @@ -1141,7 +1170,12 @@ static void tcg_out_qemu_ld(TCGContext * int data_reg, data_reg2 = 0; int addrlo_idx; #if defined(CONFIG_SOFTMMU) - int mem_index, s_bits, arg_idx; + int mem_index, s_bits; +#if TCG_TARGET_REG_BITS == 64 + int arg_idx; +#else + int stack_adjust; +#endif uint8_t *label_ptr[3]; #endif @@ -1177,16 +1211,48 @@ static void tcg_out_qemu_ld(TCGContext * } /* XXX: move that code at the end of the TB */ +#if TCG_TARGET_REG_BITS == 32 + tcg_out_pushi(s, mem_index); + stack_adjust = 4; + if (TARGET_LONG_BITS == 64) { + tcg_out_push(s, args[addrlo_idx + 1]); + stack_adjust += 4; + } + tcg_out_push(s, args[addrlo_idx]); + stack_adjust += 4; +#ifdef CONFIG_TCG_PASS_AREG0 + tcg_out_push(s, TCG_AREG0); + stack_adjust += 4; +#endif +#else /* The first argument is already loaded with addrlo. */ arg_idx = 1; - if (TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 64) { - tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[arg_idx++], - args[addrlo_idx + 1]); - } tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[arg_idx], mem_index); +#ifdef CONFIG_TCG_PASS_AREG0 + /* XXX/FIXME: suboptimal */ + tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[3], + tcg_target_call_iarg_regs[2]); + tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2], + tcg_target_call_iarg_regs[1]); + tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[1], + tcg_target_call_iarg_regs[0]); + tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0], + TCG_AREG0); +#endif +#endif + tcg_out_calli(s, (tcg_target_long)qemu_ld_helpers[s_bits]); +#if TCG_TARGET_REG_BITS == 32 + if (stack_adjust == (TCG_TARGET_REG_BITS / 8)) { + /* Pop and discard. This is 2 bytes smaller than the add. */ + tcg_out_pop(s, TCG_REG_ECX); + } else if (stack_adjust != 0) { + tcg_out_addi(s, TCG_REG_CALL_STACK, stack_adjust); + } +#endif + switch(opc) { case 0 | 4: tcg_out_ext8s(s, data_reg, TCG_REG_EAX, P_REXW); @@ -1239,9 +1305,12 @@ static void tcg_out_qemu_ld(TCGContext * use the ADDR32 prefix. For now, do nothing. */ if (offset != GUEST_BASE) { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RDI, GUEST_BASE); - tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_RDI, base); - base = TCG_REG_RDI, offset = 0; + tcg_out_movi(s, TCG_TYPE_I64, + tcg_target_call_iarg_regs[0], GUEST_BASE); + tgen_arithr(s, ARITH_ADD + P_REXW, + tcg_target_call_iarg_regs[0], base); + base = tcg_target_call_iarg_regs[0]; + offset = 0; } } @@ -1352,45 +1421,42 @@ static void tcg_out_qemu_st(TCGContext * } /* XXX: move that code at the end of the TB */ - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_mov(s, (opc == 3 ? TCG_TYPE_I64 : TCG_TYPE_I32), - TCG_REG_RSI, data_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index); - stack_adjust = 0; - } else if (TARGET_LONG_BITS == 32) { - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_EDX, data_reg); - if (opc == 3) { - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_ECX, data_reg2); - tcg_out_pushi(s, mem_index); - stack_adjust = 4; - } else { - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index); - stack_adjust = 0; - } - } else { - if (opc == 3) { - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_EDX, args[addrlo_idx + 1]); - tcg_out_pushi(s, mem_index); - tcg_out_push(s, data_reg2); - tcg_out_push(s, data_reg); - stack_adjust = 12; - } else { - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_EDX, args[addrlo_idx + 1]); - switch(opc) { - case 0: - tcg_out_ext8u(s, TCG_REG_ECX, data_reg); - break; - case 1: - tcg_out_ext16u(s, TCG_REG_ECX, data_reg); - break; - case 2: - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_ECX, data_reg); - break; - } - tcg_out_pushi(s, mem_index); - stack_adjust = 4; - } - } +#if TCG_TARGET_REG_BITS == 32 + tcg_out_pushi(s, mem_index); + stack_adjust = 4; + if (opc == 3) { + tcg_out_push(s, data_reg2); + stack_adjust += 4; + } + tcg_out_push(s, data_reg); + stack_adjust += 4; + if (TARGET_LONG_BITS == 64) { + tcg_out_push(s, args[addrlo_idx + 1]); + stack_adjust += 4; + } + tcg_out_push(s, args[addrlo_idx]); + stack_adjust += 4; +#ifdef CONFIG_TCG_PASS_AREG0 + tcg_out_push(s, TCG_AREG0); + stack_adjust += 4; +#endif +#else + tcg_out_mov(s, (opc == 3 ? TCG_TYPE_I64 : TCG_TYPE_I32), + tcg_target_call_iarg_regs[1], data_reg); + tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], mem_index); + stack_adjust = 0; +#ifdef CONFIG_TCG_PASS_AREG0 + /* XXX/FIXME: suboptimal */ + tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[3], + tcg_target_call_iarg_regs[2]); + tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2], + tcg_target_call_iarg_regs[1]); + tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[1], + tcg_target_call_iarg_regs[0]); + tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0], + TCG_AREG0); +#endif +#endif tcg_out_calli(s, (tcg_target_long)qemu_st_helpers[s_bits]); @@ -1416,9 +1482,12 @@ static void tcg_out_qemu_st(TCGContext * use the ADDR32 prefix. For now, do nothing. */ if (offset != GUEST_BASE) { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RDI, GUEST_BASE); - tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_RDI, base); - base = TCG_REG_RDI, offset = 0; + tcg_out_movi(s, TCG_TYPE_I64, + tcg_target_call_iarg_regs[0], GUEST_BASE); + tgen_arithr(s, ARITH_ADD + P_REXW, + tcg_target_call_iarg_regs[0], base); + base = tcg_target_call_iarg_regs[0]; + offset = 0; } } @@ -1745,6 +1814,22 @@ static inline void tcg_out_op(TCGContext break; #endif + OP_32_64(deposit): + if (args[3] == 0 && args[4] == 8) { + /* load bits 0..7 */ + tcg_out_modrm(s, OPC_MOVB_EvGv | P_REXB_R | P_REXB_RM, + args[2], args[0]); + } else if (args[3] == 8 && args[4] == 8) { + /* load bits 8..15 */ + tcg_out_modrm(s, OPC_MOVB_EvGv, args[2], args[0] + 4); + } else if (args[3] == 0 && args[4] == 16) { + /* load bits 0..15 */ + tcg_out_modrm(s, OPC_MOVL_EvGv | P_DATA16, args[2], args[0]); + } else { + tcg_abort(); + } + break; + default: tcg_abort(); } @@ -1800,6 +1885,8 @@ static const TCGTargetOpDef x86_op_defs[ { INDEX_op_setcond_i32, { "q", "r", "ri" } }, + { INDEX_op_deposit_i32, { "Q", "0", "Q" } }, + #if TCG_TARGET_REG_BITS == 32 { INDEX_op_mulu2_i32, { "a", "d", "a", "r" } }, { INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } }, @@ -1851,6 +1938,8 @@ static const TCGTargetOpDef x86_op_defs[ { INDEX_op_ext8u_i64, { "r", "r" } }, { INDEX_op_ext16u_i64, { "r", "r" } }, { INDEX_op_ext32u_i64, { "r", "r" } }, + + { INDEX_op_deposit_i64, { "Q", "0", "Q" } }, #endif #if TCG_TARGET_REG_BITS == 64 @@ -1899,6 +1988,10 @@ static int tcg_target_callee_save_regs[] #if TCG_TARGET_REG_BITS == 64 TCG_REG_RBP, TCG_REG_RBX, +#if defined(_WIN64) + TCG_REG_RDI, + TCG_REG_RSI, +#endif TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, /* Currently used for the global env. */ @@ -1911,22 +2004,29 @@ static int tcg_target_callee_save_regs[] #endif }; +/* Compute frame size via macros, to share between tcg_target_qemu_prologue + and tcg_register_jit. */ + +#define PUSH_SIZE \ + ((1 + ARRAY_SIZE(tcg_target_callee_save_regs)) \ + * (TCG_TARGET_REG_BITS / 8)) + +#define FRAME_SIZE \ + ((PUSH_SIZE \ + + TCG_STATIC_CALL_ARGS_SIZE \ + + CPU_TEMP_BUF_NLONGS * sizeof(long) \ + + TCG_TARGET_STACK_ALIGN - 1) \ + & ~(TCG_TARGET_STACK_ALIGN - 1)) + /* Generate global QEMU prologue and epilogue code */ static void tcg_target_qemu_prologue(TCGContext *s) { - int i, frame_size, push_size, stack_addend; + int i, stack_addend; /* TB prologue */ /* Reserve some stack space, also for TCG temps. */ - push_size = 1 + ARRAY_SIZE(tcg_target_callee_save_regs); - push_size *= TCG_TARGET_REG_BITS / 8; - - frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE + - CPU_TEMP_BUF_NLONGS * sizeof(long); - frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) & - ~(TCG_TARGET_STACK_ALIGN - 1); - stack_addend = frame_size - push_size; + stack_addend = FRAME_SIZE - PUSH_SIZE; tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE, CPU_TEMP_BUF_NLONGS * sizeof(long)); @@ -1935,9 +2035,15 @@ static void tcg_target_qemu_prologue(TCG tcg_out_push(s, tcg_target_callee_save_regs[i]); } - tcg_out_addi(s, TCG_REG_ESP, -stack_addend); - +#if TCG_TARGET_REG_BITS == 32 + tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, + (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4); + tcg_out_ld(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[1], TCG_REG_ESP, + (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4); +#else tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); +#endif + tcg_out_addi(s, TCG_REG_ESP, -stack_addend); /* jmp *tb. */ tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]); @@ -1973,8 +2079,10 @@ static void tcg_target_init(TCGContext * tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EDX); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_ECX); if (TCG_TARGET_REG_BITS == 64) { +#if !defined(_WIN64) tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RDI); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RSI); +#endif tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); @@ -1986,3 +2094,96 @@ static void tcg_target_init(TCGContext * tcg_add_target_add_op_defs(x86_op_defs); } + +typedef struct { + uint32_t len __attribute__((aligned((sizeof(void *))))); + uint32_t id; + uint8_t version; + char augmentation[1]; + uint8_t code_align; + uint8_t data_align; + uint8_t return_column; +} DebugFrameCIE; + +typedef struct { + uint32_t len __attribute__((aligned((sizeof(void *))))); + uint32_t cie_offset; + tcg_target_long func_start __attribute__((packed)); + tcg_target_long func_len __attribute__((packed)); + uint8_t def_cfa[4]; + uint8_t reg_ofs[14]; +} DebugFrameFDE; + +typedef struct { + DebugFrameCIE cie; + DebugFrameFDE fde; +} DebugFrame; + +#if !defined(__ELF__) + /* Host machine without ELF. */ +#elif TCG_TARGET_REG_BITS == 64 +#define ELF_HOST_MACHINE EM_X86_64 +static DebugFrame debug_frame = { + .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ + .cie.id = -1, + .cie.version = 1, + .cie.code_align = 1, + .cie.data_align = 0x78, /* sleb128 -8 */ + .cie.return_column = 16, + + .fde.len = sizeof(DebugFrameFDE)-4, /* length after .len member */ + .fde.def_cfa = { + 12, 7, /* DW_CFA_def_cfa %rsp, ... */ + (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ + (FRAME_SIZE >> 7) + }, + .fde.reg_ofs = { + 0x90, 1, /* DW_CFA_offset, %rip, -8 */ + /* The following ordering must match tcg_target_callee_save_regs. */ + 0x86, 2, /* DW_CFA_offset, %rbp, -16 */ + 0x83, 3, /* DW_CFA_offset, %rbx, -24 */ + 0x8c, 4, /* DW_CFA_offset, %r12, -32 */ + 0x8d, 5, /* DW_CFA_offset, %r13, -40 */ + 0x8e, 6, /* DW_CFA_offset, %r14, -48 */ + 0x8f, 7, /* DW_CFA_offset, %r15, -56 */ + } +}; +#else +#define ELF_HOST_MACHINE EM_386 +static DebugFrame debug_frame = { + .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ + .cie.id = -1, + .cie.version = 1, + .cie.code_align = 1, + .cie.data_align = 0x7c, /* sleb128 -4 */ + .cie.return_column = 8, + + .fde.len = sizeof(DebugFrameFDE)-4, /* length after .len member */ + .fde.def_cfa = { + 12, 4, /* DW_CFA_def_cfa %esp, ... */ + (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ + (FRAME_SIZE >> 7) + }, + .fde.reg_ofs = { + 0x88, 1, /* DW_CFA_offset, %eip, -4 */ + /* The following ordering must match tcg_target_callee_save_regs. */ + 0x85, 2, /* DW_CFA_offset, %ebp, -8 */ + 0x83, 3, /* DW_CFA_offset, %ebx, -12 */ + 0x86, 4, /* DW_CFA_offset, %esi, -16 */ + 0x87, 5, /* DW_CFA_offset, %edi, -20 */ + } +}; +#endif + +#if defined(ELF_HOST_MACHINE) +void tcg_register_jit(void *buf, size_t buf_size) +{ + /* We're expecting a 2 byte uleb128 encoded value. */ + assert(FRAME_SIZE >> 14 == 0); + + debug_frame.fde.func_start = (tcg_target_long) buf; + debug_frame.fde.func_len = buf_size; + + tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); +} +#endif