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1.1 root 1: /*
2: * Tiny Code Generator for QEMU
3: *
4: * Copyright (c) 2008 Fabrice Bellard
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
24: #define TCG_TARGET_I386 1
25:
26: //#define TCG_TARGET_WORDS_BIGENDIAN
27:
1.1.1.4 root 28: #if TCG_TARGET_REG_BITS == 64
29: # define TCG_TARGET_NB_REGS 16
30: #else
31: # define TCG_TARGET_NB_REGS 8
32: #endif
1.1 root 33:
1.1.1.5 root 34: typedef enum {
1.1 root 35: TCG_REG_EAX = 0,
36: TCG_REG_ECX,
37: TCG_REG_EDX,
38: TCG_REG_EBX,
39: TCG_REG_ESP,
40: TCG_REG_EBP,
41: TCG_REG_ESI,
42: TCG_REG_EDI,
1.1.1.4 root 43:
44: /* 64-bit registers; always define the symbols to avoid
45: too much if-deffing. */
46: TCG_REG_R8,
47: TCG_REG_R9,
48: TCG_REG_R10,
49: TCG_REG_R11,
50: TCG_REG_R12,
51: TCG_REG_R13,
52: TCG_REG_R14,
53: TCG_REG_R15,
54: TCG_REG_RAX = TCG_REG_EAX,
55: TCG_REG_RCX = TCG_REG_ECX,
56: TCG_REG_RDX = TCG_REG_EDX,
57: TCG_REG_RBX = TCG_REG_EBX,
58: TCG_REG_RSP = TCG_REG_ESP,
59: TCG_REG_RBP = TCG_REG_EBP,
60: TCG_REG_RSI = TCG_REG_ESI,
61: TCG_REG_RDI = TCG_REG_EDI,
1.1.1.5 root 62: } TCGReg;
1.1 root 63:
1.1.1.4 root 64: #define TCG_CT_CONST_S32 0x100
65: #define TCG_CT_CONST_U32 0x200
66:
1.1 root 67: /* used for function call generation */
68: #define TCG_REG_CALL_STACK TCG_REG_ESP
69: #define TCG_TARGET_STACK_ALIGN 16
70: #define TCG_TARGET_CALL_STACK_OFFSET 0
71:
1.1.1.2 root 72: /* optional instructions */
1.1.1.5 root 73: #define TCG_TARGET_HAS_div2_i32 1
74: #define TCG_TARGET_HAS_rot_i32 1
75: #define TCG_TARGET_HAS_ext8s_i32 1
76: #define TCG_TARGET_HAS_ext16s_i32 1
77: #define TCG_TARGET_HAS_ext8u_i32 1
78: #define TCG_TARGET_HAS_ext16u_i32 1
79: #define TCG_TARGET_HAS_bswap16_i32 1
80: #define TCG_TARGET_HAS_bswap32_i32 1
81: #define TCG_TARGET_HAS_neg_i32 1
82: #define TCG_TARGET_HAS_not_i32 1
83: #define TCG_TARGET_HAS_andc_i32 0
84: #define TCG_TARGET_HAS_orc_i32 0
85: #define TCG_TARGET_HAS_eqv_i32 0
86: #define TCG_TARGET_HAS_nand_i32 0
87: #define TCG_TARGET_HAS_nor_i32 0
88: #define TCG_TARGET_HAS_deposit_i32 1
1.1.1.4 root 89:
90: #if TCG_TARGET_REG_BITS == 64
1.1.1.5 root 91: #define TCG_TARGET_HAS_div2_i64 1
92: #define TCG_TARGET_HAS_rot_i64 1
93: #define TCG_TARGET_HAS_ext8s_i64 1
94: #define TCG_TARGET_HAS_ext16s_i64 1
95: #define TCG_TARGET_HAS_ext32s_i64 1
96: #define TCG_TARGET_HAS_ext8u_i64 1
97: #define TCG_TARGET_HAS_ext16u_i64 1
98: #define TCG_TARGET_HAS_ext32u_i64 1
99: #define TCG_TARGET_HAS_bswap16_i64 1
100: #define TCG_TARGET_HAS_bswap32_i64 1
101: #define TCG_TARGET_HAS_bswap64_i64 1
102: #define TCG_TARGET_HAS_neg_i64 1
103: #define TCG_TARGET_HAS_not_i64 1
104: #define TCG_TARGET_HAS_andc_i64 0
105: #define TCG_TARGET_HAS_orc_i64 0
106: #define TCG_TARGET_HAS_eqv_i64 0
107: #define TCG_TARGET_HAS_nand_i64 0
108: #define TCG_TARGET_HAS_nor_i64 0
109: #define TCG_TARGET_HAS_deposit_i64 1
1.1.1.4 root 110: #endif
1.1.1.3 root 111:
1.1.1.5 root 112: #define TCG_TARGET_deposit_i32_valid(ofs, len) \
113: (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
114: ((ofs) == 0 && (len) == 16))
115: #define TCG_TARGET_deposit_i64_valid TCG_TARGET_deposit_i32_valid
116:
1.1.1.3 root 117: #define TCG_TARGET_HAS_GUEST_BASE
1.1.1.2 root 118:
1.1 root 119: /* Note: must be synced with dyngen-exec.h */
1.1.1.4 root 120: #if TCG_TARGET_REG_BITS == 64
121: # define TCG_AREG0 TCG_REG_R14
122: #else
123: # define TCG_AREG0 TCG_REG_EBP
124: #endif
1.1 root 125:
1.1.1.6 ! root 126: static inline void flush_icache_range(tcg_target_ulong start,
! 127: tcg_target_ulong stop)
1.1 root 128: {
129: }
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