--- qemu/tcg/ia64/tcg-target.c 2018/04/24 18:25:19 1.1 +++ qemu/tcg/ia64/tcg-target.c 2018/04/24 19:35:50 1.1.1.5 @@ -45,6 +45,9 @@ static const char * const tcg_target_reg #else #define TCG_GUEST_BASE_REG TCG_REG_R0 #endif +#ifndef GUEST_BASE +#define GUEST_BASE 0 +#endif /* Branch registers */ enum { @@ -169,9 +172,8 @@ static const int tcg_target_call_iarg_re TCG_REG_R63, }; -static const int tcg_target_call_oarg_regs[2] = { - TCG_REG_R8, - TCG_REG_R9 +static const int tcg_target_call_oarg_regs[] = { + TCG_REG_R8 }; /* maximum number of register used for input function arguments */ @@ -828,7 +830,7 @@ static inline void tcg_out_bundle(TCGCon } static inline void tcg_out_mov(TCGContext *s, TCGType type, - TCGArg ret, TCGArg arg) + TCGReg ret, TCGReg arg) { tcg_out_bundle(s, mmI, tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), @@ -837,7 +839,7 @@ static inline void tcg_out_mov(TCGContex } static inline void tcg_out_movi(TCGContext *s, TCGType type, - TCGArg reg, tcg_target_long arg) + TCGReg reg, tcg_target_long arg) { tcg_out_bundle(s, mLX, tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), @@ -845,29 +847,13 @@ static inline void tcg_out_movi(TCGConte tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, reg, arg)); } -static inline void tcg_out_addi(TCGContext *s, TCGArg reg, tcg_target_long val) -{ - if (val == ((int32_t)val << 10) >> 10) { - tcg_out_bundle(s, MmI, - tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, - TCG_REG_R2, val, TCG_REG_R0), - tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), - tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, reg, - reg, TCG_REG_R2)); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, val); - tcg_out_bundle(s, mmI, - tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), - tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), - tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, reg, - reg, TCG_REG_R2)); - } -} - static void tcg_out_br(TCGContext *s, int label_index) { TCGLabel *l = &s->labels[label_index]; + /* We pay attention here to not modify the branch target by reading + the existing value and using it again. This ensure that caches and + memory are kept coherent during retranslation. */ tcg_out_bundle(s, mmB, tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), @@ -986,8 +972,8 @@ static inline void tcg_out_st_rel(TCGCon } } -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGArg arg, - TCGArg arg1, tcg_target_long arg2) +static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, tcg_target_long arg2) { if (type == TCG_TYPE_I32) { tcg_out_ld_rel(s, OPC_LD4_M1, arg, arg1, arg2); @@ -996,8 +982,8 @@ static inline void tcg_out_ld(TCGContext } } -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGArg arg, - TCGArg arg1, tcg_target_long arg2) +static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, tcg_target_long arg2) { if (type == TCG_TYPE_I32) { tcg_out_st_rel(s, OPC_ST4_M4, arg, arg1, arg2); @@ -1326,7 +1312,7 @@ static inline void tcg_out_bswap32(TCGCo static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg) { - tcg_out_bundle(s, mII, + tcg_out_bundle(s, miI, tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0), tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb)); @@ -1456,7 +1442,9 @@ static inline void tcg_out_qemu_tlb(TCGC tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2, TCG_REG_R2, TCG_AREG0)); tcg_out_bundle(s, mII, - tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R57, + tcg_opc_m3 (TCG_REG_P0, + (TARGET_LONG_BITS == 32 + ? OPC_LD4_M3 : OPC_LD8_M3), TCG_REG_R57, TCG_REG_R2, offset_addend - offset_rw), tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, TCG_REG_R3, TCG_REG_R3, TCG_REG_R56), @@ -1464,12 +1452,25 @@ static inline void tcg_out_qemu_tlb(TCGC TCG_REG_P7, TCG_REG_R3, TCG_REG_R57)); } +#ifdef CONFIG_TCG_PASS_AREG0 +/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, + int mmu_idx) */ +static const void * const qemu_ld_helpers[4] = { + helper_ldb_mmu, + helper_ldw_mmu, + helper_ldl_mmu, + helper_ldq_mmu, +}; +#else +/* legacy helper signature: __ld_mmu(target_ulong addr, int + mmu_idx) */ static void *qemu_ld_helpers[4] = { __ldb_mmu, __ldw_mmu, __ldl_mmu, __ldq_mmu, }; +#endif static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) { @@ -1491,8 +1492,8 @@ static inline void tcg_out_qemu_ld(TCGCo /* Read the TLB entry */ tcg_out_qemu_tlb(s, addr_reg, s_bits, - offsetof(CPUState, tlb_table[mem_index][0].addr_read), - offsetof(CPUState, tlb_table[mem_index][0].addend)); + offsetof(CPUArchState, tlb_table[mem_index][0].addr_read), + offsetof(CPUArchState, tlb_table[mem_index][0].addend)); /* P6 is the fast path, and P7 the slow path */ tcg_out_bundle(s, mLX, @@ -1529,6 +1530,15 @@ static inline void tcg_out_qemu_ld(TCGCo tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0)); } +#ifdef CONFIG_TCG_PASS_AREG0 + /* XXX/FIXME: suboptimal */ + tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], + tcg_target_call_iarg_regs[1]); + tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], + tcg_target_call_iarg_regs[0]); + tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], + TCG_AREG0); +#endif if (!bswap || s_bits == 0) { tcg_out_bundle(s, miB, tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), @@ -1559,12 +1569,25 @@ static inline void tcg_out_qemu_ld(TCGCo } } +#ifdef CONFIG_TCG_PASS_AREG0 +/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr, + uintxx_t val, int mmu_idx) */ +static const void * const qemu_st_helpers[4] = { + helper_stb_mmu, + helper_stw_mmu, + helper_stl_mmu, + helper_stq_mmu, +}; +#else +/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val, + int mmu_idx) */ static void *qemu_st_helpers[4] = { __stb_mmu, __stw_mmu, __stl_mmu, __stq_mmu, }; +#endif static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) { @@ -1582,8 +1605,8 @@ static inline void tcg_out_qemu_st(TCGCo #endif tcg_out_qemu_tlb(s, addr_reg, opc, - offsetof(CPUState, tlb_table[mem_index][0].addr_write), - offsetof(CPUState, tlb_table[mem_index][0].addend)); + offsetof(CPUArchState, tlb_table[mem_index][0].addr_write), + offsetof(CPUArchState, tlb_table[mem_index][0].addend)); /* P6 is the fast path, and P7 the slow path */ tcg_out_bundle(s, mLX, @@ -1634,6 +1657,17 @@ static inline void tcg_out_qemu_st(TCGCo data_reg = TCG_REG_R2; } +#ifdef CONFIG_TCG_PASS_AREG0 + /* XXX/FIXME: suboptimal */ + tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], + tcg_target_call_iarg_regs[2]); + tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2], + tcg_target_call_iarg_regs[1]); + tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], + tcg_target_call_iarg_regs[0]); + tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], + TCG_AREG0); +#endif tcg_out_bundle(s, miB, tcg_opc_m4 (TCG_REG_P6, opc_st_m4[opc], data_reg, TCG_REG_R3), @@ -1653,11 +1687,10 @@ static inline void tcg_out_qemu_ld(TCGCo static uint64_t const opc_sxt_i29[4] = { OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 }; - int addr_reg, data_reg, mem_index, s_bits, bswap; + int addr_reg, data_reg, s_bits, bswap; data_reg = *args++; addr_reg = *args++; - mem_index = *args; s_bits = opc & 3; #ifdef TARGET_WORDS_BIGENDIAN @@ -1813,7 +1846,7 @@ static inline void tcg_out_qemu_st(TCGCo tcg_out_bundle(s, miI, tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, - TCG_REG_R3, addr_reg), + TCG_REG_R2, addr_reg), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0)); } @@ -2121,6 +2154,7 @@ static inline void tcg_out_op(TCGContext case INDEX_op_qemu_ld16s: tcg_out_qemu_ld(s, args, 1 | 4); break; + case INDEX_op_qemu_ld32: case INDEX_op_qemu_ld32u: tcg_out_qemu_ld(s, args, 2); break; @@ -2284,7 +2318,7 @@ static void tcg_target_qemu_prologue(TCG tcg_opc_m34(TCG_REG_P0, OPC_ALLOC_M34, TCG_REG_R33, 32, 24, 0), tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, - TCG_REG_B6, TCG_REG_R32, 0), + TCG_REG_B6, TCG_REG_R33, 0), tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22, TCG_REG_R32, TCG_REG_B0)); @@ -2300,7 +2334,8 @@ static void tcg_target_qemu_prologue(TCG } tcg_out_bundle(s, miB, - tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), + tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, + TCG_AREG0, 0, TCG_REG_R32), tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R12, -frame_size, TCG_REG_R12), tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6)); @@ -2379,4 +2414,6 @@ static void tcg_target_init(TCGContext * tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6); tcg_add_target_add_op_defs(ia64_op_defs); + tcg_set_frame(s, TCG_AREG0, offsetof(CPUArchState, temp_buf), + CPU_TEMP_BUF_NLONGS * sizeof(long)); }