![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to tcg-target.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Qemu by Fabrice Bellard] / qemu / tcg / ia64|
Return to tcg-target.c CVS log | Up to [Qemu by Fabrice Bellard] / qemu / tcg / ia64 |
1.1 root 1: /*
2: * Tiny Code Generator for QEMU
3: *
4: * Copyright (c) 2009-2010 Aurelien Jarno <[email protected]>
5: * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
6: *
7: * Permission is hereby granted, free of charge, to any person obtaining a copy
8: * of this software and associated documentation files (the "Software"), to deal
9: * in the Software without restriction, including without limitation the rights
10: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11: * copies of the Software, and to permit persons to whom the Software is
12: * furnished to do so, subject to the following conditions:
13: *
14: * The above copyright notice and this permission notice shall be included in
15: * all copies or substantial portions of the Software.
16: *
17: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23: * THE SOFTWARE.
24: */
25:
26: /*
27: * Register definitions
28: */
29:
30: #ifndef NDEBUG
31: static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
32: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
33: "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
34: "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
35: "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
36: "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
37: "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
38: "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
39: "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
40: };
41: #endif
42:
43: #ifdef CONFIG_USE_GUEST_BASE
44: #define TCG_GUEST_BASE_REG TCG_REG_R55
45: #else
46: #define TCG_GUEST_BASE_REG TCG_REG_R0
47: #endif
48:
49: /* Branch registers */
50: enum {
51: TCG_REG_B0 = 0,
52: TCG_REG_B1,
53: TCG_REG_B2,
54: TCG_REG_B3,
55: TCG_REG_B4,
56: TCG_REG_B5,
57: TCG_REG_B6,
58: TCG_REG_B7,
59: };
60:
61: /* Floating point registers */
62: enum {
63: TCG_REG_F0 = 0,
64: TCG_REG_F1,
65: TCG_REG_F2,
66: TCG_REG_F3,
67: TCG_REG_F4,
68: TCG_REG_F5,
69: TCG_REG_F6,
70: TCG_REG_F7,
71: TCG_REG_F8,
72: TCG_REG_F9,
73: TCG_REG_F10,
74: TCG_REG_F11,
75: TCG_REG_F12,
76: TCG_REG_F13,
77: TCG_REG_F14,
78: TCG_REG_F15,
79: };
80:
81: /* Predicate registers */
82: enum {
83: TCG_REG_P0 = 0,
84: TCG_REG_P1,
85: TCG_REG_P2,
86: TCG_REG_P3,
87: TCG_REG_P4,
88: TCG_REG_P5,
89: TCG_REG_P6,
90: TCG_REG_P7,
91: TCG_REG_P8,
92: TCG_REG_P9,
93: TCG_REG_P10,
94: TCG_REG_P11,
95: TCG_REG_P12,
96: TCG_REG_P13,
97: TCG_REG_P14,
98: TCG_REG_P15,
99: };
100:
101: /* Application registers */
102: enum {
103: TCG_REG_PFS = 64,
104: };
105:
106: static const int tcg_target_reg_alloc_order[] = {
107: TCG_REG_R34,
108: TCG_REG_R35,
109: TCG_REG_R36,
110: TCG_REG_R37,
111: TCG_REG_R38,
112: TCG_REG_R39,
113: TCG_REG_R40,
114: TCG_REG_R41,
115: TCG_REG_R42,
116: TCG_REG_R43,
117: TCG_REG_R44,
118: TCG_REG_R45,
119: TCG_REG_R46,
120: TCG_REG_R47,
121: TCG_REG_R48,
122: TCG_REG_R49,
123: TCG_REG_R50,
124: TCG_REG_R51,
125: TCG_REG_R52,
126: TCG_REG_R53,
127: TCG_REG_R54,
128: TCG_REG_R55,
129: TCG_REG_R14,
130: TCG_REG_R15,
131: TCG_REG_R16,
132: TCG_REG_R17,
133: TCG_REG_R18,
134: TCG_REG_R19,
135: TCG_REG_R20,
136: TCG_REG_R21,
137: TCG_REG_R22,
138: TCG_REG_R23,
139: TCG_REG_R24,
140: TCG_REG_R25,
141: TCG_REG_R26,
142: TCG_REG_R27,
143: TCG_REG_R28,
144: TCG_REG_R29,
145: TCG_REG_R30,
146: TCG_REG_R31,
147: TCG_REG_R56,
148: TCG_REG_R57,
149: TCG_REG_R58,
150: TCG_REG_R59,
151: TCG_REG_R60,
152: TCG_REG_R61,
153: TCG_REG_R62,
154: TCG_REG_R63,
155: TCG_REG_R8,
156: TCG_REG_R9,
157: TCG_REG_R10,
158: TCG_REG_R11
159: };
160:
161: static const int tcg_target_call_iarg_regs[8] = {
162: TCG_REG_R56,
163: TCG_REG_R57,
164: TCG_REG_R58,
165: TCG_REG_R59,
166: TCG_REG_R60,
167: TCG_REG_R61,
168: TCG_REG_R62,
169: TCG_REG_R63,
170: };
171:
172: static const int tcg_target_call_oarg_regs[2] = {
173: TCG_REG_R8,
174: TCG_REG_R9
175: };
176:
177: /* maximum number of register used for input function arguments */
178: static inline int tcg_target_get_call_iarg_regs_count(int flags)
179: {
180: return 8;
181: }
182:
183: /*
184: * opcode formation
185: */
186:
187: /* bundle templates: stops (double bar in the IA64 manual) are marked with
188: an uppercase letter. */
189: enum {
190: mii = 0x00,
191: miI = 0x01,
192: mIi = 0x02,
193: mII = 0x03,
194: mlx = 0x04,
195: mLX = 0x05,
196: mmi = 0x08,
197: mmI = 0x09,
198: Mmi = 0x0a,
199: MmI = 0x0b,
200: mfi = 0x0c,
201: mfI = 0x0d,
202: mmf = 0x0e,
203: mmF = 0x0f,
204: mib = 0x10,
205: miB = 0x11,
206: mbb = 0x12,
207: mbB = 0x13,
208: bbb = 0x16,
209: bbB = 0x17,
210: mmb = 0x18,
211: mmB = 0x19,
212: mfb = 0x1c,
213: mfB = 0x1d,
214: };
215:
216: enum {
217: OPC_ADD_A1 = 0x10000000000ull,
218: OPC_AND_A1 = 0x10060000000ull,
219: OPC_AND_A3 = 0x10160000000ull,
220: OPC_ANDCM_A1 = 0x10068000000ull,
221: OPC_ANDCM_A3 = 0x10168000000ull,
222: OPC_ADDS_A4 = 0x10800000000ull,
223: OPC_ADDL_A5 = 0x12000000000ull,
224: OPC_ALLOC_M34 = 0x02c00000000ull,
225: OPC_BR_DPTK_FEW_B1 = 0x08400000000ull,
226: OPC_BR_SPTK_MANY_B1 = 0x08000001000ull,
227: OPC_BR_SPTK_MANY_B4 = 0x00100001000ull,
228: OPC_BR_CALL_SPTK_MANY_B5 = 0x02100001000ull,
229: OPC_BR_RET_SPTK_MANY_B4 = 0x00108001100ull,
230: OPC_BRL_SPTK_MANY_X3 = 0x18000001000ull,
231: OPC_CMP_LT_A6 = 0x18000000000ull,
232: OPC_CMP_LTU_A6 = 0x1a000000000ull,
233: OPC_CMP_EQ_A6 = 0x1c000000000ull,
234: OPC_CMP4_LT_A6 = 0x18400000000ull,
235: OPC_CMP4_LTU_A6 = 0x1a400000000ull,
236: OPC_CMP4_EQ_A6 = 0x1c400000000ull,
237: OPC_DEP_Z_I12 = 0x0a600000000ull,
238: OPC_EXTR_I11 = 0x0a400002000ull,
239: OPC_EXTR_U_I11 = 0x0a400000000ull,
240: OPC_FCVT_FX_TRUNC_S1_F10 = 0x004d0000000ull,
241: OPC_FCVT_FXU_TRUNC_S1_F10 = 0x004d8000000ull,
242: OPC_FCVT_XF_F11 = 0x000e0000000ull,
243: OPC_FMA_S1_F1 = 0x10400000000ull,
244: OPC_FNMA_S1_F1 = 0x18400000000ull,
245: OPC_FRCPA_S1_F6 = 0x00600000000ull,
246: OPC_GETF_SIG_M19 = 0x08708000000ull,
247: OPC_LD1_M1 = 0x08000000000ull,
248: OPC_LD1_M3 = 0x0a000000000ull,
249: OPC_LD2_M1 = 0x08040000000ull,
250: OPC_LD2_M3 = 0x0a040000000ull,
251: OPC_LD4_M1 = 0x08080000000ull,
252: OPC_LD4_M3 = 0x0a080000000ull,
253: OPC_LD8_M1 = 0x080c0000000ull,
254: OPC_LD8_M3 = 0x0a0c0000000ull,
255: OPC_MUX1_I3 = 0x0eca0000000ull,
256: OPC_NOP_B9 = 0x04008000000ull,
257: OPC_NOP_F16 = 0x00008000000ull,
258: OPC_NOP_I18 = 0x00008000000ull,
259: OPC_NOP_M48 = 0x00008000000ull,
260: OPC_MOV_I21 = 0x00e00100000ull,
261: OPC_MOV_RET_I21 = 0x00e00500000ull,
262: OPC_MOV_I22 = 0x00188000000ull,
263: OPC_MOV_I_I26 = 0x00150000000ull,
264: OPC_MOVL_X2 = 0x0c000000000ull,
265: OPC_OR_A1 = 0x10070000000ull,
266: OPC_SETF_EXP_M18 = 0x0c748000000ull,
267: OPC_SETF_SIG_M18 = 0x0c708000000ull,
268: OPC_SHL_I7 = 0x0f240000000ull,
269: OPC_SHR_I5 = 0x0f220000000ull,
270: OPC_SHR_U_I5 = 0x0f200000000ull,
271: OPC_SHRP_I10 = 0x0ac00000000ull,
272: OPC_SXT1_I29 = 0x000a0000000ull,
273: OPC_SXT2_I29 = 0x000a8000000ull,
274: OPC_SXT4_I29 = 0x000b0000000ull,
275: OPC_ST1_M4 = 0x08c00000000ull,
276: OPC_ST2_M4 = 0x08c40000000ull,
277: OPC_ST4_M4 = 0x08c80000000ull,
278: OPC_ST8_M4 = 0x08cc0000000ull,
279: OPC_SUB_A1 = 0x10028000000ull,
280: OPC_SUB_A3 = 0x10128000000ull,
281: OPC_UNPACK4_L_I2 = 0x0f860000000ull,
282: OPC_XMA_L_F2 = 0x1d000000000ull,
283: OPC_XOR_A1 = 0x10078000000ull,
284: OPC_ZXT1_I29 = 0x00080000000ull,
285: OPC_ZXT2_I29 = 0x00088000000ull,
286: OPC_ZXT4_I29 = 0x00090000000ull,
287: };
288:
289: static inline uint64_t tcg_opc_a1(int qp, uint64_t opc, int r1,
290: int r2, int r3)
291: {
292: return opc
293: | ((r3 & 0x7f) << 20)
294: | ((r2 & 0x7f) << 13)
295: | ((r1 & 0x7f) << 6)
296: | (qp & 0x3f);
297: }
298:
299: static inline uint64_t tcg_opc_a3(int qp, uint64_t opc, int r1,
300: uint64_t imm, int r3)
301: {
302: return opc
303: | ((imm & 0x80) << 29) /* s */
304: | ((imm & 0x7f) << 13) /* imm7b */
305: | ((r3 & 0x7f) << 20)
306: | ((r1 & 0x7f) << 6)
307: | (qp & 0x3f);
308: }
309:
310: static inline uint64_t tcg_opc_a4(int qp, uint64_t opc, int r1,
311: uint64_t imm, int r3)
312: {
313: return opc
314: | ((imm & 0x2000) << 23) /* s */
315: | ((imm & 0x1f80) << 20) /* imm6d */
316: | ((imm & 0x007f) << 13) /* imm7b */
317: | ((r3 & 0x7f) << 20)
318: | ((r1 & 0x7f) << 6)
319: | (qp & 0x3f);
320: }
321:
322: static inline uint64_t tcg_opc_a5(int qp, uint64_t opc, int r1,
323: uint64_t imm, int r3)
324: {
325: return opc
326: | ((imm & 0x200000) << 15) /* s */
327: | ((imm & 0x1f0000) << 6) /* imm5c */
328: | ((imm & 0x00ff80) << 20) /* imm9d */
329: | ((imm & 0x00007f) << 13) /* imm7b */
330: | ((r3 & 0x03) << 20)
331: | ((r1 & 0x7f) << 6)
332: | (qp & 0x3f);
333: }
334:
335: static inline uint64_t tcg_opc_a6(int qp, uint64_t opc, int p1,
336: int p2, int r2, int r3)
337: {
338: return opc
339: | ((p2 & 0x3f) << 27)
340: | ((r3 & 0x7f) << 20)
341: | ((r2 & 0x7f) << 13)
342: | ((p1 & 0x3f) << 6)
343: | (qp & 0x3f);
344: }
345:
346: static inline uint64_t tcg_opc_b1(int qp, uint64_t opc, uint64_t imm)
347: {
348: return opc
349: | ((imm & 0x100000) << 16) /* s */
350: | ((imm & 0x0fffff) << 13) /* imm20b */
351: | (qp & 0x3f);
352: }
353:
354: static inline uint64_t tcg_opc_b4(int qp, uint64_t opc, int b2)
355: {
356: return opc
357: | ((b2 & 0x7) << 13)
358: | (qp & 0x3f);
359: }
360:
361: static inline uint64_t tcg_opc_b5(int qp, uint64_t opc, int b1, int b2)
362: {
363: return opc
364: | ((b2 & 0x7) << 13)
365: | ((b1 & 0x7) << 6)
366: | (qp & 0x3f);
367: }
368:
369:
370: static inline uint64_t tcg_opc_b9(int qp, uint64_t opc, uint64_t imm)
371: {
372: return opc
373: | ((imm & 0x100000) << 16) /* i */
374: | ((imm & 0x0fffff) << 6) /* imm20a */
375: | (qp & 0x3f);
376: }
377:
378: static inline uint64_t tcg_opc_f1(int qp, uint64_t opc, int f1,
379: int f3, int f4, int f2)
380: {
381: return opc
382: | ((f4 & 0x7f) << 27)
383: | ((f3 & 0x7f) << 20)
384: | ((f2 & 0x7f) << 13)
385: | ((f1 & 0x7f) << 6)
386: | (qp & 0x3f);
387: }
388:
389: static inline uint64_t tcg_opc_f2(int qp, uint64_t opc, int f1,
390: int f3, int f4, int f2)
391: {
392: return opc
393: | ((f4 & 0x7f) << 27)
394: | ((f3 & 0x7f) << 20)
395: | ((f2 & 0x7f) << 13)
396: | ((f1 & 0x7f) << 6)
397: | (qp & 0x3f);
398: }
399:
400: static inline uint64_t tcg_opc_f6(int qp, uint64_t opc, int f1,
401: int p2, int f2, int f3)
402: {
403: return opc
404: | ((p2 & 0x3f) << 27)
405: | ((f3 & 0x7f) << 20)
406: | ((f2 & 0x7f) << 13)
407: | ((f1 & 0x7f) << 6)
408: | (qp & 0x3f);
409: }
410:
411: static inline uint64_t tcg_opc_f10(int qp, uint64_t opc, int f1, int f2)
412: {
413: return opc
414: | ((f2 & 0x7f) << 13)
415: | ((f1 & 0x7f) << 6)
416: | (qp & 0x3f);
417: }
418:
419: static inline uint64_t tcg_opc_f11(int qp, uint64_t opc, int f1, int f2)
420: {
421: return opc
422: | ((f2 & 0x7f) << 13)
423: | ((f1 & 0x7f) << 6)
424: | (qp & 0x3f);
425: }
426:
427: static inline uint64_t tcg_opc_f16(int qp, uint64_t opc, uint64_t imm)
428: {
429: return opc
430: | ((imm & 0x100000) << 16) /* i */
431: | ((imm & 0x0fffff) << 6) /* imm20a */
432: | (qp & 0x3f);
433: }
434:
435: static inline uint64_t tcg_opc_i2(int qp, uint64_t opc, int r1,
436: int r2, int r3)
437: {
438: return opc
439: | ((r3 & 0x7f) << 20)
440: | ((r2 & 0x7f) << 13)
441: | ((r1 & 0x7f) << 6)
442: | (qp & 0x3f);
443: }
444:
445: static inline uint64_t tcg_opc_i3(int qp, uint64_t opc, int r1,
446: int r2, int mbtype)
447: {
448: return opc
449: | ((mbtype & 0x0f) << 20)
450: | ((r2 & 0x7f) << 13)
451: | ((r1 & 0x7f) << 6)
452: | (qp & 0x3f);
453: }
454:
455: static inline uint64_t tcg_opc_i5(int qp, uint64_t opc, int r1,
456: int r3, int r2)
457: {
458: return opc
459: | ((r3 & 0x7f) << 20)
460: | ((r2 & 0x7f) << 13)
461: | ((r1 & 0x7f) << 6)
462: | (qp & 0x3f);
463: }
464:
465: static inline uint64_t tcg_opc_i7(int qp, uint64_t opc, int r1,
466: int r2, int r3)
467: {
468: return opc
469: | ((r3 & 0x7f) << 20)
470: | ((r2 & 0x7f) << 13)
471: | ((r1 & 0x7f) << 6)
472: | (qp & 0x3f);
473: }
474:
475: static inline uint64_t tcg_opc_i10(int qp, uint64_t opc, int r1,
476: int r2, int r3, uint64_t count)
477: {
478: return opc
479: | ((count & 0x3f) << 27)
480: | ((r3 & 0x7f) << 20)
481: | ((r2 & 0x7f) << 13)
482: | ((r1 & 0x7f) << 6)
483: | (qp & 0x3f);
484: }
485:
486: static inline uint64_t tcg_opc_i11(int qp, uint64_t opc, int r1,
487: int r3, uint64_t pos, uint64_t len)
488: {
489: return opc
490: | ((len & 0x3f) << 27)
491: | ((r3 & 0x7f) << 20)
492: | ((pos & 0x3f) << 14)
493: | ((r1 & 0x7f) << 6)
494: | (qp & 0x3f);
495: }
496:
497: static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1,
498: int r2, uint64_t pos, uint64_t len)
499: {
500: return opc
501: | ((len & 0x3f) << 27)
502: | ((pos & 0x3f) << 20)
503: | ((r2 & 0x7f) << 13)
504: | ((r1 & 0x7f) << 6)
505: | (qp & 0x3f);
506: }
507:
508: static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm)
509: {
510: return opc
511: | ((imm & 0x100000) << 16) /* i */
512: | ((imm & 0x0fffff) << 6) /* imm20a */
513: | (qp & 0x3f);
514: }
515:
516: static inline uint64_t tcg_opc_i21(int qp, uint64_t opc, int b1,
517: int r2, uint64_t imm)
518: {
519: return opc
520: | ((imm & 0x1ff) << 24)
521: | ((r2 & 0x7f) << 13)
522: | ((b1 & 0x7) << 6)
523: | (qp & 0x3f);
524: }
525:
526: static inline uint64_t tcg_opc_i22(int qp, uint64_t opc, int r1, int b2)
527: {
528: return opc
529: | ((b2 & 0x7) << 13)
530: | ((r1 & 0x7f) << 6)
531: | (qp & 0x3f);
532: }
533:
534: static inline uint64_t tcg_opc_i26(int qp, uint64_t opc, int ar3, int r2)
535: {
536: return opc
537: | ((ar3 & 0x7f) << 20)
538: | ((r2 & 0x7f) << 13)
539: | (qp & 0x3f);
540: }
541:
542: static inline uint64_t tcg_opc_i29(int qp, uint64_t opc, int r1, int r3)
543: {
544: return opc
545: | ((r3 & 0x7f) << 20)
546: | ((r1 & 0x7f) << 6)
547: | (qp & 0x3f);
548: }
549:
550: static inline uint64_t tcg_opc_l2(uint64_t imm)
551: {
552: return (imm & 0x7fffffffffc00000ull) >> 22;
553: }
554:
555: static inline uint64_t tcg_opc_l3(uint64_t imm)
556: {
557: return (imm & 0x07fffffffff00000ull) >> 18;
558: }
559:
560: static inline uint64_t tcg_opc_m1(int qp, uint64_t opc, int r1, int r3)
561: {
562: return opc
563: | ((r3 & 0x7f) << 20)
564: | ((r1 & 0x7f) << 6)
565: | (qp & 0x3f);
566: }
567:
568: static inline uint64_t tcg_opc_m3(int qp, uint64_t opc, int r1,
569: int r3, uint64_t imm)
570: {
571: return opc
572: | ((imm & 0x100) << 28) /* s */
573: | ((imm & 0x080) << 20) /* i */
574: | ((imm & 0x07f) << 13) /* imm7b */
575: | ((r3 & 0x7f) << 20)
576: | ((r1 & 0x7f) << 6)
577: | (qp & 0x3f);
578: }
579:
580: static inline uint64_t tcg_opc_m4(int qp, uint64_t opc, int r2, int r3)
581: {
582: return opc
583: | ((r3 & 0x7f) << 20)
584: | ((r2 & 0x7f) << 13)
585: | (qp & 0x3f);
586: }
587:
588: static inline uint64_t tcg_opc_m18(int qp, uint64_t opc, int f1, int r2)
589: {
590: return opc
591: | ((r2 & 0x7f) << 13)
592: | ((f1 & 0x7f) << 6)
593: | (qp & 0x3f);
594: }
595:
596: static inline uint64_t tcg_opc_m19(int qp, uint64_t opc, int r1, int f2)
597: {
598: return opc
599: | ((f2 & 0x7f) << 13)
600: | ((r1 & 0x7f) << 6)
601: | (qp & 0x3f);
602: }
603:
604: static inline uint64_t tcg_opc_m34(int qp, uint64_t opc, int r1,
605: int sof, int sol, int sor)
606: {
607: return opc
608: | ((sor & 0x0f) << 27)
609: | ((sol & 0x7f) << 20)
610: | ((sof & 0x7f) << 13)
611: | ((r1 & 0x7f) << 6)
612: | (qp & 0x3f);
613: }
614:
615: static inline uint64_t tcg_opc_m48(int qp, uint64_t opc, uint64_t imm)
616: {
617: return opc
618: | ((imm & 0x100000) << 16) /* i */
619: | ((imm & 0x0fffff) << 6) /* imm20a */
620: | (qp & 0x3f);
621: }
622:
623: static inline uint64_t tcg_opc_x2(int qp, uint64_t opc,
624: int r1, uint64_t imm)
625: {
626: return opc
627: | ((imm & 0x8000000000000000ull) >> 27) /* i */
628: | (imm & 0x0000000000200000ull) /* ic */
629: | ((imm & 0x00000000001f0000ull) << 6) /* imm5c */
630: | ((imm & 0x000000000000ff80ull) << 20) /* imm9d */
631: | ((imm & 0x000000000000007full) << 13) /* imm7b */
632: | ((r1 & 0x7f) << 6)
633: | (qp & 0x3f);
634: }
635:
636: static inline uint64_t tcg_opc_x3(int qp, uint64_t opc, uint64_t imm)
637: {
638: return opc
639: | ((imm & 0x0800000000000000ull) >> 23) /* i */
640: | ((imm & 0x00000000000fffffull) << 13) /* imm20b */
641: | (qp & 0x3f);
642: }
643:
644:
645: /*
646: * Relocations
647: */
648:
649: static inline void reloc_pcrel21b (void *pc, tcg_target_long target)
650: {
651: uint64_t imm;
652: int64_t disp;
653: int slot;
654:
655: slot = (tcg_target_long) pc & 3;
656: pc = (void *)((tcg_target_long) pc & ~3);
657:
658: disp = target - (tcg_target_long) pc;
659: imm = (uint64_t) disp >> 4;
660:
661: switch(slot) {
662: case 0:
663: *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 8) & 0xfffffdc00003ffffull)
664: | ((imm & 0x100000) << 21) /* s */
665: | ((imm & 0x0fffff) << 18); /* imm20b */
666: break;
667: case 1:
668: *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xfffffffffffb8000ull)
669: | ((imm & 0x100000) >> 2) /* s */
670: | ((imm & 0x0fffe0) >> 5); /* imm20b */
671: *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x07ffffffffffffffull)
672: | ((imm & 0x00001f) << 59); /* imm20b */
673: break;
674: case 2:
675: *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fffffffffull)
676: | ((imm & 0x100000) << 39) /* s */
677: | ((imm & 0x0fffff) << 36); /* imm20b */
678: break;
679: }
680: }
681:
682: static inline uint64_t get_reloc_pcrel21b (void *pc)
683: {
684: int64_t low, high;
685: int slot;
686:
687: slot = (tcg_target_long) pc & 3;
688: pc = (void *)((tcg_target_long) pc & ~3);
689:
690: low = (*(uint64_t *)(pc + 0));
691: high = (*(uint64_t *)(pc + 8));
692:
693: switch(slot) {
694: case 0:
695: return ((low >> 21) & 0x100000) + /* s */
696: ((low >> 18) & 0x0fffff); /* imm20b */
697: case 1:
698: return ((high << 2) & 0x100000) + /* s */
699: ((high << 5) & 0x0fffe0) + /* imm20b */
700: ((low >> 59) & 0x00001f); /* imm20b */
701: case 2:
702: return ((high >> 39) & 0x100000) + /* s */
703: ((high >> 36) & 0x0fffff); /* imm20b */
704: default:
705: tcg_abort();
706: }
707: }
708:
709: static inline void reloc_pcrel60b (void *pc, tcg_target_long target)
710: {
711: int64_t disp;
712: uint64_t imm;
713:
714: disp = target - (tcg_target_long) pc;
715: imm = (uint64_t) disp >> 4;
716:
717: *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fff800000ull)
718: | (imm & 0x0800000000000000ull) /* s */
719: | ((imm & 0x07fffff000000000ull) >> 36) /* imm39 */
720: | ((imm & 0x00000000000fffffull) << 36); /* imm20b */
721: *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x00003fffffffffffull)
722: | ((imm & 0x0000000ffff00000ull) << 28); /* imm39 */
723: }
724:
725: static inline uint64_t get_reloc_pcrel60b (void *pc)
726: {
727: int64_t low, high;
728:
729: low = (*(uint64_t *)(pc + 0));
730: high = (*(uint64_t *)(pc + 8));
731:
732: return ((high) & 0x0800000000000000ull) + /* s */
733: ((high >> 36) & 0x00000000000fffffull) + /* imm20b */
734: ((high << 36) & 0x07fffff000000000ull) + /* imm39 */
735: ((low >> 28) & 0x0000000ffff00000ull); /* imm39 */
736: }
737:
738:
739: static void patch_reloc(uint8_t *code_ptr, int type,
740: tcg_target_long value, tcg_target_long addend)
741: {
742: value += addend;
743: switch (type) {
744: case R_IA64_PCREL21B:
745: reloc_pcrel21b(code_ptr, value);
746: break;
747: case R_IA64_PCREL60B:
748: reloc_pcrel60b(code_ptr, value);
749: default:
750: tcg_abort();
751: }
752: }
753:
754: /*
755: * Constraints
756: */
757:
758: /* parse target specific constraints */
759: static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
760: {
761: const char *ct_str;
762:
763: ct_str = *pct_str;
764: switch(ct_str[0]) {
765: case 'r':
766: ct->ct |= TCG_CT_REG;
767: tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
768: break;
769: case 'I':
770: ct->ct |= TCG_CT_CONST_S22;
771: break;
772: case 'S':
773: ct->ct |= TCG_CT_REG;
774: tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
775: #if defined(CONFIG_SOFTMMU)
776: tcg_regset_reset_reg(ct->u.regs, TCG_REG_R56);
777: tcg_regset_reset_reg(ct->u.regs, TCG_REG_R57);
778: #endif
779: break;
780: case 'Z':
781: /* We are cheating a bit here, using the fact that the register
782: r0 is also the register number 0. Hence there is no need
783: to check for const_args in each instruction. */
784: ct->ct |= TCG_CT_CONST_ZERO;
785: break;
786: default:
787: return -1;
788: }
789: ct_str++;
790: *pct_str = ct_str;
791: return 0;
792: }
793:
794: /* test if a constant matches the constraint */
795: static inline int tcg_target_const_match(tcg_target_long val,
796: const TCGArgConstraint *arg_ct)
797: {
798: int ct;
799: ct = arg_ct->ct;
800: if (ct & TCG_CT_CONST)
801: return 1;
802: else if ((ct & TCG_CT_CONST_ZERO) && val == 0)
803: return 1;
804: else if ((ct & TCG_CT_CONST_S22) && val == ((int32_t)val << 10) >> 10)
805: return 1;
806: else
807: return 0;
808: }
809:
810: /*
811: * Code generation
812: */
813:
814: static uint8_t *tb_ret_addr;
815:
816: static inline void tcg_out_bundle(TCGContext *s, int template,
817: uint64_t slot0, uint64_t slot1,
818: uint64_t slot2)
819: {
820: template &= 0x1f; /* 5 bits */
821: slot0 &= 0x1ffffffffffull; /* 41 bits */
822: slot1 &= 0x1ffffffffffull; /* 41 bits */
823: slot2 &= 0x1ffffffffffull; /* 41 bits */
824:
825: *(uint64_t *)(s->code_ptr + 0) = (slot1 << 46) | (slot0 << 5) | template;
826: *(uint64_t *)(s->code_ptr + 8) = (slot2 << 23) | (slot1 >> 18);
827: s->code_ptr += 16;
828: }
829:
830: static inline void tcg_out_mov(TCGContext *s, TCGType type,
831: TCGArg ret, TCGArg arg)
832: {
833: tcg_out_bundle(s, mmI,
834: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
835: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
836: tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, 0, arg));
837: }
838:
839: static inline void tcg_out_movi(TCGContext *s, TCGType type,
840: TCGArg reg, tcg_target_long arg)
841: {
842: tcg_out_bundle(s, mLX,
843: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
844: tcg_opc_l2 (arg),
845: tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, reg, arg));
846: }
847:
848: static inline void tcg_out_addi(TCGContext *s, TCGArg reg, tcg_target_long val)
849: {
850: if (val == ((int32_t)val << 10) >> 10) {
851: tcg_out_bundle(s, MmI,
852: tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
853: TCG_REG_R2, val, TCG_REG_R0),
854: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
855: tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, reg,
856: reg, TCG_REG_R2));
857: } else {
858: tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, val);
859: tcg_out_bundle(s, mmI,
860: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
861: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
862: tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, reg,
863: reg, TCG_REG_R2));
864: }
865: }
866:
867: static void tcg_out_br(TCGContext *s, int label_index)
868: {
869: TCGLabel *l = &s->labels[label_index];
870:
871: tcg_out_bundle(s, mmB,
872: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
873: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
874: tcg_opc_b1 (TCG_REG_P0, OPC_BR_SPTK_MANY_B1,
875: get_reloc_pcrel21b(s->code_ptr + 2)));
876:
877: if (l->has_value) {
878: reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
879: } else {
880: tcg_out_reloc(s, (s->code_ptr - 16) + 2,
881: R_IA64_PCREL21B, label_index, 0);
882: }
883: }
884:
885: static inline void tcg_out_call(TCGContext *s, TCGArg addr)
886: {
887: tcg_out_bundle(s, MmI,
888: tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, addr),
889: tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R3, 8, addr),
890: tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
891: TCG_REG_B6, TCG_REG_R2, 0));
892: tcg_out_bundle(s, mmB,
893: tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R3),
894: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
895: tcg_opc_b5 (TCG_REG_P0, OPC_BR_CALL_SPTK_MANY_B5,
896: TCG_REG_B0, TCG_REG_B6));
897: }
898:
899: static void tcg_out_exit_tb(TCGContext *s, tcg_target_long arg)
900: {
901: int64_t disp;
902: uint64_t imm;
903:
904: tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R8, arg);
905:
906: disp = tb_ret_addr - s->code_ptr;
907: imm = (uint64_t)disp >> 4;
908:
909: tcg_out_bundle(s, mLX,
910: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
911: tcg_opc_l3 (imm),
912: tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, imm));
913: }
914:
915: static inline void tcg_out_goto_tb(TCGContext *s, TCGArg arg)
916: {
917: if (s->tb_jmp_offset) {
918: /* direct jump method */
919: tcg_abort();
920: } else {
921: /* indirect jump method */
922: tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2,
923: (tcg_target_long)(s->tb_next + arg));
924: tcg_out_bundle(s, MmI,
925: tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1,
926: TCG_REG_R2, TCG_REG_R2),
927: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
928: tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6,
929: TCG_REG_R2, 0));
930: tcg_out_bundle(s, mmB,
931: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
932: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
933: tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4,
934: TCG_REG_B6));
935: }
936: s->tb_next_offset[arg] = s->code_ptr - s->code_buf;
937: }
938:
939: static inline void tcg_out_jmp(TCGContext *s, TCGArg addr)
940: {
941: tcg_out_bundle(s, mmI,
942: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
943: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
944: tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, addr, 0));
945: tcg_out_bundle(s, mmB,
946: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
947: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
948: tcg_opc_b4(TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
949: }
950:
951: static inline void tcg_out_ld_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
952: TCGArg arg1, tcg_target_long arg2)
953: {
954: if (arg2 == ((int16_t)arg2 >> 2) << 2) {
955: tcg_out_bundle(s, MmI,
956: tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
957: TCG_REG_R2, arg2, arg1),
958: tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
959: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
960: } else {
961: tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
962: tcg_out_bundle(s, MmI,
963: tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
964: TCG_REG_R2, TCG_REG_R2, arg1),
965: tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
966: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
967: }
968: }
969:
970: static inline void tcg_out_st_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
971: TCGArg arg1, tcg_target_long arg2)
972: {
973: if (arg2 == ((int16_t)arg2 >> 2) << 2) {
974: tcg_out_bundle(s, MmI,
975: tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
976: TCG_REG_R2, arg2, arg1),
977: tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
978: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
979: } else {
980: tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
981: tcg_out_bundle(s, MmI,
982: tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
983: TCG_REG_R2, TCG_REG_R2, arg1),
984: tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
985: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
986: }
987: }
988:
989: static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGArg arg,
990: TCGArg arg1, tcg_target_long arg2)
991: {
992: if (type == TCG_TYPE_I32) {
993: tcg_out_ld_rel(s, OPC_LD4_M1, arg, arg1, arg2);
994: } else {
995: tcg_out_ld_rel(s, OPC_LD8_M1, arg, arg1, arg2);
996: }
997: }
998:
999: static inline void tcg_out_st(TCGContext *s, TCGType type, TCGArg arg,
1000: TCGArg arg1, tcg_target_long arg2)
1001: {
1002: if (type == TCG_TYPE_I32) {
1003: tcg_out_st_rel(s, OPC_ST4_M4, arg, arg1, arg2);
1004: } else {
1005: tcg_out_st_rel(s, OPC_ST8_M4, arg, arg1, arg2);
1006: }
1007: }
1008:
1009: static inline void tcg_out_alu(TCGContext *s, uint64_t opc_a1, TCGArg ret,
1010: TCGArg arg1, int const_arg1,
1011: TCGArg arg2, int const_arg2)
1012: {
1013: uint64_t opc1, opc2;
1014:
1015: if (const_arg1 && arg1 != 0) {
1016: opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1017: TCG_REG_R2, arg1, TCG_REG_R0);
1018: arg1 = TCG_REG_R2;
1019: } else {
1020: opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1021: }
1022:
1023: if (const_arg2 && arg2 != 0) {
1024: opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1025: TCG_REG_R3, arg2, TCG_REG_R0);
1026: arg2 = TCG_REG_R3;
1027: } else {
1028: opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
1029: }
1030:
1031: tcg_out_bundle(s, mII,
1032: opc1,
1033: opc2,
1034: tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2));
1035: }
1036:
1037: static inline void tcg_out_eqv(TCGContext *s, TCGArg ret,
1038: TCGArg arg1, int const_arg1,
1039: TCGArg arg2, int const_arg2)
1040: {
1041: tcg_out_bundle(s, mII,
1042: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1043: tcg_opc_a1 (TCG_REG_P0, OPC_XOR_A1, ret, arg1, arg2),
1044: tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1045: }
1046:
1047: static inline void tcg_out_nand(TCGContext *s, TCGArg ret,
1048: TCGArg arg1, int const_arg1,
1049: TCGArg arg2, int const_arg2)
1050: {
1051: tcg_out_bundle(s, mII,
1052: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1053: tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, ret, arg1, arg2),
1054: tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1055: }
1056:
1057: static inline void tcg_out_nor(TCGContext *s, TCGArg ret,
1058: TCGArg arg1, int const_arg1,
1059: TCGArg arg2, int const_arg2)
1060: {
1061: tcg_out_bundle(s, mII,
1062: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1063: tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, arg2),
1064: tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1065: }
1066:
1067: static inline void tcg_out_orc(TCGContext *s, TCGArg ret,
1068: TCGArg arg1, int const_arg1,
1069: TCGArg arg2, int const_arg2)
1070: {
1071: tcg_out_bundle(s, mII,
1072: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1073: tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, TCG_REG_R2, -1, arg2),
1074: tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, TCG_REG_R2));
1075: }
1076:
1077: static inline void tcg_out_mul(TCGContext *s, TCGArg ret,
1078: TCGArg arg1, TCGArg arg2)
1079: {
1080: tcg_out_bundle(s, mmI,
1081: tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F6, arg1),
1082: tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F7, arg2),
1083: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1084: tcg_out_bundle(s, mmF,
1085: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1086: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1087: tcg_opc_f2 (TCG_REG_P0, OPC_XMA_L_F2, TCG_REG_F6, TCG_REG_F6,
1088: TCG_REG_F7, TCG_REG_F0));
1089: tcg_out_bundle(s, miI,
1090: tcg_opc_m19(TCG_REG_P0, OPC_GETF_SIG_M19, ret, TCG_REG_F6),
1091: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1092: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1093: }
1094:
1095: static inline void tcg_out_sar_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1096: TCGArg arg2, int const_arg2)
1097: {
1098: if (const_arg2) {
1099: tcg_out_bundle(s, miI,
1100: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1101: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1102: tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1103: ret, arg1, arg2, 31 - arg2));
1104: } else {
1105: tcg_out_bundle(s, mII,
1106: tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3,
1107: TCG_REG_R3, 0x1f, arg2),
1108: tcg_opc_i29(TCG_REG_P0, OPC_SXT4_I29, TCG_REG_R2, arg1),
1109: tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret,
1110: TCG_REG_R2, TCG_REG_R3));
1111: }
1112: }
1113:
1114: static inline void tcg_out_sar_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1115: TCGArg arg2, int const_arg2)
1116: {
1117: if (const_arg2) {
1118: tcg_out_bundle(s, miI,
1119: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1120: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1121: tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1122: ret, arg1, arg2, 63 - arg2));
1123: } else {
1124: tcg_out_bundle(s, miI,
1125: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1126: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1127: tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, arg1, arg2));
1128: }
1129: }
1130:
1131: static inline void tcg_out_shl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1132: TCGArg arg2, int const_arg2)
1133: {
1134: if (const_arg2) {
1135: tcg_out_bundle(s, miI,
1136: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1137: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1138: tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1139: arg1, 63 - arg2, 31 - arg2));
1140: } else {
1141: tcg_out_bundle(s, mII,
1142: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1143: tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R2,
1144: 0x1f, arg2),
1145: tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1146: arg1, TCG_REG_R2));
1147: }
1148: }
1149:
1150: static inline void tcg_out_shl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1151: TCGArg arg2, int const_arg2)
1152: {
1153: if (const_arg2) {
1154: tcg_out_bundle(s, miI,
1155: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1156: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1157: tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1158: arg1, 63 - arg2, 63 - arg2));
1159: } else {
1160: tcg_out_bundle(s, miI,
1161: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1162: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1163: tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1164: arg1, arg2));
1165: }
1166: }
1167:
1168: static inline void tcg_out_shr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1169: TCGArg arg2, int const_arg2)
1170: {
1171: if (const_arg2) {
1172: tcg_out_bundle(s, miI,
1173: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1174: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1175: tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1176: arg1, arg2, 31 - arg2));
1177: } else {
1178: tcg_out_bundle(s, mII,
1179: tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1180: 0x1f, arg2),
1181: tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R2, arg1),
1182: tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1183: TCG_REG_R2, TCG_REG_R3));
1184: }
1185: }
1186:
1187: static inline void tcg_out_shr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1188: TCGArg arg2, int const_arg2)
1189: {
1190: if (const_arg2) {
1191: tcg_out_bundle(s, miI,
1192: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1193: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1194: tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1195: arg1, arg2, 63 - arg2));
1196: } else {
1197: tcg_out_bundle(s, miI,
1198: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1199: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1200: tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1201: arg1, arg2));
1202: }
1203: }
1204:
1205: static inline void tcg_out_rotl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1206: TCGArg arg2, int const_arg2)
1207: {
1208: if (const_arg2) {
1209: tcg_out_bundle(s, mII,
1210: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1211: tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1212: TCG_REG_R2, arg1, arg1),
1213: tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1214: TCG_REG_R2, 32 - arg2, 31));
1215: } else {
1216: tcg_out_bundle(s, miI,
1217: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1218: tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1219: TCG_REG_R2, arg1, arg1),
1220: tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1221: 0x1f, arg2));
1222: tcg_out_bundle(s, mII,
1223: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1224: tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R3,
1225: 0x20, TCG_REG_R3),
1226: tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1227: TCG_REG_R2, TCG_REG_R3));
1228: }
1229: }
1230:
1231: static inline void tcg_out_rotl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1232: TCGArg arg2, int const_arg2)
1233: {
1234: if (const_arg2) {
1235: tcg_out_bundle(s, miI,
1236: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1237: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1238: tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1239: arg1, 0x40 - arg2));
1240: } else {
1241: tcg_out_bundle(s, mII,
1242: tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1243: 0x40, arg2),
1244: tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R3,
1245: arg1, arg2),
1246: tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R2,
1247: arg1, TCG_REG_R2));
1248: tcg_out_bundle(s, miI,
1249: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1250: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1251: tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1252: TCG_REG_R2, TCG_REG_R3));
1253: }
1254: }
1255:
1256: static inline void tcg_out_rotr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1257: TCGArg arg2, int const_arg2)
1258: {
1259: if (const_arg2) {
1260: tcg_out_bundle(s, mII,
1261: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1262: tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1263: TCG_REG_R2, arg1, arg1),
1264: tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1265: TCG_REG_R2, arg2, 31));
1266: } else {
1267: tcg_out_bundle(s, mII,
1268: tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1269: 0x1f, arg2),
1270: tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1271: TCG_REG_R2, arg1, arg1),
1272: tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1273: TCG_REG_R2, TCG_REG_R3));
1274: }
1275: }
1276:
1277: static inline void tcg_out_rotr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1278: TCGArg arg2, int const_arg2)
1279: {
1280: if (const_arg2) {
1281: tcg_out_bundle(s, miI,
1282: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1283: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1284: tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1285: arg1, arg2));
1286: } else {
1287: tcg_out_bundle(s, mII,
1288: tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1289: 0x40, arg2),
1290: tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R3,
1291: arg1, arg2),
1292: tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R2,
1293: arg1, TCG_REG_R2));
1294: tcg_out_bundle(s, miI,
1295: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1296: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1297: tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1298: TCG_REG_R2, TCG_REG_R3));
1299: }
1300: }
1301:
1302: static inline void tcg_out_ext(TCGContext *s, uint64_t opc_i29,
1303: TCGArg ret, TCGArg arg)
1304: {
1305: tcg_out_bundle(s, miI,
1306: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1307: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1308: tcg_opc_i29(TCG_REG_P0, opc_i29, ret, arg));
1309: }
1310:
1311: static inline void tcg_out_bswap16(TCGContext *s, TCGArg ret, TCGArg arg)
1312: {
1313: tcg_out_bundle(s, mII,
1314: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1315: tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 15, 15),
1316: tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1317: }
1318:
1319: static inline void tcg_out_bswap32(TCGContext *s, TCGArg ret, TCGArg arg)
1320: {
1321: tcg_out_bundle(s, mII,
1322: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1323: tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 31, 31),
1324: tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1325: }
1326:
1327: static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg)
1328: {
1329: tcg_out_bundle(s, mII,
1330: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1331: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1332: tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb));
1333: }
1334:
1335: static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1,
1336: TCGArg arg2, int cmp4)
1337: {
1338: uint64_t opc_eq_a6, opc_lt_a6, opc_ltu_a6;
1339:
1340: if (cmp4) {
1341: opc_eq_a6 = OPC_CMP4_EQ_A6;
1342: opc_lt_a6 = OPC_CMP4_LT_A6;
1343: opc_ltu_a6 = OPC_CMP4_LTU_A6;
1344: } else {
1345: opc_eq_a6 = OPC_CMP_EQ_A6;
1346: opc_lt_a6 = OPC_CMP_LT_A6;
1347: opc_ltu_a6 = OPC_CMP_LTU_A6;
1348: }
1349:
1350: switch (cond) {
1351: case TCG_COND_EQ:
1352: return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1353: case TCG_COND_NE:
1354: return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1355: case TCG_COND_LT:
1356: return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1357: case TCG_COND_LTU:
1358: return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1359: case TCG_COND_GE:
1360: return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1361: case TCG_COND_GEU:
1362: return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1363: case TCG_COND_LE:
1364: return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1365: case TCG_COND_LEU:
1366: return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1367: case TCG_COND_GT:
1368: return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1369: case TCG_COND_GTU:
1370: return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1371: default:
1372: tcg_abort();
1373: break;
1374: }
1375: }
1376:
1377: static inline void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGArg arg1,
1378: int const_arg1, TCGArg arg2, int const_arg2,
1379: int label_index, int cmp4)
1380: {
1381: TCGLabel *l = &s->labels[label_index];
1382: uint64_t opc1, opc2;
1383:
1384: if (const_arg1 && arg1 != 0) {
1385: opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2,
1386: arg1, TCG_REG_R0);
1387: arg1 = TCG_REG_R2;
1388: } else {
1389: opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1390: }
1391:
1392: if (const_arg2 && arg2 != 0) {
1393: opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R3,
1394: arg2, TCG_REG_R0);
1395: arg2 = TCG_REG_R3;
1396: } else {
1397: opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
1398: }
1399:
1400: tcg_out_bundle(s, mII,
1401: opc1,
1402: opc2,
1403: tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4));
1404: tcg_out_bundle(s, mmB,
1405: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1406: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1407: tcg_opc_b1 (TCG_REG_P6, OPC_BR_DPTK_FEW_B1,
1408: get_reloc_pcrel21b(s->code_ptr + 2)));
1409:
1410: if (l->has_value) {
1411: reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
1412: } else {
1413: tcg_out_reloc(s, (s->code_ptr - 16) + 2,
1414: R_IA64_PCREL21B, label_index, 0);
1415: }
1416: }
1417:
1418: static inline void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg ret,
1419: TCGArg arg1, TCGArg arg2, int cmp4)
1420: {
1421: tcg_out_bundle(s, MmI,
1422: tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4),
1423: tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, 1, TCG_REG_R0),
1424: tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, 0, TCG_REG_R0));
1425: }
1426:
1427: #if defined(CONFIG_SOFTMMU)
1428:
1429: #include "../../softmmu_defs.h"
1430:
1431: /* Load and compare a TLB entry, and return the result in (p6, p7).
1432: R2 is loaded with the address of the addend TLB entry.
1433: R56 is loaded with the address, zero extented on 32-bit targets. */
1434: static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
1435: int s_bits, uint64_t offset_rw,
1436: uint64_t offset_addend)
1437: {
1438: tcg_out_bundle(s, mII,
1439: tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R3,
1440: TARGET_PAGE_MASK | ((1 << s_bits) - 1),
1441: TCG_REG_R0),
1442: tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, TCG_REG_R2,
1443: addr_reg, TARGET_PAGE_BITS, CPU_TLB_BITS - 1),
1444: tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, TCG_REG_R2,
1445: TCG_REG_R2, 63 - CPU_TLB_ENTRY_BITS,
1446: 63 - CPU_TLB_ENTRY_BITS));
1447: tcg_out_bundle(s, mII,
1448: tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2,
1449: offset_rw, TCG_REG_R2),
1450: #if TARGET_LONG_BITS == 32
1451: tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R56, addr_reg),
1452: #else
1453: tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R56,
1454: 0, addr_reg),
1455: #endif
1456: tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1457: TCG_REG_R2, TCG_AREG0));
1458: tcg_out_bundle(s, mII,
1459: tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R57,
1460: TCG_REG_R2, offset_addend - offset_rw),
1461: tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, TCG_REG_R3,
1462: TCG_REG_R3, TCG_REG_R56),
1463: tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6,
1464: TCG_REG_P7, TCG_REG_R3, TCG_REG_R57));
1465: }
1466:
1467: static void *qemu_ld_helpers[4] = {
1468: __ldb_mmu,
1469: __ldw_mmu,
1470: __ldl_mmu,
1471: __ldq_mmu,
1472: };
1473:
1474: static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
1475: {
1476: int addr_reg, data_reg, mem_index, s_bits, bswap;
1477: uint64_t opc_ld_m1[4] = { OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 };
1478: uint64_t opc_ext_i29[8] = { OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0,
1479: OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 };
1480:
1481: data_reg = *args++;
1482: addr_reg = *args++;
1483: mem_index = *args;
1484: s_bits = opc & 3;
1485:
1486: #ifdef TARGET_WORDS_BIGENDIAN
1487: bswap = 1;
1488: #else
1489: bswap = 0;
1490: #endif
1491:
1492: /* Read the TLB entry */
1493: tcg_out_qemu_tlb(s, addr_reg, s_bits,
1494: offsetof(CPUState, tlb_table[mem_index][0].addr_read),
1495: offsetof(CPUState, tlb_table[mem_index][0].addend));
1496:
1497: /* P6 is the fast path, and P7 the slow path */
1498: tcg_out_bundle(s, mLX,
1499: tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R57,
1500: mem_index, TCG_REG_R0),
1501: tcg_opc_l2 ((tcg_target_long) qemu_ld_helpers[s_bits]),
1502: tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1503: (tcg_target_long) qemu_ld_helpers[s_bits]));
1504: tcg_out_bundle(s, MmI,
1505: tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1506: TCG_REG_R2, 8),
1507: tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
1508: TCG_REG_R3, TCG_REG_R56),
1509: tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1510: TCG_REG_R3, 0));
1511: if (bswap && s_bits == 1) {
1512: tcg_out_bundle(s, MmI,
1513: tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1514: TCG_REG_R8, TCG_REG_R3),
1515: tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1516: tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1517: TCG_REG_R8, TCG_REG_R8, 15, 15));
1518: } else if (bswap && s_bits == 2) {
1519: tcg_out_bundle(s, MmI,
1520: tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1521: TCG_REG_R8, TCG_REG_R3),
1522: tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1523: tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1524: TCG_REG_R8, TCG_REG_R8, 31, 31));
1525: } else {
1526: tcg_out_bundle(s, mmI,
1527: tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1528: TCG_REG_R8, TCG_REG_R3),
1529: tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1530: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1531: }
1532: if (!bswap || s_bits == 0) {
1533: tcg_out_bundle(s, miB,
1534: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1535: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1536: tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1537: TCG_REG_B0, TCG_REG_B6));
1538: } else {
1539: tcg_out_bundle(s, miB,
1540: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1541: tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1542: TCG_REG_R8, TCG_REG_R8, 0xb),
1543: tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1544: TCG_REG_B0, TCG_REG_B6));
1545: }
1546:
1547: if (opc == 3) {
1548: tcg_out_bundle(s, miI,
1549: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1550: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1551: tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
1552: data_reg, 0, TCG_REG_R8));
1553: } else {
1554: tcg_out_bundle(s, miI,
1555: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1556: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1557: tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc],
1558: data_reg, TCG_REG_R8));
1559: }
1560: }
1561:
1562: static void *qemu_st_helpers[4] = {
1563: __stb_mmu,
1564: __stw_mmu,
1565: __stl_mmu,
1566: __stq_mmu,
1567: };
1568:
1569: static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
1570: {
1571: int addr_reg, data_reg, mem_index, bswap;
1572: uint64_t opc_st_m4[4] = { OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 };
1573:
1574: data_reg = *args++;
1575: addr_reg = *args++;
1576: mem_index = *args;
1577:
1578: #ifdef TARGET_WORDS_BIGENDIAN
1579: bswap = 1;
1580: #else
1581: bswap = 0;
1582: #endif
1583:
1584: tcg_out_qemu_tlb(s, addr_reg, opc,
1585: offsetof(CPUState, tlb_table[mem_index][0].addr_write),
1586: offsetof(CPUState, tlb_table[mem_index][0].addend));
1587:
1588: /* P6 is the fast path, and P7 the slow path */
1589: tcg_out_bundle(s, mLX,
1590: tcg_opc_a4(TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R57,
1591: 0, data_reg),
1592: tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[opc]),
1593: tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1594: (tcg_target_long) qemu_st_helpers[opc]));
1595: tcg_out_bundle(s, MmI,
1596: tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1597: TCG_REG_R2, 8),
1598: tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
1599: TCG_REG_R3, TCG_REG_R56),
1600: tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1601: TCG_REG_R3, 0));
1602:
1603: if (!bswap || opc == 0) {
1604: tcg_out_bundle(s, mII,
1605: tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1606: TCG_REG_R1, TCG_REG_R2),
1607: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1608: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1609: } else if (opc == 1) {
1610: tcg_out_bundle(s, mII,
1611: tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1612: TCG_REG_R1, TCG_REG_R2),
1613: tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1614: TCG_REG_R2, data_reg, 15, 15),
1615: tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1616: TCG_REG_R2, TCG_REG_R2, 0xb));
1617: data_reg = TCG_REG_R2;
1618: } else if (opc == 2) {
1619: tcg_out_bundle(s, mII,
1620: tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1621: TCG_REG_R1, TCG_REG_R2),
1622: tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1623: TCG_REG_R2, data_reg, 31, 31),
1624: tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1625: TCG_REG_R2, TCG_REG_R2, 0xb));
1626: data_reg = TCG_REG_R2;
1627: } else if (opc == 3) {
1628: tcg_out_bundle(s, miI,
1629: tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1630: TCG_REG_R1, TCG_REG_R2),
1631: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1632: tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1633: TCG_REG_R2, data_reg, 0xb));
1634: data_reg = TCG_REG_R2;
1635: }
1636:
1637: tcg_out_bundle(s, miB,
1638: tcg_opc_m4 (TCG_REG_P6, opc_st_m4[opc],
1639: data_reg, TCG_REG_R3),
1640: tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
1641: mem_index, TCG_REG_R0),
1642: tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1643: TCG_REG_B0, TCG_REG_B6));
1644: }
1645:
1646: #else /* !CONFIG_SOFTMMU */
1647:
1648: static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
1649: {
1650: static uint64_t const opc_ld_m1[4] = {
1651: OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
1652: };
1653: static uint64_t const opc_sxt_i29[4] = {
1654: OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
1655: };
1656: int addr_reg, data_reg, mem_index, s_bits, bswap;
1657:
1658: data_reg = *args++;
1659: addr_reg = *args++;
1660: mem_index = *args;
1661: s_bits = opc & 3;
1662:
1663: #ifdef TARGET_WORDS_BIGENDIAN
1664: bswap = 1;
1665: #else
1666: bswap = 0;
1667: #endif
1668:
1669: #if TARGET_LONG_BITS == 32
1670: if (GUEST_BASE != 0) {
1671: tcg_out_bundle(s, mII,
1672: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1673: tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1674: TCG_REG_R3, addr_reg),
1675: tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1676: TCG_GUEST_BASE_REG, TCG_REG_R3));
1677: } else {
1678: tcg_out_bundle(s, miI,
1679: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1680: tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1681: TCG_REG_R2, addr_reg),
1682: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1683: }
1684:
1685: if (!bswap || s_bits == 0) {
1686: if (s_bits == opc) {
1687: tcg_out_bundle(s, miI,
1688: tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1689: data_reg, TCG_REG_R2),
1690: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1691: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1692: } else {
1693: tcg_out_bundle(s, mII,
1694: tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1695: data_reg, TCG_REG_R2),
1696: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1697: tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1698: data_reg, data_reg));
1699: }
1700: } else if (s_bits == 3) {
1701: tcg_out_bundle(s, mII,
1702: tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1703: data_reg, TCG_REG_R2),
1704: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1705: tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1706: data_reg, data_reg, 0xb));
1707: } else {
1708: if (s_bits == 1) {
1709: tcg_out_bundle(s, mII,
1710: tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1711: data_reg, TCG_REG_R2),
1712: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1713: tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1714: data_reg, data_reg, 15, 15));
1715: } else {
1716: tcg_out_bundle(s, mII,
1717: tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1718: data_reg, TCG_REG_R2),
1719: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1720: tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1721: data_reg, data_reg, 31, 31));
1722: }
1723: if (opc == s_bits) {
1724: tcg_out_bundle(s, miI,
1725: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1726: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1727: tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1728: data_reg, data_reg, 0xb));
1729: } else {
1730: tcg_out_bundle(s, mII,
1731: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1732: tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1733: data_reg, data_reg, 0xb),
1734: tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1735: data_reg, data_reg));
1736: }
1737: }
1738: #else
1739: if (GUEST_BASE != 0) {
1740: tcg_out_bundle(s, MmI,
1741: tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1742: TCG_GUEST_BASE_REG, addr_reg),
1743: tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1744: data_reg, TCG_REG_R2),
1745: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1746: } else {
1747: tcg_out_bundle(s, mmI,
1748: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1749: tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1750: data_reg, addr_reg),
1751: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1752: }
1753:
1754: if (bswap && s_bits == 1) {
1755: tcg_out_bundle(s, mII,
1756: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1757: tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1758: data_reg, data_reg, 15, 15),
1759: tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1760: data_reg, data_reg, 0xb));
1761: } else if (bswap && s_bits == 2) {
1762: tcg_out_bundle(s, mII,
1763: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1764: tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1765: data_reg, data_reg, 31, 31),
1766: tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1767: data_reg, data_reg, 0xb));
1768: } else if (bswap && s_bits == 3) {
1769: tcg_out_bundle(s, miI,
1770: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1771: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1772: tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1773: data_reg, data_reg, 0xb));
1774: }
1775: if (s_bits != opc) {
1776: tcg_out_bundle(s, miI,
1777: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1778: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1779: tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1780: data_reg, data_reg));
1781: }
1782: #endif
1783: }
1784:
1785: static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
1786: {
1787: static uint64_t const opc_st_m4[4] = {
1788: OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
1789: };
1790: int addr_reg, data_reg, bswap;
1791: #if TARGET_LONG_BITS == 64
1792: uint64_t add_guest_base;
1793: #endif
1794:
1795: data_reg = *args++;
1796: addr_reg = *args++;
1797:
1798: #ifdef TARGET_WORDS_BIGENDIAN
1799: bswap = 1;
1800: #else
1801: bswap = 0;
1802: #endif
1803:
1804: #if TARGET_LONG_BITS == 32
1805: if (GUEST_BASE != 0) {
1806: tcg_out_bundle(s, mII,
1807: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1808: tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1809: TCG_REG_R3, addr_reg),
1810: tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1811: TCG_GUEST_BASE_REG, TCG_REG_R3));
1812: } else {
1813: tcg_out_bundle(s, miI,
1814: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1815: tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1816: TCG_REG_R3, addr_reg),
1817: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1818: }
1819:
1820: if (bswap) {
1821: if (opc == 1) {
1822: tcg_out_bundle(s, mII,
1823: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1824: tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1825: TCG_REG_R3, data_reg, 15, 15),
1826: tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1827: TCG_REG_R3, TCG_REG_R3, 0xb));
1828: data_reg = TCG_REG_R3;
1829: } else if (opc == 2) {
1830: tcg_out_bundle(s, mII,
1831: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1832: tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1833: TCG_REG_R3, data_reg, 31, 31),
1834: tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1835: TCG_REG_R3, TCG_REG_R3, 0xb));
1836: data_reg = TCG_REG_R3;
1837: } else if (opc == 3) {
1838: tcg_out_bundle(s, miI,
1839: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1840: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1841: tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1842: TCG_REG_R3, data_reg, 0xb));
1843: data_reg = TCG_REG_R3;
1844: }
1845: }
1846: tcg_out_bundle(s, mmI,
1847: tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
1848: data_reg, TCG_REG_R2),
1849: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1850: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1851: #else
1852: if (GUEST_BASE != 0) {
1853: add_guest_base = tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1854: TCG_GUEST_BASE_REG, addr_reg);
1855: addr_reg = TCG_REG_R2;
1856: } else {
1857: add_guest_base = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1858: }
1859:
1860: if (!bswap || opc == 0) {
1861: tcg_out_bundle(s, (GUEST_BASE ? MmI : mmI),
1862: add_guest_base,
1863: tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
1864: data_reg, addr_reg),
1865: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1866: } else {
1867: if (opc == 1) {
1868: tcg_out_bundle(s, mII,
1869: add_guest_base,
1870: tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1871: TCG_REG_R3, data_reg, 15, 15),
1872: tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1873: TCG_REG_R3, TCG_REG_R3, 0xb));
1874: data_reg = TCG_REG_R3;
1875: } else if (opc == 2) {
1876: tcg_out_bundle(s, mII,
1877: add_guest_base,
1878: tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1879: TCG_REG_R3, data_reg, 31, 31),
1880: tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1881: TCG_REG_R3, TCG_REG_R3, 0xb));
1882: data_reg = TCG_REG_R3;
1883: } else if (opc == 3) {
1884: tcg_out_bundle(s, miI,
1885: add_guest_base,
1886: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1887: tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1888: TCG_REG_R3, data_reg, 0xb));
1889: data_reg = TCG_REG_R3;
1890: }
1891: tcg_out_bundle(s, miI,
1892: tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
1893: data_reg, addr_reg),
1894: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1895: tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1896: }
1897: #endif
1898: }
1899:
1900: #endif
1901:
1902: static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
1903: const TCGArg *args, const int *const_args)
1904: {
1905: switch(opc) {
1906: case INDEX_op_exit_tb:
1907: tcg_out_exit_tb(s, args[0]);
1908: break;
1909: case INDEX_op_br:
1910: tcg_out_br(s, args[0]);
1911: break;
1912: case INDEX_op_call:
1913: tcg_out_call(s, args[0]);
1914: break;
1915: case INDEX_op_goto_tb:
1916: tcg_out_goto_tb(s, args[0]);
1917: break;
1918: case INDEX_op_jmp:
1919: tcg_out_jmp(s, args[0]);
1920: break;
1921:
1922: case INDEX_op_movi_i32:
1923: tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1924: break;
1925: case INDEX_op_movi_i64:
1926: tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1927: break;
1928:
1929: case INDEX_op_ld8u_i32:
1930: case INDEX_op_ld8u_i64:
1931: tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
1932: break;
1933: case INDEX_op_ld8s_i32:
1934: case INDEX_op_ld8s_i64:
1935: tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
1936: tcg_out_ext(s, OPC_SXT1_I29, args[0], args[0]);
1937: break;
1938: case INDEX_op_ld16u_i32:
1939: case INDEX_op_ld16u_i64:
1940: tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
1941: break;
1942: case INDEX_op_ld16s_i32:
1943: case INDEX_op_ld16s_i64:
1944: tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
1945: tcg_out_ext(s, OPC_SXT2_I29, args[0], args[0]);
1946: break;
1947: case INDEX_op_ld_i32:
1948: case INDEX_op_ld32u_i64:
1949: tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
1950: break;
1951: case INDEX_op_ld32s_i64:
1952: tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
1953: tcg_out_ext(s, OPC_SXT4_I29, args[0], args[0]);
1954: break;
1955: case INDEX_op_ld_i64:
1956: tcg_out_ld_rel(s, OPC_LD8_M1, args[0], args[1], args[2]);
1957: break;
1958: case INDEX_op_st8_i32:
1959: case INDEX_op_st8_i64:
1960: tcg_out_st_rel(s, OPC_ST1_M4, args[0], args[1], args[2]);
1961: break;
1962: case INDEX_op_st16_i32:
1963: case INDEX_op_st16_i64:
1964: tcg_out_st_rel(s, OPC_ST2_M4, args[0], args[1], args[2]);
1965: break;
1966: case INDEX_op_st_i32:
1967: case INDEX_op_st32_i64:
1968: tcg_out_st_rel(s, OPC_ST4_M4, args[0], args[1], args[2]);
1969: break;
1970: case INDEX_op_st_i64:
1971: tcg_out_st_rel(s, OPC_ST8_M4, args[0], args[1], args[2]);
1972: break;
1973:
1974: case INDEX_op_add_i32:
1975: case INDEX_op_add_i64:
1976: tcg_out_alu(s, OPC_ADD_A1, args[0], args[1], const_args[1],
1977: args[2], const_args[2]);
1978: break;
1979: case INDEX_op_sub_i32:
1980: case INDEX_op_sub_i64:
1981: tcg_out_alu(s, OPC_SUB_A1, args[0], args[1], const_args[1],
1982: args[2], const_args[2]);
1983: break;
1984:
1985: case INDEX_op_and_i32:
1986: case INDEX_op_and_i64:
1987: tcg_out_alu(s, OPC_AND_A1, args[0], args[1], const_args[1],
1988: args[2], const_args[2]);
1989: break;
1990: case INDEX_op_andc_i32:
1991: case INDEX_op_andc_i64:
1992: tcg_out_alu(s, OPC_ANDCM_A1, args[0], args[1], const_args[1],
1993: args[2], const_args[2]);
1994: break;
1995: case INDEX_op_eqv_i32:
1996: case INDEX_op_eqv_i64:
1997: tcg_out_eqv(s, args[0], args[1], const_args[1],
1998: args[2], const_args[2]);
1999: break;
2000: case INDEX_op_nand_i32:
2001: case INDEX_op_nand_i64:
2002: tcg_out_nand(s, args[0], args[1], const_args[1],
2003: args[2], const_args[2]);
2004: break;
2005: case INDEX_op_nor_i32:
2006: case INDEX_op_nor_i64:
2007: tcg_out_nor(s, args[0], args[1], const_args[1],
2008: args[2], const_args[2]);
2009: break;
2010: case INDEX_op_or_i32:
2011: case INDEX_op_or_i64:
2012: tcg_out_alu(s, OPC_OR_A1, args[0], args[1], const_args[1],
2013: args[2], const_args[2]);
2014: break;
2015: case INDEX_op_orc_i32:
2016: case INDEX_op_orc_i64:
2017: tcg_out_orc(s, args[0], args[1], const_args[1],
2018: args[2], const_args[2]);
2019: break;
2020: case INDEX_op_xor_i32:
2021: case INDEX_op_xor_i64:
2022: tcg_out_alu(s, OPC_XOR_A1, args[0], args[1], const_args[1],
2023: args[2], const_args[2]);
2024: break;
2025:
2026: case INDEX_op_mul_i32:
2027: case INDEX_op_mul_i64:
2028: tcg_out_mul(s, args[0], args[1], args[2]);
2029: break;
2030:
2031: case INDEX_op_sar_i32:
2032: tcg_out_sar_i32(s, args[0], args[1], args[2], const_args[2]);
2033: break;
2034: case INDEX_op_sar_i64:
2035: tcg_out_sar_i64(s, args[0], args[1], args[2], const_args[2]);
2036: break;
2037: case INDEX_op_shl_i32:
2038: tcg_out_shl_i32(s, args[0], args[1], args[2], const_args[2]);
2039: break;
2040: case INDEX_op_shl_i64:
2041: tcg_out_shl_i64(s, args[0], args[1], args[2], const_args[2]);
2042: break;
2043: case INDEX_op_shr_i32:
2044: tcg_out_shr_i32(s, args[0], args[1], args[2], const_args[2]);
2045: break;
2046: case INDEX_op_shr_i64:
2047: tcg_out_shr_i64(s, args[0], args[1], args[2], const_args[2]);
2048: break;
2049: case INDEX_op_rotl_i32:
2050: tcg_out_rotl_i32(s, args[0], args[1], args[2], const_args[2]);
2051: break;
2052: case INDEX_op_rotl_i64:
2053: tcg_out_rotl_i64(s, args[0], args[1], args[2], const_args[2]);
2054: break;
2055: case INDEX_op_rotr_i32:
2056: tcg_out_rotr_i32(s, args[0], args[1], args[2], const_args[2]);
2057: break;
2058: case INDEX_op_rotr_i64:
2059: tcg_out_rotr_i64(s, args[0], args[1], args[2], const_args[2]);
2060: break;
2061:
2062: case INDEX_op_ext8s_i32:
2063: case INDEX_op_ext8s_i64:
2064: tcg_out_ext(s, OPC_SXT1_I29, args[0], args[1]);
2065: break;
2066: case INDEX_op_ext8u_i32:
2067: case INDEX_op_ext8u_i64:
2068: tcg_out_ext(s, OPC_ZXT1_I29, args[0], args[1]);
2069: break;
2070: case INDEX_op_ext16s_i32:
2071: case INDEX_op_ext16s_i64:
2072: tcg_out_ext(s, OPC_SXT2_I29, args[0], args[1]);
2073: break;
2074: case INDEX_op_ext16u_i32:
2075: case INDEX_op_ext16u_i64:
2076: tcg_out_ext(s, OPC_ZXT2_I29, args[0], args[1]);
2077: break;
2078: case INDEX_op_ext32s_i64:
2079: tcg_out_ext(s, OPC_SXT4_I29, args[0], args[1]);
2080: break;
2081: case INDEX_op_ext32u_i64:
2082: tcg_out_ext(s, OPC_ZXT4_I29, args[0], args[1]);
2083: break;
2084:
2085: case INDEX_op_bswap16_i32:
2086: case INDEX_op_bswap16_i64:
2087: tcg_out_bswap16(s, args[0], args[1]);
2088: break;
2089: case INDEX_op_bswap32_i32:
2090: case INDEX_op_bswap32_i64:
2091: tcg_out_bswap32(s, args[0], args[1]);
2092: break;
2093: case INDEX_op_bswap64_i64:
2094: tcg_out_bswap64(s, args[0], args[1]);
2095: break;
2096:
2097: case INDEX_op_brcond_i32:
2098: tcg_out_brcond(s, args[2], args[0], const_args[0],
2099: args[1], const_args[1], args[3], 1);
2100: break;
2101: case INDEX_op_brcond_i64:
2102: tcg_out_brcond(s, args[2], args[0], const_args[0],
2103: args[1], const_args[1], args[3], 0);
2104: break;
2105: case INDEX_op_setcond_i32:
2106: tcg_out_setcond(s, args[3], args[0], args[1], args[2], 1);
2107: break;
2108: case INDEX_op_setcond_i64:
2109: tcg_out_setcond(s, args[3], args[0], args[1], args[2], 0);
2110: break;
2111:
2112: case INDEX_op_qemu_ld8u:
2113: tcg_out_qemu_ld(s, args, 0);
2114: break;
2115: case INDEX_op_qemu_ld8s:
2116: tcg_out_qemu_ld(s, args, 0 | 4);
2117: break;
2118: case INDEX_op_qemu_ld16u:
2119: tcg_out_qemu_ld(s, args, 1);
2120: break;
2121: case INDEX_op_qemu_ld16s:
2122: tcg_out_qemu_ld(s, args, 1 | 4);
2123: break;
2124: case INDEX_op_qemu_ld32u:
2125: tcg_out_qemu_ld(s, args, 2);
2126: break;
2127: case INDEX_op_qemu_ld32s:
2128: tcg_out_qemu_ld(s, args, 2 | 4);
2129: break;
2130: case INDEX_op_qemu_ld64:
2131: tcg_out_qemu_ld(s, args, 3);
2132: break;
2133:
2134: case INDEX_op_qemu_st8:
2135: tcg_out_qemu_st(s, args, 0);
2136: break;
2137: case INDEX_op_qemu_st16:
2138: tcg_out_qemu_st(s, args, 1);
2139: break;
2140: case INDEX_op_qemu_st32:
2141: tcg_out_qemu_st(s, args, 2);
2142: break;
2143: case INDEX_op_qemu_st64:
2144: tcg_out_qemu_st(s, args, 3);
2145: break;
2146:
2147: default:
2148: tcg_abort();
2149: }
2150: }
2151:
2152: static const TCGTargetOpDef ia64_op_defs[] = {
2153: { INDEX_op_br, { } },
2154: { INDEX_op_call, { "r" } },
2155: { INDEX_op_exit_tb, { } },
2156: { INDEX_op_goto_tb, { } },
2157: { INDEX_op_jmp, { "r" } },
2158:
2159: { INDEX_op_mov_i32, { "r", "r" } },
2160: { INDEX_op_movi_i32, { "r" } },
2161:
2162: { INDEX_op_ld8u_i32, { "r", "r" } },
2163: { INDEX_op_ld8s_i32, { "r", "r" } },
2164: { INDEX_op_ld16u_i32, { "r", "r" } },
2165: { INDEX_op_ld16s_i32, { "r", "r" } },
2166: { INDEX_op_ld_i32, { "r", "r" } },
2167: { INDEX_op_st8_i32, { "rZ", "r" } },
2168: { INDEX_op_st16_i32, { "rZ", "r" } },
2169: { INDEX_op_st_i32, { "rZ", "r" } },
2170:
2171: { INDEX_op_add_i32, { "r", "rI", "rI" } },
2172: { INDEX_op_sub_i32, { "r", "rI", "rI" } },
2173:
2174: { INDEX_op_and_i32, { "r", "rI", "rI" } },
2175: { INDEX_op_andc_i32, { "r", "rI", "rI" } },
2176: { INDEX_op_eqv_i32, { "r", "rZ", "rZ" } },
2177: { INDEX_op_nand_i32, { "r", "rZ", "rZ" } },
2178: { INDEX_op_nor_i32, { "r", "rZ", "rZ" } },
2179: { INDEX_op_or_i32, { "r", "rI", "rI" } },
2180: { INDEX_op_orc_i32, { "r", "rZ", "rZ" } },
2181: { INDEX_op_xor_i32, { "r", "rI", "rI" } },
2182:
2183: { INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
2184:
2185: { INDEX_op_sar_i32, { "r", "rZ", "ri" } },
2186: { INDEX_op_shl_i32, { "r", "rZ", "ri" } },
2187: { INDEX_op_shr_i32, { "r", "rZ", "ri" } },
2188: { INDEX_op_rotl_i32, { "r", "rZ", "ri" } },
2189: { INDEX_op_rotr_i32, { "r", "rZ", "ri" } },
2190:
2191: { INDEX_op_ext8s_i32, { "r", "rZ"} },
2192: { INDEX_op_ext8u_i32, { "r", "rZ"} },
2193: { INDEX_op_ext16s_i32, { "r", "rZ"} },
2194: { INDEX_op_ext16u_i32, { "r", "rZ"} },
2195:
2196: { INDEX_op_bswap16_i32, { "r", "rZ" } },
2197: { INDEX_op_bswap32_i32, { "r", "rZ" } },
2198:
2199: { INDEX_op_brcond_i32, { "rI", "rI" } },
2200: { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
2201:
2202: { INDEX_op_mov_i64, { "r", "r" } },
2203: { INDEX_op_movi_i64, { "r" } },
2204:
2205: { INDEX_op_ld8u_i64, { "r", "r" } },
2206: { INDEX_op_ld8s_i64, { "r", "r" } },
2207: { INDEX_op_ld16u_i64, { "r", "r" } },
2208: { INDEX_op_ld16s_i64, { "r", "r" } },
2209: { INDEX_op_ld32u_i64, { "r", "r" } },
2210: { INDEX_op_ld32s_i64, { "r", "r" } },
2211: { INDEX_op_ld_i64, { "r", "r" } },
2212: { INDEX_op_st8_i64, { "rZ", "r" } },
2213: { INDEX_op_st16_i64, { "rZ", "r" } },
2214: { INDEX_op_st32_i64, { "rZ", "r" } },
2215: { INDEX_op_st_i64, { "rZ", "r" } },
2216:
2217: { INDEX_op_add_i64, { "r", "rI", "rI" } },
2218: { INDEX_op_sub_i64, { "r", "rI", "rI" } },
2219:
2220: { INDEX_op_and_i64, { "r", "rI", "rI" } },
2221: { INDEX_op_andc_i64, { "r", "rI", "rI" } },
2222: { INDEX_op_eqv_i64, { "r", "rZ", "rZ" } },
2223: { INDEX_op_nand_i64, { "r", "rZ", "rZ" } },
2224: { INDEX_op_nor_i64, { "r", "rZ", "rZ" } },
2225: { INDEX_op_or_i64, { "r", "rI", "rI" } },
2226: { INDEX_op_orc_i64, { "r", "rZ", "rZ" } },
2227: { INDEX_op_xor_i64, { "r", "rI", "rI" } },
2228:
2229: { INDEX_op_mul_i64, { "r", "rZ", "rZ" } },
2230:
2231: { INDEX_op_sar_i64, { "r", "rZ", "ri" } },
2232: { INDEX_op_shl_i64, { "r", "rZ", "ri" } },
2233: { INDEX_op_shr_i64, { "r", "rZ", "ri" } },
2234: { INDEX_op_rotl_i64, { "r", "rZ", "ri" } },
2235: { INDEX_op_rotr_i64, { "r", "rZ", "ri" } },
2236:
2237: { INDEX_op_ext8s_i64, { "r", "rZ"} },
2238: { INDEX_op_ext8u_i64, { "r", "rZ"} },
2239: { INDEX_op_ext16s_i64, { "r", "rZ"} },
2240: { INDEX_op_ext16u_i64, { "r", "rZ"} },
2241: { INDEX_op_ext32s_i64, { "r", "rZ"} },
2242: { INDEX_op_ext32u_i64, { "r", "rZ"} },
2243:
2244: { INDEX_op_bswap16_i64, { "r", "rZ" } },
2245: { INDEX_op_bswap32_i64, { "r", "rZ" } },
2246: { INDEX_op_bswap64_i64, { "r", "rZ" } },
2247:
2248: { INDEX_op_brcond_i64, { "rI", "rI" } },
2249: { INDEX_op_setcond_i64, { "r", "rZ", "rZ" } },
2250:
2251: { INDEX_op_qemu_ld8u, { "r", "r" } },
2252: { INDEX_op_qemu_ld8s, { "r", "r" } },
2253: { INDEX_op_qemu_ld16u, { "r", "r" } },
2254: { INDEX_op_qemu_ld16s, { "r", "r" } },
2255: { INDEX_op_qemu_ld32, { "r", "r" } },
2256: { INDEX_op_qemu_ld32u, { "r", "r" } },
2257: { INDEX_op_qemu_ld32s, { "r", "r" } },
2258: { INDEX_op_qemu_ld64, { "r", "r" } },
2259:
2260: { INDEX_op_qemu_st8, { "SZ", "r" } },
2261: { INDEX_op_qemu_st16, { "SZ", "r" } },
2262: { INDEX_op_qemu_st32, { "SZ", "r" } },
2263: { INDEX_op_qemu_st64, { "SZ", "r" } },
2264:
2265: { -1 },
2266: };
2267:
2268: /* Generate global QEMU prologue and epilogue code */
2269: static void tcg_target_qemu_prologue(TCGContext *s)
2270: {
2271: int frame_size;
2272:
2273: /* reserve some stack space */
2274: frame_size = TCG_STATIC_CALL_ARGS_SIZE;
2275: frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
2276: ~(TCG_TARGET_STACK_ALIGN - 1);
2277:
2278: /* First emit adhoc function descriptor */
2279: *(uint64_t *)(s->code_ptr) = (uint64_t)s->code_ptr + 16; /* entry point */
2280: s->code_ptr += 16; /* skip GP */
2281:
2282: /* prologue */
2283: tcg_out_bundle(s, mII,
2284: tcg_opc_m34(TCG_REG_P0, OPC_ALLOC_M34,
2285: TCG_REG_R33, 32, 24, 0),
2286: tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
2287: TCG_REG_B6, TCG_REG_R32, 0),
2288: tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22,
2289: TCG_REG_R32, TCG_REG_B0));
2290:
2291: /* ??? If GUEST_BASE < 0x200000, we could load the register via
2292: an ADDL in the M slot of the next bundle. */
2293: if (GUEST_BASE != 0) {
2294: tcg_out_bundle(s, mlx,
2295: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2296: tcg_opc_l2 (GUEST_BASE),
2297: tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2,
2298: TCG_GUEST_BASE_REG, GUEST_BASE));
2299: tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2300: }
2301:
2302: tcg_out_bundle(s, miB,
2303: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2304: tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2305: TCG_REG_R12, -frame_size, TCG_REG_R12),
2306: tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
2307:
2308: /* epilogue */
2309: tb_ret_addr = s->code_ptr;
2310: tcg_out_bundle(s, miI,
2311: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2312: tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
2313: TCG_REG_B0, TCG_REG_R32, 0),
2314: tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2315: TCG_REG_R12, frame_size, TCG_REG_R12));
2316: tcg_out_bundle(s, miB,
2317: tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2318: tcg_opc_i26(TCG_REG_P0, OPC_MOV_I_I26,
2319: TCG_REG_PFS, TCG_REG_R33),
2320: tcg_opc_b4 (TCG_REG_P0, OPC_BR_RET_SPTK_MANY_B4,
2321: TCG_REG_B0));
2322: }
2323:
2324: static void tcg_target_init(TCGContext *s)
2325: {
2326: tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32],
2327: 0xffffffffffffffffull);
2328: tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64],
2329: 0xffffffffffffffffull);
2330:
2331: tcg_regset_clear(tcg_target_call_clobber_regs);
2332: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
2333: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
2334: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
2335: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
2336: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
2337: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R15);
2338: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R16);
2339: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R17);
2340: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R18);
2341: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R19);
2342: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R20);
2343: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R21);
2344: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R22);
2345: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R23);
2346: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R24);
2347: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R25);
2348: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R26);
2349: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R27);
2350: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R28);
2351: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R29);
2352: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R30);
2353: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R31);
2354: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R56);
2355: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R57);
2356: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R58);
2357: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R59);
2358: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R60);
2359: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R61);
2360: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R62);
2361: tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R63);
2362:
2363: tcg_regset_clear(s->reserved_regs);
2364: tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* zero register */
2365: tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* global pointer */
2366: tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* internal use */
2367: tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3); /* internal use */
2368: tcg_regset_set_reg(s->reserved_regs, TCG_REG_R12); /* stack pointer */
2369: tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
2370: tcg_regset_set_reg(s->reserved_regs, TCG_REG_R32); /* return address */
2371: tcg_regset_set_reg(s->reserved_regs, TCG_REG_R33); /* PFS */
2372:
2373: /* The following 3 are not in use, are call-saved, but *not* saved
2374: by the prologue. Therefore we cannot use them without modifying
2375: the prologue. There doesn't seem to be any good reason to use
2376: these as opposed to the windowed registers. */
2377: tcg_regset_set_reg(s->reserved_regs, TCG_REG_R4);
2378: tcg_regset_set_reg(s->reserved_regs, TCG_REG_R5);
2379: tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6);
2380:
2381: tcg_add_target_add_op_defs(ia64_op_defs);
2382: }
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.