--- qemu/tcg/sparc/tcg-target.c 2018/04/24 18:25:12 1.1.1.3 +++ qemu/tcg/sparc/tcg-target.c 2018/04/24 19:35:45 1.1.1.6 @@ -59,6 +59,12 @@ static const char * const tcg_target_reg }; #endif +#ifdef CONFIG_TCG_PASS_AREG0 +#define ARG_OFFSET 1 +#else +#define ARG_OFFSET 0 +#endif + static const int tcg_target_reg_alloc_order[] = { TCG_REG_L0, TCG_REG_L1, @@ -84,9 +90,11 @@ static const int tcg_target_call_iarg_re TCG_REG_O5, }; -static const int tcg_target_call_oarg_regs[2] = { +static const int tcg_target_call_oarg_regs[] = { TCG_REG_O0, TCG_REG_O1, + TCG_REG_O2, + TCG_REG_O3, }; static inline int check_fit_tl(tcg_target_long val, unsigned int bits) @@ -153,6 +161,9 @@ static int target_parse_constraint(TCGAr tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0); tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1); tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2); +#ifdef CONFIG_TCG_PASS_AREG0 + tcg_regset_reset_reg(ct->u.regs, TCG_REG_O3); +#endif break; case 'I': ct->ct |= TCG_CT_CONST_S11; @@ -304,7 +315,8 @@ static void tcg_out_arithc(TCGContext *s | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2))); } -static inline void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg) +static inline void tcg_out_mov(TCGContext *s, TCGType type, + TCGReg ret, TCGReg arg) { tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); } @@ -331,7 +343,7 @@ static inline void tcg_out_movi_imm32(TC } static inline void tcg_out_movi(TCGContext *s, TCGType type, - int ret, tcg_target_long arg) + TCGReg ret, tcg_target_long arg) { /* All 32-bit constants, as well as 64-bit constants with no high bits set go through movi_imm32. */ @@ -396,8 +408,8 @@ static inline void tcg_out_ldst_asi(TCGC INSN_ASI(asi) | INSN_RS2(addr)); } -static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret, - int arg1, tcg_target_long arg2) +static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, + TCGReg arg1, tcg_target_long arg2) { if (type == TCG_TYPE_I32) tcg_out_ldst(s, ret, arg1, arg2, LDUW); @@ -405,8 +417,8 @@ static inline void tcg_out_ld(TCGContext tcg_out_ldst(s, ret, arg1, arg2, LDX); } -static inline void tcg_out_st(TCGContext *s, TCGType type, int arg, - int arg1, tcg_target_long arg2) +static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, tcg_target_long arg2) { if (type == TCG_TYPE_I32) tcg_out_ldst(s, arg, arg1, arg2, STW); @@ -470,11 +482,9 @@ static inline void tcg_out_nop(TCGContex static void tcg_out_branch_i32(TCGContext *s, int opc, int label_index) { - int32_t val; TCGLabel *l = &s->labels[label_index]; if (l->has_value) { - val = l->u.value - (tcg_target_long)s->code_ptr; tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | INSN_OFF22(l->u.value - (unsigned long)s->code_ptr))); } else { @@ -486,11 +496,9 @@ static void tcg_out_branch_i32(TCGContex #if TCG_TARGET_REG_BITS == 64 static void tcg_out_branch_i64(TCGContext *s, int opc, int label_index) { - int32_t val; TCGLabel *l = &s->labels[label_index]; if (l->has_value) { - val = l->u.value - (tcg_target_long)s->code_ptr; tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) | (0x5 << 19) | INSN_OFF19(l->u.value - (unsigned long)s->code_ptr))); @@ -583,7 +591,7 @@ static void tcg_out_brcond2_i32(TCGConte } tcg_out_nop(s); - tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr); + tcg_out_label(s, label_next, s->code_ptr); } #endif @@ -629,7 +637,7 @@ static void tcg_out_setcond_i32(TCGConte tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), t); tcg_out_movi_imm13(s, ret, 1); tcg_out_movi_imm13(s, ret, 0); - tcg_out_label(s, t, (tcg_target_long)s->code_ptr); + tcg_out_label(s, t, s->code_ptr); #endif return; } @@ -684,7 +692,7 @@ static void tcg_out_setcond2_i32(TCGCont tcg_out_setcond_i32(s, tcg_unsigned_cond(cond), ret, al, bl, blconst); - tcg_out_label(s, lab, (tcg_target_long)s->code_ptr); + tcg_out_label(s, lab, s->code_ptr); break; } } @@ -693,17 +701,41 @@ static void tcg_out_setcond2_i32(TCGCont /* Generate global QEMU prologue and epilogue code */ static void tcg_target_qemu_prologue(TCGContext *s) { + tcg_set_frame(s, TCG_REG_I6, TCG_TARGET_CALL_STACK_OFFSET, + CPU_TEMP_BUF_NLONGS * (int)sizeof(long)); tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) | - INSN_IMM13(-TCG_TARGET_STACK_MINFRAME)); - tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I0) | + INSN_IMM13(-(TCG_TARGET_STACK_MINFRAME + + CPU_TEMP_BUF_NLONGS * (int)sizeof(long)))); + tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I1) | INSN_RS2(TCG_REG_G0)); - tcg_out_nop(s); + tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_I0); } #if defined(CONFIG_SOFTMMU) #include "../../softmmu_defs.h" +#ifdef CONFIG_TCG_PASS_AREG0 +/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, + int mmu_idx) */ +static const void * const qemu_ld_helpers[4] = { + helper_ldb_mmu, + helper_ldw_mmu, + helper_ldl_mmu, + helper_ldq_mmu, +}; + +/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr, + uintxx_t val, int mmu_idx) */ +static const void * const qemu_st_helpers[4] = { + helper_stb_mmu, + helper_stw_mmu, + helper_stl_mmu, + helper_stq_mmu, +}; +#else +/* legacy helper signature: __ld_mmu(target_ulong addr, int + mmu_idx) */ static const void * const qemu_ld_helpers[4] = { __ldb_mmu, __ldw_mmu, @@ -711,6 +743,8 @@ static const void * const qemu_ld_helper __ldq_mmu, }; +/* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val, + int mmu_idx) */ static const void * const qemu_st_helpers[4] = { __stb_mmu, __stw_mmu, @@ -718,6 +752,7 @@ static const void * const qemu_st_helper __stq_mmu, }; #endif +#endif #if TARGET_LONG_BITS == 32 #define TARGET_LD_OP LDUW @@ -774,7 +809,7 @@ static void tcg_out_qemu_ld(TCGContext * tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS); /* add arg1, x, arg1 */ - tcg_out_addi(s, arg1, offsetof(CPUState, + tcg_out_addi(s, arg1, offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)); /* add env, arg1, arg1 */ @@ -799,6 +834,17 @@ static void tcg_out_qemu_ld(TCGContext * /* mov */ tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index); +#ifdef CONFIG_TCG_PASS_AREG0 + /* XXX/FIXME: suboptimal */ + tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], + tcg_target_call_iarg_regs[2]); + tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2], + tcg_target_call_iarg_regs[1]); + tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], + tcg_target_call_iarg_regs[0]); + tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], + TCG_AREG0); +#endif /* XXX: move that code at the end of the TB */ /* qemu_ld_helper[s_bits](arg0, arg1) */ @@ -986,7 +1032,7 @@ static void tcg_out_qemu_st(TCGContext * tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS); /* add arg1, x, arg1 */ - tcg_out_addi(s, arg1, offsetof(CPUState, + tcg_out_addi(s, arg1, offsetof(CPUArchState, tlb_table[mem_index][0].addr_write)); /* add env, arg1, arg1 */ @@ -1015,6 +1061,17 @@ static void tcg_out_qemu_st(TCGContext * /* mov */ tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index); +#ifdef CONFIG_TCG_PASS_AREG0 + /* XXX/FIXME: suboptimal */ + tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], + tcg_target_call_iarg_regs[2]); + tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2], + tcg_target_call_iarg_regs[1]); + tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], + tcg_target_call_iarg_regs[0]); + tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], + TCG_AREG0); +#endif /* XXX: move that code at the end of the TB */ /* qemu_st_helper[s_bits](arg0, arg1, arg2) */ tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits] @@ -1567,3 +1624,66 @@ static void tcg_target_init(TCGContext * tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7); tcg_add_target_add_op_defs(sparc_op_defs); } + +#if TCG_TARGET_REG_BITS == 64 +# define ELF_HOST_MACHINE EM_SPARCV9 +#elif defined(__sparc_v8plus__) +# define ELF_HOST_MACHINE EM_SPARC32PLUS +# define ELF_HOST_FLAGS EF_SPARC_32PLUS +#else +# define ELF_HOST_MACHINE EM_SPARC +#endif + +typedef struct { + uint32_t len __attribute__((aligned((sizeof(void *))))); + uint32_t id; + uint8_t version; + char augmentation[1]; + uint8_t code_align; + uint8_t data_align; + uint8_t return_column; +} DebugFrameCIE; + +typedef struct { + uint32_t len __attribute__((aligned((sizeof(void *))))); + uint32_t cie_offset; + tcg_target_long func_start __attribute__((packed)); + tcg_target_long func_len __attribute__((packed)); + uint8_t def_cfa[TCG_TARGET_REG_BITS == 64 ? 4 : 2]; + uint8_t win_save; + uint8_t ret_save[3]; +} DebugFrameFDE; + +typedef struct { + DebugFrameCIE cie; + DebugFrameFDE fde; +} DebugFrame; + +static DebugFrame debug_frame = { + .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ + .cie.id = -1, + .cie.version = 1, + .cie.code_align = 1, + .cie.data_align = -sizeof(void *) & 0x7f, + .cie.return_column = 15, /* o7 */ + + .fde.len = sizeof(DebugFrameFDE)-4, /* length after .len member */ + .fde.def_cfa = { +#if TCG_TARGET_REG_BITS == 64 + 12, 30, /* DW_CFA_def_cfa i6, 2047 */ + (2047 & 0x7f) | 0x80, (2047 >> 7) +#else + 13, 30 /* DW_CFA_def_cfa_register i6 */ +#endif + }, + .fde.win_save = 0x2d, /* DW_CFA_GNU_window_save */ + .fde.ret_save = { 9, 15, 31 }, /* DW_CFA_register o7, i7 */ +}; + +void tcg_register_jit(void *buf, size_t buf_size) +{ + debug_frame.fde.func_start = (tcg_target_long) buf; + debug_frame.fde.func_len = buf_size; + + tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); +}