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1.1 root 1: /*
2: * Tiny Code Generator for QEMU
3: *
4: * Copyright (c) 2008 Fabrice Bellard
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
24:
25: #ifndef NDEBUG
26: static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
27: "%g0",
28: "%g1",
29: "%g2",
30: "%g3",
31: "%g4",
32: "%g5",
33: "%g6",
34: "%g7",
35: "%o0",
36: "%o1",
37: "%o2",
38: "%o3",
39: "%o4",
40: "%o5",
41: "%o6",
42: "%o7",
43: "%l0",
44: "%l1",
45: "%l2",
46: "%l3",
47: "%l4",
48: "%l5",
49: "%l6",
50: "%l7",
51: "%i0",
52: "%i1",
53: "%i2",
54: "%i3",
55: "%i4",
56: "%i5",
57: "%i6",
58: "%i7",
59: };
60: #endif
61:
62: static const int tcg_target_reg_alloc_order[] = {
63: TCG_REG_L0,
64: TCG_REG_L1,
65: TCG_REG_L2,
66: TCG_REG_L3,
67: TCG_REG_L4,
68: TCG_REG_L5,
69: TCG_REG_L6,
70: TCG_REG_L7,
71: TCG_REG_I0,
72: TCG_REG_I1,
73: TCG_REG_I2,
74: TCG_REG_I3,
75: TCG_REG_I4,
76: };
77:
78: static const int tcg_target_call_iarg_regs[6] = {
79: TCG_REG_O0,
80: TCG_REG_O1,
81: TCG_REG_O2,
82: TCG_REG_O3,
83: TCG_REG_O4,
84: TCG_REG_O5,
85: };
86:
87: static const int tcg_target_call_oarg_regs[2] = {
88: TCG_REG_O0,
89: TCG_REG_O1,
90: };
91:
92: static inline int check_fit_tl(tcg_target_long val, unsigned int bits)
93: {
94: return (val << ((sizeof(tcg_target_long) * 8 - bits))
95: >> (sizeof(tcg_target_long) * 8 - bits)) == val;
96: }
97:
98: static inline int check_fit_i32(uint32_t val, unsigned int bits)
99: {
100: return ((val << (32 - bits)) >> (32 - bits)) == val;
101: }
102:
103: static void patch_reloc(uint8_t *code_ptr, int type,
104: tcg_target_long value, tcg_target_long addend)
105: {
106: value += addend;
107: switch (type) {
108: case R_SPARC_32:
109: if (value != (uint32_t)value)
110: tcg_abort();
111: *(uint32_t *)code_ptr = value;
112: break;
113: case R_SPARC_WDISP22:
114: value -= (long)code_ptr;
115: value >>= 2;
116: if (!check_fit_tl(value, 22))
117: tcg_abort();
118: *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
119: break;
1.1.1.2 root 120: case R_SPARC_WDISP19:
121: value -= (long)code_ptr;
122: value >>= 2;
123: if (!check_fit_tl(value, 19))
124: tcg_abort();
125: *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x7ffff) | value;
126: break;
1.1 root 127: default:
128: tcg_abort();
129: }
130: }
131:
132: /* maximum number of register used for input function arguments */
133: static inline int tcg_target_get_call_iarg_regs_count(int flags)
134: {
135: return 6;
136: }
137:
138: /* parse target specific constraints */
139: static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
140: {
141: const char *ct_str;
142:
143: ct_str = *pct_str;
144: switch (ct_str[0]) {
145: case 'r':
1.1.1.3 root 146: ct->ct |= TCG_CT_REG;
147: tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
148: break;
1.1 root 149: case 'L': /* qemu_ld/st constraint */
150: ct->ct |= TCG_CT_REG;
151: tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
152: // Helper args
153: tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
154: tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
155: tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
156: break;
157: case 'I':
158: ct->ct |= TCG_CT_CONST_S11;
159: break;
160: case 'J':
161: ct->ct |= TCG_CT_CONST_S13;
162: break;
163: default:
164: return -1;
165: }
166: ct_str++;
167: *pct_str = ct_str;
168: return 0;
169: }
170:
171: /* test if a constant matches the constraint */
172: static inline int tcg_target_const_match(tcg_target_long val,
173: const TCGArgConstraint *arg_ct)
174: {
175: int ct;
176:
177: ct = arg_ct->ct;
178: if (ct & TCG_CT_CONST)
179: return 1;
180: else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11))
181: return 1;
182: else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13))
183: return 1;
184: else
185: return 0;
186: }
187:
188: #define INSN_OP(x) ((x) << 30)
189: #define INSN_OP2(x) ((x) << 22)
190: #define INSN_OP3(x) ((x) << 19)
191: #define INSN_OPF(x) ((x) << 5)
192: #define INSN_RD(x) ((x) << 25)
193: #define INSN_RS1(x) ((x) << 14)
194: #define INSN_RS2(x) (x)
195: #define INSN_ASI(x) ((x) << 5)
196:
1.1.1.3 root 197: #define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff))
1.1 root 198: #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
1.1.1.2 root 199: #define INSN_OFF19(x) (((x) >> 2) & 0x07ffff)
1.1 root 200: #define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
201:
202: #define INSN_COND(x, a) (((x) << 25) | ((a) << 29))
203: #define COND_N 0x0
204: #define COND_E 0x1
205: #define COND_LE 0x2
206: #define COND_L 0x3
207: #define COND_LEU 0x4
208: #define COND_CS 0x5
209: #define COND_NEG 0x6
210: #define COND_VS 0x7
211: #define COND_A 0x8
212: #define COND_NE 0x9
213: #define COND_G 0xa
214: #define COND_GE 0xb
215: #define COND_GU 0xc
216: #define COND_CC 0xd
217: #define COND_POS 0xe
218: #define COND_VC 0xf
219: #define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
220:
1.1.1.3 root 221: #define MOVCC_ICC (1 << 18)
222: #define MOVCC_XCC (1 << 18 | 1 << 12)
223:
1.1 root 224: #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
1.1.1.3 root 225: #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
1.1 root 226: #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
1.1.1.3 root 227: #define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05))
1.1 root 228: #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02))
229: #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
1.1.1.3 root 230: #define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06))
1.1 root 231: #define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03))
232: #define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04))
233: #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
234: #define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10))
235: #define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
236: #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
237: #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
238: #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
239: #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
240: #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
241: #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
1.1.1.3 root 242: #define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c))
1.1 root 243:
244: #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
245: #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
246: #define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27))
247:
248: #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
249: #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
250: #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
251:
1.1.1.3 root 252: #define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0))
253: #define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0))
1.1 root 254: #define JMPL (INSN_OP(2) | INSN_OP3(0x38))
255: #define SAVE (INSN_OP(2) | INSN_OP3(0x3c))
256: #define RESTORE (INSN_OP(2) | INSN_OP3(0x3d))
257: #define SETHI (INSN_OP(0) | INSN_OP2(0x4))
258: #define CALL INSN_OP(1)
259: #define LDUB (INSN_OP(3) | INSN_OP3(0x01))
260: #define LDSB (INSN_OP(3) | INSN_OP3(0x09))
261: #define LDUH (INSN_OP(3) | INSN_OP3(0x02))
262: #define LDSH (INSN_OP(3) | INSN_OP3(0x0a))
263: #define LDUW (INSN_OP(3) | INSN_OP3(0x00))
264: #define LDSW (INSN_OP(3) | INSN_OP3(0x08))
265: #define LDX (INSN_OP(3) | INSN_OP3(0x0b))
266: #define STB (INSN_OP(3) | INSN_OP3(0x05))
267: #define STH (INSN_OP(3) | INSN_OP3(0x06))
268: #define STW (INSN_OP(3) | INSN_OP3(0x04))
269: #define STX (INSN_OP(3) | INSN_OP3(0x0e))
270: #define LDUBA (INSN_OP(3) | INSN_OP3(0x11))
271: #define LDSBA (INSN_OP(3) | INSN_OP3(0x19))
272: #define LDUHA (INSN_OP(3) | INSN_OP3(0x12))
273: #define LDSHA (INSN_OP(3) | INSN_OP3(0x1a))
274: #define LDUWA (INSN_OP(3) | INSN_OP3(0x10))
275: #define LDSWA (INSN_OP(3) | INSN_OP3(0x18))
276: #define LDXA (INSN_OP(3) | INSN_OP3(0x1b))
277: #define STBA (INSN_OP(3) | INSN_OP3(0x15))
278: #define STHA (INSN_OP(3) | INSN_OP3(0x16))
279: #define STWA (INSN_OP(3) | INSN_OP3(0x14))
280: #define STXA (INSN_OP(3) | INSN_OP3(0x1e))
281:
282: #ifndef ASI_PRIMARY_LITTLE
283: #define ASI_PRIMARY_LITTLE 0x88
284: #endif
285:
286: static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2,
287: int op)
288: {
289: tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
290: INSN_RS2(rs2));
291: }
292:
293: static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1,
294: uint32_t offset, int op)
295: {
296: tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
297: INSN_IMM13(offset));
298: }
299:
1.1.1.3 root 300: static void tcg_out_arithc(TCGContext *s, int rd, int rs1,
301: int val2, int val2const, int op)
302: {
303: tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1)
304: | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2)));
305: }
306:
307: static inline void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg)
1.1 root 308: {
309: tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
310: }
311:
312: static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg)
313: {
314: tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
315: }
316:
317: static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg)
318: {
319: tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR);
320: }
321:
322: static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg)
323: {
1.1.1.3 root 324: if (check_fit_tl(arg, 13))
1.1 root 325: tcg_out_movi_imm13(s, ret, arg);
326: else {
327: tcg_out_sethi(s, ret, arg);
328: if (arg & 0x3ff)
329: tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
330: }
331: }
332:
333: static inline void tcg_out_movi(TCGContext *s, TCGType type,
334: int ret, tcg_target_long arg)
335: {
1.1.1.3 root 336: /* All 32-bit constants, as well as 64-bit constants with
337: no high bits set go through movi_imm32. */
338: if (TCG_TARGET_REG_BITS == 32
339: || type == TCG_TYPE_I32
340: || (arg & ~(tcg_target_long)0xffffffff) == 0) {
341: tcg_out_movi_imm32(s, ret, arg);
342: } else if (check_fit_tl(arg, 13)) {
343: /* A 13-bit constant sign-extended to 64-bits. */
344: tcg_out_movi_imm13(s, ret, arg);
345: } else if (check_fit_tl(arg, 32)) {
346: /* A 32-bit constant sign-extended to 64-bits. */
347: tcg_out_sethi(s, ret, ~arg);
348: tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR);
349: } else {
350: tcg_out_movi_imm32(s, TCG_REG_I4, arg >> (TCG_TARGET_REG_BITS / 2));
1.1 root 351: tcg_out_arithi(s, TCG_REG_I4, TCG_REG_I4, 32, SHIFT_SLLX);
352: tcg_out_movi_imm32(s, ret, arg);
353: tcg_out_arith(s, ret, ret, TCG_REG_I4, ARITH_OR);
354: }
355: }
356:
357: static inline void tcg_out_ld_raw(TCGContext *s, int ret,
358: tcg_target_long arg)
359: {
360: tcg_out_sethi(s, ret, arg);
361: tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
362: INSN_IMM13(arg & 0x3ff));
363: }
364:
365: static inline void tcg_out_ld_ptr(TCGContext *s, int ret,
366: tcg_target_long arg)
367: {
368: if (!check_fit_tl(arg, 10))
369: tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
1.1.1.3 root 370: if (TCG_TARGET_REG_BITS == 64) {
371: tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
372: INSN_IMM13(arg & 0x3ff));
373: } else {
374: tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
375: INSN_IMM13(arg & 0x3ff));
376: }
1.1 root 377: }
378:
379: static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op)
380: {
381: if (check_fit_tl(offset, 13))
382: tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
383: INSN_IMM13(offset));
384: else {
385: tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
386: tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
387: INSN_RS2(addr));
388: }
389: }
390:
391: static inline void tcg_out_ldst_asi(TCGContext *s, int ret, int addr,
392: int offset, int op, int asi)
393: {
394: tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
395: tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
396: INSN_ASI(asi) | INSN_RS2(addr));
397: }
398:
399: static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
400: int arg1, tcg_target_long arg2)
401: {
402: if (type == TCG_TYPE_I32)
403: tcg_out_ldst(s, ret, arg1, arg2, LDUW);
404: else
405: tcg_out_ldst(s, ret, arg1, arg2, LDX);
406: }
407:
408: static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
409: int arg1, tcg_target_long arg2)
410: {
411: if (type == TCG_TYPE_I32)
412: tcg_out_ldst(s, arg, arg1, arg2, STW);
413: else
414: tcg_out_ldst(s, arg, arg1, arg2, STX);
415: }
416:
1.1.1.3 root 417: static inline void tcg_out_sety(TCGContext *s, int rs)
1.1 root 418: {
1.1.1.3 root 419: tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs));
420: }
421:
422: static inline void tcg_out_rdy(TCGContext *s, int rd)
423: {
424: tcg_out32(s, RDY | INSN_RD(rd));
1.1 root 425: }
426:
427: static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
428: {
429: if (val != 0) {
430: if (check_fit_tl(val, 13))
431: tcg_out_arithi(s, reg, reg, val, ARITH_ADD);
432: else {
433: tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, val);
434: tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_ADD);
435: }
436: }
437: }
438:
439: static inline void tcg_out_andi(TCGContext *s, int reg, tcg_target_long val)
440: {
441: if (val != 0) {
442: if (check_fit_tl(val, 13))
443: tcg_out_arithi(s, reg, reg, val, ARITH_AND);
444: else {
445: tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, val);
446: tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_AND);
447: }
448: }
449: }
450:
1.1.1.3 root 451: static void tcg_out_div32(TCGContext *s, int rd, int rs1,
452: int val2, int val2const, int uns)
453: {
454: /* Load Y with the sign/zero extension of RS1 to 64-bits. */
455: if (uns) {
456: tcg_out_sety(s, TCG_REG_G0);
457: } else {
458: tcg_out_arithi(s, TCG_REG_I5, rs1, 31, SHIFT_SRA);
459: tcg_out_sety(s, TCG_REG_I5);
460: }
461:
462: tcg_out_arithc(s, rd, rs1, val2, val2const,
463: uns ? ARITH_UDIV : ARITH_SDIV);
464: }
465:
1.1 root 466: static inline void tcg_out_nop(TCGContext *s)
467: {
468: tcg_out_sethi(s, TCG_REG_G0, 0);
469: }
470:
1.1.1.2 root 471: static void tcg_out_branch_i32(TCGContext *s, int opc, int label_index)
1.1 root 472: {
473: int32_t val;
474: TCGLabel *l = &s->labels[label_index];
475:
476: if (l->has_value) {
477: val = l->u.value - (tcg_target_long)s->code_ptr;
478: tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2)
479: | INSN_OFF22(l->u.value - (unsigned long)s->code_ptr)));
480: } else {
481: tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
482: tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0));
483: }
484: }
485:
1.1.1.3 root 486: #if TCG_TARGET_REG_BITS == 64
1.1.1.2 root 487: static void tcg_out_branch_i64(TCGContext *s, int opc, int label_index)
488: {
489: int32_t val;
490: TCGLabel *l = &s->labels[label_index];
491:
492: if (l->has_value) {
493: val = l->u.value - (tcg_target_long)s->code_ptr;
494: tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
495: (0x5 << 19) |
496: INSN_OFF19(l->u.value - (unsigned long)s->code_ptr)));
497: } else {
498: tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, label_index, 0);
499: tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
500: (0x5 << 19) | 0));
501: }
502: }
503: #endif
504:
1.1 root 505: static const uint8_t tcg_cond_to_bcond[10] = {
506: [TCG_COND_EQ] = COND_E,
507: [TCG_COND_NE] = COND_NE,
508: [TCG_COND_LT] = COND_L,
509: [TCG_COND_GE] = COND_GE,
510: [TCG_COND_LE] = COND_LE,
511: [TCG_COND_GT] = COND_G,
512: [TCG_COND_LTU] = COND_CS,
513: [TCG_COND_GEU] = COND_CC,
514: [TCG_COND_LEU] = COND_LEU,
515: [TCG_COND_GTU] = COND_GU,
516: };
517:
1.1.1.3 root 518: static void tcg_out_cmp(TCGContext *s, TCGArg c1, TCGArg c2, int c2const)
519: {
520: tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC);
521: }
522:
523: static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond,
1.1.1.2 root 524: TCGArg arg1, TCGArg arg2, int const_arg2,
525: int label_index)
526: {
1.1.1.3 root 527: tcg_out_cmp(s, arg1, arg2, const_arg2);
1.1.1.2 root 528: tcg_out_branch_i32(s, tcg_cond_to_bcond[cond], label_index);
529: tcg_out_nop(s);
530: }
531:
1.1.1.3 root 532: #if TCG_TARGET_REG_BITS == 64
533: static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond,
1.1.1.2 root 534: TCGArg arg1, TCGArg arg2, int const_arg2,
535: int label_index)
1.1 root 536: {
1.1.1.3 root 537: tcg_out_cmp(s, arg1, arg2, const_arg2);
1.1.1.2 root 538: tcg_out_branch_i64(s, tcg_cond_to_bcond[cond], label_index);
1.1 root 539: tcg_out_nop(s);
540: }
1.1.1.3 root 541: #else
542: static void tcg_out_brcond2_i32(TCGContext *s, TCGCond cond,
543: TCGArg al, TCGArg ah,
544: TCGArg bl, int blconst,
545: TCGArg bh, int bhconst, int label_dest)
546: {
547: int cc, label_next = gen_new_label();
548:
549: tcg_out_cmp(s, ah, bh, bhconst);
550:
551: /* Note that we fill one of the delay slots with the second compare. */
552: switch (cond) {
553: case TCG_COND_EQ:
554: cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
555: tcg_out_branch_i32(s, cc, label_next);
556: tcg_out_cmp(s, al, bl, blconst);
557: cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_EQ], 0);
558: tcg_out_branch_i32(s, cc, label_dest);
559: break;
560:
561: case TCG_COND_NE:
562: cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
563: tcg_out_branch_i32(s, cc, label_dest);
564: tcg_out_cmp(s, al, bl, blconst);
565: tcg_out_branch_i32(s, cc, label_dest);
566: break;
567:
568: default:
569: /* ??? One could fairly easily special-case 64-bit unsigned
570: compares against 32-bit zero-extended constants. For instance,
571: we know that (unsigned)AH < 0 is false and need not emit it.
572: Similarly, (unsigned)AH > 0 being true implies AH != 0, so the
573: second branch will never be taken. */
574: cc = INSN_COND(tcg_cond_to_bcond[cond], 0);
575: tcg_out_branch_i32(s, cc, label_dest);
576: tcg_out_nop(s);
577: cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
578: tcg_out_branch_i32(s, cc, label_next);
579: tcg_out_cmp(s, al, bl, blconst);
580: cc = INSN_COND(tcg_cond_to_bcond[tcg_unsigned_cond(cond)], 0);
581: tcg_out_branch_i32(s, cc, label_dest);
582: break;
583: }
584: tcg_out_nop(s);
585:
586: tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
587: }
588: #endif
589:
590: static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGArg ret,
591: TCGArg c1, TCGArg c2, int c2const)
592: {
593: TCGArg t;
594:
595: /* For 32-bit comparisons, we can play games with ADDX/SUBX. */
596: switch (cond) {
597: case TCG_COND_EQ:
598: case TCG_COND_NE:
599: if (c2 != 0) {
600: tcg_out_arithc(s, ret, c1, c2, c2const, ARITH_XOR);
601: }
602: c1 = TCG_REG_G0, c2 = ret, c2const = 0;
603: cond = (cond == TCG_COND_EQ ? TCG_COND_LEU : TCG_COND_LTU);
604: break;
605:
606: case TCG_COND_GTU:
607: case TCG_COND_GEU:
608: if (c2const && c2 != 0) {
609: tcg_out_movi_imm13(s, TCG_REG_I5, c2);
610: c2 = TCG_REG_I5;
611: }
612: t = c1, c1 = c2, c2 = t, c2const = 0;
613: cond = tcg_swap_cond(cond);
614: break;
615:
616: case TCG_COND_LTU:
617: case TCG_COND_LEU:
618: break;
619:
620: default:
621: tcg_out_cmp(s, c1, c2, c2const);
622: #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
623: tcg_out_movi_imm13(s, ret, 0);
624: tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
625: | INSN_RS1(tcg_cond_to_bcond[cond])
626: | MOVCC_ICC | INSN_IMM11(1));
627: #else
628: t = gen_new_label();
629: tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), t);
630: tcg_out_movi_imm13(s, ret, 1);
631: tcg_out_movi_imm13(s, ret, 0);
632: tcg_out_label(s, t, (tcg_target_long)s->code_ptr);
633: #endif
634: return;
635: }
636:
637: tcg_out_cmp(s, c1, c2, c2const);
638: if (cond == TCG_COND_LTU) {
639: tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDX);
640: } else {
641: tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBX);
642: }
643: }
644:
645: #if TCG_TARGET_REG_BITS == 64
646: static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGArg ret,
647: TCGArg c1, TCGArg c2, int c2const)
648: {
649: tcg_out_cmp(s, c1, c2, c2const);
650: tcg_out_movi_imm13(s, ret, 0);
651: tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
652: | INSN_RS1(tcg_cond_to_bcond[cond])
653: | MOVCC_XCC | INSN_IMM11(1));
654: }
655: #else
656: static void tcg_out_setcond2_i32(TCGContext *s, TCGCond cond, TCGArg ret,
657: TCGArg al, TCGArg ah,
658: TCGArg bl, int blconst,
659: TCGArg bh, int bhconst)
660: {
661: int lab;
662:
663: switch (cond) {
664: case TCG_COND_EQ:
665: tcg_out_setcond_i32(s, TCG_COND_EQ, TCG_REG_I5, al, bl, blconst);
666: tcg_out_setcond_i32(s, TCG_COND_EQ, ret, ah, bh, bhconst);
667: tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_AND);
668: break;
669:
670: case TCG_COND_NE:
671: tcg_out_setcond_i32(s, TCG_COND_NE, TCG_REG_I5, al, al, blconst);
672: tcg_out_setcond_i32(s, TCG_COND_NE, ret, ah, bh, bhconst);
673: tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_OR);
674: break;
675:
676: default:
677: lab = gen_new_label();
678:
679: tcg_out_cmp(s, ah, bh, bhconst);
680: tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), lab);
681: tcg_out_movi_imm13(s, ret, 1);
682: tcg_out_branch_i32(s, INSN_COND(COND_NE, 1), lab);
683: tcg_out_movi_imm13(s, ret, 0);
684:
685: tcg_out_setcond_i32(s, tcg_unsigned_cond(cond), ret, al, bl, blconst);
686:
687: tcg_out_label(s, lab, (tcg_target_long)s->code_ptr);
688: break;
689: }
690: }
1.1.1.2 root 691: #endif
1.1 root 692:
693: /* Generate global QEMU prologue and epilogue code */
1.1.1.3 root 694: static void tcg_target_qemu_prologue(TCGContext *s)
1.1 root 695: {
1.1.1.4 ! root 696: tcg_set_frame(s, TCG_REG_I6, TCG_TARGET_CALL_STACK_OFFSET,
! 697: CPU_TEMP_BUF_NLONGS * (int)sizeof(long));
1.1 root 698: tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
1.1.1.4 ! root 699: INSN_IMM13(-(TCG_TARGET_STACK_MINFRAME +
! 700: CPU_TEMP_BUF_NLONGS * (int)sizeof(long))));
! 701: tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I1) |
1.1 root 702: INSN_RS2(TCG_REG_G0));
1.1.1.4 ! root 703: tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_I0);
1.1 root 704: }
705:
706: #if defined(CONFIG_SOFTMMU)
707:
708: #include "../../softmmu_defs.h"
709:
710: static const void * const qemu_ld_helpers[4] = {
711: __ldb_mmu,
712: __ldw_mmu,
713: __ldl_mmu,
714: __ldq_mmu,
715: };
716:
717: static const void * const qemu_st_helpers[4] = {
718: __stb_mmu,
719: __stw_mmu,
720: __stl_mmu,
721: __stq_mmu,
722: };
723: #endif
724:
725: #if TARGET_LONG_BITS == 32
726: #define TARGET_LD_OP LDUW
727: #else
728: #define TARGET_LD_OP LDX
729: #endif
730:
1.1.1.3 root 731: #if defined(CONFIG_SOFTMMU)
732: #if HOST_LONG_BITS == 32
1.1 root 733: #define TARGET_ADDEND_LD_OP LDUW
734: #else
735: #define TARGET_ADDEND_LD_OP LDX
736: #endif
1.1.1.3 root 737: #endif
1.1 root 738:
739: #ifdef __arch64__
740: #define HOST_LD_OP LDX
741: #define HOST_ST_OP STX
742: #define HOST_SLL_OP SHIFT_SLLX
743: #define HOST_SRA_OP SHIFT_SRAX
744: #else
745: #define HOST_LD_OP LDUW
746: #define HOST_ST_OP STW
747: #define HOST_SLL_OP SHIFT_SLL
748: #define HOST_SRA_OP SHIFT_SRA
749: #endif
750:
751: static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
752: int opc)
753: {
754: int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
755: #if defined(CONFIG_SOFTMMU)
756: uint32_t *label1_ptr, *label2_ptr;
757: #endif
758:
759: data_reg = *args++;
760: addr_reg = *args++;
761: mem_index = *args;
762: s_bits = opc & 3;
763:
764: arg0 = TCG_REG_O0;
765: arg1 = TCG_REG_O1;
766: arg2 = TCG_REG_O2;
767:
768: #if defined(CONFIG_SOFTMMU)
769: /* srl addr_reg, x, arg1 */
770: tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
771: SHIFT_SRL);
772: /* and addr_reg, x, arg0 */
773: tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
774: ARITH_AND);
775:
776: /* and arg1, x, arg1 */
777: tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
778:
779: /* add arg1, x, arg1 */
780: tcg_out_addi(s, arg1, offsetof(CPUState,
781: tlb_table[mem_index][0].addr_read));
782:
783: /* add env, arg1, arg1 */
784: tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
785:
786: /* ld [arg1], arg2 */
787: tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
788: INSN_RS2(TCG_REG_G0));
789:
790: /* subcc arg0, arg2, %g0 */
791: tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC);
792:
793: /* will become:
1.1.1.2 root 794: be label1
795: or
796: be,pt %xcc label1 */
1.1 root 797: label1_ptr = (uint32_t *)s->code_ptr;
798: tcg_out32(s, 0);
799:
800: /* mov (delay slot) */
1.1.1.3 root 801: tcg_out_mov(s, TCG_TYPE_PTR, arg0, addr_reg);
1.1 root 802:
803: /* mov */
804: tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
805:
806: /* XXX: move that code at the end of the TB */
807: /* qemu_ld_helper[s_bits](arg0, arg1) */
808: tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits]
809: - (tcg_target_ulong)s->code_ptr) >> 2)
810: & 0x3fffffff));
811: /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
812: global registers */
813: // delay slot
814: tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1.1.1.2 root 815: TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
816: sizeof(long), HOST_ST_OP);
1.1 root 817: tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1.1.1.2 root 818: TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
819: sizeof(long), HOST_LD_OP);
1.1 root 820:
821: /* data_reg = sign_extend(arg0) */
822: switch(opc) {
823: case 0 | 4:
824: /* sll arg0, 24/56, data_reg */
825: tcg_out_arithi(s, data_reg, arg0, (int)sizeof(tcg_target_long) * 8 - 8,
826: HOST_SLL_OP);
827: /* sra data_reg, 24/56, data_reg */
828: tcg_out_arithi(s, data_reg, data_reg,
829: (int)sizeof(tcg_target_long) * 8 - 8, HOST_SRA_OP);
830: break;
831: case 1 | 4:
832: /* sll arg0, 16/48, data_reg */
833: tcg_out_arithi(s, data_reg, arg0,
834: (int)sizeof(tcg_target_long) * 8 - 16, HOST_SLL_OP);
835: /* sra data_reg, 16/48, data_reg */
836: tcg_out_arithi(s, data_reg, data_reg,
837: (int)sizeof(tcg_target_long) * 8 - 16, HOST_SRA_OP);
838: break;
839: case 2 | 4:
840: /* sll arg0, 32, data_reg */
841: tcg_out_arithi(s, data_reg, arg0, 32, HOST_SLL_OP);
842: /* sra data_reg, 32, data_reg */
843: tcg_out_arithi(s, data_reg, data_reg, 32, HOST_SRA_OP);
844: break;
845: case 0:
846: case 1:
847: case 2:
848: case 3:
849: default:
850: /* mov */
1.1.1.3 root 851: tcg_out_mov(s, TCG_TYPE_REG, data_reg, arg0);
1.1 root 852: break;
853: }
854:
855: /* will become:
856: ba label2 */
857: label2_ptr = (uint32_t *)s->code_ptr;
858: tcg_out32(s, 0);
859:
860: /* nop (delay slot */
861: tcg_out_nop(s);
862:
863: /* label1: */
1.1.1.2 root 864: #if TARGET_LONG_BITS == 32
865: /* be label1 */
1.1 root 866: *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
867: INSN_OFF22((unsigned long)s->code_ptr -
868: (unsigned long)label1_ptr));
1.1.1.2 root 869: #else
870: /* be,pt %xcc label1 */
871: *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) |
872: (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr -
873: (unsigned long)label1_ptr));
874: #endif
1.1 root 875:
876: /* ld [arg1 + x], arg1 */
877: tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) -
878: offsetof(CPUTLBEntry, addr_read), TARGET_ADDEND_LD_OP);
879:
880: #if TARGET_LONG_BITS == 32
881: /* and addr_reg, x, arg0 */
882: tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
883: tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND);
884: /* add arg0, arg1, arg0 */
885: tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD);
886: #else
887: /* add addr_reg, arg1, arg0 */
888: tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD);
889: #endif
890:
891: #else
892: arg0 = addr_reg;
893: #endif
894:
895: switch(opc) {
896: case 0:
897: /* ldub [arg0], data_reg */
898: tcg_out_ldst(s, data_reg, arg0, 0, LDUB);
899: break;
900: case 0 | 4:
901: /* ldsb [arg0], data_reg */
902: tcg_out_ldst(s, data_reg, arg0, 0, LDSB);
903: break;
904: case 1:
905: #ifdef TARGET_WORDS_BIGENDIAN
906: /* lduh [arg0], data_reg */
907: tcg_out_ldst(s, data_reg, arg0, 0, LDUH);
908: #else
909: /* lduha [arg0] ASI_PRIMARY_LITTLE, data_reg */
910: tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUHA, ASI_PRIMARY_LITTLE);
911: #endif
912: break;
913: case 1 | 4:
914: #ifdef TARGET_WORDS_BIGENDIAN
915: /* ldsh [arg0], data_reg */
916: tcg_out_ldst(s, data_reg, arg0, 0, LDSH);
917: #else
918: /* ldsha [arg0] ASI_PRIMARY_LITTLE, data_reg */
919: tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSHA, ASI_PRIMARY_LITTLE);
920: #endif
921: break;
922: case 2:
923: #ifdef TARGET_WORDS_BIGENDIAN
924: /* lduw [arg0], data_reg */
925: tcg_out_ldst(s, data_reg, arg0, 0, LDUW);
926: #else
927: /* lduwa [arg0] ASI_PRIMARY_LITTLE, data_reg */
928: tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUWA, ASI_PRIMARY_LITTLE);
929: #endif
930: break;
931: case 2 | 4:
932: #ifdef TARGET_WORDS_BIGENDIAN
933: /* ldsw [arg0], data_reg */
934: tcg_out_ldst(s, data_reg, arg0, 0, LDSW);
935: #else
936: /* ldswa [arg0] ASI_PRIMARY_LITTLE, data_reg */
937: tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSWA, ASI_PRIMARY_LITTLE);
938: #endif
939: break;
940: case 3:
941: #ifdef TARGET_WORDS_BIGENDIAN
942: /* ldx [arg0], data_reg */
943: tcg_out_ldst(s, data_reg, arg0, 0, LDX);
944: #else
945: /* ldxa [arg0] ASI_PRIMARY_LITTLE, data_reg */
946: tcg_out_ldst_asi(s, data_reg, arg0, 0, LDXA, ASI_PRIMARY_LITTLE);
947: #endif
948: break;
949: default:
950: tcg_abort();
951: }
952:
953: #if defined(CONFIG_SOFTMMU)
954: /* label2: */
955: *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
956: INSN_OFF22((unsigned long)s->code_ptr -
957: (unsigned long)label2_ptr));
958: #endif
959: }
960:
961: static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
962: int opc)
963: {
964: int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
965: #if defined(CONFIG_SOFTMMU)
966: uint32_t *label1_ptr, *label2_ptr;
967: #endif
968:
969: data_reg = *args++;
970: addr_reg = *args++;
971: mem_index = *args;
972:
973: s_bits = opc;
974:
975: arg0 = TCG_REG_O0;
976: arg1 = TCG_REG_O1;
977: arg2 = TCG_REG_O2;
978:
979: #if defined(CONFIG_SOFTMMU)
980: /* srl addr_reg, x, arg1 */
981: tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
982: SHIFT_SRL);
983:
984: /* and addr_reg, x, arg0 */
985: tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
986: ARITH_AND);
987:
988: /* and arg1, x, arg1 */
989: tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
990:
991: /* add arg1, x, arg1 */
992: tcg_out_addi(s, arg1, offsetof(CPUState,
993: tlb_table[mem_index][0].addr_write));
994:
995: /* add env, arg1, arg1 */
996: tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
997:
998: /* ld [arg1], arg2 */
999: tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
1000: INSN_RS2(TCG_REG_G0));
1001:
1002: /* subcc arg0, arg2, %g0 */
1003: tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC);
1004:
1005: /* will become:
1.1.1.2 root 1006: be label1
1007: or
1008: be,pt %xcc label1 */
1.1 root 1009: label1_ptr = (uint32_t *)s->code_ptr;
1010: tcg_out32(s, 0);
1011:
1012: /* mov (delay slot) */
1.1.1.3 root 1013: tcg_out_mov(s, TCG_TYPE_PTR, arg0, addr_reg);
1.1 root 1014:
1015: /* mov */
1.1.1.3 root 1016: tcg_out_mov(s, TCG_TYPE_REG, arg1, data_reg);
1.1 root 1017:
1018: /* mov */
1019: tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index);
1020:
1021: /* XXX: move that code at the end of the TB */
1022: /* qemu_st_helper[s_bits](arg0, arg1, arg2) */
1023: tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits]
1024: - (tcg_target_ulong)s->code_ptr) >> 2)
1025: & 0x3fffffff));
1026: /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
1027: global registers */
1028: // delay slot
1029: tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1.1.1.2 root 1030: TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1031: sizeof(long), HOST_ST_OP);
1.1 root 1032: tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1.1.1.2 root 1033: TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1034: sizeof(long), HOST_LD_OP);
1.1 root 1035:
1036: /* will become:
1037: ba label2 */
1038: label2_ptr = (uint32_t *)s->code_ptr;
1039: tcg_out32(s, 0);
1040:
1041: /* nop (delay slot) */
1042: tcg_out_nop(s);
1043:
1.1.1.2 root 1044: #if TARGET_LONG_BITS == 32
1045: /* be label1 */
1.1 root 1046: *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
1047: INSN_OFF22((unsigned long)s->code_ptr -
1048: (unsigned long)label1_ptr));
1.1.1.2 root 1049: #else
1050: /* be,pt %xcc label1 */
1051: *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) |
1052: (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr -
1053: (unsigned long)label1_ptr));
1054: #endif
1.1 root 1055:
1056: /* ld [arg1 + x], arg1 */
1057: tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) -
1058: offsetof(CPUTLBEntry, addr_write), TARGET_ADDEND_LD_OP);
1059:
1060: #if TARGET_LONG_BITS == 32
1061: /* and addr_reg, x, arg0 */
1062: tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
1063: tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND);
1064: /* add arg0, arg1, arg0 */
1065: tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD);
1066: #else
1067: /* add addr_reg, arg1, arg0 */
1068: tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD);
1069: #endif
1070:
1071: #else
1072: arg0 = addr_reg;
1073: #endif
1074:
1075: switch(opc) {
1076: case 0:
1077: /* stb data_reg, [arg0] */
1078: tcg_out_ldst(s, data_reg, arg0, 0, STB);
1079: break;
1080: case 1:
1081: #ifdef TARGET_WORDS_BIGENDIAN
1082: /* sth data_reg, [arg0] */
1083: tcg_out_ldst(s, data_reg, arg0, 0, STH);
1084: #else
1085: /* stha data_reg, [arg0] ASI_PRIMARY_LITTLE */
1086: tcg_out_ldst_asi(s, data_reg, arg0, 0, STHA, ASI_PRIMARY_LITTLE);
1087: #endif
1088: break;
1089: case 2:
1090: #ifdef TARGET_WORDS_BIGENDIAN
1091: /* stw data_reg, [arg0] */
1092: tcg_out_ldst(s, data_reg, arg0, 0, STW);
1093: #else
1094: /* stwa data_reg, [arg0] ASI_PRIMARY_LITTLE */
1095: tcg_out_ldst_asi(s, data_reg, arg0, 0, STWA, ASI_PRIMARY_LITTLE);
1096: #endif
1097: break;
1098: case 3:
1099: #ifdef TARGET_WORDS_BIGENDIAN
1100: /* stx data_reg, [arg0] */
1101: tcg_out_ldst(s, data_reg, arg0, 0, STX);
1102: #else
1103: /* stxa data_reg, [arg0] ASI_PRIMARY_LITTLE */
1104: tcg_out_ldst_asi(s, data_reg, arg0, 0, STXA, ASI_PRIMARY_LITTLE);
1105: #endif
1106: break;
1107: default:
1108: tcg_abort();
1109: }
1110:
1111: #if defined(CONFIG_SOFTMMU)
1112: /* label2: */
1113: *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
1114: INSN_OFF22((unsigned long)s->code_ptr -
1115: (unsigned long)label2_ptr));
1116: #endif
1117: }
1118:
1.1.1.3 root 1119: static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
1.1 root 1120: const int *const_args)
1121: {
1122: int c;
1123:
1124: switch (opc) {
1125: case INDEX_op_exit_tb:
1126: tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
1127: tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) |
1128: INSN_IMM13(8));
1129: tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) |
1130: INSN_RS2(TCG_REG_G0));
1131: break;
1132: case INDEX_op_goto_tb:
1133: if (s->tb_jmp_offset) {
1134: /* direct jump method */
1135: tcg_out_sethi(s, TCG_REG_I5, args[0] & 0xffffe000);
1136: tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
1137: INSN_IMM13((args[0] & 0x1fff)));
1138: s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1139: } else {
1140: /* indirect jump method */
1141: tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
1142: tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
1143: INSN_RS2(TCG_REG_G0));
1144: }
1145: tcg_out_nop(s);
1146: s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1147: break;
1148: case INDEX_op_call:
1149: if (const_args[0])
1150: tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
1151: - (tcg_target_ulong)s->code_ptr) >> 2)
1152: & 0x3fffffff));
1153: else {
1154: tcg_out_ld_ptr(s, TCG_REG_I5,
1155: (tcg_target_long)(s->tb_next + args[0]));
1156: tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) |
1157: INSN_RS2(TCG_REG_G0));
1158: }
1159: /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
1160: global registers */
1161: // delay slot
1162: tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1.1.1.2 root 1163: TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1164: sizeof(long), HOST_ST_OP);
1.1 root 1165: tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1.1.1.2 root 1166: TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1167: sizeof(long), HOST_LD_OP);
1.1 root 1168: break;
1169: case INDEX_op_jmp:
1170: case INDEX_op_br:
1.1.1.2 root 1171: tcg_out_branch_i32(s, COND_A, args[0]);
1.1 root 1172: tcg_out_nop(s);
1173: break;
1174: case INDEX_op_movi_i32:
1175: tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
1176: break;
1177:
1.1.1.3 root 1178: #if TCG_TARGET_REG_BITS == 64
1.1 root 1179: #define OP_32_64(x) \
1.1.1.3 root 1180: glue(glue(case INDEX_op_, x), _i32): \
1181: glue(glue(case INDEX_op_, x), _i64)
1.1 root 1182: #else
1183: #define OP_32_64(x) \
1.1.1.3 root 1184: glue(glue(case INDEX_op_, x), _i32)
1.1 root 1185: #endif
1.1.1.3 root 1186: OP_32_64(ld8u):
1.1 root 1187: tcg_out_ldst(s, args[0], args[1], args[2], LDUB);
1188: break;
1.1.1.3 root 1189: OP_32_64(ld8s):
1.1 root 1190: tcg_out_ldst(s, args[0], args[1], args[2], LDSB);
1191: break;
1.1.1.3 root 1192: OP_32_64(ld16u):
1.1 root 1193: tcg_out_ldst(s, args[0], args[1], args[2], LDUH);
1194: break;
1.1.1.3 root 1195: OP_32_64(ld16s):
1.1 root 1196: tcg_out_ldst(s, args[0], args[1], args[2], LDSH);
1197: break;
1198: case INDEX_op_ld_i32:
1.1.1.3 root 1199: #if TCG_TARGET_REG_BITS == 64
1.1 root 1200: case INDEX_op_ld32u_i64:
1201: #endif
1202: tcg_out_ldst(s, args[0], args[1], args[2], LDUW);
1203: break;
1.1.1.3 root 1204: OP_32_64(st8):
1.1 root 1205: tcg_out_ldst(s, args[0], args[1], args[2], STB);
1206: break;
1.1.1.3 root 1207: OP_32_64(st16):
1.1 root 1208: tcg_out_ldst(s, args[0], args[1], args[2], STH);
1209: break;
1210: case INDEX_op_st_i32:
1.1.1.3 root 1211: #if TCG_TARGET_REG_BITS == 64
1.1 root 1212: case INDEX_op_st32_i64:
1213: #endif
1214: tcg_out_ldst(s, args[0], args[1], args[2], STW);
1215: break;
1.1.1.3 root 1216: OP_32_64(add):
1.1 root 1217: c = ARITH_ADD;
1.1.1.3 root 1218: goto gen_arith;
1219: OP_32_64(sub):
1.1 root 1220: c = ARITH_SUB;
1.1.1.3 root 1221: goto gen_arith;
1222: OP_32_64(and):
1.1 root 1223: c = ARITH_AND;
1.1.1.3 root 1224: goto gen_arith;
1225: OP_32_64(andc):
1226: c = ARITH_ANDN;
1227: goto gen_arith;
1228: OP_32_64(or):
1.1 root 1229: c = ARITH_OR;
1.1.1.3 root 1230: goto gen_arith;
1231: OP_32_64(orc):
1232: c = ARITH_ORN;
1233: goto gen_arith;
1234: OP_32_64(xor):
1.1 root 1235: c = ARITH_XOR;
1.1.1.3 root 1236: goto gen_arith;
1.1 root 1237: case INDEX_op_shl_i32:
1238: c = SHIFT_SLL;
1.1.1.3 root 1239: goto gen_arith;
1.1 root 1240: case INDEX_op_shr_i32:
1241: c = SHIFT_SRL;
1.1.1.3 root 1242: goto gen_arith;
1.1 root 1243: case INDEX_op_sar_i32:
1244: c = SHIFT_SRA;
1.1.1.3 root 1245: goto gen_arith;
1.1 root 1246: case INDEX_op_mul_i32:
1247: c = ARITH_UMUL;
1.1.1.3 root 1248: goto gen_arith;
1249:
1250: OP_32_64(neg):
1251: c = ARITH_SUB;
1252: goto gen_arith1;
1253: OP_32_64(not):
1254: c = ARITH_ORN;
1255: goto gen_arith1;
1256:
1257: case INDEX_op_div_i32:
1258: tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 0);
1259: break;
1260: case INDEX_op_divu_i32:
1261: tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 1);
1262: break;
1263:
1264: case INDEX_op_rem_i32:
1265: case INDEX_op_remu_i32:
1266: tcg_out_div32(s, TCG_REG_I5, args[1], args[2], const_args[2],
1267: opc == INDEX_op_remu_i32);
1268: tcg_out_arithc(s, TCG_REG_I5, TCG_REG_I5, args[2], const_args[2],
1269: ARITH_UMUL);
1270: tcg_out_arith(s, args[0], args[1], TCG_REG_I5, ARITH_SUB);
1271: break;
1.1 root 1272:
1273: case INDEX_op_brcond_i32:
1.1.1.2 root 1274: tcg_out_brcond_i32(s, args[2], args[0], args[1], const_args[1],
1275: args[3]);
1.1 root 1276: break;
1.1.1.3 root 1277: case INDEX_op_setcond_i32:
1278: tcg_out_setcond_i32(s, args[3], args[0], args[1],
1279: args[2], const_args[2]);
1280: break;
1281:
1282: #if TCG_TARGET_REG_BITS == 32
1283: case INDEX_op_brcond2_i32:
1284: tcg_out_brcond2_i32(s, args[4], args[0], args[1],
1285: args[2], const_args[2],
1286: args[3], const_args[3], args[5]);
1287: break;
1288: case INDEX_op_setcond2_i32:
1289: tcg_out_setcond2_i32(s, args[5], args[0], args[1], args[2],
1290: args[3], const_args[3],
1291: args[4], const_args[4]);
1292: break;
1293: case INDEX_op_add2_i32:
1294: tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
1295: ARITH_ADDCC);
1296: tcg_out_arithc(s, args[1], args[3], args[5], const_args[5],
1297: ARITH_ADDX);
1298: break;
1299: case INDEX_op_sub2_i32:
1300: tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
1301: ARITH_SUBCC);
1302: tcg_out_arithc(s, args[1], args[3], args[5], const_args[5],
1303: ARITH_SUBX);
1304: break;
1305: case INDEX_op_mulu2_i32:
1306: tcg_out_arithc(s, args[0], args[2], args[3], const_args[3],
1307: ARITH_UMUL);
1308: tcg_out_rdy(s, args[1]);
1309: break;
1310: #endif
1.1 root 1311:
1312: case INDEX_op_qemu_ld8u:
1313: tcg_out_qemu_ld(s, args, 0);
1314: break;
1315: case INDEX_op_qemu_ld8s:
1316: tcg_out_qemu_ld(s, args, 0 | 4);
1317: break;
1318: case INDEX_op_qemu_ld16u:
1319: tcg_out_qemu_ld(s, args, 1);
1320: break;
1321: case INDEX_op_qemu_ld16s:
1322: tcg_out_qemu_ld(s, args, 1 | 4);
1323: break;
1.1.1.3 root 1324: case INDEX_op_qemu_ld32:
1325: #if TCG_TARGET_REG_BITS == 64
1.1 root 1326: case INDEX_op_qemu_ld32u:
1.1.1.3 root 1327: #endif
1.1 root 1328: tcg_out_qemu_ld(s, args, 2);
1329: break;
1.1.1.3 root 1330: #if TCG_TARGET_REG_BITS == 64
1.1 root 1331: case INDEX_op_qemu_ld32s:
1332: tcg_out_qemu_ld(s, args, 2 | 4);
1333: break;
1.1.1.3 root 1334: #endif
1.1 root 1335: case INDEX_op_qemu_st8:
1336: tcg_out_qemu_st(s, args, 0);
1337: break;
1338: case INDEX_op_qemu_st16:
1339: tcg_out_qemu_st(s, args, 1);
1340: break;
1341: case INDEX_op_qemu_st32:
1342: tcg_out_qemu_st(s, args, 2);
1343: break;
1344:
1.1.1.3 root 1345: #if TCG_TARGET_REG_BITS == 64
1.1 root 1346: case INDEX_op_movi_i64:
1347: tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1348: break;
1349: case INDEX_op_ld32s_i64:
1350: tcg_out_ldst(s, args[0], args[1], args[2], LDSW);
1351: break;
1352: case INDEX_op_ld_i64:
1353: tcg_out_ldst(s, args[0], args[1], args[2], LDX);
1354: break;
1355: case INDEX_op_st_i64:
1356: tcg_out_ldst(s, args[0], args[1], args[2], STX);
1357: break;
1358: case INDEX_op_shl_i64:
1359: c = SHIFT_SLLX;
1.1.1.3 root 1360: goto gen_arith;
1.1 root 1361: case INDEX_op_shr_i64:
1362: c = SHIFT_SRLX;
1.1.1.3 root 1363: goto gen_arith;
1.1 root 1364: case INDEX_op_sar_i64:
1365: c = SHIFT_SRAX;
1.1.1.3 root 1366: goto gen_arith;
1.1 root 1367: case INDEX_op_mul_i64:
1368: c = ARITH_MULX;
1.1.1.3 root 1369: goto gen_arith;
1370: case INDEX_op_div_i64:
1.1 root 1371: c = ARITH_SDIVX;
1.1.1.3 root 1372: goto gen_arith;
1373: case INDEX_op_divu_i64:
1.1 root 1374: c = ARITH_UDIVX;
1.1.1.3 root 1375: goto gen_arith;
1376: case INDEX_op_rem_i64:
1377: case INDEX_op_remu_i64:
1378: tcg_out_arithc(s, TCG_REG_I5, args[1], args[2], const_args[2],
1379: opc == INDEX_op_rem_i64 ? ARITH_SDIVX : ARITH_UDIVX);
1380: tcg_out_arithc(s, TCG_REG_I5, TCG_REG_I5, args[2], const_args[2],
1381: ARITH_MULX);
1382: tcg_out_arith(s, args[0], args[1], TCG_REG_I5, ARITH_SUB);
1383: break;
1384: case INDEX_op_ext32s_i64:
1385: if (const_args[1]) {
1386: tcg_out_movi(s, TCG_TYPE_I64, args[0], (int32_t)args[1]);
1387: } else {
1388: tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRA);
1389: }
1390: break;
1391: case INDEX_op_ext32u_i64:
1392: if (const_args[1]) {
1393: tcg_out_movi_imm32(s, args[0], args[1]);
1394: } else {
1395: tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRL);
1396: }
1397: break;
1.1 root 1398:
1399: case INDEX_op_brcond_i64:
1.1.1.2 root 1400: tcg_out_brcond_i64(s, args[2], args[0], args[1], const_args[1],
1401: args[3]);
1.1 root 1402: break;
1.1.1.3 root 1403: case INDEX_op_setcond_i64:
1404: tcg_out_setcond_i64(s, args[3], args[0], args[1],
1405: args[2], const_args[2]);
1406: break;
1407:
1.1 root 1408: case INDEX_op_qemu_ld64:
1409: tcg_out_qemu_ld(s, args, 3);
1410: break;
1411: case INDEX_op_qemu_st64:
1412: tcg_out_qemu_st(s, args, 3);
1413: break;
1414:
1415: #endif
1.1.1.3 root 1416: gen_arith:
1417: tcg_out_arithc(s, args[0], args[1], args[2], const_args[2], c);
1.1 root 1418: break;
1419:
1.1.1.3 root 1420: gen_arith1:
1421: tcg_out_arithc(s, args[0], TCG_REG_G0, args[1], const_args[1], c);
1422: break;
1423:
1.1 root 1424: default:
1425: fprintf(stderr, "unknown opcode 0x%x\n", opc);
1426: tcg_abort();
1427: }
1428: }
1429:
1430: static const TCGTargetOpDef sparc_op_defs[] = {
1431: { INDEX_op_exit_tb, { } },
1432: { INDEX_op_goto_tb, { } },
1433: { INDEX_op_call, { "ri" } },
1434: { INDEX_op_jmp, { "ri" } },
1435: { INDEX_op_br, { } },
1436:
1437: { INDEX_op_mov_i32, { "r", "r" } },
1438: { INDEX_op_movi_i32, { "r" } },
1439: { INDEX_op_ld8u_i32, { "r", "r" } },
1440: { INDEX_op_ld8s_i32, { "r", "r" } },
1441: { INDEX_op_ld16u_i32, { "r", "r" } },
1442: { INDEX_op_ld16s_i32, { "r", "r" } },
1443: { INDEX_op_ld_i32, { "r", "r" } },
1444: { INDEX_op_st8_i32, { "r", "r" } },
1445: { INDEX_op_st16_i32, { "r", "r" } },
1446: { INDEX_op_st_i32, { "r", "r" } },
1447:
1448: { INDEX_op_add_i32, { "r", "r", "rJ" } },
1449: { INDEX_op_mul_i32, { "r", "r", "rJ" } },
1.1.1.3 root 1450: { INDEX_op_div_i32, { "r", "r", "rJ" } },
1451: { INDEX_op_divu_i32, { "r", "r", "rJ" } },
1452: { INDEX_op_rem_i32, { "r", "r", "rJ" } },
1453: { INDEX_op_remu_i32, { "r", "r", "rJ" } },
1.1 root 1454: { INDEX_op_sub_i32, { "r", "r", "rJ" } },
1455: { INDEX_op_and_i32, { "r", "r", "rJ" } },
1.1.1.3 root 1456: { INDEX_op_andc_i32, { "r", "r", "rJ" } },
1.1 root 1457: { INDEX_op_or_i32, { "r", "r", "rJ" } },
1.1.1.3 root 1458: { INDEX_op_orc_i32, { "r", "r", "rJ" } },
1.1 root 1459: { INDEX_op_xor_i32, { "r", "r", "rJ" } },
1460:
1461: { INDEX_op_shl_i32, { "r", "r", "rJ" } },
1462: { INDEX_op_shr_i32, { "r", "r", "rJ" } },
1463: { INDEX_op_sar_i32, { "r", "r", "rJ" } },
1464:
1.1.1.3 root 1465: { INDEX_op_neg_i32, { "r", "rJ" } },
1466: { INDEX_op_not_i32, { "r", "rJ" } },
1467:
1468: { INDEX_op_brcond_i32, { "r", "rJ" } },
1469: { INDEX_op_setcond_i32, { "r", "r", "rJ" } },
1470:
1471: #if TCG_TARGET_REG_BITS == 32
1472: { INDEX_op_brcond2_i32, { "r", "r", "rJ", "rJ" } },
1473: { INDEX_op_setcond2_i32, { "r", "r", "r", "rJ", "rJ" } },
1474: { INDEX_op_add2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
1475: { INDEX_op_sub2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
1476: { INDEX_op_mulu2_i32, { "r", "r", "r", "rJ" } },
1477: #endif
1.1 root 1478:
1479: { INDEX_op_qemu_ld8u, { "r", "L" } },
1480: { INDEX_op_qemu_ld8s, { "r", "L" } },
1481: { INDEX_op_qemu_ld16u, { "r", "L" } },
1482: { INDEX_op_qemu_ld16s, { "r", "L" } },
1.1.1.3 root 1483: { INDEX_op_qemu_ld32, { "r", "L" } },
1484: #if TCG_TARGET_REG_BITS == 64
1.1 root 1485: { INDEX_op_qemu_ld32u, { "r", "L" } },
1486: { INDEX_op_qemu_ld32s, { "r", "L" } },
1.1.1.3 root 1487: #endif
1.1 root 1488:
1489: { INDEX_op_qemu_st8, { "L", "L" } },
1490: { INDEX_op_qemu_st16, { "L", "L" } },
1491: { INDEX_op_qemu_st32, { "L", "L" } },
1492:
1.1.1.3 root 1493: #if TCG_TARGET_REG_BITS == 64
1.1 root 1494: { INDEX_op_mov_i64, { "r", "r" } },
1495: { INDEX_op_movi_i64, { "r" } },
1496: { INDEX_op_ld8u_i64, { "r", "r" } },
1497: { INDEX_op_ld8s_i64, { "r", "r" } },
1498: { INDEX_op_ld16u_i64, { "r", "r" } },
1499: { INDEX_op_ld16s_i64, { "r", "r" } },
1500: { INDEX_op_ld32u_i64, { "r", "r" } },
1501: { INDEX_op_ld32s_i64, { "r", "r" } },
1502: { INDEX_op_ld_i64, { "r", "r" } },
1503: { INDEX_op_st8_i64, { "r", "r" } },
1504: { INDEX_op_st16_i64, { "r", "r" } },
1505: { INDEX_op_st32_i64, { "r", "r" } },
1506: { INDEX_op_st_i64, { "r", "r" } },
1507: { INDEX_op_qemu_ld64, { "L", "L" } },
1508: { INDEX_op_qemu_st64, { "L", "L" } },
1509:
1510: { INDEX_op_add_i64, { "r", "r", "rJ" } },
1511: { INDEX_op_mul_i64, { "r", "r", "rJ" } },
1.1.1.3 root 1512: { INDEX_op_div_i64, { "r", "r", "rJ" } },
1513: { INDEX_op_divu_i64, { "r", "r", "rJ" } },
1514: { INDEX_op_rem_i64, { "r", "r", "rJ" } },
1515: { INDEX_op_remu_i64, { "r", "r", "rJ" } },
1.1 root 1516: { INDEX_op_sub_i64, { "r", "r", "rJ" } },
1517: { INDEX_op_and_i64, { "r", "r", "rJ" } },
1.1.1.3 root 1518: { INDEX_op_andc_i64, { "r", "r", "rJ" } },
1.1 root 1519: { INDEX_op_or_i64, { "r", "r", "rJ" } },
1.1.1.3 root 1520: { INDEX_op_orc_i64, { "r", "r", "rJ" } },
1.1 root 1521: { INDEX_op_xor_i64, { "r", "r", "rJ" } },
1522:
1523: { INDEX_op_shl_i64, { "r", "r", "rJ" } },
1524: { INDEX_op_shr_i64, { "r", "r", "rJ" } },
1525: { INDEX_op_sar_i64, { "r", "r", "rJ" } },
1526:
1.1.1.3 root 1527: { INDEX_op_neg_i64, { "r", "rJ" } },
1528: { INDEX_op_not_i64, { "r", "rJ" } },
1529:
1530: { INDEX_op_ext32s_i64, { "r", "ri" } },
1531: { INDEX_op_ext32u_i64, { "r", "ri" } },
1532:
1533: { INDEX_op_brcond_i64, { "r", "rJ" } },
1534: { INDEX_op_setcond_i64, { "r", "r", "rJ" } },
1.1 root 1535: #endif
1536: { -1 },
1537: };
1538:
1.1.1.3 root 1539: static void tcg_target_init(TCGContext *s)
1.1 root 1540: {
1541: tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1.1.1.3 root 1542: #if TCG_TARGET_REG_BITS == 64
1.1 root 1543: tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1544: #endif
1545: tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1546: (1 << TCG_REG_G1) |
1547: (1 << TCG_REG_G2) |
1548: (1 << TCG_REG_G3) |
1549: (1 << TCG_REG_G4) |
1550: (1 << TCG_REG_G5) |
1551: (1 << TCG_REG_G6) |
1552: (1 << TCG_REG_G7) |
1553: (1 << TCG_REG_O0) |
1554: (1 << TCG_REG_O1) |
1555: (1 << TCG_REG_O2) |
1556: (1 << TCG_REG_O3) |
1557: (1 << TCG_REG_O4) |
1558: (1 << TCG_REG_O5) |
1559: (1 << TCG_REG_O7));
1560:
1561: tcg_regset_clear(s->reserved_regs);
1562: tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0);
1.1.1.3 root 1563: #if TCG_TARGET_REG_BITS == 64
1.1 root 1564: tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use
1565: #endif
1566: tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
1567: tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6);
1568: tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7);
1569: tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6);
1570: tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7);
1571: tcg_add_target_add_op_defs(sparc_op_defs);
1572: }
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