--- qemu/tcg/sparc/tcg-target.h 2018/04/24 16:51:10 1.1.1.1 +++ qemu/tcg/sparc/tcg-target.h 2018/04/24 19:35:45 1.1.1.6 @@ -23,17 +23,11 @@ */ #define TCG_TARGET_SPARC 1 -#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) -#define TCG_TARGET_REG_BITS 64 -#else -#define TCG_TARGET_REG_BITS 32 -#endif - #define TCG_TARGET_WORDS_BIGENDIAN #define TCG_TARGET_NB_REGS 32 -enum { +typedef enum { TCG_REG_G0 = 0, TCG_REG_G1, TCG_REG_G2, @@ -66,7 +60,7 @@ enum { TCG_REG_I5, TCG_REG_I6, TCG_REG_I7, -}; +} TCGReg; #define TCG_CT_CONST_S11 0x100 #define TCG_CT_CONST_S13 0x200 @@ -75,42 +69,73 @@ enum { #define TCG_REG_CALL_STACK TCG_REG_I6 #ifdef __arch64__ // Reserve space for AREG0 -#define TCG_TARGET_STACK_MINFRAME (176 + 2 * (int)sizeof(long)) -#define TCG_TARGET_CALL_STACK_OFFSET (2047 + TCG_TARGET_STACK_MINFRAME) +#define TCG_TARGET_STACK_MINFRAME (176 + 4 * (int)sizeof(long) + \ + TCG_STATIC_CALL_ARGS_SIZE) +#define TCG_TARGET_CALL_STACK_OFFSET (2047 - 16) #define TCG_TARGET_STACK_ALIGN 16 #else // AREG0 + one word for alignment -#define TCG_TARGET_STACK_MINFRAME (92 + (2 + 1) * (int)sizeof(long)) +#define TCG_TARGET_STACK_MINFRAME (92 + (2 + 1) * (int)sizeof(long) + \ + TCG_STATIC_CALL_ARGS_SIZE) #define TCG_TARGET_CALL_STACK_OFFSET TCG_TARGET_STACK_MINFRAME #define TCG_TARGET_STACK_ALIGN 8 #endif -/* optional instructions */ -//#define TCG_TARGET_HAS_bswap_i32 -//#define TCG_TARGET_HAS_bswap_i64 -//#define TCG_TARGET_HAS_neg_i32 -//#define TCG_TARGET_HAS_neg_i64 +#ifdef __arch64__ +#define TCG_TARGET_EXTEND_ARGS 1 +#endif +/* optional instructions */ +#define TCG_TARGET_HAS_div_i32 1 +#define TCG_TARGET_HAS_rot_i32 0 +#define TCG_TARGET_HAS_ext8s_i32 0 +#define TCG_TARGET_HAS_ext16s_i32 0 +#define TCG_TARGET_HAS_ext8u_i32 0 +#define TCG_TARGET_HAS_ext16u_i32 0 +#define TCG_TARGET_HAS_bswap16_i32 0 +#define TCG_TARGET_HAS_bswap32_i32 0 +#define TCG_TARGET_HAS_neg_i32 1 +#define TCG_TARGET_HAS_not_i32 1 +#define TCG_TARGET_HAS_andc_i32 1 +#define TCG_TARGET_HAS_orc_i32 1 +#define TCG_TARGET_HAS_eqv_i32 0 +#define TCG_TARGET_HAS_nand_i32 0 +#define TCG_TARGET_HAS_nor_i32 0 +#define TCG_TARGET_HAS_deposit_i32 0 + +#if TCG_TARGET_REG_BITS == 64 +#define TCG_TARGET_HAS_div_i64 1 +#define TCG_TARGET_HAS_rot_i64 0 +#define TCG_TARGET_HAS_ext8s_i64 0 +#define TCG_TARGET_HAS_ext16s_i64 0 +#define TCG_TARGET_HAS_ext32s_i64 1 +#define TCG_TARGET_HAS_ext8u_i64 0 +#define TCG_TARGET_HAS_ext16u_i64 0 +#define TCG_TARGET_HAS_ext32u_i64 1 +#define TCG_TARGET_HAS_bswap16_i64 0 +#define TCG_TARGET_HAS_bswap32_i64 0 +#define TCG_TARGET_HAS_bswap64_i64 0 +#define TCG_TARGET_HAS_neg_i64 1 +#define TCG_TARGET_HAS_not_i64 1 +#define TCG_TARGET_HAS_andc_i64 1 +#define TCG_TARGET_HAS_orc_i64 1 +#define TCG_TARGET_HAS_eqv_i64 0 +#define TCG_TARGET_HAS_nand_i64 0 +#define TCG_TARGET_HAS_nor_i64 0 +#define TCG_TARGET_HAS_deposit_i64 0 +#endif -/* Note: must be synced with dyngen-exec.h and Makefile.target */ -#ifdef HOST_SOLARIS +/* Note: must be synced with dyngen-exec.h */ +#ifdef CONFIG_SOLARIS #define TCG_AREG0 TCG_REG_G2 -#define TCG_AREG1 TCG_REG_G3 -#define TCG_AREG2 TCG_REG_G4 -#define TCG_AREG3 TCG_REG_G5 -#define TCG_AREG4 TCG_REG_G6 #elif defined(__sparc_v9__) #define TCG_AREG0 TCG_REG_G5 -#define TCG_AREG1 TCG_REG_G6 -#define TCG_AREG2 TCG_REG_G7 #else #define TCG_AREG0 TCG_REG_G6 -#define TCG_AREG1 TCG_REG_G1 -#define TCG_AREG2 TCG_REG_G2 -#define TCG_AREG3 TCG_REG_G3 #endif -static inline void flush_icache_range(unsigned long start, unsigned long stop) +static inline void flush_icache_range(tcg_target_ulong start, + tcg_target_ulong stop) { unsigned long p;