![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to tcg-target.h CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Qemu by Fabrice Bellard] / qemu / tcg / sparc|
Return to tcg-target.h CVS log | Up to [Qemu by Fabrice Bellard] / qemu / tcg / sparc |
1.1 root 1: /*
2: * Tiny Code Generator for QEMU
3: *
4: * Copyright (c) 2008 Fabrice Bellard
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
24: #define TCG_TARGET_SPARC 1
25:
26: #define TCG_TARGET_WORDS_BIGENDIAN
27:
28: #define TCG_TARGET_NB_REGS 32
29:
1.1.1.5 ! root 30: typedef enum {
1.1 root 31: TCG_REG_G0 = 0,
32: TCG_REG_G1,
33: TCG_REG_G2,
34: TCG_REG_G3,
35: TCG_REG_G4,
36: TCG_REG_G5,
37: TCG_REG_G6,
38: TCG_REG_G7,
39: TCG_REG_O0,
40: TCG_REG_O1,
41: TCG_REG_O2,
42: TCG_REG_O3,
43: TCG_REG_O4,
44: TCG_REG_O5,
45: TCG_REG_O6,
46: TCG_REG_O7,
47: TCG_REG_L0,
48: TCG_REG_L1,
49: TCG_REG_L2,
50: TCG_REG_L3,
51: TCG_REG_L4,
52: TCG_REG_L5,
53: TCG_REG_L6,
54: TCG_REG_L7,
55: TCG_REG_I0,
56: TCG_REG_I1,
57: TCG_REG_I2,
58: TCG_REG_I3,
59: TCG_REG_I4,
60: TCG_REG_I5,
61: TCG_REG_I6,
62: TCG_REG_I7,
1.1.1.5 ! root 63: } TCGReg;
1.1 root 64:
65: #define TCG_CT_CONST_S11 0x100
66: #define TCG_CT_CONST_S13 0x200
67:
68: /* used for function call generation */
69: #define TCG_REG_CALL_STACK TCG_REG_I6
70: #ifdef __arch64__
71: // Reserve space for AREG0
1.1.1.2 root 72: #define TCG_TARGET_STACK_MINFRAME (176 + 4 * (int)sizeof(long) + \
73: TCG_STATIC_CALL_ARGS_SIZE)
74: #define TCG_TARGET_CALL_STACK_OFFSET (2047 - 16)
1.1 root 75: #define TCG_TARGET_STACK_ALIGN 16
76: #else
77: // AREG0 + one word for alignment
1.1.1.2 root 78: #define TCG_TARGET_STACK_MINFRAME (92 + (2 + 1) * (int)sizeof(long) + \
79: TCG_STATIC_CALL_ARGS_SIZE)
1.1 root 80: #define TCG_TARGET_CALL_STACK_OFFSET TCG_TARGET_STACK_MINFRAME
81: #define TCG_TARGET_STACK_ALIGN 8
82: #endif
83:
1.1.1.4 root 84: #ifdef __arch64__
85: #define TCG_TARGET_EXTEND_ARGS 1
86: #endif
87:
1.1 root 88: /* optional instructions */
1.1.1.5 ! root 89: #define TCG_TARGET_HAS_div_i32 1
! 90: #define TCG_TARGET_HAS_rot_i32 0
! 91: #define TCG_TARGET_HAS_ext8s_i32 0
! 92: #define TCG_TARGET_HAS_ext16s_i32 0
! 93: #define TCG_TARGET_HAS_ext8u_i32 0
! 94: #define TCG_TARGET_HAS_ext16u_i32 0
! 95: #define TCG_TARGET_HAS_bswap16_i32 0
! 96: #define TCG_TARGET_HAS_bswap32_i32 0
! 97: #define TCG_TARGET_HAS_neg_i32 1
! 98: #define TCG_TARGET_HAS_not_i32 1
! 99: #define TCG_TARGET_HAS_andc_i32 1
! 100: #define TCG_TARGET_HAS_orc_i32 1
! 101: #define TCG_TARGET_HAS_eqv_i32 0
! 102: #define TCG_TARGET_HAS_nand_i32 0
! 103: #define TCG_TARGET_HAS_nor_i32 0
! 104: #define TCG_TARGET_HAS_deposit_i32 0
1.1 root 105:
1.1.1.4 root 106: #if TCG_TARGET_REG_BITS == 64
1.1.1.5 ! root 107: #define TCG_TARGET_HAS_div_i64 1
! 108: #define TCG_TARGET_HAS_rot_i64 0
! 109: #define TCG_TARGET_HAS_ext8s_i64 0
! 110: #define TCG_TARGET_HAS_ext16s_i64 0
! 111: #define TCG_TARGET_HAS_ext32s_i64 1
! 112: #define TCG_TARGET_HAS_ext8u_i64 0
! 113: #define TCG_TARGET_HAS_ext16u_i64 0
! 114: #define TCG_TARGET_HAS_ext32u_i64 1
! 115: #define TCG_TARGET_HAS_bswap16_i64 0
! 116: #define TCG_TARGET_HAS_bswap32_i64 0
! 117: #define TCG_TARGET_HAS_bswap64_i64 0
! 118: #define TCG_TARGET_HAS_neg_i64 1
! 119: #define TCG_TARGET_HAS_not_i64 1
! 120: #define TCG_TARGET_HAS_andc_i64 1
! 121: #define TCG_TARGET_HAS_orc_i64 1
! 122: #define TCG_TARGET_HAS_eqv_i64 0
! 123: #define TCG_TARGET_HAS_nand_i64 0
! 124: #define TCG_TARGET_HAS_nor_i64 0
! 125: #define TCG_TARGET_HAS_deposit_i64 0
1.1.1.4 root 126: #endif
1.1 root 127:
1.1.1.4 root 128: /* Note: must be synced with dyngen-exec.h */
1.1.1.3 root 129: #ifdef CONFIG_SOLARIS
1.1 root 130: #define TCG_AREG0 TCG_REG_G2
131: #elif defined(__sparc_v9__)
132: #define TCG_AREG0 TCG_REG_G5
133: #else
134: #define TCG_AREG0 TCG_REG_G6
135: #endif
136:
137: static inline void flush_icache_range(unsigned long start, unsigned long stop)
138: {
139: unsigned long p;
140:
141: p = start & ~(8UL - 1UL);
142: stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
143:
144: for (; p < stop; p += 8)
145: __asm__ __volatile__("flush\t%0" : : "r" (p));
146: }
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.