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1.1 root 1: /*
2: * Tiny Code Generator for QEMU
3: *
4: * Copyright (c) 2008 Fabrice Bellard
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
24: #include "tcg.h"
25:
26: int gen_new_label(void);
27:
1.1.1.4 root 28: static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1)
1.1 root 29: {
30: *gen_opc_ptr++ = opc;
31: *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
32: }
33:
1.1.1.4 root 34: static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1)
1.1 root 35: {
36: *gen_opc_ptr++ = opc;
37: *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
38: }
39:
1.1.1.4 root 40: static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1)
1.1 root 41: {
42: *gen_opc_ptr++ = opc;
43: *gen_opparam_ptr++ = arg1;
44: }
45:
1.1.1.4 root 46: static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2)
1.1 root 47: {
48: *gen_opc_ptr++ = opc;
49: *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
50: *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
51: }
52:
1.1.1.4 root 53: static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2)
1.1 root 54: {
55: *gen_opc_ptr++ = opc;
56: *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
57: *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
58: }
59:
1.1.1.4 root 60: static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGArg arg2)
1.1 root 61: {
62: *gen_opc_ptr++ = opc;
63: *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
64: *gen_opparam_ptr++ = arg2;
65: }
66:
1.1.1.4 root 67: static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGArg arg2)
1.1 root 68: {
69: *gen_opc_ptr++ = opc;
70: *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
71: *gen_opparam_ptr++ = arg2;
72: }
73:
1.1.1.4 root 74: static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg arg1, TCGArg arg2)
1.1 root 75: {
76: *gen_opc_ptr++ = opc;
77: *gen_opparam_ptr++ = arg1;
78: *gen_opparam_ptr++ = arg2;
79: }
80:
1.1.1.4 root 81: static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
1.1 root 82: TCGv_i32 arg3)
83: {
84: *gen_opc_ptr++ = opc;
85: *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
86: *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
87: *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
88: }
89:
1.1.1.4 root 90: static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
1.1 root 91: TCGv_i64 arg3)
92: {
93: *gen_opc_ptr++ = opc;
94: *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
95: *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
96: *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
97: }
98:
1.1.1.4 root 99: static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 arg1,
100: TCGv_i32 arg2, TCGArg arg3)
1.1 root 101: {
102: *gen_opc_ptr++ = opc;
103: *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
104: *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
105: *gen_opparam_ptr++ = arg3;
106: }
107:
1.1.1.4 root 108: static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 arg1,
109: TCGv_i64 arg2, TCGArg arg3)
1.1 root 110: {
111: *gen_opc_ptr++ = opc;
112: *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
113: *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
114: *gen_opparam_ptr++ = arg3;
115: }
116:
1.1.1.4 root 117: static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
118: TCGv_ptr base, TCGArg offset)
1.1 root 119: {
120: *gen_opc_ptr++ = opc;
121: *gen_opparam_ptr++ = GET_TCGV_I32(val);
122: *gen_opparam_ptr++ = GET_TCGV_PTR(base);
123: *gen_opparam_ptr++ = offset;
124: }
125:
1.1.1.4 root 126: static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
127: TCGv_ptr base, TCGArg offset)
1.1 root 128: {
129: *gen_opc_ptr++ = opc;
130: *gen_opparam_ptr++ = GET_TCGV_I64(val);
131: *gen_opparam_ptr++ = GET_TCGV_PTR(base);
132: *gen_opparam_ptr++ = offset;
133: }
134:
1.1.1.4 root 135: static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val,
136: TCGv_i32 addr, TCGArg mem_index)
1.1 root 137: {
138: *gen_opc_ptr++ = opc;
139: *gen_opparam_ptr++ = GET_TCGV_I64(val);
140: *gen_opparam_ptr++ = GET_TCGV_I32(addr);
141: *gen_opparam_ptr++ = mem_index;
142: }
143:
1.1.1.4 root 144: static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val,
145: TCGv_i64 addr, TCGArg mem_index)
1.1 root 146: {
147: *gen_opc_ptr++ = opc;
148: *gen_opparam_ptr++ = GET_TCGV_I64(val);
149: *gen_opparam_ptr++ = GET_TCGV_I64(addr);
150: *gen_opparam_ptr++ = mem_index;
151: }
152:
1.1.1.4 root 153: static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
1.1 root 154: TCGv_i32 arg3, TCGv_i32 arg4)
155: {
156: *gen_opc_ptr++ = opc;
157: *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
158: *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
159: *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
160: *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
161: }
162:
1.1.1.4 root 163: static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
1.1 root 164: TCGv_i64 arg3, TCGv_i64 arg4)
165: {
166: *gen_opc_ptr++ = opc;
167: *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
168: *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
169: *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
170: *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
171: }
172:
1.1.1.4 root 173: static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
1.1 root 174: TCGv_i32 arg3, TCGArg arg4)
175: {
176: *gen_opc_ptr++ = opc;
177: *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
178: *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
179: *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
180: *gen_opparam_ptr++ = arg4;
181: }
182:
1.1.1.4 root 183: static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
1.1 root 184: TCGv_i64 arg3, TCGArg arg4)
185: {
186: *gen_opc_ptr++ = opc;
187: *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
188: *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
189: *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
190: *gen_opparam_ptr++ = arg4;
191: }
192:
1.1.1.4 root 193: static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
1.1 root 194: TCGArg arg3, TCGArg arg4)
195: {
196: *gen_opc_ptr++ = opc;
197: *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
198: *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
199: *gen_opparam_ptr++ = arg3;
200: *gen_opparam_ptr++ = arg4;
201: }
202:
1.1.1.4 root 203: static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
1.1 root 204: TCGArg arg3, TCGArg arg4)
205: {
206: *gen_opc_ptr++ = opc;
207: *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
208: *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
209: *gen_opparam_ptr++ = arg3;
210: *gen_opparam_ptr++ = arg4;
211: }
212:
1.1.1.4 root 213: static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
1.1 root 214: TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5)
215: {
216: *gen_opc_ptr++ = opc;
217: *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
218: *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
219: *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
220: *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
221: *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
222: }
223:
1.1.1.4 root 224: static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
1.1 root 225: TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5)
226: {
227: *gen_opc_ptr++ = opc;
228: *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
229: *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
230: *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
231: *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
232: *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
233: }
234:
1.1.1.4 root 235: static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
1.1 root 236: TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5)
237: {
238: *gen_opc_ptr++ = opc;
239: *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
240: *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
241: *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
242: *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
243: *gen_opparam_ptr++ = arg5;
244: }
245:
1.1.1.4 root 246: static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
1.1 root 247: TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5)
248: {
249: *gen_opc_ptr++ = opc;
250: *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
251: *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
252: *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
253: *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
254: *gen_opparam_ptr++ = arg5;
255: }
256:
1.1.1.5 ! root 257: static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 arg1,
! 258: TCGv_i32 arg2, TCGv_i32 arg3,
! 259: TCGArg arg4, TCGArg arg5)
! 260: {
! 261: *gen_opc_ptr++ = opc;
! 262: *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
! 263: *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
! 264: *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
! 265: *gen_opparam_ptr++ = arg4;
! 266: *gen_opparam_ptr++ = arg5;
! 267: }
! 268:
! 269: static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 arg1,
! 270: TCGv_i64 arg2, TCGv_i64 arg3,
! 271: TCGArg arg4, TCGArg arg5)
! 272: {
! 273: *gen_opc_ptr++ = opc;
! 274: *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
! 275: *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
! 276: *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
! 277: *gen_opparam_ptr++ = arg4;
! 278: *gen_opparam_ptr++ = arg5;
! 279: }
! 280:
1.1.1.4 root 281: static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
1.1 root 282: TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
283: TCGv_i32 arg6)
284: {
285: *gen_opc_ptr++ = opc;
286: *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
287: *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
288: *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
289: *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
290: *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
291: *gen_opparam_ptr++ = GET_TCGV_I32(arg6);
292: }
293:
1.1.1.4 root 294: static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
1.1 root 295: TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5,
296: TCGv_i64 arg6)
297: {
298: *gen_opc_ptr++ = opc;
299: *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
300: *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
301: *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
302: *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
303: *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
304: *gen_opparam_ptr++ = GET_TCGV_I64(arg6);
305: }
306:
1.1.1.4 root 307: static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
308: TCGv_i32 arg3, TCGv_i32 arg4,
309: TCGv_i32 arg5, TCGArg arg6)
310: {
311: *gen_opc_ptr++ = opc;
312: *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
313: *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
314: *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
315: *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
316: *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
317: *gen_opparam_ptr++ = arg6;
318: }
319:
320: static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
321: TCGv_i64 arg3, TCGv_i64 arg4,
322: TCGv_i64 arg5, TCGArg arg6)
323: {
324: *gen_opc_ptr++ = opc;
325: *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
326: *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
327: *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
328: *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
329: *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
330: *gen_opparam_ptr++ = arg6;
331: }
332:
333: static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 arg1,
334: TCGv_i32 arg2, TCGv_i32 arg3,
335: TCGv_i32 arg4, TCGArg arg5, TCGArg arg6)
1.1 root 336: {
337: *gen_opc_ptr++ = opc;
338: *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
339: *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
340: *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
341: *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
342: *gen_opparam_ptr++ = arg5;
343: *gen_opparam_ptr++ = arg6;
344: }
345:
1.1.1.4 root 346: static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 arg1,
347: TCGv_i64 arg2, TCGv_i64 arg3,
348: TCGv_i64 arg4, TCGArg arg5, TCGArg arg6)
1.1 root 349: {
350: *gen_opc_ptr++ = opc;
351: *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
352: *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
353: *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
354: *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
355: *gen_opparam_ptr++ = arg5;
356: *gen_opparam_ptr++ = arg6;
357: }
358:
359: static inline void gen_set_label(int n)
360: {
361: tcg_gen_op1i(INDEX_op_set_label, n);
362: }
363:
364: static inline void tcg_gen_br(int label)
365: {
366: tcg_gen_op1i(INDEX_op_br, label);
367: }
368:
369: static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
370: {
1.1.1.2 root 371: if (!TCGV_EQUAL_I32(ret, arg))
1.1 root 372: tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
373: }
374:
375: static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
376: {
377: tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
378: }
379:
1.1.1.4 root 380: /* A version of dh_sizemask from def-helper.h that doesn't rely on
381: preprocessor magic. */
382: static inline int tcg_gen_sizemask(int n, int is_64bit, int is_signed)
383: {
384: return (is_64bit << n*2) | (is_signed << (n*2 + 1));
385: }
386:
1.1 root 387: /* helper calls */
388: static inline void tcg_gen_helperN(void *func, int flags, int sizemask,
389: TCGArg ret, int nargs, TCGArg *args)
390: {
391: TCGv_ptr fn;
392: fn = tcg_const_ptr((tcg_target_long)func);
393: tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret,
394: nargs, args);
395: tcg_temp_free_ptr(fn);
396: }
397:
1.1.1.4 root 398: /* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently
399: reserved for helpers in tcg-runtime.c. These helpers are all const
400: and pure, hence the call to tcg_gen_callN() with TCG_CALL_CONST |
401: TCG_CALL_PURE. This may need to be adjusted if these functions
402: start to be used with other helpers. */
403: static inline void tcg_gen_helper32(void *func, int sizemask, TCGv_i32 ret,
404: TCGv_i32 a, TCGv_i32 b)
405: {
406: TCGv_ptr fn;
407: TCGArg args[2];
408: fn = tcg_const_ptr((tcg_target_long)func);
409: args[0] = GET_TCGV_I32(a);
410: args[1] = GET_TCGV_I32(b);
411: tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask,
412: GET_TCGV_I32(ret), 2, args);
413: tcg_temp_free_ptr(fn);
414: }
415:
416: static inline void tcg_gen_helper64(void *func, int sizemask, TCGv_i64 ret,
1.1 root 417: TCGv_i64 a, TCGv_i64 b)
418: {
419: TCGv_ptr fn;
420: TCGArg args[2];
421: fn = tcg_const_ptr((tcg_target_long)func);
422: args[0] = GET_TCGV_I64(a);
423: args[1] = GET_TCGV_I64(b);
1.1.1.4 root 424: tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask,
425: GET_TCGV_I64(ret), 2, args);
1.1 root 426: tcg_temp_free_ptr(fn);
427: }
428:
429: /* 32 bit ops */
430:
431: static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
432: {
433: tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
434: }
435:
436: static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
437: {
438: tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
439: }
440:
441: static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
442: {
443: tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
444: }
445:
446: static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
447: {
448: tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
449: }
450:
451: static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
452: {
453: tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
454: }
455:
456: static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
457: {
458: tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
459: }
460:
461: static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
462: {
463: tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
464: }
465:
466: static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
467: {
468: tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
469: }
470:
471: static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
472: {
473: tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
474: }
475:
476: static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
477: {
478: /* some cases can be optimized here */
479: if (arg2 == 0) {
480: tcg_gen_mov_i32(ret, arg1);
481: } else {
482: TCGv_i32 t0 = tcg_const_i32(arg2);
483: tcg_gen_add_i32(ret, arg1, t0);
484: tcg_temp_free_i32(t0);
485: }
486: }
487:
488: static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
489: {
490: tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
491: }
492:
493: static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
494: {
495: TCGv_i32 t0 = tcg_const_i32(arg1);
496: tcg_gen_sub_i32(ret, t0, arg2);
497: tcg_temp_free_i32(t0);
498: }
499:
500: static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
501: {
502: /* some cases can be optimized here */
503: if (arg2 == 0) {
504: tcg_gen_mov_i32(ret, arg1);
505: } else {
506: TCGv_i32 t0 = tcg_const_i32(arg2);
507: tcg_gen_sub_i32(ret, arg1, t0);
508: tcg_temp_free_i32(t0);
509: }
510: }
511:
512: static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
513: {
1.1.1.2 root 514: if (TCGV_EQUAL_I32(arg1, arg2)) {
515: tcg_gen_mov_i32(ret, arg1);
516: } else {
517: tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
518: }
1.1 root 519: }
520:
521: static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
522: {
523: /* some cases can be optimized here */
524: if (arg2 == 0) {
525: tcg_gen_movi_i32(ret, 0);
526: } else if (arg2 == 0xffffffff) {
527: tcg_gen_mov_i32(ret, arg1);
528: } else {
529: TCGv_i32 t0 = tcg_const_i32(arg2);
530: tcg_gen_and_i32(ret, arg1, t0);
531: tcg_temp_free_i32(t0);
532: }
533: }
534:
535: static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
536: {
1.1.1.2 root 537: if (TCGV_EQUAL_I32(arg1, arg2)) {
538: tcg_gen_mov_i32(ret, arg1);
539: } else {
540: tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
541: }
1.1 root 542: }
543:
544: static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
545: {
546: /* some cases can be optimized here */
547: if (arg2 == 0xffffffff) {
548: tcg_gen_movi_i32(ret, 0xffffffff);
549: } else if (arg2 == 0) {
550: tcg_gen_mov_i32(ret, arg1);
551: } else {
552: TCGv_i32 t0 = tcg_const_i32(arg2);
553: tcg_gen_or_i32(ret, arg1, t0);
554: tcg_temp_free_i32(t0);
555: }
556: }
557:
558: static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
559: {
1.1.1.2 root 560: if (TCGV_EQUAL_I32(arg1, arg2)) {
561: tcg_gen_movi_i32(ret, 0);
562: } else {
563: tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
564: }
1.1 root 565: }
566:
567: static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
568: {
569: /* some cases can be optimized here */
570: if (arg2 == 0) {
571: tcg_gen_mov_i32(ret, arg1);
572: } else {
573: TCGv_i32 t0 = tcg_const_i32(arg2);
574: tcg_gen_xor_i32(ret, arg1, t0);
575: tcg_temp_free_i32(t0);
576: }
577: }
578:
579: static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
580: {
581: tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
582: }
583:
584: static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
585: {
586: if (arg2 == 0) {
587: tcg_gen_mov_i32(ret, arg1);
588: } else {
589: TCGv_i32 t0 = tcg_const_i32(arg2);
590: tcg_gen_shl_i32(ret, arg1, t0);
591: tcg_temp_free_i32(t0);
592: }
593: }
594:
595: static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
596: {
597: tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
598: }
599:
600: static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
601: {
602: if (arg2 == 0) {
603: tcg_gen_mov_i32(ret, arg1);
604: } else {
605: TCGv_i32 t0 = tcg_const_i32(arg2);
606: tcg_gen_shr_i32(ret, arg1, t0);
607: tcg_temp_free_i32(t0);
608: }
609: }
610:
611: static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
612: {
613: tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
614: }
615:
616: static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
617: {
618: if (arg2 == 0) {
619: tcg_gen_mov_i32(ret, arg1);
620: } else {
621: TCGv_i32 t0 = tcg_const_i32(arg2);
622: tcg_gen_sar_i32(ret, arg1, t0);
623: tcg_temp_free_i32(t0);
624: }
625: }
626:
1.1.1.4 root 627: static inline void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1,
628: TCGv_i32 arg2, int label_index)
1.1 root 629: {
630: tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
631: }
632:
1.1.1.4 root 633: static inline void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1,
634: int32_t arg2, int label_index)
1.1 root 635: {
636: TCGv_i32 t0 = tcg_const_i32(arg2);
637: tcg_gen_brcond_i32(cond, arg1, t0, label_index);
638: tcg_temp_free_i32(t0);
639: }
640:
1.1.1.4 root 641: static inline void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
642: TCGv_i32 arg1, TCGv_i32 arg2)
643: {
644: tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond);
645: }
646:
647: static inline void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
648: TCGv_i32 arg1, int32_t arg2)
649: {
650: TCGv_i32 t0 = tcg_const_i32(arg2);
651: tcg_gen_setcond_i32(cond, ret, arg1, t0);
652: tcg_temp_free_i32(t0);
653: }
654:
1.1 root 655: static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
656: {
657: tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
658: }
659:
660: static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
661: {
662: TCGv_i32 t0 = tcg_const_i32(arg2);
663: tcg_gen_mul_i32(ret, arg1, t0);
664: tcg_temp_free_i32(t0);
665: }
666:
667: #ifdef TCG_TARGET_HAS_div_i32
668: static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
669: {
670: tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2);
671: }
672:
673: static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
674: {
675: tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
676: }
677:
678: static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
679: {
680: tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2);
681: }
682:
683: static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
684: {
685: tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
686: }
1.1.1.4 root 687: #elif defined(TCG_TARGET_HAS_div2_i32)
1.1 root 688: static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
689: {
690: TCGv_i32 t0;
691: t0 = tcg_temp_new_i32();
692: tcg_gen_sari_i32(t0, arg1, 31);
693: tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
694: tcg_temp_free_i32(t0);
695: }
696:
697: static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
698: {
699: TCGv_i32 t0;
700: t0 = tcg_temp_new_i32();
701: tcg_gen_sari_i32(t0, arg1, 31);
702: tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
703: tcg_temp_free_i32(t0);
704: }
705:
706: static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
707: {
708: TCGv_i32 t0;
709: t0 = tcg_temp_new_i32();
710: tcg_gen_movi_i32(t0, 0);
711: tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
712: tcg_temp_free_i32(t0);
713: }
714:
715: static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
716: {
717: TCGv_i32 t0;
718: t0 = tcg_temp_new_i32();
719: tcg_gen_movi_i32(t0, 0);
720: tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
721: tcg_temp_free_i32(t0);
722: }
1.1.1.4 root 723: #else
724: static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
725: {
726: int sizemask = 0;
727: /* Return value and both arguments are 32-bit and signed. */
728: sizemask |= tcg_gen_sizemask(0, 0, 1);
729: sizemask |= tcg_gen_sizemask(1, 0, 1);
730: sizemask |= tcg_gen_sizemask(2, 0, 1);
731:
732: tcg_gen_helper32(tcg_helper_div_i32, sizemask, ret, arg1, arg2);
733: }
734:
735: static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
736: {
737: int sizemask = 0;
738: /* Return value and both arguments are 32-bit and signed. */
739: sizemask |= tcg_gen_sizemask(0, 0, 1);
740: sizemask |= tcg_gen_sizemask(1, 0, 1);
741: sizemask |= tcg_gen_sizemask(2, 0, 1);
742:
743: tcg_gen_helper32(tcg_helper_rem_i32, sizemask, ret, arg1, arg2);
744: }
745:
746: static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
747: {
748: int sizemask = 0;
749: /* Return value and both arguments are 32-bit and unsigned. */
750: sizemask |= tcg_gen_sizemask(0, 0, 0);
751: sizemask |= tcg_gen_sizemask(1, 0, 0);
752: sizemask |= tcg_gen_sizemask(2, 0, 0);
753:
1.1.1.5 ! root 754: tcg_gen_helper32(tcg_helper_divu_i32, sizemask, ret, arg1, arg2);
1.1.1.4 root 755: }
756:
757: static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
758: {
759: int sizemask = 0;
760: /* Return value and both arguments are 32-bit and unsigned. */
761: sizemask |= tcg_gen_sizemask(0, 0, 0);
762: sizemask |= tcg_gen_sizemask(1, 0, 0);
763: sizemask |= tcg_gen_sizemask(2, 0, 0);
764:
1.1.1.5 ! root 765: tcg_gen_helper32(tcg_helper_remu_i32, sizemask, ret, arg1, arg2);
1.1.1.4 root 766: }
1.1 root 767: #endif
768:
769: #if TCG_TARGET_REG_BITS == 32
770:
771: static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
772: {
1.1.1.2 root 773: if (!TCGV_EQUAL_I64(ret, arg)) {
1.1 root 774: tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
775: tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
776: }
777: }
778:
779: static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
780: {
781: tcg_gen_movi_i32(TCGV_LOW(ret), arg);
782: tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
783: }
784:
785: static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
786: tcg_target_long offset)
787: {
788: tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset);
789: tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
790: }
791:
792: static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
793: tcg_target_long offset)
794: {
795: tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset);
796: tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
797: }
798:
799: static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
800: tcg_target_long offset)
801: {
802: tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset);
803: tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
804: }
805:
806: static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
807: tcg_target_long offset)
808: {
809: tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset);
810: tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
811: }
812:
813: static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
814: tcg_target_long offset)
815: {
816: tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
817: tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
818: }
819:
820: static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
821: tcg_target_long offset)
822: {
823: tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
824: tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
825: }
826:
827: static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
828: tcg_target_long offset)
829: {
830: /* since arg2 and ret have different types, they cannot be the
831: same temporary */
832: #ifdef TCG_TARGET_WORDS_BIGENDIAN
833: tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
834: tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
835: #else
836: tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
837: tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
838: #endif
839: }
840:
841: static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
842: tcg_target_long offset)
843: {
844: tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
845: }
846:
847: static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
848: tcg_target_long offset)
849: {
850: tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
851: }
852:
853: static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
854: tcg_target_long offset)
855: {
856: tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
857: }
858:
859: static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
860: tcg_target_long offset)
861: {
862: #ifdef TCG_TARGET_WORDS_BIGENDIAN
863: tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
864: tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
865: #else
866: tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
867: tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
868: #endif
869: }
870:
871: static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
872: {
873: tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
874: TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
875: TCGV_HIGH(arg2));
876: }
877:
878: static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
879: {
880: tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
881: TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
882: TCGV_HIGH(arg2));
883: }
884:
885: static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
886: {
887: tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
888: tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
889: }
890:
891: static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
892: {
893: tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
894: tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
895: }
896:
897: static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
898: {
899: tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
900: tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
901: }
902:
903: static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
904: {
905: tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
906: tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
907: }
908:
909: static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
910: {
911: tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
912: tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
913: }
914:
915: static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
916: {
917: tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
918: tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
919: }
920:
921: /* XXX: use generic code when basic block handling is OK or CPU
922: specific code (x86) */
923: static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
924: {
1.1.1.4 root 925: int sizemask = 0;
926: /* Return value and both arguments are 64-bit and signed. */
927: sizemask |= tcg_gen_sizemask(0, 1, 1);
928: sizemask |= tcg_gen_sizemask(1, 1, 1);
929: sizemask |= tcg_gen_sizemask(2, 1, 1);
930:
931: tcg_gen_helper64(tcg_helper_shl_i64, sizemask, ret, arg1, arg2);
1.1 root 932: }
933:
934: static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
935: {
936: tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
937: }
938:
939: static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
940: {
1.1.1.4 root 941: int sizemask = 0;
942: /* Return value and both arguments are 64-bit and signed. */
943: sizemask |= tcg_gen_sizemask(0, 1, 1);
944: sizemask |= tcg_gen_sizemask(1, 1, 1);
945: sizemask |= tcg_gen_sizemask(2, 1, 1);
946:
947: tcg_gen_helper64(tcg_helper_shr_i64, sizemask, ret, arg1, arg2);
1.1 root 948: }
949:
950: static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
951: {
952: tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
953: }
954:
955: static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
956: {
1.1.1.4 root 957: int sizemask = 0;
958: /* Return value and both arguments are 64-bit and signed. */
959: sizemask |= tcg_gen_sizemask(0, 1, 1);
960: sizemask |= tcg_gen_sizemask(1, 1, 1);
961: sizemask |= tcg_gen_sizemask(2, 1, 1);
962:
963: tcg_gen_helper64(tcg_helper_sar_i64, sizemask, ret, arg1, arg2);
1.1 root 964: }
965:
966: static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
967: {
968: tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
969: }
970:
1.1.1.4 root 971: static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
972: TCGv_i64 arg2, int label_index)
1.1 root 973: {
974: tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
975: TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
976: TCGV_HIGH(arg2), cond, label_index);
977: }
978:
1.1.1.4 root 979: static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
980: TCGv_i64 arg1, TCGv_i64 arg2)
981: {
982: tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
983: TCGV_LOW(arg1), TCGV_HIGH(arg1),
984: TCGV_LOW(arg2), TCGV_HIGH(arg2), cond);
985: tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
986: }
987:
1.1 root 988: static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
989: {
990: TCGv_i64 t0;
991: TCGv_i32 t1;
992:
993: t0 = tcg_temp_new_i64();
994: t1 = tcg_temp_new_i32();
995:
996: tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0),
997: TCGV_LOW(arg1), TCGV_LOW(arg2));
998:
999: tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
1000: tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
1001: tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
1002: tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
1003:
1004: tcg_gen_mov_i64(ret, t0);
1005: tcg_temp_free_i64(t0);
1006: tcg_temp_free_i32(t1);
1007: }
1008:
1009: static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1010: {
1.1.1.4 root 1011: int sizemask = 0;
1012: /* Return value and both arguments are 64-bit and signed. */
1013: sizemask |= tcg_gen_sizemask(0, 1, 1);
1014: sizemask |= tcg_gen_sizemask(1, 1, 1);
1015: sizemask |= tcg_gen_sizemask(2, 1, 1);
1016:
1017: tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2);
1.1 root 1018: }
1019:
1020: static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1021: {
1.1.1.4 root 1022: int sizemask = 0;
1023: /* Return value and both arguments are 64-bit and signed. */
1024: sizemask |= tcg_gen_sizemask(0, 1, 1);
1025: sizemask |= tcg_gen_sizemask(1, 1, 1);
1026: sizemask |= tcg_gen_sizemask(2, 1, 1);
1027:
1028: tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2);
1.1 root 1029: }
1030:
1031: static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1032: {
1.1.1.4 root 1033: int sizemask = 0;
1034: /* Return value and both arguments are 64-bit and unsigned. */
1035: sizemask |= tcg_gen_sizemask(0, 1, 0);
1036: sizemask |= tcg_gen_sizemask(1, 1, 0);
1037: sizemask |= tcg_gen_sizemask(2, 1, 0);
1038:
1039: tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2);
1.1 root 1040: }
1041:
1042: static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1043: {
1.1.1.4 root 1044: int sizemask = 0;
1045: /* Return value and both arguments are 64-bit and unsigned. */
1046: sizemask |= tcg_gen_sizemask(0, 1, 0);
1047: sizemask |= tcg_gen_sizemask(1, 1, 0);
1048: sizemask |= tcg_gen_sizemask(2, 1, 0);
1049:
1050: tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2);
1.1 root 1051: }
1052:
1053: #else
1054:
1055: static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
1056: {
1.1.1.2 root 1057: if (!TCGV_EQUAL_I64(ret, arg))
1.1 root 1058: tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
1059: }
1060:
1061: static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
1062: {
1063: tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
1064: }
1065:
1066: static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_i64 arg2,
1067: tcg_target_long offset)
1068: {
1069: tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
1070: }
1071:
1072: static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_i64 arg2,
1073: tcg_target_long offset)
1074: {
1075: tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
1076: }
1077:
1078: static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_i64 arg2,
1079: tcg_target_long offset)
1080: {
1081: tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
1082: }
1083:
1084: static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_i64 arg2,
1085: tcg_target_long offset)
1086: {
1087: tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
1088: }
1089:
1090: static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_i64 arg2,
1091: tcg_target_long offset)
1092: {
1093: tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
1094: }
1095:
1096: static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_i64 arg2,
1097: tcg_target_long offset)
1098: {
1099: tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
1100: }
1101:
1102: static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_i64 arg2, tcg_target_long offset)
1103: {
1104: tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
1105: }
1106:
1107: static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_i64 arg2,
1108: tcg_target_long offset)
1109: {
1110: tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
1111: }
1112:
1113: static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_i64 arg2,
1114: tcg_target_long offset)
1115: {
1116: tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
1117: }
1118:
1119: static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_i64 arg2,
1120: tcg_target_long offset)
1121: {
1122: tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
1123: }
1124:
1125: static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_i64 arg2, tcg_target_long offset)
1126: {
1127: tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
1128: }
1129:
1130: static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1131: {
1132: tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
1133: }
1134:
1135: static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1136: {
1137: tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
1138: }
1139:
1140: static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1141: {
1.1.1.2 root 1142: if (TCGV_EQUAL_I64(arg1, arg2)) {
1143: tcg_gen_mov_i64(ret, arg1);
1144: } else {
1145: tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
1146: }
1.1 root 1147: }
1148:
1149: static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1150: {
1151: TCGv_i64 t0 = tcg_const_i64(arg2);
1152: tcg_gen_and_i64(ret, arg1, t0);
1153: tcg_temp_free_i64(t0);
1154: }
1155:
1156: static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1157: {
1.1.1.2 root 1158: if (TCGV_EQUAL_I64(arg1, arg2)) {
1159: tcg_gen_mov_i64(ret, arg1);
1160: } else {
1161: tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
1162: }
1.1 root 1163: }
1164:
1165: static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1166: {
1167: TCGv_i64 t0 = tcg_const_i64(arg2);
1168: tcg_gen_or_i64(ret, arg1, t0);
1169: tcg_temp_free_i64(t0);
1170: }
1171:
1172: static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1173: {
1.1.1.2 root 1174: if (TCGV_EQUAL_I64(arg1, arg2)) {
1175: tcg_gen_movi_i64(ret, 0);
1176: } else {
1177: tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
1178: }
1.1 root 1179: }
1180:
1181: static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1182: {
1183: TCGv_i64 t0 = tcg_const_i64(arg2);
1184: tcg_gen_xor_i64(ret, arg1, t0);
1185: tcg_temp_free_i64(t0);
1186: }
1187:
1188: static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1189: {
1190: tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
1191: }
1192:
1193: static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1194: {
1195: if (arg2 == 0) {
1196: tcg_gen_mov_i64(ret, arg1);
1197: } else {
1198: TCGv_i64 t0 = tcg_const_i64(arg2);
1199: tcg_gen_shl_i64(ret, arg1, t0);
1200: tcg_temp_free_i64(t0);
1201: }
1202: }
1203:
1204: static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1205: {
1206: tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
1207: }
1208:
1209: static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1210: {
1211: if (arg2 == 0) {
1212: tcg_gen_mov_i64(ret, arg1);
1213: } else {
1214: TCGv_i64 t0 = tcg_const_i64(arg2);
1215: tcg_gen_shr_i64(ret, arg1, t0);
1216: tcg_temp_free_i64(t0);
1217: }
1218: }
1219:
1220: static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1221: {
1222: tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
1223: }
1224:
1225: static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1226: {
1227: if (arg2 == 0) {
1228: tcg_gen_mov_i64(ret, arg1);
1229: } else {
1230: TCGv_i64 t0 = tcg_const_i64(arg2);
1231: tcg_gen_sar_i64(ret, arg1, t0);
1232: tcg_temp_free_i64(t0);
1233: }
1234: }
1235:
1.1.1.4 root 1236: static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
1237: TCGv_i64 arg2, int label_index)
1.1 root 1238: {
1239: tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
1240: }
1241:
1.1.1.4 root 1242: static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
1243: TCGv_i64 arg1, TCGv_i64 arg2)
1244: {
1245: tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond);
1246: }
1247:
1.1 root 1248: static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1249: {
1250: tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
1251: }
1252:
1253: #ifdef TCG_TARGET_HAS_div_i64
1254: static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1255: {
1256: tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2);
1257: }
1258:
1259: static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1260: {
1261: tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
1262: }
1263:
1264: static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1265: {
1266: tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2);
1267: }
1268:
1269: static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1270: {
1271: tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
1272: }
1.1.1.4 root 1273: #elif defined(TCG_TARGET_HAS_div2_i64)
1.1 root 1274: static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1275: {
1276: TCGv_i64 t0;
1277: t0 = tcg_temp_new_i64();
1278: tcg_gen_sari_i64(t0, arg1, 63);
1279: tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
1280: tcg_temp_free_i64(t0);
1281: }
1282:
1283: static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1284: {
1285: TCGv_i64 t0;
1286: t0 = tcg_temp_new_i64();
1287: tcg_gen_sari_i64(t0, arg1, 63);
1288: tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
1289: tcg_temp_free_i64(t0);
1290: }
1291:
1292: static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1293: {
1294: TCGv_i64 t0;
1295: t0 = tcg_temp_new_i64();
1296: tcg_gen_movi_i64(t0, 0);
1297: tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
1298: tcg_temp_free_i64(t0);
1299: }
1300:
1301: static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1302: {
1303: TCGv_i64 t0;
1304: t0 = tcg_temp_new_i64();
1305: tcg_gen_movi_i64(t0, 0);
1306: tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
1307: tcg_temp_free_i64(t0);
1308: }
1.1.1.4 root 1309: #else
1310: static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1311: {
1312: int sizemask = 0;
1313: /* Return value and both arguments are 64-bit and signed. */
1314: sizemask |= tcg_gen_sizemask(0, 1, 1);
1315: sizemask |= tcg_gen_sizemask(1, 1, 1);
1316: sizemask |= tcg_gen_sizemask(2, 1, 1);
1317:
1318: tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2);
1319: }
1320:
1321: static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1322: {
1323: int sizemask = 0;
1324: /* Return value and both arguments are 64-bit and signed. */
1325: sizemask |= tcg_gen_sizemask(0, 1, 1);
1326: sizemask |= tcg_gen_sizemask(1, 1, 1);
1327: sizemask |= tcg_gen_sizemask(2, 1, 1);
1328:
1329: tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2);
1330: }
1331:
1332: static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1333: {
1334: int sizemask = 0;
1335: /* Return value and both arguments are 64-bit and unsigned. */
1336: sizemask |= tcg_gen_sizemask(0, 1, 0);
1337: sizemask |= tcg_gen_sizemask(1, 1, 0);
1338: sizemask |= tcg_gen_sizemask(2, 1, 0);
1339:
1340: tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2);
1341: }
1342:
1343: static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1344: {
1345: int sizemask = 0;
1346: /* Return value and both arguments are 64-bit and unsigned. */
1347: sizemask |= tcg_gen_sizemask(0, 1, 0);
1348: sizemask |= tcg_gen_sizemask(1, 1, 0);
1349: sizemask |= tcg_gen_sizemask(2, 1, 0);
1350:
1351: tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2);
1352: }
1.1 root 1353: #endif
1354:
1355: #endif
1356:
1357: static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1358: {
1359: /* some cases can be optimized here */
1360: if (arg2 == 0) {
1361: tcg_gen_mov_i64(ret, arg1);
1362: } else {
1363: TCGv_i64 t0 = tcg_const_i64(arg2);
1364: tcg_gen_add_i64(ret, arg1, t0);
1365: tcg_temp_free_i64(t0);
1366: }
1367: }
1368:
1369: static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
1370: {
1371: TCGv_i64 t0 = tcg_const_i64(arg1);
1372: tcg_gen_sub_i64(ret, t0, arg2);
1373: tcg_temp_free_i64(t0);
1374: }
1375:
1376: static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1377: {
1378: /* some cases can be optimized here */
1379: if (arg2 == 0) {
1380: tcg_gen_mov_i64(ret, arg1);
1381: } else {
1382: TCGv_i64 t0 = tcg_const_i64(arg2);
1383: tcg_gen_sub_i64(ret, arg1, t0);
1384: tcg_temp_free_i64(t0);
1385: }
1386: }
1.1.1.4 root 1387: static inline void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1,
1388: int64_t arg2, int label_index)
1.1 root 1389: {
1390: TCGv_i64 t0 = tcg_const_i64(arg2);
1391: tcg_gen_brcond_i64(cond, arg1, t0, label_index);
1392: tcg_temp_free_i64(t0);
1393: }
1394:
1.1.1.4 root 1395: static inline void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
1396: TCGv_i64 arg1, int64_t arg2)
1397: {
1398: TCGv_i64 t0 = tcg_const_i64(arg2);
1399: tcg_gen_setcond_i64(cond, ret, arg1, t0);
1400: tcg_temp_free_i64(t0);
1401: }
1402:
1.1 root 1403: static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1404: {
1405: TCGv_i64 t0 = tcg_const_i64(arg2);
1406: tcg_gen_mul_i64(ret, arg1, t0);
1407: tcg_temp_free_i64(t0);
1408: }
1409:
1410:
1411: /***************************************/
1412: /* optional operations */
1413:
1414: static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg)
1415: {
1416: #ifdef TCG_TARGET_HAS_ext8s_i32
1417: tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg);
1418: #else
1419: tcg_gen_shli_i32(ret, arg, 24);
1420: tcg_gen_sari_i32(ret, ret, 24);
1421: #endif
1422: }
1423:
1424: static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg)
1425: {
1426: #ifdef TCG_TARGET_HAS_ext16s_i32
1427: tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg);
1428: #else
1429: tcg_gen_shli_i32(ret, arg, 16);
1430: tcg_gen_sari_i32(ret, ret, 16);
1431: #endif
1432: }
1433:
1434: static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg)
1435: {
1.1.1.3 root 1436: #ifdef TCG_TARGET_HAS_ext8u_i32
1437: tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg);
1438: #else
1.1 root 1439: tcg_gen_andi_i32(ret, arg, 0xffu);
1.1.1.3 root 1440: #endif
1.1 root 1441: }
1442:
1443: static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
1444: {
1.1.1.3 root 1445: #ifdef TCG_TARGET_HAS_ext16u_i32
1446: tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg);
1447: #else
1.1 root 1448: tcg_gen_andi_i32(ret, arg, 0xffffu);
1.1.1.3 root 1449: #endif
1.1 root 1450: }
1451:
1452: /* Note: we assume the two high bytes are set to zero */
1453: static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
1454: {
1455: #ifdef TCG_TARGET_HAS_bswap16_i32
1456: tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg);
1457: #else
1.1.1.2 root 1458: TCGv_i32 t0 = tcg_temp_new_i32();
1.1 root 1459:
1.1.1.2 root 1460: tcg_gen_ext8u_i32(t0, arg);
1461: tcg_gen_shli_i32(t0, t0, 8);
1462: tcg_gen_shri_i32(ret, arg, 8);
1463: tcg_gen_or_i32(ret, ret, t0);
1.1 root 1464: tcg_temp_free_i32(t0);
1465: #endif
1466: }
1467:
1.1.1.2 root 1468: static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
1.1 root 1469: {
1.1.1.2 root 1470: #ifdef TCG_TARGET_HAS_bswap32_i32
1471: tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg);
1.1 root 1472: #else
1473: TCGv_i32 t0, t1;
1474: t0 = tcg_temp_new_i32();
1475: t1 = tcg_temp_new_i32();
1476:
1477: tcg_gen_shli_i32(t0, arg, 24);
1478:
1479: tcg_gen_andi_i32(t1, arg, 0x0000ff00);
1480: tcg_gen_shli_i32(t1, t1, 8);
1481: tcg_gen_or_i32(t0, t0, t1);
1482:
1483: tcg_gen_shri_i32(t1, arg, 8);
1484: tcg_gen_andi_i32(t1, t1, 0x0000ff00);
1485: tcg_gen_or_i32(t0, t0, t1);
1486:
1487: tcg_gen_shri_i32(t1, arg, 24);
1488: tcg_gen_or_i32(ret, t0, t1);
1489: tcg_temp_free_i32(t0);
1490: tcg_temp_free_i32(t1);
1491: #endif
1492: }
1493:
1494: #if TCG_TARGET_REG_BITS == 32
1495: static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1496: {
1497: tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1498: tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1499: }
1500:
1501: static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1502: {
1503: tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1504: tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1505: }
1506:
1507: static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1508: {
1509: tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1510: tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1511: }
1512:
1513: static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1514: {
1515: tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1516: tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1517: }
1518:
1519: static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1520: {
1521: tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1522: tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1523: }
1524:
1525: static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1526: {
1527: tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1528: tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1529: }
1530:
1531: static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1532: {
1533: tcg_gen_mov_i32(ret, TCGV_LOW(arg));
1534: }
1535:
1536: static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1537: {
1538: tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1539: tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1540: }
1541:
1542: static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1543: {
1544: tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1545: tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1546: }
1547:
1.1.1.2 root 1548: /* Note: we assume the six high bytes are set to zero */
1549: static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1550: {
1551: tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1552: tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1553: }
1554:
1555: /* Note: we assume the four high bytes are set to zero */
1556: static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1557: {
1558: tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1559: tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1560: }
1561:
1562: static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1.1 root 1563: {
1564: TCGv_i32 t0, t1;
1565: t0 = tcg_temp_new_i32();
1566: t1 = tcg_temp_new_i32();
1567:
1.1.1.2 root 1568: tcg_gen_bswap32_i32(t0, TCGV_LOW(arg));
1569: tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg));
1.1 root 1570: tcg_gen_mov_i32(TCGV_LOW(ret), t1);
1571: tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1572: tcg_temp_free_i32(t0);
1573: tcg_temp_free_i32(t1);
1574: }
1575: #else
1576:
1577: static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1578: {
1579: #ifdef TCG_TARGET_HAS_ext8s_i64
1580: tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg);
1581: #else
1582: tcg_gen_shli_i64(ret, arg, 56);
1583: tcg_gen_sari_i64(ret, ret, 56);
1584: #endif
1585: }
1586:
1587: static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1588: {
1589: #ifdef TCG_TARGET_HAS_ext16s_i64
1590: tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg);
1591: #else
1592: tcg_gen_shli_i64(ret, arg, 48);
1593: tcg_gen_sari_i64(ret, ret, 48);
1594: #endif
1595: }
1596:
1597: static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1598: {
1599: #ifdef TCG_TARGET_HAS_ext32s_i64
1600: tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg);
1601: #else
1602: tcg_gen_shli_i64(ret, arg, 32);
1603: tcg_gen_sari_i64(ret, ret, 32);
1604: #endif
1605: }
1606:
1607: static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1608: {
1.1.1.3 root 1609: #ifdef TCG_TARGET_HAS_ext8u_i64
1610: tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg);
1611: #else
1.1 root 1612: tcg_gen_andi_i64(ret, arg, 0xffu);
1.1.1.3 root 1613: #endif
1.1 root 1614: }
1615:
1616: static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1617: {
1.1.1.3 root 1618: #ifdef TCG_TARGET_HAS_ext16u_i64
1619: tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg);
1620: #else
1.1 root 1621: tcg_gen_andi_i64(ret, arg, 0xffffu);
1.1.1.3 root 1622: #endif
1.1 root 1623: }
1624:
1625: static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1626: {
1.1.1.3 root 1627: #ifdef TCG_TARGET_HAS_ext32u_i64
1628: tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg);
1629: #else
1.1 root 1630: tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1.1.1.3 root 1631: #endif
1.1 root 1632: }
1633:
1634: /* Note: we assume the target supports move between 32 and 64 bit
1635: registers. This will probably break MIPS64 targets. */
1636: static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1637: {
1638: tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
1639: }
1640:
1641: /* Note: we assume the target supports move between 32 and 64 bit
1642: registers */
1643: static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1644: {
1.1.1.3 root 1645: tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1.1 root 1646: }
1647:
1648: /* Note: we assume the target supports move between 32 and 64 bit
1649: registers */
1650: static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1651: {
1652: tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1653: }
1654:
1.1.1.2 root 1655: /* Note: we assume the six high bytes are set to zero */
1656: static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1.1 root 1657: {
1.1.1.2 root 1658: #ifdef TCG_TARGET_HAS_bswap16_i64
1659: tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg);
1.1 root 1660: #else
1.1.1.2 root 1661: TCGv_i64 t0 = tcg_temp_new_i64();
1662:
1663: tcg_gen_ext8u_i64(t0, arg);
1664: tcg_gen_shli_i64(t0, t0, 8);
1665: tcg_gen_shri_i64(ret, arg, 8);
1666: tcg_gen_or_i64(ret, ret, t0);
1667: tcg_temp_free_i64(t0);
1668: #endif
1669: }
1670:
1671: /* Note: we assume the four high bytes are set to zero */
1672: static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1673: {
1674: #ifdef TCG_TARGET_HAS_bswap32_i64
1675: tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg);
1676: #else
1677: TCGv_i64 t0, t1;
1678: t0 = tcg_temp_new_i64();
1679: t1 = tcg_temp_new_i64();
1680:
1681: tcg_gen_shli_i64(t0, arg, 24);
1682: tcg_gen_ext32u_i64(t0, t0);
1683:
1684: tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1685: tcg_gen_shli_i64(t1, t1, 8);
1686: tcg_gen_or_i64(t0, t0, t1);
1687:
1688: tcg_gen_shri_i64(t1, arg, 8);
1689: tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1690: tcg_gen_or_i64(t0, t0, t1);
1691:
1692: tcg_gen_shri_i64(t1, arg, 24);
1693: tcg_gen_or_i64(ret, t0, t1);
1694: tcg_temp_free_i64(t0);
1695: tcg_temp_free_i64(t1);
1696: #endif
1697: }
1698:
1699: static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1700: {
1701: #ifdef TCG_TARGET_HAS_bswap64_i64
1702: tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg);
1703: #else
1704: TCGv_i64 t0 = tcg_temp_new_i64();
1705: TCGv_i64 t1 = tcg_temp_new_i64();
1.1 root 1706:
1707: tcg_gen_shli_i64(t0, arg, 56);
1708:
1709: tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1710: tcg_gen_shli_i64(t1, t1, 40);
1711: tcg_gen_or_i64(t0, t0, t1);
1712:
1713: tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1714: tcg_gen_shli_i64(t1, t1, 24);
1715: tcg_gen_or_i64(t0, t0, t1);
1716:
1717: tcg_gen_andi_i64(t1, arg, 0xff000000);
1718: tcg_gen_shli_i64(t1, t1, 8);
1719: tcg_gen_or_i64(t0, t0, t1);
1720:
1721: tcg_gen_shri_i64(t1, arg, 8);
1722: tcg_gen_andi_i64(t1, t1, 0xff000000);
1723: tcg_gen_or_i64(t0, t0, t1);
1724:
1725: tcg_gen_shri_i64(t1, arg, 24);
1726: tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1727: tcg_gen_or_i64(t0, t0, t1);
1728:
1729: tcg_gen_shri_i64(t1, arg, 40);
1730: tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1731: tcg_gen_or_i64(t0, t0, t1);
1732:
1733: tcg_gen_shri_i64(t1, arg, 56);
1734: tcg_gen_or_i64(ret, t0, t1);
1.1.1.2 root 1735: tcg_temp_free_i64(t0);
1736: tcg_temp_free_i64(t1);
1.1 root 1737: #endif
1738: }
1739:
1740: #endif
1741:
1742: static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
1743: {
1744: #ifdef TCG_TARGET_HAS_neg_i32
1745: tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
1746: #else
1747: TCGv_i32 t0 = tcg_const_i32(0);
1748: tcg_gen_sub_i32(ret, t0, arg);
1749: tcg_temp_free_i32(t0);
1750: #endif
1751: }
1752:
1753: static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
1754: {
1755: #ifdef TCG_TARGET_HAS_neg_i64
1756: tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
1757: #else
1758: TCGv_i64 t0 = tcg_const_i64(0);
1759: tcg_gen_sub_i64(ret, t0, arg);
1760: tcg_temp_free_i64(t0);
1761: #endif
1762: }
1763:
1764: static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
1765: {
1.1.1.2 root 1766: #ifdef TCG_TARGET_HAS_not_i32
1767: tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
1768: #else
1.1 root 1769: tcg_gen_xori_i32(ret, arg, -1);
1.1.1.2 root 1770: #endif
1.1 root 1771: }
1772:
1773: static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
1774: {
1.1.1.2 root 1775: #ifdef TCG_TARGET_HAS_not_i64
1776: tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
1.1.1.4 root 1777: #elif defined(TCG_TARGET_HAS_not_i32) && TCG_TARGET_REG_BITS == 32
1778: tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1779: tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1.1.1.2 root 1780: #else
1.1 root 1781: tcg_gen_xori_i64(ret, arg, -1);
1.1.1.2 root 1782: #endif
1.1 root 1783: }
1784:
1785: static inline void tcg_gen_discard_i32(TCGv_i32 arg)
1786: {
1787: tcg_gen_op1_i32(INDEX_op_discard, arg);
1788: }
1789:
1790: #if TCG_TARGET_REG_BITS == 32
1791: static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1792: {
1793: tcg_gen_discard_i32(TCGV_LOW(arg));
1794: tcg_gen_discard_i32(TCGV_HIGH(arg));
1795: }
1796: #else
1797: static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1798: {
1799: tcg_gen_op1_i64(INDEX_op_discard, arg);
1800: }
1801: #endif
1802:
1803: static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high)
1804: {
1805: #if TCG_TARGET_REG_BITS == 32
1806: tcg_gen_mov_i32(TCGV_LOW(dest), low);
1807: tcg_gen_mov_i32(TCGV_HIGH(dest), high);
1808: #else
1809: TCGv_i64 tmp = tcg_temp_new_i64();
1810: /* This extension is only needed for type correctness.
1811: We may be able to do better given target specific information. */
1812: tcg_gen_extu_i32_i64(tmp, high);
1813: tcg_gen_shli_i64(tmp, tmp, 32);
1814: tcg_gen_extu_i32_i64(dest, low);
1815: tcg_gen_or_i64(dest, dest, tmp);
1816: tcg_temp_free_i64(tmp);
1817: #endif
1818: }
1819:
1820: static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high)
1821: {
1822: #if TCG_TARGET_REG_BITS == 32
1823: tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high));
1824: #else
1825: TCGv_i64 tmp = tcg_temp_new_i64();
1826: tcg_gen_ext32u_i64(dest, low);
1827: tcg_gen_shli_i64(tmp, high, 32);
1828: tcg_gen_or_i64(dest, dest, tmp);
1829: tcg_temp_free_i64(tmp);
1830: #endif
1831: }
1832:
1833: static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1834: {
1.1.1.4 root 1835: #ifdef TCG_TARGET_HAS_andc_i32
1836: tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2);
1837: #else
1.1 root 1838: TCGv_i32 t0;
1839: t0 = tcg_temp_new_i32();
1840: tcg_gen_not_i32(t0, arg2);
1841: tcg_gen_and_i32(ret, arg1, t0);
1842: tcg_temp_free_i32(t0);
1.1.1.4 root 1843: #endif
1.1 root 1844: }
1845:
1846: static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1847: {
1.1.1.4 root 1848: #ifdef TCG_TARGET_HAS_andc_i64
1849: tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2);
1850: #elif defined(TCG_TARGET_HAS_andc_i32) && TCG_TARGET_REG_BITS == 32
1851: tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1852: tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1853: #else
1.1 root 1854: TCGv_i64 t0;
1855: t0 = tcg_temp_new_i64();
1856: tcg_gen_not_i64(t0, arg2);
1857: tcg_gen_and_i64(ret, arg1, t0);
1858: tcg_temp_free_i64(t0);
1.1.1.4 root 1859: #endif
1.1 root 1860: }
1861:
1862: static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1863: {
1.1.1.4 root 1864: #ifdef TCG_TARGET_HAS_eqv_i32
1865: tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2);
1866: #else
1.1.1.2 root 1867: tcg_gen_xor_i32(ret, arg1, arg2);
1868: tcg_gen_not_i32(ret, ret);
1.1.1.4 root 1869: #endif
1.1 root 1870: }
1871:
1872: static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1873: {
1.1.1.4 root 1874: #ifdef TCG_TARGET_HAS_eqv_i64
1875: tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2);
1876: #elif defined(TCG_TARGET_HAS_eqv_i32) && TCG_TARGET_REG_BITS == 32
1877: tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1878: tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1879: #else
1.1.1.2 root 1880: tcg_gen_xor_i64(ret, arg1, arg2);
1881: tcg_gen_not_i64(ret, ret);
1.1.1.4 root 1882: #endif
1.1 root 1883: }
1884:
1885: static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1886: {
1.1.1.4 root 1887: #ifdef TCG_TARGET_HAS_nand_i32
1888: tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2);
1889: #else
1.1.1.2 root 1890: tcg_gen_and_i32(ret, arg1, arg2);
1891: tcg_gen_not_i32(ret, ret);
1.1.1.4 root 1892: #endif
1.1 root 1893: }
1894:
1895: static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1896: {
1.1.1.4 root 1897: #ifdef TCG_TARGET_HAS_nand_i64
1898: tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2);
1899: #elif defined(TCG_TARGET_HAS_nand_i32) && TCG_TARGET_REG_BITS == 32
1900: tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1901: tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1902: #else
1.1.1.2 root 1903: tcg_gen_and_i64(ret, arg1, arg2);
1904: tcg_gen_not_i64(ret, ret);
1.1.1.4 root 1905: #endif
1.1 root 1906: }
1907:
1908: static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1909: {
1.1.1.4 root 1910: #ifdef TCG_TARGET_HAS_nor_i32
1911: tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2);
1912: #else
1.1.1.2 root 1913: tcg_gen_or_i32(ret, arg1, arg2);
1914: tcg_gen_not_i32(ret, ret);
1.1.1.4 root 1915: #endif
1.1 root 1916: }
1917:
1918: static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1919: {
1.1.1.4 root 1920: #ifdef TCG_TARGET_HAS_nor_i64
1921: tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2);
1922: #elif defined(TCG_TARGET_HAS_nor_i32) && TCG_TARGET_REG_BITS == 32
1923: tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1924: tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1925: #else
1.1.1.2 root 1926: tcg_gen_or_i64(ret, arg1, arg2);
1927: tcg_gen_not_i64(ret, ret);
1.1.1.4 root 1928: #endif
1.1 root 1929: }
1930:
1931: static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1932: {
1.1.1.4 root 1933: #ifdef TCG_TARGET_HAS_orc_i32
1934: tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2);
1935: #else
1.1 root 1936: TCGv_i32 t0;
1937: t0 = tcg_temp_new_i32();
1938: tcg_gen_not_i32(t0, arg2);
1939: tcg_gen_or_i32(ret, arg1, t0);
1940: tcg_temp_free_i32(t0);
1.1.1.4 root 1941: #endif
1.1 root 1942: }
1943:
1944: static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1945: {
1.1.1.4 root 1946: #ifdef TCG_TARGET_HAS_orc_i64
1947: tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2);
1948: #elif defined(TCG_TARGET_HAS_orc_i32) && TCG_TARGET_REG_BITS == 32
1949: tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1950: tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1951: #else
1.1 root 1952: TCGv_i64 t0;
1953: t0 = tcg_temp_new_i64();
1954: tcg_gen_not_i64(t0, arg2);
1955: tcg_gen_or_i64(ret, arg1, t0);
1956: tcg_temp_free_i64(t0);
1.1.1.4 root 1957: #endif
1.1 root 1958: }
1959:
1960: static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1961: {
1.1.1.2 root 1962: #ifdef TCG_TARGET_HAS_rot_i32
1963: tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2);
1964: #else
1.1 root 1965: TCGv_i32 t0, t1;
1966:
1967: t0 = tcg_temp_new_i32();
1968: t1 = tcg_temp_new_i32();
1969: tcg_gen_shl_i32(t0, arg1, arg2);
1970: tcg_gen_subfi_i32(t1, 32, arg2);
1971: tcg_gen_shr_i32(t1, arg1, t1);
1972: tcg_gen_or_i32(ret, t0, t1);
1973: tcg_temp_free_i32(t0);
1974: tcg_temp_free_i32(t1);
1.1.1.2 root 1975: #endif
1.1 root 1976: }
1977:
1978: static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1979: {
1.1.1.2 root 1980: #ifdef TCG_TARGET_HAS_rot_i64
1981: tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2);
1982: #else
1.1 root 1983: TCGv_i64 t0, t1;
1984:
1985: t0 = tcg_temp_new_i64();
1986: t1 = tcg_temp_new_i64();
1987: tcg_gen_shl_i64(t0, arg1, arg2);
1988: tcg_gen_subfi_i64(t1, 64, arg2);
1989: tcg_gen_shr_i64(t1, arg1, t1);
1990: tcg_gen_or_i64(ret, t0, t1);
1991: tcg_temp_free_i64(t0);
1992: tcg_temp_free_i64(t1);
1.1.1.2 root 1993: #endif
1.1 root 1994: }
1995:
1996: static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1997: {
1998: /* some cases can be optimized here */
1999: if (arg2 == 0) {
2000: tcg_gen_mov_i32(ret, arg1);
2001: } else {
1.1.1.2 root 2002: #ifdef TCG_TARGET_HAS_rot_i32
2003: TCGv_i32 t0 = tcg_const_i32(arg2);
2004: tcg_gen_rotl_i32(ret, arg1, t0);
2005: tcg_temp_free_i32(t0);
2006: #else
1.1 root 2007: TCGv_i32 t0, t1;
2008: t0 = tcg_temp_new_i32();
2009: t1 = tcg_temp_new_i32();
2010: tcg_gen_shli_i32(t0, arg1, arg2);
2011: tcg_gen_shri_i32(t1, arg1, 32 - arg2);
2012: tcg_gen_or_i32(ret, t0, t1);
2013: tcg_temp_free_i32(t0);
2014: tcg_temp_free_i32(t1);
1.1.1.2 root 2015: #endif
1.1 root 2016: }
2017: }
2018:
2019: static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
2020: {
2021: /* some cases can be optimized here */
2022: if (arg2 == 0) {
2023: tcg_gen_mov_i64(ret, arg1);
2024: } else {
1.1.1.2 root 2025: #ifdef TCG_TARGET_HAS_rot_i64
2026: TCGv_i64 t0 = tcg_const_i64(arg2);
2027: tcg_gen_rotl_i64(ret, arg1, t0);
2028: tcg_temp_free_i64(t0);
2029: #else
1.1 root 2030: TCGv_i64 t0, t1;
2031: t0 = tcg_temp_new_i64();
2032: t1 = tcg_temp_new_i64();
2033: tcg_gen_shli_i64(t0, arg1, arg2);
2034: tcg_gen_shri_i64(t1, arg1, 64 - arg2);
2035: tcg_gen_or_i64(ret, t0, t1);
2036: tcg_temp_free_i64(t0);
2037: tcg_temp_free_i64(t1);
1.1.1.2 root 2038: #endif
1.1 root 2039: }
2040: }
2041:
2042: static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
2043: {
1.1.1.2 root 2044: #ifdef TCG_TARGET_HAS_rot_i32
2045: tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2);
2046: #else
1.1 root 2047: TCGv_i32 t0, t1;
2048:
2049: t0 = tcg_temp_new_i32();
2050: t1 = tcg_temp_new_i32();
2051: tcg_gen_shr_i32(t0, arg1, arg2);
2052: tcg_gen_subfi_i32(t1, 32, arg2);
2053: tcg_gen_shl_i32(t1, arg1, t1);
2054: tcg_gen_or_i32(ret, t0, t1);
2055: tcg_temp_free_i32(t0);
2056: tcg_temp_free_i32(t1);
1.1.1.2 root 2057: #endif
1.1 root 2058: }
2059:
2060: static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
2061: {
1.1.1.2 root 2062: #ifdef TCG_TARGET_HAS_rot_i64
2063: tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2);
2064: #else
1.1 root 2065: TCGv_i64 t0, t1;
2066:
2067: t0 = tcg_temp_new_i64();
2068: t1 = tcg_temp_new_i64();
1.1.1.2 root 2069: tcg_gen_shr_i64(t0, arg1, arg2);
1.1 root 2070: tcg_gen_subfi_i64(t1, 64, arg2);
2071: tcg_gen_shl_i64(t1, arg1, t1);
2072: tcg_gen_or_i64(ret, t0, t1);
2073: tcg_temp_free_i64(t0);
2074: tcg_temp_free_i64(t1);
1.1.1.2 root 2075: #endif
1.1 root 2076: }
2077:
2078: static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
2079: {
2080: /* some cases can be optimized here */
2081: if (arg2 == 0) {
2082: tcg_gen_mov_i32(ret, arg1);
2083: } else {
2084: tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
2085: }
2086: }
2087:
2088: static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
2089: {
2090: /* some cases can be optimized here */
2091: if (arg2 == 0) {
2092: tcg_gen_mov_i64(ret, arg1);
2093: } else {
2094: tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
2095: }
2096: }
2097:
1.1.1.5 ! root 2098: static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
! 2099: TCGv_i32 arg2, unsigned int ofs,
! 2100: unsigned int len)
! 2101: {
! 2102: #ifdef TCG_TARGET_HAS_deposit_i32
! 2103: tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len);
! 2104: #else
! 2105: uint32_t mask = (1u << len) - 1;
! 2106: TCGv_i32 t1 = tcg_temp_new_i32 ();
! 2107:
! 2108: tcg_gen_andi_i32(t1, arg2, mask);
! 2109: tcg_gen_shli_i32(t1, t1, ofs);
! 2110: tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
! 2111: tcg_gen_or_i32(ret, ret, t1);
! 2112:
! 2113: tcg_temp_free_i32(t1);
! 2114: #endif
! 2115: }
! 2116:
! 2117: static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
! 2118: TCGv_i64 arg2, unsigned int ofs,
! 2119: unsigned int len)
! 2120: {
! 2121: #ifdef TCG_TARGET_HAS_deposit_i64
! 2122: tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len);
! 2123: #else
! 2124: uint64_t mask = (1ull << len) - 1;
! 2125: TCGv_i64 t1 = tcg_temp_new_i64 ();
! 2126:
! 2127: tcg_gen_andi_i64(t1, arg2, mask);
! 2128: tcg_gen_shli_i64(t1, t1, ofs);
! 2129: tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
! 2130: tcg_gen_or_i64(ret, ret, t1);
! 2131:
! 2132: tcg_temp_free_i64(t1);
! 2133: #endif
! 2134: }
! 2135:
1.1 root 2136: /***************************************/
2137: /* QEMU specific operations. Their type depend on the QEMU CPU
2138: type. */
2139: #ifndef TARGET_LONG_BITS
2140: #error must include QEMU headers
2141: #endif
2142:
2143: #if TARGET_LONG_BITS == 32
2144: #define TCGv TCGv_i32
2145: #define tcg_temp_new() tcg_temp_new_i32()
2146: #define tcg_global_reg_new tcg_global_reg_new_i32
2147: #define tcg_global_mem_new tcg_global_mem_new_i32
2148: #define tcg_temp_local_new() tcg_temp_local_new_i32()
2149: #define tcg_temp_free tcg_temp_free_i32
2150: #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
2151: #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
2152: #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
1.1.1.2 root 2153: #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
1.1 root 2154: #else
2155: #define TCGv TCGv_i64
2156: #define tcg_temp_new() tcg_temp_new_i64()
2157: #define tcg_global_reg_new tcg_global_reg_new_i64
2158: #define tcg_global_mem_new tcg_global_mem_new_i64
2159: #define tcg_temp_local_new() tcg_temp_local_new_i64()
2160: #define tcg_temp_free tcg_temp_free_i64
2161: #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
2162: #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
2163: #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
1.1.1.2 root 2164: #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
1.1 root 2165: #endif
2166:
2167: /* debug info: write the PC of the corresponding QEMU CPU instruction */
2168: static inline void tcg_gen_debug_insn_start(uint64_t pc)
2169: {
2170: /* XXX: must really use a 32 bit size for TCGArg in all cases */
2171: #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
2172: tcg_gen_op2ii(INDEX_op_debug_insn_start,
2173: (uint32_t)(pc), (uint32_t)(pc >> 32));
2174: #else
2175: tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
2176: #endif
2177: }
2178:
2179: static inline void tcg_gen_exit_tb(tcg_target_long val)
2180: {
2181: tcg_gen_op1i(INDEX_op_exit_tb, val);
2182: }
2183:
2184: static inline void tcg_gen_goto_tb(int idx)
2185: {
2186: tcg_gen_op1i(INDEX_op_goto_tb, idx);
2187: }
2188:
2189: #if TCG_TARGET_REG_BITS == 32
2190: static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
2191: {
2192: #if TARGET_LONG_BITS == 32
2193: tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index);
2194: #else
2195: tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr),
2196: TCGV_HIGH(addr), mem_index);
2197: tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2198: #endif
2199: }
2200:
2201: static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
2202: {
2203: #if TARGET_LONG_BITS == 32
2204: tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index);
2205: #else
2206: tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr),
2207: TCGV_HIGH(addr), mem_index);
2208: tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2209: #endif
2210: }
2211:
2212: static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
2213: {
2214: #if TARGET_LONG_BITS == 32
2215: tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index);
2216: #else
2217: tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr),
2218: TCGV_HIGH(addr), mem_index);
2219: tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2220: #endif
2221: }
2222:
2223: static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
2224: {
2225: #if TARGET_LONG_BITS == 32
2226: tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index);
2227: #else
2228: tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr),
2229: TCGV_HIGH(addr), mem_index);
2230: tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2231: #endif
2232: }
2233:
2234: static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
2235: {
2236: #if TARGET_LONG_BITS == 32
1.1.1.4 root 2237: tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
1.1 root 2238: #else
1.1.1.4 root 2239: tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
1.1 root 2240: TCGV_HIGH(addr), mem_index);
2241: tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2242: #endif
2243: }
2244:
2245: static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
2246: {
2247: #if TARGET_LONG_BITS == 32
1.1.1.4 root 2248: tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
1.1 root 2249: #else
1.1.1.4 root 2250: tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
1.1 root 2251: TCGV_HIGH(addr), mem_index);
2252: tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2253: #endif
2254: }
2255:
2256: static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
2257: {
2258: #if TARGET_LONG_BITS == 32
2259: tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index);
2260: #else
2261: tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret),
2262: TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
2263: #endif
2264: }
2265:
2266: static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
2267: {
2268: #if TARGET_LONG_BITS == 32
2269: tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index);
2270: #else
2271: tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr),
2272: TCGV_HIGH(addr), mem_index);
2273: #endif
2274: }
2275:
2276: static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
2277: {
2278: #if TARGET_LONG_BITS == 32
2279: tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index);
2280: #else
2281: tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr),
2282: TCGV_HIGH(addr), mem_index);
2283: #endif
2284: }
2285:
2286: static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2287: {
2288: #if TARGET_LONG_BITS == 32
2289: tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index);
2290: #else
2291: tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr),
2292: TCGV_HIGH(addr), mem_index);
2293: #endif
2294: }
2295:
2296: static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2297: {
2298: #if TARGET_LONG_BITS == 32
2299: tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr,
2300: mem_index);
2301: #else
2302: tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg),
2303: TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
2304: #endif
2305: }
2306:
2307: #define tcg_gen_ld_ptr tcg_gen_ld_i32
2308: #define tcg_gen_discard_ptr tcg_gen_discard_i32
2309:
2310: #else /* TCG_TARGET_REG_BITS == 32 */
2311:
2312: static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
2313: {
2314: tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index);
2315: }
2316:
2317: static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
2318: {
2319: tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index);
2320: }
2321:
2322: static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
2323: {
2324: tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index);
2325: }
2326:
2327: static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
2328: {
2329: tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index);
2330: }
2331:
2332: static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
2333: {
1.1.1.4 root 2334: #if TARGET_LONG_BITS == 32
2335: tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index);
2336: #else
1.1 root 2337: tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1.1.1.4 root 2338: #endif
1.1 root 2339: }
2340:
2341: static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
2342: {
1.1.1.4 root 2343: #if TARGET_LONG_BITS == 32
2344: tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index);
2345: #else
1.1 root 2346: tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index);
1.1.1.4 root 2347: #endif
1.1 root 2348: }
2349:
2350: static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
2351: {
2352: tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index);
2353: }
2354:
2355: static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
2356: {
2357: tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index);
2358: }
2359:
2360: static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
2361: {
2362: tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index);
2363: }
2364:
2365: static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2366: {
2367: tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index);
2368: }
2369:
2370: static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2371: {
2372: tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index);
2373: }
2374:
2375: #define tcg_gen_ld_ptr tcg_gen_ld_i64
2376: #define tcg_gen_discard_ptr tcg_gen_discard_i64
2377:
2378: #endif /* TCG_TARGET_REG_BITS != 32 */
2379:
2380: #if TARGET_LONG_BITS == 64
2381: #define tcg_gen_movi_tl tcg_gen_movi_i64
2382: #define tcg_gen_mov_tl tcg_gen_mov_i64
2383: #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
2384: #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
2385: #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
2386: #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
2387: #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
2388: #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
2389: #define tcg_gen_ld_tl tcg_gen_ld_i64
2390: #define tcg_gen_st8_tl tcg_gen_st8_i64
2391: #define tcg_gen_st16_tl tcg_gen_st16_i64
2392: #define tcg_gen_st32_tl tcg_gen_st32_i64
2393: #define tcg_gen_st_tl tcg_gen_st_i64
2394: #define tcg_gen_add_tl tcg_gen_add_i64
2395: #define tcg_gen_addi_tl tcg_gen_addi_i64
2396: #define tcg_gen_sub_tl tcg_gen_sub_i64
2397: #define tcg_gen_neg_tl tcg_gen_neg_i64
2398: #define tcg_gen_subfi_tl tcg_gen_subfi_i64
2399: #define tcg_gen_subi_tl tcg_gen_subi_i64
2400: #define tcg_gen_and_tl tcg_gen_and_i64
2401: #define tcg_gen_andi_tl tcg_gen_andi_i64
2402: #define tcg_gen_or_tl tcg_gen_or_i64
2403: #define tcg_gen_ori_tl tcg_gen_ori_i64
2404: #define tcg_gen_xor_tl tcg_gen_xor_i64
2405: #define tcg_gen_xori_tl tcg_gen_xori_i64
2406: #define tcg_gen_not_tl tcg_gen_not_i64
2407: #define tcg_gen_shl_tl tcg_gen_shl_i64
2408: #define tcg_gen_shli_tl tcg_gen_shli_i64
2409: #define tcg_gen_shr_tl tcg_gen_shr_i64
2410: #define tcg_gen_shri_tl tcg_gen_shri_i64
2411: #define tcg_gen_sar_tl tcg_gen_sar_i64
2412: #define tcg_gen_sari_tl tcg_gen_sari_i64
2413: #define tcg_gen_brcond_tl tcg_gen_brcond_i64
2414: #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
1.1.1.4 root 2415: #define tcg_gen_setcond_tl tcg_gen_setcond_i64
2416: #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
1.1 root 2417: #define tcg_gen_mul_tl tcg_gen_mul_i64
2418: #define tcg_gen_muli_tl tcg_gen_muli_i64
1.1.1.2 root 2419: #define tcg_gen_div_tl tcg_gen_div_i64
2420: #define tcg_gen_rem_tl tcg_gen_rem_i64
2421: #define tcg_gen_divu_tl tcg_gen_divu_i64
2422: #define tcg_gen_remu_tl tcg_gen_remu_i64
1.1 root 2423: #define tcg_gen_discard_tl tcg_gen_discard_i64
2424: #define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
2425: #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
2426: #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
2427: #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
2428: #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
2429: #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
2430: #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
2431: #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
2432: #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
2433: #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
2434: #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
2435: #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
1.1.1.2 root 2436: #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
2437: #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
2438: #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
1.1 root 2439: #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
2440: #define tcg_gen_andc_tl tcg_gen_andc_i64
2441: #define tcg_gen_eqv_tl tcg_gen_eqv_i64
2442: #define tcg_gen_nand_tl tcg_gen_nand_i64
2443: #define tcg_gen_nor_tl tcg_gen_nor_i64
2444: #define tcg_gen_orc_tl tcg_gen_orc_i64
2445: #define tcg_gen_rotl_tl tcg_gen_rotl_i64
2446: #define tcg_gen_rotli_tl tcg_gen_rotli_i64
2447: #define tcg_gen_rotr_tl tcg_gen_rotr_i64
2448: #define tcg_gen_rotri_tl tcg_gen_rotri_i64
1.1.1.5 ! root 2449: #define tcg_gen_deposit_tl tcg_gen_deposit_i64
1.1 root 2450: #define tcg_const_tl tcg_const_i64
2451: #define tcg_const_local_tl tcg_const_local_i64
2452: #else
2453: #define tcg_gen_movi_tl tcg_gen_movi_i32
2454: #define tcg_gen_mov_tl tcg_gen_mov_i32
2455: #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
2456: #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
2457: #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
2458: #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
2459: #define tcg_gen_ld32u_tl tcg_gen_ld_i32
2460: #define tcg_gen_ld32s_tl tcg_gen_ld_i32
2461: #define tcg_gen_ld_tl tcg_gen_ld_i32
2462: #define tcg_gen_st8_tl tcg_gen_st8_i32
2463: #define tcg_gen_st16_tl tcg_gen_st16_i32
2464: #define tcg_gen_st32_tl tcg_gen_st_i32
2465: #define tcg_gen_st_tl tcg_gen_st_i32
2466: #define tcg_gen_add_tl tcg_gen_add_i32
2467: #define tcg_gen_addi_tl tcg_gen_addi_i32
2468: #define tcg_gen_sub_tl tcg_gen_sub_i32
2469: #define tcg_gen_neg_tl tcg_gen_neg_i32
2470: #define tcg_gen_subfi_tl tcg_gen_subfi_i32
2471: #define tcg_gen_subi_tl tcg_gen_subi_i32
2472: #define tcg_gen_and_tl tcg_gen_and_i32
2473: #define tcg_gen_andi_tl tcg_gen_andi_i32
2474: #define tcg_gen_or_tl tcg_gen_or_i32
2475: #define tcg_gen_ori_tl tcg_gen_ori_i32
2476: #define tcg_gen_xor_tl tcg_gen_xor_i32
2477: #define tcg_gen_xori_tl tcg_gen_xori_i32
2478: #define tcg_gen_not_tl tcg_gen_not_i32
2479: #define tcg_gen_shl_tl tcg_gen_shl_i32
2480: #define tcg_gen_shli_tl tcg_gen_shli_i32
2481: #define tcg_gen_shr_tl tcg_gen_shr_i32
2482: #define tcg_gen_shri_tl tcg_gen_shri_i32
2483: #define tcg_gen_sar_tl tcg_gen_sar_i32
2484: #define tcg_gen_sari_tl tcg_gen_sari_i32
2485: #define tcg_gen_brcond_tl tcg_gen_brcond_i32
2486: #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
1.1.1.4 root 2487: #define tcg_gen_setcond_tl tcg_gen_setcond_i32
2488: #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
1.1 root 2489: #define tcg_gen_mul_tl tcg_gen_mul_i32
2490: #define tcg_gen_muli_tl tcg_gen_muli_i32
1.1.1.2 root 2491: #define tcg_gen_div_tl tcg_gen_div_i32
2492: #define tcg_gen_rem_tl tcg_gen_rem_i32
2493: #define tcg_gen_divu_tl tcg_gen_divu_i32
2494: #define tcg_gen_remu_tl tcg_gen_remu_i32
1.1 root 2495: #define tcg_gen_discard_tl tcg_gen_discard_i32
2496: #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
2497: #define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
2498: #define tcg_gen_extu_i32_tl tcg_gen_mov_i32
2499: #define tcg_gen_ext_i32_tl tcg_gen_mov_i32
2500: #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
2501: #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
2502: #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
2503: #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
2504: #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
2505: #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
2506: #define tcg_gen_ext32u_tl tcg_gen_mov_i32
2507: #define tcg_gen_ext32s_tl tcg_gen_mov_i32
1.1.1.2 root 2508: #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
2509: #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
1.1 root 2510: #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
2511: #define tcg_gen_andc_tl tcg_gen_andc_i32
2512: #define tcg_gen_eqv_tl tcg_gen_eqv_i32
2513: #define tcg_gen_nand_tl tcg_gen_nand_i32
2514: #define tcg_gen_nor_tl tcg_gen_nor_i32
2515: #define tcg_gen_orc_tl tcg_gen_orc_i32
2516: #define tcg_gen_rotl_tl tcg_gen_rotl_i32
2517: #define tcg_gen_rotli_tl tcg_gen_rotli_i32
2518: #define tcg_gen_rotr_tl tcg_gen_rotr_i32
2519: #define tcg_gen_rotri_tl tcg_gen_rotri_i32
1.1.1.5 ! root 2520: #define tcg_gen_deposit_tl tcg_gen_deposit_i32
1.1 root 2521: #define tcg_const_tl tcg_const_i32
2522: #define tcg_const_local_tl tcg_const_local_i32
2523: #endif
2524:
2525: #if TCG_TARGET_REG_BITS == 32
2526: #define tcg_gen_add_ptr tcg_gen_add_i32
2527: #define tcg_gen_addi_ptr tcg_gen_addi_i32
2528: #define tcg_gen_ext_i32_ptr tcg_gen_mov_i32
2529: #else /* TCG_TARGET_REG_BITS == 32 */
2530: #define tcg_gen_add_ptr tcg_gen_add_i64
2531: #define tcg_gen_addi_ptr tcg_gen_addi_i64
2532: #define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64
2533: #endif /* TCG_TARGET_REG_BITS != 32 */
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