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1.1 ! root 1: /* ! 2: * Tiny Code Generator for QEMU ! 3: * ! 4: * Copyright (c) 2008 Fabrice Bellard ! 5: * ! 6: * Permission is hereby granted, free of charge, to any person obtaining a copy ! 7: * of this software and associated documentation files (the "Software"), to deal ! 8: * in the Software without restriction, including without limitation the rights ! 9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ! 10: * copies of the Software, and to permit persons to whom the Software is ! 11: * furnished to do so, subject to the following conditions: ! 12: * ! 13: * The above copyright notice and this permission notice shall be included in ! 14: * all copies or substantial portions of the Software. ! 15: * ! 16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ! 17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ! 18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ! 19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ! 20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, ! 21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN ! 22: * THE SOFTWARE. ! 23: */ ! 24: #ifndef DEF2 ! 25: #define DEF2(name, oargs, iargs, cargs, flags) DEF(name, oargs + iargs + cargs, 0) ! 26: #endif ! 27: ! 28: /* predefined ops */ ! 29: DEF2(end, 0, 0, 0, 0) /* must be kept first */ ! 30: DEF2(nop, 0, 0, 0, 0) ! 31: DEF2(nop1, 0, 0, 1, 0) ! 32: DEF2(nop2, 0, 0, 2, 0) ! 33: DEF2(nop3, 0, 0, 3, 0) ! 34: DEF2(nopn, 0, 0, 1, 0) /* variable number of parameters */ ! 35: ! 36: DEF2(discard, 1, 0, 0, 0) ! 37: ! 38: DEF2(set_label, 0, 0, 1, 0) ! 39: DEF2(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */ ! 40: DEF2(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) ! 41: DEF2(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) ! 42: ! 43: DEF2(mov_i32, 1, 1, 0, 0) ! 44: DEF2(movi_i32, 1, 0, 1, 0) ! 45: /* load/store */ ! 46: DEF2(ld8u_i32, 1, 1, 1, 0) ! 47: DEF2(ld8s_i32, 1, 1, 1, 0) ! 48: DEF2(ld16u_i32, 1, 1, 1, 0) ! 49: DEF2(ld16s_i32, 1, 1, 1, 0) ! 50: DEF2(ld_i32, 1, 1, 1, 0) ! 51: DEF2(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) ! 52: DEF2(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) ! 53: DEF2(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) ! 54: /* arith */ ! 55: DEF2(add_i32, 1, 2, 0, 0) ! 56: DEF2(sub_i32, 1, 2, 0, 0) ! 57: DEF2(mul_i32, 1, 2, 0, 0) ! 58: #ifdef TCG_TARGET_HAS_div_i32 ! 59: DEF2(div_i32, 1, 2, 0, 0) ! 60: DEF2(divu_i32, 1, 2, 0, 0) ! 61: DEF2(rem_i32, 1, 2, 0, 0) ! 62: DEF2(remu_i32, 1, 2, 0, 0) ! 63: #else ! 64: DEF2(div2_i32, 2, 3, 0, 0) ! 65: DEF2(divu2_i32, 2, 3, 0, 0) ! 66: #endif ! 67: DEF2(and_i32, 1, 2, 0, 0) ! 68: DEF2(or_i32, 1, 2, 0, 0) ! 69: DEF2(xor_i32, 1, 2, 0, 0) ! 70: /* shifts */ ! 71: DEF2(shl_i32, 1, 2, 0, 0) ! 72: DEF2(shr_i32, 1, 2, 0, 0) ! 73: DEF2(sar_i32, 1, 2, 0, 0) ! 74: ! 75: DEF2(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) ! 76: #if TCG_TARGET_REG_BITS == 32 ! 77: DEF2(add2_i32, 2, 4, 0, 0) ! 78: DEF2(sub2_i32, 2, 4, 0, 0) ! 79: DEF2(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) ! 80: DEF2(mulu2_i32, 2, 2, 0, 0) ! 81: #endif ! 82: #ifdef TCG_TARGET_HAS_ext8s_i32 ! 83: DEF2(ext8s_i32, 1, 1, 0, 0) ! 84: #endif ! 85: #ifdef TCG_TARGET_HAS_ext16s_i32 ! 86: DEF2(ext16s_i32, 1, 1, 0, 0) ! 87: #endif ! 88: #ifdef TCG_TARGET_HAS_bswap_i32 ! 89: DEF2(bswap_i32, 1, 1, 0, 0) ! 90: #endif ! 91: ! 92: #if TCG_TARGET_REG_BITS == 64 ! 93: DEF2(mov_i64, 1, 1, 0, 0) ! 94: DEF2(movi_i64, 1, 0, 1, 0) ! 95: /* load/store */ ! 96: DEF2(ld8u_i64, 1, 1, 1, 0) ! 97: DEF2(ld8s_i64, 1, 1, 1, 0) ! 98: DEF2(ld16u_i64, 1, 1, 1, 0) ! 99: DEF2(ld16s_i64, 1, 1, 1, 0) ! 100: DEF2(ld32u_i64, 1, 1, 1, 0) ! 101: DEF2(ld32s_i64, 1, 1, 1, 0) ! 102: DEF2(ld_i64, 1, 1, 1, 0) ! 103: DEF2(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) ! 104: DEF2(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) ! 105: DEF2(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) ! 106: DEF2(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) ! 107: /* arith */ ! 108: DEF2(add_i64, 1, 2, 0, 0) ! 109: DEF2(sub_i64, 1, 2, 0, 0) ! 110: DEF2(mul_i64, 1, 2, 0, 0) ! 111: #ifdef TCG_TARGET_HAS_div_i64 ! 112: DEF2(div_i64, 1, 2, 0, 0) ! 113: DEF2(divu_i64, 1, 2, 0, 0) ! 114: DEF2(rem_i64, 1, 2, 0, 0) ! 115: DEF2(remu_i64, 1, 2, 0, 0) ! 116: #else ! 117: DEF2(div2_i64, 2, 3, 0, 0) ! 118: DEF2(divu2_i64, 2, 3, 0, 0) ! 119: #endif ! 120: DEF2(and_i64, 1, 2, 0, 0) ! 121: DEF2(or_i64, 1, 2, 0, 0) ! 122: DEF2(xor_i64, 1, 2, 0, 0) ! 123: /* shifts */ ! 124: DEF2(shl_i64, 1, 2, 0, 0) ! 125: DEF2(shr_i64, 1, 2, 0, 0) ! 126: DEF2(sar_i64, 1, 2, 0, 0) ! 127: ! 128: DEF2(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) ! 129: #ifdef TCG_TARGET_HAS_ext8s_i64 ! 130: DEF2(ext8s_i64, 1, 1, 0, 0) ! 131: #endif ! 132: #ifdef TCG_TARGET_HAS_ext16s_i64 ! 133: DEF2(ext16s_i64, 1, 1, 0, 0) ! 134: #endif ! 135: #ifdef TCG_TARGET_HAS_ext32s_i64 ! 136: DEF2(ext32s_i64, 1, 1, 0, 0) ! 137: #endif ! 138: #ifdef TCG_TARGET_HAS_bswap_i64 ! 139: DEF2(bswap_i64, 1, 1, 0, 0) ! 140: #endif ! 141: #endif ! 142: #ifdef TCG_TARGET_HAS_neg_i32 ! 143: DEF2(neg_i32, 1, 1, 0, 0) ! 144: #endif ! 145: #ifdef TCG_TARGET_HAS_neg_i64 ! 146: DEF2(neg_i64, 1, 1, 0, 0) ! 147: #endif ! 148: ! 149: /* QEMU specific */ ! 150: #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS ! 151: DEF2(debug_insn_start, 0, 0, 2, 0) ! 152: #else ! 153: DEF2(debug_insn_start, 0, 0, 1, 0) ! 154: #endif ! 155: DEF2(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) ! 156: DEF2(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) ! 157: /* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op ! 158: constants must be defined */ ! 159: #if TCG_TARGET_REG_BITS == 32 ! 160: #if TARGET_LONG_BITS == 32 ! 161: DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 162: #else ! 163: DEF2(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 164: #endif ! 165: #if TARGET_LONG_BITS == 32 ! 166: DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 167: #else ! 168: DEF2(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 169: #endif ! 170: #if TARGET_LONG_BITS == 32 ! 171: DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 172: #else ! 173: DEF2(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 174: #endif ! 175: #if TARGET_LONG_BITS == 32 ! 176: DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 177: #else ! 178: DEF2(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 179: #endif ! 180: #if TARGET_LONG_BITS == 32 ! 181: DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 182: #else ! 183: DEF2(qemu_ld32u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 184: #endif ! 185: #if TARGET_LONG_BITS == 32 ! 186: DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 187: #else ! 188: DEF2(qemu_ld32s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 189: #endif ! 190: #if TARGET_LONG_BITS == 32 ! 191: DEF2(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 192: #else ! 193: DEF2(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 194: #endif ! 195: ! 196: #if TARGET_LONG_BITS == 32 ! 197: DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 198: #else ! 199: DEF2(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 200: #endif ! 201: #if TARGET_LONG_BITS == 32 ! 202: DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 203: #else ! 204: DEF2(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 205: #endif ! 206: #if TARGET_LONG_BITS == 32 ! 207: DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 208: #else ! 209: DEF2(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 210: #endif ! 211: #if TARGET_LONG_BITS == 32 ! 212: DEF2(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 213: #else ! 214: DEF2(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 215: #endif ! 216: ! 217: #else /* TCG_TARGET_REG_BITS == 32 */ ! 218: ! 219: DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 220: DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 221: DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 222: DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 223: DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 224: DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 225: DEF2(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 226: ! 227: DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 228: DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 229: DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 230: DEF2(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) ! 231: ! 232: #endif /* TCG_TARGET_REG_BITS != 32 */ ! 233: ! 234: #undef DEF2
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