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1.1 root 1: /*
2: * Tiny Code Generator for QEMU
3: *
4: * Copyright (c) 2008 Fabrice Bellard
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
24: #ifndef DEF2
25: #define DEF2(name, oargs, iargs, cargs, flags) DEF(name, oargs + iargs + cargs, 0)
26: #endif
27:
28: /* predefined ops */
29: DEF2(end, 0, 0, 0, 0) /* must be kept first */
30: DEF2(nop, 0, 0, 0, 0)
31: DEF2(nop1, 0, 0, 1, 0)
32: DEF2(nop2, 0, 0, 2, 0)
33: DEF2(nop3, 0, 0, 3, 0)
34: DEF2(nopn, 0, 0, 1, 0) /* variable number of parameters */
35:
36: DEF2(discard, 1, 0, 0, 0)
37:
38: DEF2(set_label, 0, 0, 1, 0)
39: DEF2(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */
40: DEF2(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
41: DEF2(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
42:
43: DEF2(mov_i32, 1, 1, 0, 0)
44: DEF2(movi_i32, 1, 0, 1, 0)
45: /* load/store */
46: DEF2(ld8u_i32, 1, 1, 1, 0)
47: DEF2(ld8s_i32, 1, 1, 1, 0)
48: DEF2(ld16u_i32, 1, 1, 1, 0)
49: DEF2(ld16s_i32, 1, 1, 1, 0)
50: DEF2(ld_i32, 1, 1, 1, 0)
51: DEF2(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
52: DEF2(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
53: DEF2(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
54: /* arith */
55: DEF2(add_i32, 1, 2, 0, 0)
56: DEF2(sub_i32, 1, 2, 0, 0)
57: DEF2(mul_i32, 1, 2, 0, 0)
58: #ifdef TCG_TARGET_HAS_div_i32
59: DEF2(div_i32, 1, 2, 0, 0)
60: DEF2(divu_i32, 1, 2, 0, 0)
61: DEF2(rem_i32, 1, 2, 0, 0)
62: DEF2(remu_i32, 1, 2, 0, 0)
63: #else
64: DEF2(div2_i32, 2, 3, 0, 0)
65: DEF2(divu2_i32, 2, 3, 0, 0)
66: #endif
67: DEF2(and_i32, 1, 2, 0, 0)
68: DEF2(or_i32, 1, 2, 0, 0)
69: DEF2(xor_i32, 1, 2, 0, 0)
1.1.1.2 ! root 70: /* shifts/rotates */
1.1 root 71: DEF2(shl_i32, 1, 2, 0, 0)
72: DEF2(shr_i32, 1, 2, 0, 0)
73: DEF2(sar_i32, 1, 2, 0, 0)
1.1.1.2 ! root 74: #ifdef TCG_TARGET_HAS_rot_i32
! 75: DEF2(rotl_i32, 1, 2, 0, 0)
! 76: DEF2(rotr_i32, 1, 2, 0, 0)
! 77: #endif
1.1 root 78:
79: DEF2(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
80: #if TCG_TARGET_REG_BITS == 32
81: DEF2(add2_i32, 2, 4, 0, 0)
82: DEF2(sub2_i32, 2, 4, 0, 0)
83: DEF2(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
84: DEF2(mulu2_i32, 2, 2, 0, 0)
85: #endif
86: #ifdef TCG_TARGET_HAS_ext8s_i32
87: DEF2(ext8s_i32, 1, 1, 0, 0)
88: #endif
89: #ifdef TCG_TARGET_HAS_ext16s_i32
90: DEF2(ext16s_i32, 1, 1, 0, 0)
91: #endif
1.1.1.2 ! root 92: #ifdef TCG_TARGET_HAS_bswap16_i32
! 93: DEF2(bswap16_i32, 1, 1, 0, 0)
! 94: #endif
! 95: #ifdef TCG_TARGET_HAS_bswap32_i32
! 96: DEF2(bswap32_i32, 1, 1, 0, 0)
! 97: #endif
! 98: #ifdef TCG_TARGET_HAS_not_i32
! 99: DEF2(not_i32, 1, 1, 0, 0)
! 100: #endif
! 101: #ifdef TCG_TARGET_HAS_neg_i32
! 102: DEF2(neg_i32, 1, 1, 0, 0)
1.1 root 103: #endif
104:
105: #if TCG_TARGET_REG_BITS == 64
106: DEF2(mov_i64, 1, 1, 0, 0)
107: DEF2(movi_i64, 1, 0, 1, 0)
108: /* load/store */
109: DEF2(ld8u_i64, 1, 1, 1, 0)
110: DEF2(ld8s_i64, 1, 1, 1, 0)
111: DEF2(ld16u_i64, 1, 1, 1, 0)
112: DEF2(ld16s_i64, 1, 1, 1, 0)
113: DEF2(ld32u_i64, 1, 1, 1, 0)
114: DEF2(ld32s_i64, 1, 1, 1, 0)
115: DEF2(ld_i64, 1, 1, 1, 0)
116: DEF2(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
117: DEF2(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
118: DEF2(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
119: DEF2(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
120: /* arith */
121: DEF2(add_i64, 1, 2, 0, 0)
122: DEF2(sub_i64, 1, 2, 0, 0)
123: DEF2(mul_i64, 1, 2, 0, 0)
124: #ifdef TCG_TARGET_HAS_div_i64
125: DEF2(div_i64, 1, 2, 0, 0)
126: DEF2(divu_i64, 1, 2, 0, 0)
127: DEF2(rem_i64, 1, 2, 0, 0)
128: DEF2(remu_i64, 1, 2, 0, 0)
129: #else
130: DEF2(div2_i64, 2, 3, 0, 0)
131: DEF2(divu2_i64, 2, 3, 0, 0)
132: #endif
133: DEF2(and_i64, 1, 2, 0, 0)
134: DEF2(or_i64, 1, 2, 0, 0)
135: DEF2(xor_i64, 1, 2, 0, 0)
1.1.1.2 ! root 136: /* shifts/rotates */
1.1 root 137: DEF2(shl_i64, 1, 2, 0, 0)
138: DEF2(shr_i64, 1, 2, 0, 0)
139: DEF2(sar_i64, 1, 2, 0, 0)
1.1.1.2 ! root 140: #ifdef TCG_TARGET_HAS_rot_i64
! 141: DEF2(rotl_i64, 1, 2, 0, 0)
! 142: DEF2(rotr_i64, 1, 2, 0, 0)
! 143: #endif
1.1 root 144:
145: DEF2(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
146: #ifdef TCG_TARGET_HAS_ext8s_i64
147: DEF2(ext8s_i64, 1, 1, 0, 0)
148: #endif
149: #ifdef TCG_TARGET_HAS_ext16s_i64
150: DEF2(ext16s_i64, 1, 1, 0, 0)
151: #endif
152: #ifdef TCG_TARGET_HAS_ext32s_i64
153: DEF2(ext32s_i64, 1, 1, 0, 0)
154: #endif
1.1.1.2 ! root 155: #ifdef TCG_TARGET_HAS_bswap16_i64
! 156: DEF2(bswap16_i64, 1, 1, 0, 0)
1.1 root 157: #endif
1.1.1.2 ! root 158: #ifdef TCG_TARGET_HAS_bswap32_i64
! 159: DEF2(bswap32_i64, 1, 1, 0, 0)
1.1 root 160: #endif
1.1.1.2 ! root 161: #ifdef TCG_TARGET_HAS_bswap64_i64
! 162: DEF2(bswap64_i64, 1, 1, 0, 0)
! 163: #endif
! 164: #ifdef TCG_TARGET_HAS_not_i64
! 165: DEF2(not_i64, 1, 1, 0, 0)
1.1 root 166: #endif
167: #ifdef TCG_TARGET_HAS_neg_i64
168: DEF2(neg_i64, 1, 1, 0, 0)
169: #endif
1.1.1.2 ! root 170: #endif
1.1 root 171:
172: /* QEMU specific */
173: #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
174: DEF2(debug_insn_start, 0, 0, 2, 0)
175: #else
176: DEF2(debug_insn_start, 0, 0, 1, 0)
177: #endif
178: DEF2(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
179: DEF2(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
180: /* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op
181: constants must be defined */
182: #if TCG_TARGET_REG_BITS == 32
183: #if TARGET_LONG_BITS == 32
184: DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
185: #else
186: DEF2(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
187: #endif
188: #if TARGET_LONG_BITS == 32
189: DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
190: #else
191: DEF2(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
192: #endif
193: #if TARGET_LONG_BITS == 32
194: DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
195: #else
196: DEF2(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
197: #endif
198: #if TARGET_LONG_BITS == 32
199: DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
200: #else
201: DEF2(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
202: #endif
203: #if TARGET_LONG_BITS == 32
204: DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
205: #else
206: DEF2(qemu_ld32u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
207: #endif
208: #if TARGET_LONG_BITS == 32
209: DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
210: #else
211: DEF2(qemu_ld32s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
212: #endif
213: #if TARGET_LONG_BITS == 32
214: DEF2(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
215: #else
216: DEF2(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
217: #endif
218:
219: #if TARGET_LONG_BITS == 32
220: DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
221: #else
222: DEF2(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
223: #endif
224: #if TARGET_LONG_BITS == 32
225: DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
226: #else
227: DEF2(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
228: #endif
229: #if TARGET_LONG_BITS == 32
230: DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
231: #else
232: DEF2(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
233: #endif
234: #if TARGET_LONG_BITS == 32
235: DEF2(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
236: #else
237: DEF2(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
238: #endif
239:
240: #else /* TCG_TARGET_REG_BITS == 32 */
241:
242: DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
243: DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
244: DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
245: DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
246: DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
247: DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
248: DEF2(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
249:
250: DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
251: DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
252: DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
253: DEF2(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
254:
255: #endif /* TCG_TARGET_REG_BITS != 32 */
256:
257: #undef DEF2
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