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1.1 ! root 1: ;;- Machine description for GNU compiler ! 2: ;;- Motorola 68000 Version ! 3: ;; Copyright (C) 1987 Free Software Foundation, Inc. ! 4: ! 5: ;; This file is part of GNU CC. ! 6: ! 7: ;; GNU CC is distributed in the hope that it will be useful, ! 8: ;; but WITHOUT ANY WARRANTY. No author or distributor ! 9: ;; accepts responsibility to anyone for the consequences of using it ! 10: ;; or for whether it serves any particular purpose or works at all, ! 11: ;; unless he says so in writing. Refer to the GNU CC General Public ! 12: ;; License for full details. ! 13: ! 14: ;; Everyone is granted permission to copy, modify and redistribute ! 15: ;; GNU CC, but only under the conditions described in the ! 16: ;; GNU CC General Public License. A copy of this license is ! 17: ;; supposed to have been given to you along with GNU CC so you ! 18: ;; can know your rights and responsibilities. It should be in a ! 19: ;; file named COPYING. Among other things, the copyright notice ! 20: ;; and this notice must be preserved on all copies. ! 21: ! 22: ! 23: ;;- instruction definitions ! 24: ! 25: ;;- @@The original PO technology requires these to be ordered by speed, ! 26: ;;- @@ so that assigner will pick the fastest. ! 27: ! 28: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ! 29: ! 30: ;;- When naming insn's (operand 0 of define_insn) be careful about using ! 31: ;;- names from other targets machine descriptions. ! 32: ! 33: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code ! 34: ;;- updates for most instructions. ! 35: ! 36: ;;- Operand classes for the register allocator: ! 37: ;;- 'a' one of the address registers can be used. ! 38: ;;- 'd' one of the data registers can be used. ! 39: ;;- 'r' either a data or an address register can be used. ! 40: ! 41: ;;- Immedidate integer operands Constrains: ! 42: ;;- 'I' 1 .. 8 ! 43: ;;- 'J' -32768 .. 32767 ! 44: ;;- 'K' -128 .. 127 ! 45: ;;- 'L' -8 .. -1 ! 46: ! 47: ;;- Some of these insn's are composites of several m68000 op codes. ! 48: ;;- The assembler (or final @@??) insures that the appropriate one is ! 49: ;;- selected. ! 50: ! 51: (define_insn "" ! 52: [(set (match_operand:DF 0 "push_operand" "=m") ! 53: (match_operand:DF 1 "general_operand" "ro<>fF"))] ! 54: "" ! 55: "* ! 56: { ! 57: if (FP_REG_P (operands[1])) ! 58: return \"fmove%.d %f1,%0\"; ! 59: return output_move_double (operands); ! 60: }") ! 61: ! 62: (define_insn "" ! 63: [(set (match_operand:DI 0 "push_operand" "=m") ! 64: (match_operand:DI 1 "general_operand" "ro<>"))] ! 65: "" ! 66: "* ! 67: { ! 68: return output_move_double (operands); ! 69: }") ! 70: ! 71: (define_insn "tstsi" ! 72: [(set (cc0) ! 73: (match_operand:SI 0 "general_operand" "rm"))] ! 74: "" ! 75: "* ! 76: { ! 77: #ifdef ISI_OV ! 78: /* ISI's assembler fails to handle tstl a0. */ ! 79: if (! ADDRESS_REG_P (operands[0])) ! 80: #else ! 81: if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) ! 82: #endif ! 83: return \"tst%.l %0\"; ! 84: /* If you think that the 68020 does not support tstl a0, ! 85: reread page B-167 of the 68020 manual more carefully. */ ! 86: /* On an address reg, cmpw may replace cmpl. */ ! 87: #ifdef HPUX_ASM ! 88: return \"cmp%.w %0,%#0\"; ! 89: #else ! 90: return \"cmp%.w %#0,%0\"; ! 91: #endif ! 92: }") ! 93: ! 94: (define_insn "tsthi" ! 95: [(set (cc0) ! 96: (match_operand:HI 0 "general_operand" "rm"))] ! 97: "" ! 98: "* ! 99: { ! 100: #ifdef ISI_OV ! 101: if (! ADDRESS_REG_P (operands[0])) ! 102: #else ! 103: if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) ! 104: #endif ! 105: return \"tst%.w %0\"; ! 106: #ifdef HPUX_ASM ! 107: return \"cmp%.w %0,%#0\"; ! 108: #else ! 109: return \"cmp%.w %#0,%0\"; ! 110: #endif ! 111: }") ! 112: ! 113: (define_insn "tstqi" ! 114: [(set (cc0) ! 115: (match_operand:QI 0 "general_operand" "dm"))] ! 116: "" ! 117: "tst%.b %0") ! 118: ! 119: (define_insn "tstsf" ! 120: [(set (cc0) ! 121: (match_operand:SF 0 "general_operand" "fdm"))] ! 122: "TARGET_68881" ! 123: "* ! 124: { ! 125: cc_status.flags = CC_IN_68881; ! 126: if (FP_REG_P (operands[0])) ! 127: return \"ftst%.x %0\"; ! 128: return \"ftst%.s %0\"; ! 129: }") ! 130: ! 131: (define_insn "tstdf" ! 132: [(set (cc0) ! 133: (match_operand:DF 0 "general_operand" "fm"))] ! 134: "TARGET_68881" ! 135: "* ! 136: { ! 137: cc_status.flags = CC_IN_68881; ! 138: if (FP_REG_P (operands[0])) ! 139: return \"ftst%.x %0\"; ! 140: return \"ftst%.d %0\"; ! 141: }") ! 142: ! 143: ;; compare instructions. ! 144: ! 145: ;; A composite of the cmp, cmpa, & cmpi m68000 op codes. ! 146: (define_insn "cmpsi" ! 147: [(set (cc0) ! 148: (minus (match_operand:SI 0 "general_operand" "rKs,mr") ! 149: (match_operand:SI 1 "general_operand" "mr,Ksr")))] ! 150: "" ! 151: "* ! 152: { ! 153: if (REG_P (operands[1]) ! 154: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) ! 155: { cc_status.flags |= CC_REVERSED; ! 156: #ifdef HPUX_ASM ! 157: return \"cmp%.l %1,%0\"; ! 158: #else ! 159: return \"cmp%.l %0,%1\"; ! 160: #endif ! 161: } ! 162: #ifdef HPUX_ASM ! 163: return \"cmp%.l %0,%1\"; ! 164: #else ! 165: return \"cmp%.l %1,%0\"; ! 166: #endif ! 167: }") ! 168: ! 169: (define_insn "cmphi" ! 170: [(set (cc0) ! 171: (minus (match_operand:HI 0 "general_operand" "rn,mr") ! 172: (match_operand:HI 1 "general_operand" "mr,nr")))] ! 173: "" ! 174: "* ! 175: { ! 176: if (REG_P (operands[1]) ! 177: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) ! 178: { cc_status.flags |= CC_REVERSED; ! 179: #ifdef HPUX_ASM ! 180: return \"cmp%.w %1,%0\"; ! 181: #else ! 182: return \"cmp%.w %0,%1\"; ! 183: #endif ! 184: } ! 185: #ifdef HPUX_ASM ! 186: return \"cmp%.w %0,%1\"; ! 187: #else ! 188: return \"cmp%.w %1,%0\"; ! 189: #endif ! 190: }") ! 191: ! 192: (define_insn "" ! 193: [(set (cc0) ! 194: (minus (mem:QI (post_inc:SI (match_operand:SI 0 "general_operand" "+a"))) ! 195: (mem:QI (post_inc:SI (match_operand:SI 1 "general_operand" "+a")))))] ! 196: "! CONSTANT_P (operands[0]) && ! CONSTANT_P (operands[1])" ! 197: "* ! 198: #ifdef MOTOROLA ! 199: return \"cmpm.b (%1)+,(%0)+\"; ! 200: #else ! 201: return \"cmpmb %1@+,%0@+\"; ! 202: #endif ! 203: ") ! 204: ! 205: (define_insn "cmpqi" ! 206: [(set (cc0) ! 207: (minus (match_operand:QI 0 "general_operand" "dn,md") ! 208: (match_operand:QI 1 "general_operand" "dm,nd")))] ! 209: "" ! 210: "* ! 211: { ! 212: if (REG_P (operands[1]) ! 213: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) ! 214: { cc_status.flags |= CC_REVERSED; ! 215: #ifdef HPUX_ASM ! 216: return \"cmp%.b %1,%0\"; ! 217: #else ! 218: return \"cmp%.b %0,%1\"; ! 219: #endif ! 220: } ! 221: #ifdef HPUX_ASM ! 222: return \"cmp%.b %0,%1\"; ! 223: #else ! 224: return \"cmp%.b %1,%0\"; ! 225: #endif ! 226: }") ! 227: ! 228: (define_insn "cmpdf" ! 229: [(set (cc0) ! 230: (minus:DF (match_operand:DF 0 "general_operand" "f,mG") ! 231: (match_operand:DF 1 "general_operand" "fmG,f")))] ! 232: "TARGET_68881" ! 233: "* ! 234: { ! 235: cc_status.flags = CC_IN_68881; ! 236: #ifdef HPUX_ASM ! 237: if (REG_P (operands[0])) ! 238: { ! 239: if (REG_P (operands[1])) ! 240: return \"fcmp%.x %0,%1\"; ! 241: else ! 242: return \"fcmp%.d %0,%f1\"; ! 243: } ! 244: cc_status.flags |= CC_REVERSED; ! 245: return \"fcmp%.d %1,%f0\"; ! 246: #else ! 247: if (REG_P (operands[0])) ! 248: { ! 249: if (REG_P (operands[1])) ! 250: return \"fcmp%.x %1,%0\"; ! 251: else ! 252: return \"fcmp%.d %f1,%0\"; ! 253: } ! 254: cc_status.flags |= CC_REVERSED; ! 255: return \"fcmp%.d %f0,%1\"; ! 256: #endif ! 257: }") ! 258: ! 259: (define_insn "cmpsf" ! 260: [(set (cc0) ! 261: (minus:SF (match_operand:SF 0 "general_operand" "f,mdG") ! 262: (match_operand:SF 1 "general_operand" "fmdG,f")))] ! 263: "TARGET_68881" ! 264: "* ! 265: { ! 266: cc_status.flags = CC_IN_68881; ! 267: #ifdef HPUX_ASM ! 268: if (FP_REG_P (operands[0])) ! 269: { ! 270: if (FP_REG_P (operands[1])) ! 271: return \"fcmp%.x %0,%1\"; ! 272: else ! 273: return \"fcmp%.s %0,%f1\"; ! 274: } ! 275: cc_status.flags |= CC_REVERSED; ! 276: return \"fcmp%.s %1,%f0\"; ! 277: #else ! 278: if (FP_REG_P (operands[0])) ! 279: { ! 280: if (FP_REG_P (operands[1])) ! 281: return \"fcmp%.x %1,%0\"; ! 282: else ! 283: return \"fcmp%.s %f1,%0\"; ! 284: } ! 285: cc_status.flags |= CC_REVERSED; ! 286: return \"fcmp%.s %f0,%1\"; ! 287: #endif ! 288: }") ! 289: ! 290: ;; Recognizers for btst instructions. ! 291: ! 292: (define_insn "" ! 293: [(set (cc0) (zero_extract (match_operand:QI 0 "general_operand" "do") ! 294: (const_int 1) ! 295: (minus:SI (const_int 7) ! 296: (match_operand:SI 1 "general_operand" "di"))))] ! 297: "" ! 298: "* { return output_btst (operands, operands[1], operands[0], insn, 7); }") ! 299: ! 300: (define_insn "" ! 301: [(set (cc0) (zero_extract (match_operand:SI 0 "general_operand" "d") ! 302: (const_int 1) ! 303: (minus:SI (const_int 31) ! 304: (match_operand:SI 1 "general_operand" "di"))))] ! 305: "" ! 306: "* { return output_btst (operands, operands[1], operands[0], insn, 31); }") ! 307: ! 308: ;; The following two patterns are like the previous two ! 309: ;; except that they use the fact that bit-number operands ! 310: ;; are automatically masked to 3 or 5 bits. ! 311: ! 312: (define_insn "" ! 313: [(set (cc0) (zero_extract (match_operand:QI 0 "general_operand" "do") ! 314: (const_int 1) ! 315: (minus:SI (const_int 7) ! 316: (and:SI ! 317: (match_operand:SI 1 "general_operand" "d") ! 318: (const_int 7)))))] ! 319: "" ! 320: "* { return output_btst (operands, operands[1], operands[0], insn, 7); }") ! 321: ! 322: (define_insn "" ! 323: [(set (cc0) (zero_extract (match_operand:SI 0 "general_operand" "d") ! 324: (const_int 1) ! 325: (minus:SI (const_int 31) ! 326: (and:SI ! 327: (match_operand:SI 1 "general_operand" "d") ! 328: (const_int 31)))))] ! 329: "" ! 330: "* { return output_btst (operands, operands[1], operands[0], insn, 31); }") ! 331: ! 332: (define_insn "" ! 333: ;; The constraint "o,d" here means that a nonoffsetable memref ! 334: ;; will match the first alternative, and its address will be reloaded. ! 335: ;; Copying the memory contents into a reg would be incorrect if the ! 336: ;; bit position is over 7. ! 337: [(set (cc0) (zero_extract (match_operand:QI 0 "general_operand" "o,d") ! 338: (const_int 1) ! 339: (match_operand:SI 1 "general_operand" "i,i")))] ! 340: "GET_CODE (operands[1]) == CONST_INT" ! 341: "* ! 342: { operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1])); ! 343: return output_btst (operands, operands[1], operands[0], insn, 7); }") ! 344: ! 345: (define_insn "" ! 346: [(set (cc0) (zero_extract (match_operand:HI 0 "general_operand" "o,d") ! 347: (const_int 1) ! 348: (match_operand:SI 1 "general_operand" "i,i")))] ! 349: "GET_CODE (operands[1]) == CONST_INT" ! 350: "* ! 351: { ! 352: if (GET_CODE (operands[0]) == MEM) ! 353: { ! 354: operands[0] = adj_offsetable_operand (operands[0], ! 355: INTVAL (operands[1]) / 8); ! 356: operands[1] = gen_rtx (CONST_INT, VOIDmode, ! 357: 7 - INTVAL (operands[1]) % 8); ! 358: return output_btst (operands, operands[1], operands[0], insn, 7); ! 359: } ! 360: operands[1] = gen_rtx (CONST_INT, VOIDmode, ! 361: 15 - INTVAL (operands[1])); ! 362: return output_btst (operands, operands[1], operands[0], insn, 15); ! 363: }") ! 364: ! 365: (define_insn "" ! 366: [(set (cc0) (zero_extract (match_operand:SI 0 "general_operand" "do") ! 367: (const_int 1) ! 368: (match_operand:SI 1 "general_operand" "i")))] ! 369: "GET_CODE (operands[1]) == CONST_INT" ! 370: "* ! 371: { ! 372: if (GET_CODE (operands[0]) == MEM) ! 373: { ! 374: operands[0] = adj_offsetable_operand (operands[0], ! 375: INTVAL (operands[1]) / 8); ! 376: operands[1] = gen_rtx (CONST_INT, VOIDmode, ! 377: 7 - INTVAL (operands[1]) % 8); ! 378: return output_btst (operands, operands[1], operands[0], insn, 7); ! 379: } ! 380: operands[1] = gen_rtx (CONST_INT, VOIDmode, ! 381: 31 - INTVAL (operands[1])); ! 382: return output_btst (operands, operands[1], operands[0], insn, 31); ! 383: }") ! 384: ! 385: (define_insn "" ! 386: [(set (cc0) (subreg:SI (lshiftrt:QI (match_operand:QI 0 "general_operand" "dm") ! 387: (const_int 7)) ! 388: 0))] ! 389: "" ! 390: "* ! 391: { ! 392: cc_status.flags = CC_Z_IN_NOT_N | CC_NOT_NEGATIVE; ! 393: return \"tst%.b %0\"; ! 394: }") ! 395: ! 396: (define_insn "" ! 397: [(set (cc0) (and:SI (sign_extend:SI (sign_extend:HI (match_operand:QI 0 "general_operand" "dm"))) ! 398: (match_operand:SI 1 "general_operand" "i")))] ! 399: "(GET_CODE (operands[1]) == CONST_INT ! 400: && (unsigned) INTVAL (operands[1]) < 0x100 ! 401: && exact_log2 (INTVAL (operands[1])) >= 0)" ! 402: "* ! 403: { register int log = exact_log2 (INTVAL (operands[1])); ! 404: operands[1] = gen_rtx (CONST_INT, VOIDmode, log); ! 405: return output_btst (operands, operands[1], operands[0], insn, 7); ! 406: }") ! 407: ! 408: ;; move instructions ! 409: (define_insn "swapsi" ! 410: [(set (match_operand:SI 0 "general_operand" "r") ! 411: (match_operand:SI 1 "general_operand" "r")) ! 412: (set (match_dup 1) (match_dup 0))] ! 413: "" ! 414: "exg %1,%0") ! 415: ! 416: ;; Special case of fullword move when source is zero. ! 417: ;; The reason this is special is to avoid loading a zero ! 418: ;; into a data reg with moveq in order to store it elsewhere. ! 419: ! 420: (define_insn "" ! 421: [(set (match_operand:SI 0 "general_operand" "=g") ! 422: (const_int 0))] ! 423: "" ! 424: "* ! 425: { ! 426: if (ADDRESS_REG_P (operands[0])) ! 427: return \"sub%.l %0,%0\"; ! 428: return \"clr%.l %0\"; ! 429: }") ! 430: ! 431: ;; Another special case in which it is not desirable ! 432: ;; to reload the constant into a data register. ! 433: (define_insn "" ! 434: [(set (match_operand:SI 0 "push_operand" "=m") ! 435: (match_operand:SI 1 "general_operand" "J"))] ! 436: "GET_CODE (operands[1]) == CONST_INT ! 437: && INTVAL (operands[1]) >= -0x8000 ! 438: && INTVAL (operands[1]) < 0x8000" ! 439: "pea %a1") ! 440: ! 441: ;; General case of fullword move. The register constraints ! 442: ;; force integer constants in range for a moveq to be reloaded ! 443: ;; if they are headed for memory. ! 444: (define_insn "movsi" ! 445: [(set (match_operand:SI 0 "general_operand" "=g,da") ! 446: (match_operand:SI 1 "general_operand" "damKs,i"))] ! 447: "" ! 448: "* ! 449: { ! 450: if (GET_CODE (operands[1]) == CONST_INT) ! 451: { ! 452: if (operands[1] == const0_rtx ! 453: && (DATA_REG_P (operands[0]) ! 454: || GET_CODE (operands[0]) == MEM)) ! 455: return \"clr%.l %0\"; ! 456: else if (DATA_REG_P (operands[0]) ! 457: && INTVAL (operands[1]) < 128 ! 458: && INTVAL (operands[1]) >= -128) ! 459: { ! 460: #ifdef MOTOROLA ! 461: return \"moveq%.l %1,%0\"; ! 462: #else ! 463: return \"moveq %1,%0\"; ! 464: #endif ! 465: } ! 466: else if (ADDRESS_REG_P (operands[0]) ! 467: && INTVAL (operands[1]) < 0x8000 ! 468: && INTVAL (operands[1]) >= -0x8000) ! 469: return \"move%.w %1,%0\"; ! 470: else if (push_operand (operands[0], SImode) ! 471: && INTVAL (operands[1]) < 0x8000 ! 472: && INTVAL (operands[1]) >= -0x8000) ! 473: return \"pea %a1\"; ! 474: } ! 475: else if ((GET_CODE (operands[1]) == SYMBOL_REF ! 476: || GET_CODE (operands[1]) == CONST) ! 477: && push_operand (operands[0], SImode)) ! 478: return \"pea %a1\"; ! 479: else if ((GET_CODE (operands[1]) == SYMBOL_REF ! 480: || GET_CODE (operands[1]) == CONST) ! 481: && ADDRESS_REG_P (operands[0])) ! 482: return \"lea %a1,%0\"; ! 483: return \"move%.l %1,%0\"; ! 484: }") ! 485: ! 486: (define_insn "movhi" ! 487: [(set (match_operand:HI 0 "general_operand" "=g") ! 488: (match_operand:HI 1 "general_operand" "g"))] ! 489: "" ! 490: "* ! 491: { ! 492: if (GET_CODE (operands[1]) == CONST_INT) ! 493: { ! 494: if (operands[1] == const0_rtx ! 495: && (DATA_REG_P (operands[0]) ! 496: || GET_CODE (operands[0]) == MEM)) ! 497: return \"clr%.w %0\"; ! 498: } ! 499: else if (CONSTANT_P (operands[1])) ! 500: return \"move%.l %1,%0\"; ! 501: /* Recognize the insn before a tablejump, one that refers ! 502: to a table of offsets. Such an insn will need to refer ! 503: to a label on the insn. So output one. Use the label-number ! 504: of the table of offsets to generate this label. */ ! 505: if (GET_CODE (operands[1]) == MEM ! 506: && GET_CODE (XEXP (operands[1], 0)) == PLUS ! 507: && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF ! 508: || GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF) ! 509: && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS ! 510: && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) != PLUS) ! 511: { ! 512: rtx labelref; ! 513: if (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF) ! 514: labelref = XEXP (XEXP (operands[1], 0), 0); ! 515: else ! 516: labelref = XEXP (XEXP (operands[1], 0), 1); ! 517: #if defined (MOTOROLA) && ! defined (SGS_3B1) ! 518: #ifdef SGS ! 519: fprintf (asm_out_file, \"\\tset %s%d,.+2\\n\", \"LI\", ! 520: CODE_LABEL_NUMBER (XEXP (labelref, 0))); ! 521: #else ! 522: fprintf (asm_out_file, \"\\t.set %s%d,.+2\\n\", \"LI\", ! 523: CODE_LABEL_NUMBER (XEXP (labelref, 0))); ! 524: #endif ! 525: #else ! 526: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\", ! 527: CODE_LABEL_NUMBER (XEXP (labelref, 0))); ! 528: #endif ! 529: } ! 530: return \"move%.w %1,%0\"; ! 531: }") ! 532: ! 533: (define_insn "movstricthi" ! 534: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) ! 535: (match_operand:HI 1 "general_operand" "rmn"))] ! 536: "" ! 537: "* ! 538: { ! 539: if (GET_CODE (operands[1]) == CONST_INT) ! 540: { ! 541: if (operands[1] == const0_rtx ! 542: && (DATA_REG_P (operands[0]) ! 543: || GET_CODE (operands[0]) == MEM)) ! 544: return \"clr%.w %0\"; ! 545: } ! 546: return \"move%.w %1,%0\"; ! 547: }") ! 548: ! 549: (define_insn "movqi" ! 550: [(set (match_operand:QI 0 "general_operand" "=d,a,m") ! 551: (match_operand:QI 1 "general_operand" "g,d,dmi"))] ! 552: "" ! 553: "* ! 554: { ! 555: if (operands[1] == const0_rtx) ! 556: return \"clr%.b %0\"; ! 557: if (GET_CODE (operands[1]) == CONST_INT ! 558: && INTVAL (operands[1]) == -1) ! 559: return \"st %0\"; ! 560: if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1])) ! 561: return \"move%.l %1,%0\"; ! 562: if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1])) ! 563: return \"move%.w %1,%0\"; ! 564: return \"move%.b %1,%0\"; ! 565: }") ! 566: ! 567: (define_insn "movstrictqi" ! 568: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) ! 569: (match_operand:QI 1 "general_operand" "dmn"))] ! 570: "" ! 571: "* ! 572: { ! 573: if (operands[1] == const0_rtx) ! 574: return \"clr%.b %0\"; ! 575: return \"move%.b %1,%0\"; ! 576: }") ! 577: ! 578: (define_insn "movsf" ! 579: [(set (match_operand:SF 0 "general_operand" "=rmf") ! 580: (match_operand:SF 1 "general_operand" "rmfF"))] ! 581: "" ! 582: "* ! 583: { ! 584: if (FP_REG_P (operands[0])) ! 585: { ! 586: if (FP_REG_P (operands[1])) ! 587: return \"fmove%.x %1,%0\"; ! 588: else if (ADDRESS_REG_P (operands[1])) ! 589: return \"move%.l %1,%-\;fmove%.s %+,%0\"; ! 590: else if (GET_CODE (operands[1]) == CONST_DOUBLE) ! 591: return output_move_const_single (operands); ! 592: return \"fmove%.s %f1,%0\"; ! 593: } ! 594: if (FP_REG_P (operands[1])) ! 595: { ! 596: if (ADDRESS_REG_P (operands[0])) ! 597: return \"fmove%.s %1,%-\;move%.l %+,%0\"; ! 598: return \"fmove%.s %f1,%0\"; ! 599: } ! 600: return \"move%.l %1,%0\"; ! 601: }") ! 602: ! 603: (define_insn "movdf" ! 604: [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>") ! 605: (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))] ! 606: "" ! 607: "* ! 608: { ! 609: if (FP_REG_P (operands[0])) ! 610: { ! 611: if (FP_REG_P (operands[1])) ! 612: return \"fmove%.x %1,%0\"; ! 613: if (REG_P (operands[1])) ! 614: { ! 615: rtx xoperands[2]; ! 616: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); ! 617: output_asm_insn (\"move%.l %1,%-\", xoperands); ! 618: output_asm_insn (\"move%.l %1,%-\", operands); ! 619: return \"fmove%.d %+,%0\"; ! 620: } ! 621: if (GET_CODE (operands[1]) == CONST_DOUBLE) ! 622: return output_move_const_double (operands); ! 623: return \"fmove%.d %f1,%0\"; ! 624: } ! 625: else if (FP_REG_P (operands[1])) ! 626: { ! 627: if (REG_P (operands[0])) ! 628: { ! 629: output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands); ! 630: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); ! 631: return \"move%.l %+,%0\"; ! 632: } ! 633: else ! 634: return \"fmove%.d %f1,%0\"; ! 635: } ! 636: return output_move_double (operands); ! 637: } ! 638: ") ! 639: ! 640: ;; movdi can apply to fp regs in some cases ! 641: (define_insn "movdi" ! 642: [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f") ! 643: (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))] ! 644: "" ! 645: "* ! 646: { ! 647: if (FP_REG_P (operands[0])) ! 648: { ! 649: if (FP_REG_P (operands[1])) ! 650: return \"fmove%.x %1,%0\"; ! 651: if (REG_P (operands[1])) ! 652: { ! 653: rtx xoperands[2]; ! 654: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); ! 655: output_asm_insn (\"move%.l %1,%-\", xoperands); ! 656: output_asm_insn (\"move%.l %1,%-\", operands); ! 657: return \"fmove%.d %+,%0\"; ! 658: } ! 659: if (GET_CODE (operands[1]) == CONST_DOUBLE) ! 660: return output_move_const_double (operands); ! 661: return \"fmove%.d %f1,%0\"; ! 662: } ! 663: else if (FP_REG_P (operands[1])) ! 664: { ! 665: if (REG_P (operands[0])) ! 666: { ! 667: output_asm_insn (\"fmove.d %f1,%-\;move%.l %+,%0\", operands); ! 668: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); ! 669: return \"move%.l %+,%0\"; ! 670: } ! 671: else ! 672: return \"fmove%.d %f1,%0\"; ! 673: } ! 674: return output_move_double (operands); ! 675: } ! 676: ") ! 677: ! 678: ;; These go after the move instructions ! 679: ;; because the move instructions are better (require no spilling) ! 680: ;; when they can apply. But these go before the add and subtract insns ! 681: ;; because it is often shorter to use these when both apply. ! 682: (define_insn "pushasi" ! 683: [(set (match_operand:SI 0 "push_operand" "=m") ! 684: (match_operand:SI 1 "address_operand" "p"))] ! 685: "" ! 686: "pea %a1") ! 687: ! 688: ! 689: (define_insn "" ! 690: [(set (match_operand:SI 0 "general_operand" "=a") ! 691: (match_operand:QI 1 "address_operand" "p"))] ! 692: "" ! 693: "lea %a1,%0") ! 694: ! 695: ;; truncation instructions ! 696: (define_insn "truncsiqi2" ! 697: [(set (match_operand:QI 0 "general_operand" "=dm,d") ! 698: (truncate:QI ! 699: (match_operand:SI 1 "general_operand" "doJ,i")))] ! 700: "" ! 701: "* ! 702: { ! 703: if (GET_CODE (operands[0]) == REG) ! 704: return \"move%.l %1,%0\"; ! 705: if (GET_CODE (operands[1]) == MEM) ! 706: operands[1] = adj_offsetable_operand (operands[1], 3); ! 707: return \"move%.b %1,%0\"; ! 708: }") ! 709: ! 710: (define_insn "trunchiqi2" ! 711: [(set (match_operand:QI 0 "general_operand" "=dm,d") ! 712: (truncate:QI ! 713: (match_operand:HI 1 "general_operand" "doJ,i")))] ! 714: "" ! 715: "* ! 716: { ! 717: if (GET_CODE (operands[0]) == REG) ! 718: return \"move%.l %1,%0\"; ! 719: if (GET_CODE (operands[1]) == MEM) ! 720: operands[1] = adj_offsetable_operand (operands[1], 1); ! 721: return \"move%.b %1,%0\"; ! 722: }") ! 723: ! 724: (define_insn "truncsihi2" ! 725: [(set (match_operand:HI 0 "general_operand" "=dm,d") ! 726: (truncate:HI ! 727: (match_operand:SI 1 "general_operand" "roJ,i")))] ! 728: "" ! 729: "* ! 730: { ! 731: if (GET_CODE (operands[0]) == REG) ! 732: return \"move%.l %1,%0\"; ! 733: if (GET_CODE (operands[1]) == MEM) ! 734: operands[1] = adj_offsetable_operand (operands[1], 2); ! 735: return \"move%.w %1,%0\"; ! 736: }") ! 737: ! 738: ;; zero extension instructions ! 739: ! 740: (define_expand "zero_extendhisi2" ! 741: [(set (match_operand:SI 0 "general_operand" "") ! 742: (const_int 0)) ! 743: (set (strict_low_part (subreg:HI (match_operand:SI 0 "general_operand" "") 0)) ! 744: (match_operand:HI 1 "general_operand" ""))] ! 745: "" ! 746: "operands[1] = make_safe_from (operands[1], operands[0]);") ! 747: ! 748: ;; Note that the one starting from HImode comes before those for QImode ! 749: ;; so that a constant operand will match HImode, not QImode. ! 750: ;(define_insn "zero_extendhisi2" ! 751: ; [(set (match_operand:SI 0 "general_operand" "=do<>") ! 752: ; (zero_extend:SI ! 753: ; (match_operand:HI 1 "general_operand" "rmn")))] ! 754: ; "" ! 755: ; "* ! 756: ;{ ! 757: ; if (DATA_REG_P (operands[0])) ! 758: ; { ! 759: ; if (GET_CODE (operands[1]) == REG ! 760: ; && REGNO (operands[0]) == REGNO (operands[1])) ! 761: ; return \"and%.l %#0xFFFF,%0\"; ! 762: ; if (reg_mentioned_p (operands[0], operands[1])) ! 763: ; return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\"; ! 764: ; return \"clr%.l %0\;move%.w %1,%0\"; ! 765: ; } ! 766: ; else if (GET_CODE (operands[0]) == MEM ! 767: ; && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) ! 768: ; return \"move%.w %1,%0\;clr%.w %0\"; ! 769: ; else if (GET_CODE (operands[0]) == MEM ! 770: ; && GET_CODE (XEXP (operands[0], 0)) == POST_INC) ! 771: ; return \"clr%.w %0\;move%.w %1,%0\"; ! 772: ; else ! 773: ; { ! 774: ; output_asm_insn (\"clr%.w %0\", operands); ! 775: ; operands[0] = adj_offsetable_operand (operands[0], 2); ! 776: ; return \"move%.w %1,%0\"; ! 777: ; } ! 778: ;}") ! 779: ! 780: (define_expand "zero_extendqihi2" ! 781: [(set (match_operand:HI 0 "general_operand" "") ! 782: (const_int 0)) ! 783: (set (strict_low_part (subreg:QI (match_operand:HI 0 "general_operand" "") 0)) ! 784: (match_operand:QI 1 "general_operand" ""))] ! 785: "" ! 786: "operands[1] = make_safe_from (operands[1], operands[0]);") ! 787: ! 788: ;(define_insn "zero_extendqihi2" ! 789: ; [(set (match_operand:HI 0 "general_operand" "=do<>") ! 790: ; (zero_extend:HI ! 791: ; (match_operand:QI 1 "general_operand" "dmn")))] ! 792: ; "" ! 793: ; "* ! 794: ;{ ! 795: ; if (DATA_REG_P (operands[0])) ! 796: ; { ! 797: ; if (GET_CODE (operands[1]) == REG ! 798: ; && REGNO (operands[0]) == REGNO (operands[1])) ! 799: ; return \"and%.w %#0xFF,%0\"; ! 800: ; if (reg_mentioned_p (operands[0], operands[1])) ! 801: ; return \"move%.b %1,%0\;and%.w %#0xFF,%0\"; ! 802: ; return \"clr%.w %0\;move%.b %1,%0\"; ! 803: ; } ! 804: ; else if (GET_CODE (operands[0]) == MEM ! 805: ; && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) ! 806: ; { ! 807: ; if (REGNO (XEXP (XEXP (operands[0], 0), 0)) ! 808: ; == STACK_POINTER_REGNUM) ! 809: ; return \"clr%.w %-\;move%.b %1,%0\"; ! 810: ; else ! 811: ; return \"move%.b %1,%0\;clr%.b %0\"; ! 812: ; } ! 813: ; else if (GET_CODE (operands[0]) == MEM ! 814: ; && GET_CODE (XEXP (operands[0], 0)) == POST_INC) ! 815: ; return \"clr%.b %0\;move%.b %1,%0\"; ! 816: ; else ! 817: ; { ! 818: ; output_asm_insn (\"clr%.b %0\", operands); ! 819: ; operands[0] = adj_offsetable_operand (operands[0], 1); ! 820: ; return \"move%.b %1,%0\"; ! 821: ; } ! 822: ;}") ! 823: ! 824: (define_expand "zero_extendqisi2" ! 825: [(set (match_operand:SI 0 "general_operand" "") ! 826: (const_int 0)) ! 827: (set (strict_low_part (subreg:QI (match_operand:SI 0 "general_operand" "") 0)) ! 828: (match_operand:QI 1 "general_operand" ""))] ! 829: "" ! 830: " operands[1] = make_safe_from (operands[1], operands[0]); ") ! 831: ! 832: ;(define_insn "zero_extendqisi2" ! 833: ; [(set (match_operand:SI 0 "general_operand" "=do<>") ! 834: ; (zero_extend:SI ! 835: ; (match_operand:QI 1 "general_operand" "dmn")))] ! 836: ; "" ! 837: ; "* ! 838: ;{ ! 839: ; if (DATA_REG_P (operands[0])) ! 840: ; { ! 841: ; if (GET_CODE (operands[1]) == REG ! 842: ; && REGNO (operands[0]) == REGNO (operands[1])) ! 843: ; return \"and%.l %#0xFF,%0\"; ! 844: ; if (reg_mentioned_p (operands[0], operands[1])) ! 845: ; return \"move%.b %1,%0\;and%.l %#0xFF,%0\"; ! 846: ; return \"clr%.l %0\;move%.b %1,%0\"; ! 847: ; } ! 848: ; else if (GET_CODE (operands[0]) == MEM ! 849: ; && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) ! 850: ; { ! 851: ; operands[0] = XEXP (XEXP (operands[0], 0), 0); ! 852: ;#ifdef MOTOROLA ! 853: ; return \"clr.l -(%0)\;move%.b %1,(3,%0)\"; ! 854: ;#else ! 855: ; return \"clrl %0@-\;moveb %1,%0@(3)\"; ! 856: ;#endif ! 857: ; } ! 858: ; else if (GET_CODE (operands[0]) == MEM ! 859: ; && GET_CODE (XEXP (operands[0], 0)) == POST_INC) ! 860: ; { ! 861: ; operands[0] = XEXP (XEXP (operands[0], 0), 0); ! 862: ;#ifdef MOTOROLA ! 863: ; return \"clr.l (%0)+\;move%.b %1,(-1,%0)\"; ! 864: ;#else ! 865: ; return \"clrl %0@+\;moveb %1,%0@(-1)\"; ! 866: ;#endif ! 867: ; } ! 868: ; else ! 869: ; { ! 870: ; output_asm_insn (\"clr%.l %0\", operands); ! 871: ; operands[0] = adj_offsetable_operand (operands[0], 3); ! 872: ; return \"move%.b %1,%0\"; ! 873: ; } ! 874: ;}") ! 875: ! 876: ;; sign extension instructions ! 877: ;; Note that the one starting from HImode comes before those for QImode ! 878: ;; so that a constant operand will match HImode, not QImode. ! 879: ! 880: (define_insn "extendhisi2" ! 881: [(set (match_operand:SI 0 "general_operand" "=*d,a") ! 882: (sign_extend:SI ! 883: (match_operand:HI 1 "general_operand" "0,rmn")))] ! 884: "" ! 885: "* ! 886: { ! 887: if (ADDRESS_REG_P (operands[0])) ! 888: return \"move%.w %1,%0\"; ! 889: return \"ext%.l %0\"; ! 890: }") ! 891: ! 892: (define_insn "extendqihi2" ! 893: [(set (match_operand:HI 0 "general_operand" "=d") ! 894: (sign_extend:HI ! 895: (match_operand:QI 1 "general_operand" "0")))] ! 896: "" ! 897: "ext%.w %0") ! 898: ! 899: (define_insn "extendqisi2" ! 900: [(set (match_operand:SI 0 "general_operand" "=d") ! 901: (sign_extend:SI ! 902: (match_operand:QI 1 "general_operand" "0")))] ! 903: "TARGET_68020" ! 904: "extb%.l %0") ! 905: ! 906: ;; Conversions between float and double. ! 907: ! 908: (define_insn "extendsfdf2" ! 909: [(set (match_operand:DF 0 "general_operand" "=*fdm,f") ! 910: (float_extend:DF ! 911: (match_operand:SF 1 "general_operand" "f,dmF")))] ! 912: "TARGET_68881" ! 913: "* ! 914: { ! 915: if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) ! 916: { ! 917: if (REGNO (operands[0]) == REGNO (operands[1])) ! 918: { ! 919: /* Extending float to double in an fp-reg is a no-op. ! 920: NOTICE_UPDATE_CC has already assumed that the ! 921: cc will be set. So cancel what it did. */ ! 922: cc_status = cc_prev_status; ! 923: return \"\"; ! 924: } ! 925: return \"fmove%.x %1,%0\"; ! 926: } ! 927: if (FP_REG_P (operands[0])) ! 928: return \"fmove%.s %f1,%0\"; ! 929: if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1])) ! 930: { ! 931: output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands); ! 932: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); ! 933: return \"move%.l %+,%0\"; ! 934: } ! 935: return \"fmove%.d %f1,%0\"; ! 936: }") ! 937: ! 938: ;; This cannot output into an f-reg because there is no way to be ! 939: ;; sure of truncating in that case. ! 940: (define_insn "truncdfsf2" ! 941: [(set (match_operand:SF 0 "general_operand" "=dm") ! 942: (float_truncate:SF ! 943: (match_operand:DF 1 "general_operand" "f")))] ! 944: "TARGET_68881" ! 945: "fmove%.s %f1,%0") ! 946: ! 947: ;; Conversion between fixed point and floating point. ! 948: ;; Note that among the fix-to-float insns ! 949: ;; the ones that start with SImode come first. ! 950: ;; That is so that an operand that is a CONST_INT ! 951: ;; (and therefore lacks a specific machine mode). ! 952: ;; will be recognized as SImode (which is always valid) ! 953: ;; rather than as QImode or HImode. ! 954: ! 955: (define_insn "floatsisf2" ! 956: [(set (match_operand:SF 0 "general_operand" "=f") ! 957: (float:SF (match_operand:SI 1 "general_operand" "dmi")))] ! 958: "TARGET_68881" ! 959: "fmove%.l %1,%0") ! 960: ! 961: (define_insn "floatsidf2" ! 962: [(set (match_operand:DF 0 "general_operand" "=f") ! 963: (float:DF (match_operand:SI 1 "general_operand" "dmi")))] ! 964: "TARGET_68881" ! 965: "fmove%.l %1,%0") ! 966: ! 967: (define_insn "floathisf2" ! 968: [(set (match_operand:SF 0 "general_operand" "=f") ! 969: (float:SF (match_operand:HI 1 "general_operand" "dmn")))] ! 970: "TARGET_68881" ! 971: "fmove%.w %1,%0") ! 972: ! 973: (define_insn "floathidf2" ! 974: [(set (match_operand:DF 0 "general_operand" "=f") ! 975: (float:DF (match_operand:HI 1 "general_operand" "dmn")))] ! 976: "TARGET_68881" ! 977: "fmove%.w %1,%0") ! 978: ! 979: (define_insn "floatqisf2" ! 980: [(set (match_operand:SF 0 "general_operand" "=f") ! 981: (float:SF (match_operand:QI 1 "general_operand" "dmn")))] ! 982: "TARGET_68881" ! 983: "fmove%.b %1,%0") ! 984: ! 985: (define_insn "floatqidf2" ! 986: [(set (match_operand:DF 0 "general_operand" "=f") ! 987: (float:DF (match_operand:QI 1 "general_operand" "dmn")))] ! 988: "TARGET_68881" ! 989: "fmove%.b %1,%0") ! 990: ! 991: ;; Convert a float to a float whose value is an integer. ! 992: ;; This is the first stage of converting it to an integer type. ! 993: ! 994: (define_insn "ftruncdf2" ! 995: [(set (match_operand:DF 0 "general_operand" "=f") ! 996: (fix:DF (match_operand:DF 1 "general_operand" "fFm")))] ! 997: "TARGET_68881" ! 998: "* ! 999: { ! 1000: if (FP_REG_P (operands[1])) ! 1001: return \"fintrz%.x %f1,%0\"; ! 1002: return \"fintrz%.d %f1,%0\"; ! 1003: }") ! 1004: ! 1005: (define_insn "ftruncsf2" ! 1006: [(set (match_operand:SF 0 "general_operand" "=f") ! 1007: (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))] ! 1008: "TARGET_68881" ! 1009: "* ! 1010: { ! 1011: if (FP_REG_P (operands[1])) ! 1012: return \"fintrz%.x %f1,%0\"; ! 1013: return \"fintrz%.s %f1,%0\"; ! 1014: }") ! 1015: ! 1016: ;; Convert a float whose value is an integer ! 1017: ;; to an actual integer. Second stage of converting float to integer type. ! 1018: (define_insn "fixsfqi2" ! 1019: [(set (match_operand:QI 0 "general_operand" "=dm") ! 1020: (fix:QI (match_operand:SF 1 "general_operand" "f")))] ! 1021: "TARGET_68881" ! 1022: "fmove%.b %1,%0") ! 1023: ! 1024: (define_insn "fixsfhi2" ! 1025: [(set (match_operand:HI 0 "general_operand" "=dm") ! 1026: (fix:HI (match_operand:SF 1 "general_operand" "f")))] ! 1027: "TARGET_68881" ! 1028: "fmove%.w %1,%0") ! 1029: ! 1030: (define_insn "fixsfsi2" ! 1031: [(set (match_operand:SI 0 "general_operand" "=dm") ! 1032: (fix:SI (match_operand:SF 1 "general_operand" "f")))] ! 1033: "TARGET_68881" ! 1034: "fmove%.l %1,%0") ! 1035: ! 1036: (define_insn "fixdfqi2" ! 1037: [(set (match_operand:QI 0 "general_operand" "=dm") ! 1038: (fix:QI (match_operand:DF 1 "general_operand" "f")))] ! 1039: "TARGET_68881" ! 1040: "fmove%.b %1,%0") ! 1041: ! 1042: (define_insn "fixdfhi2" ! 1043: [(set (match_operand:HI 0 "general_operand" "=dm") ! 1044: (fix:HI (match_operand:DF 1 "general_operand" "f")))] ! 1045: "TARGET_68881" ! 1046: "fmove%.w %1,%0") ! 1047: ! 1048: (define_insn "fixdfsi2" ! 1049: [(set (match_operand:SI 0 "general_operand" "=dm") ! 1050: (fix:SI (match_operand:DF 1 "general_operand" "f")))] ! 1051: "TARGET_68881" ! 1052: "fmove%.l %1,%0") ! 1053: ! 1054: ;; add instructions ! 1055: ! 1056: (define_insn "addsi3" ! 1057: [(set (match_operand:SI 0 "general_operand" "=m,r,!a") ! 1058: (plus:SI (match_operand:SI 1 "general_operand" "%0,0,a") ! 1059: (match_operand:SI 2 "general_operand" "dIKLs,mrIKLs,rJK")))] ! 1060: "" ! 1061: "* ! 1062: { ! 1063: if (! operands_match_p (operands[0], operands[1])) ! 1064: { ! 1065: /* These insns can result from reloads to access ! 1066: stack slots over 64k from the frame pointer. */ ! 1067: if (GET_CODE (operands[2]) == CONST_INT ! 1068: && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000) ! 1069: return \"move%.l %2,%0\;add%.l %1,%0\"; ! 1070: #ifdef SGS ! 1071: if (GET_CODE (operands[2]) == REG) ! 1072: return \"lea (%1,%2.l),%0\"; ! 1073: else ! 1074: return \"lea %c2(%1),%0\"; ! 1075: #else /* not SGS */ ! 1076: #ifdef MOTOROLA ! 1077: if (GET_CODE (operands[2]) == REG) ! 1078: return \"lea (%1,%2.l),%0\"; ! 1079: else ! 1080: return \"lea (%c2,%1),%0\"; ! 1081: #else /* not MOTOROLA (MIT syntax) */ ! 1082: if (GET_CODE (operands[2]) == REG) ! 1083: return \"lea %1@(0,%2:l),%0\"; ! 1084: else ! 1085: return \"lea %1@(%c2),%0\"; ! 1086: #endif /* not MOTOROLA */ ! 1087: #endif /* not SGS */ ! 1088: } ! 1089: if (GET_CODE (operands[2]) == CONST_INT) ! 1090: { ! 1091: if (INTVAL (operands[2]) > 0 ! 1092: && INTVAL (operands[2]) <= 8) ! 1093: return \"addq%.l %2,%0\"; ! 1094: if (INTVAL (operands[2]) < 0 ! 1095: && INTVAL (operands[2]) >= -8) ! 1096: { ! 1097: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 1098: - INTVAL (operands[2])); ! 1099: return \"subq%.l %2,%0\"; ! 1100: } ! 1101: if (ADDRESS_REG_P (operands[0]) ! 1102: && INTVAL (operands[2]) >= -0x8000 ! 1103: && INTVAL (operands[2]) < 0x8000) ! 1104: return \"add%.w %2,%0\"; ! 1105: } ! 1106: return \"add%.l %2,%0\"; ! 1107: }") ! 1108: ! 1109: (define_insn "" ! 1110: [(set (match_operand:SI 0 "general_operand" "=a") ! 1111: (plus:SI (match_operand:SI 1 "general_operand" "0") ! 1112: (sign_extend:SI (match_operand:HI 2 "general_operand" "rmn"))))] ! 1113: "" ! 1114: "add%.w %2,%0") ! 1115: ! 1116: (define_insn "addhi3" ! 1117: [(set (match_operand:HI 0 "general_operand" "=m,r") ! 1118: (plus:HI (match_operand:HI 1 "general_operand" "%0,0") ! 1119: (match_operand:HI 2 "general_operand" "dn,rmn")))] ! 1120: "" ! 1121: "* ! 1122: { ! 1123: if (GET_CODE (operands[2]) == CONST_INT) ! 1124: { ! 1125: if (INTVAL (operands[2]) > 0 ! 1126: && INTVAL (operands[2]) <= 8) ! 1127: return \"addq%.w %2,%0\"; ! 1128: } ! 1129: if (GET_CODE (operands[2]) == CONST_INT) ! 1130: { ! 1131: if (INTVAL (operands[2]) < 0 ! 1132: && INTVAL (operands[2]) >= -8) ! 1133: { ! 1134: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 1135: - INTVAL (operands[2])); ! 1136: return \"subq%.w %2,%0\"; ! 1137: } ! 1138: } ! 1139: return \"add%.w %2,%0\"; ! 1140: }") ! 1141: ! 1142: (define_insn "" ! 1143: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) ! 1144: (plus:HI (match_dup 0) ! 1145: (match_operand:HI 1 "general_operand" "dn,rmn")))] ! 1146: "" ! 1147: "add%.w %1,%0") ! 1148: ! 1149: (define_insn "addqi3" ! 1150: [(set (match_operand:QI 0 "general_operand" "=m,d") ! 1151: (plus:QI (match_operand:QI 1 "general_operand" "%0,0") ! 1152: (match_operand:QI 2 "general_operand" "dn,dmn")))] ! 1153: "" ! 1154: "* ! 1155: { ! 1156: if (GET_CODE (operands[2]) == CONST_INT) ! 1157: { ! 1158: if (INTVAL (operands[2]) > 0 ! 1159: && INTVAL (operands[2]) <= 8) ! 1160: return \"addq%.b %2,%0\"; ! 1161: } ! 1162: if (GET_CODE (operands[2]) == CONST_INT) ! 1163: { ! 1164: if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8) ! 1165: { ! 1166: operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2])); ! 1167: return \"subq%.b %2,%0\"; ! 1168: } ! 1169: } ! 1170: return \"add%.b %2,%0\"; ! 1171: }") ! 1172: ! 1173: (define_insn "" ! 1174: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) ! 1175: (plus:QI (match_dup 0) ! 1176: (match_operand:QI 1 "general_operand" "dn,dmn")))] ! 1177: "" ! 1178: "add%.b %1,%0") ! 1179: ! 1180: (define_insn "adddf3" ! 1181: [(set (match_operand:DF 0 "general_operand" "=f") ! 1182: (plus:DF (match_operand:DF 1 "general_operand" "%0") ! 1183: (match_operand:DF 2 "general_operand" "fmG")))] ! 1184: "TARGET_68881" ! 1185: "* ! 1186: { ! 1187: if (REG_P (operands[2])) ! 1188: return \"fadd%.x %2,%0\"; ! 1189: return \"fadd%.d %f2,%0\"; ! 1190: }") ! 1191: ! 1192: (define_insn "addsf3" ! 1193: [(set (match_operand:SF 0 "general_operand" "=f") ! 1194: (plus:SF (match_operand:SF 1 "general_operand" "%0") ! 1195: (match_operand:SF 2 "general_operand" "fdmF")))] ! 1196: "TARGET_68881" ! 1197: "* ! 1198: { ! 1199: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) ! 1200: return \"fadd%.x %2,%0\"; ! 1201: return \"fadd%.s %f2,%0\"; ! 1202: }") ! 1203: ! 1204: ;; subtract instructions ! 1205: ! 1206: (define_insn "subsi3" ! 1207: [(set (match_operand:SI 0 "general_operand" "=m,r,!a,?d") ! 1208: (minus:SI (match_operand:SI 1 "general_operand" "0,0,a,mrIKs") ! 1209: (match_operand:SI 2 "general_operand" "dIKs,mrIKs,J,0")))] ! 1210: "" ! 1211: "* ! 1212: { ! 1213: if (! operands_match_p (operands[0], operands[1])) ! 1214: { ! 1215: if (operands_match_p (operands[0], operands[2])) ! 1216: { ! 1217: if (GET_CODE (operands[1]) == CONST_INT) ! 1218: { ! 1219: if (INTVAL (operands[1]) > 0 ! 1220: && INTVAL (operands[1]) <= 8) ! 1221: return \"subq%.l %1,%0\;neg%.l %0\"; ! 1222: } ! 1223: return \"sub%.l %1,%0\;neg%.l %0\"; ! 1224: } ! 1225: /* This case is matched by J, but negating -0x8000 ! 1226: in an lea would give an invalid displacement. ! 1227: So do this specially. */ ! 1228: if (INTVAL (operands[2]) == -0x8000) ! 1229: return \"move%.l %1,%0\;sub%.l %2,%0\"; ! 1230: #ifdef SGS ! 1231: return \"lea %n2(%1),%0\"; ! 1232: #else ! 1233: #ifdef MOTOROLA ! 1234: return \"lea (%n2,%1),%0\"; ! 1235: #else /* not MOTOROLA (MIT syntax) */ ! 1236: return \"lea %1@(%n2),%0\"; ! 1237: #endif /* not MOTOROLA */ ! 1238: #endif /* not SGS */ ! 1239: } ! 1240: if (GET_CODE (operands[2]) == CONST_INT) ! 1241: { ! 1242: if (INTVAL (operands[2]) > 0 ! 1243: && INTVAL (operands[2]) <= 8) ! 1244: return \"subq%.l %2,%0\"; ! 1245: if (ADDRESS_REG_P (operands[0]) ! 1246: && INTVAL (operands[2]) >= -0x8000 ! 1247: && INTVAL (operands[2]) < 0x8000) ! 1248: return \"sub%.w %2,%0\"; ! 1249: } ! 1250: return \"sub%.l %2,%0\"; ! 1251: }") ! 1252: ! 1253: (define_insn "" ! 1254: [(set (match_operand:SI 0 "general_operand" "=a") ! 1255: (minus:SI (match_operand:SI 1 "general_operand" "0") ! 1256: (sign_extend:SI (match_operand:HI 2 "general_operand" "rmn"))))] ! 1257: "" ! 1258: "sub%.w %2,%0") ! 1259: ! 1260: (define_insn "subhi3" ! 1261: [(set (match_operand:HI 0 "general_operand" "=m,r") ! 1262: (minus:HI (match_operand:HI 1 "general_operand" "0,0") ! 1263: (match_operand:HI 2 "general_operand" "dn,rmn")))] ! 1264: "" ! 1265: "sub%.w %2,%0") ! 1266: ! 1267: (define_insn "" ! 1268: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) ! 1269: (minus:HI (match_dup 0) ! 1270: (match_operand:HI 1 "general_operand" "dn,rmn")))] ! 1271: "" ! 1272: "sub%.w %1,%0") ! 1273: ! 1274: (define_insn "subqi3" ! 1275: [(set (match_operand:QI 0 "general_operand" "=m,d") ! 1276: (minus:QI (match_operand:QI 1 "general_operand" "0,0") ! 1277: (match_operand:QI 2 "general_operand" "dn,dmn")))] ! 1278: "" ! 1279: "sub%.b %2,%0") ! 1280: ! 1281: (define_insn "" ! 1282: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) ! 1283: (minus:QI (match_dup 0) ! 1284: (match_operand:QI 1 "general_operand" "dn,dmn")))] ! 1285: "" ! 1286: "sub%.b %1,%0") ! 1287: ! 1288: (define_insn "subdf3" ! 1289: [(set (match_operand:DF 0 "general_operand" "=f") ! 1290: (minus:DF (match_operand:DF 1 "general_operand" "0") ! 1291: (match_operand:DF 2 "general_operand" "fmG")))] ! 1292: "TARGET_68881" ! 1293: "* ! 1294: { ! 1295: if (REG_P (operands[2])) ! 1296: return \"fsub%.x %2,%0\"; ! 1297: return \"fsub%.d %f2,%0\"; ! 1298: }") ! 1299: ! 1300: (define_insn "subsf3" ! 1301: [(set (match_operand:SF 0 "general_operand" "=f") ! 1302: (minus:SF (match_operand:SF 1 "general_operand" "0") ! 1303: (match_operand:SF 2 "general_operand" "fdmF")))] ! 1304: "TARGET_68881" ! 1305: "* ! 1306: { ! 1307: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) ! 1308: return \"fsub%.x %2,%0\"; ! 1309: return \"fsub%.s %f2,%0\"; ! 1310: }") ! 1311: ! 1312: ;; multiply instructions ! 1313: ! 1314: (define_insn "mulhi3" ! 1315: [(set (match_operand:HI 0 "general_operand" "=d") ! 1316: (mult:HI (match_operand:HI 1 "general_operand" "%0") ! 1317: (match_operand:HI 2 "general_operand" "dmn")))] ! 1318: "" ! 1319: "* ! 1320: { ! 1321: #ifdef MOTOROLA ! 1322: return \"muls.w %2,%0\"; ! 1323: #else ! 1324: return \"muls %2,%0\"; ! 1325: #endif ! 1326: }") ! 1327: ! 1328: (define_insn "mulhisi3" ! 1329: [(set (match_operand:SI 0 "general_operand" "=d") ! 1330: (mult:SI (match_operand:HI 1 "general_operand" "%0") ! 1331: (match_operand:HI 2 "general_operand" "dmn")))] ! 1332: "" ! 1333: "* ! 1334: { ! 1335: #ifdef MOTOROLA ! 1336: return \"muls.w %2,%0\"; ! 1337: #else ! 1338: return \"muls %2,%0\"; ! 1339: #endif ! 1340: }") ! 1341: ! 1342: (define_insn "mulsi3" ! 1343: [(set (match_operand:SI 0 "general_operand" "=d") ! 1344: (mult:SI (match_operand:SI 1 "general_operand" "%0") ! 1345: (match_operand:SI 2 "general_operand" "dmsK")))] ! 1346: "TARGET_68020" ! 1347: "muls%.l %2,%0") ! 1348: ! 1349: (define_insn "umulhi3" ! 1350: [(set (match_operand:HI 0 "general_operand" "=d") ! 1351: (umult:HI (match_operand:HI 1 "general_operand" "%0") ! 1352: (match_operand:HI 2 "general_operand" "dmn")))] ! 1353: "" ! 1354: "* ! 1355: { ! 1356: #ifdef MOTOROLA ! 1357: return \"mulu.w %2,%0\"; ! 1358: #else ! 1359: return \"mulu %2,%0\"; ! 1360: #endif ! 1361: }") ! 1362: ! 1363: (define_insn "umulhisi3" ! 1364: [(set (match_operand:SI 0 "general_operand" "=d") ! 1365: (umult:SI (match_operand:HI 1 "general_operand" "%0") ! 1366: (match_operand:HI 2 "general_operand" "dmn")))] ! 1367: "" ! 1368: "* ! 1369: { ! 1370: #ifdef MOTOROLA ! 1371: return \"mulu.w %2,%0\"; ! 1372: #else ! 1373: return \"mulu %2,%0\"; ! 1374: #endif ! 1375: }") ! 1376: ! 1377: (define_insn "umulsi3" ! 1378: [(set (match_operand:SI 0 "general_operand" "=d") ! 1379: (umult:SI (match_operand:SI 1 "general_operand" "%0") ! 1380: (match_operand:SI 2 "general_operand" "dmsK")))] ! 1381: "TARGET_68020" ! 1382: "mulu%.l %2,%0") ! 1383: ! 1384: (define_insn "muldf3" ! 1385: [(set (match_operand:DF 0 "general_operand" "=f") ! 1386: (mult:DF (match_operand:DF 1 "general_operand" "%0") ! 1387: (match_operand:DF 2 "general_operand" "fmG")))] ! 1388: "TARGET_68881" ! 1389: "* ! 1390: { ! 1391: if (REG_P (operands[2])) ! 1392: return \"fmul%.x %2,%0\"; ! 1393: return \"fmul%.d %f2,%0\"; ! 1394: }") ! 1395: ! 1396: (define_insn "mulsf3" ! 1397: [(set (match_operand:SF 0 "general_operand" "=f") ! 1398: (mult:SF (match_operand:SF 1 "general_operand" "%0") ! 1399: (match_operand:SF 2 "general_operand" "fdmF")))] ! 1400: "TARGET_68881" ! 1401: "* ! 1402: { ! 1403: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) ! 1404: return \"fsglmul%.x %2,%0\"; ! 1405: return \"fsglmul%.s %f2,%0\"; ! 1406: }") ! 1407: ! 1408: ;; divide instructions ! 1409: ! 1410: (define_insn "divhi3" ! 1411: [(set (match_operand:HI 0 "general_operand" "=d") ! 1412: (div:HI (match_operand:HI 1 "general_operand" "0") ! 1413: (match_operand:HI 2 "general_operand" "dmn")))] ! 1414: "" ! 1415: "* ! 1416: { ! 1417: #ifdef MOTOROLA ! 1418: return \"ext.l %0\;divs.w %2,%0\"; ! 1419: #else ! 1420: return \"extl %0\;divs %2,%0\"; ! 1421: #endif ! 1422: }") ! 1423: ! 1424: (define_insn "divhisi3" ! 1425: [(set (match_operand:HI 0 "general_operand" "=d") ! 1426: (div:HI (match_operand:SI 1 "general_operand" "0") ! 1427: (match_operand:HI 2 "general_operand" "dmn")))] ! 1428: "" ! 1429: "* ! 1430: { ! 1431: #ifdef MOTOROLA ! 1432: return \"divs.w %2,%0\"; ! 1433: #else ! 1434: return \"divs %2,%0\"; ! 1435: #endif ! 1436: }") ! 1437: ! 1438: (define_insn "divsi3" ! 1439: [(set (match_operand:SI 0 "general_operand" "=d") ! 1440: (div:SI (match_operand:SI 1 "general_operand" "0") ! 1441: (match_operand:SI 2 "general_operand" "dmsK")))] ! 1442: "TARGET_68020" ! 1443: "divs%.l %2,%0") ! 1444: ! 1445: (define_insn "udivhi3" ! 1446: [(set (match_operand:HI 0 "general_operand" "=d") ! 1447: (udiv:HI (match_operand:HI 1 "general_operand" "0") ! 1448: (match_operand:HI 2 "general_operand" "dmn")))] ! 1449: "" ! 1450: "* ! 1451: { ! 1452: #ifdef MOTOROLA ! 1453: return \"and.l %#0xFFFF,%0\;divu.w %2,%0\"; ! 1454: #else ! 1455: return \"andl %#0xFFFF,%0\;divu %2,%0\"; ! 1456: #endif ! 1457: }") ! 1458: ! 1459: (define_insn "udivhisi3" ! 1460: [(set (match_operand:HI 0 "general_operand" "=d") ! 1461: (udiv:HI (match_operand:SI 1 "general_operand" "0") ! 1462: (match_operand:HI 2 "general_operand" "dmn")))] ! 1463: "" ! 1464: "* ! 1465: { ! 1466: #ifdef MOTOROLA ! 1467: return \"divu.w %2,%0\"; ! 1468: #else ! 1469: return \"divu %2,%0\"; ! 1470: #endif ! 1471: }") ! 1472: ! 1473: (define_insn "udivsi3" ! 1474: [(set (match_operand:SI 0 "general_operand" "=d") ! 1475: (udiv:SI (match_operand:SI 1 "general_operand" "0") ! 1476: (match_operand:SI 2 "general_operand" "dmsK")))] ! 1477: "TARGET_68020" ! 1478: "divu%.l %2,%0") ! 1479: ! 1480: (define_insn "divdf3" ! 1481: [(set (match_operand:DF 0 "general_operand" "=f") ! 1482: (div:DF (match_operand:DF 1 "general_operand" "0") ! 1483: (match_operand:DF 2 "general_operand" "fmG")))] ! 1484: "TARGET_68881" ! 1485: "* ! 1486: { ! 1487: if (REG_P (operands[2])) ! 1488: return \"fdiv%.x %2,%0\"; ! 1489: return \"fdiv%.d %f2,%0\"; ! 1490: }") ! 1491: ! 1492: (define_insn "divsf3" ! 1493: [(set (match_operand:SF 0 "general_operand" "=f") ! 1494: (div:SF (match_operand:SF 1 "general_operand" "0") ! 1495: (match_operand:SF 2 "general_operand" "fdmF")))] ! 1496: "TARGET_68881" ! 1497: "* ! 1498: { ! 1499: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) ! 1500: return \"fsgldiv%.x %2,%0\"; ! 1501: return \"fsgldiv%.s %f2,%0\"; ! 1502: }") ! 1503: ! 1504: ;; Remainder instructions. ! 1505: ! 1506: (define_insn "modhi3" ! 1507: [(set (match_operand:HI 0 "general_operand" "=d") ! 1508: (mod:HI (match_operand:HI 1 "general_operand" "0") ! 1509: (match_operand:HI 2 "general_operand" "dmn")))] ! 1510: "" ! 1511: "* ! 1512: { ! 1513: /* The swap insn produces cc's that don't correspond to the result. */ ! 1514: CC_STATUS_INIT; ! 1515: #ifdef MOTOROLA ! 1516: return \"ext.l %0\;divs.w %2,%0\;swap %0\"; ! 1517: #else ! 1518: return \"extl %0\;divs %2,%0\;swap %0\"; ! 1519: #endif ! 1520: }") ! 1521: ! 1522: (define_insn "modhisi3" ! 1523: [(set (match_operand:HI 0 "general_operand" "=d") ! 1524: (mod:HI (match_operand:SI 1 "general_operand" "0") ! 1525: (match_operand:HI 2 "general_operand" "dmn")))] ! 1526: "" ! 1527: "* ! 1528: { ! 1529: /* The swap insn produces cc's that don't correspond to the result. */ ! 1530: CC_STATUS_INIT; ! 1531: #ifdef MOTOROLA ! 1532: return \"divs.w %2,%0\;swap %0\"; ! 1533: #else ! 1534: return \"divs %2,%0\;swap %0\"; ! 1535: #endif ! 1536: }") ! 1537: ! 1538: (define_insn "umodhi3" ! 1539: [(set (match_operand:HI 0 "general_operand" "=d") ! 1540: (umod:HI (match_operand:HI 1 "general_operand" "0") ! 1541: (match_operand:HI 2 "general_operand" "dmn")))] ! 1542: "" ! 1543: "* ! 1544: { ! 1545: /* The swap insn produces cc's that don't correspond to the result. */ ! 1546: CC_STATUS_INIT; ! 1547: #ifdef MOTOROLA ! 1548: return \"and.l %#0xFFFF,%0\;divu.w %2,%0\;swap %0\"; ! 1549: #else ! 1550: return \"andl %#0xFFFF,%0\;divu %2,%0\;swap %0\"; ! 1551: #endif ! 1552: }") ! 1553: ! 1554: (define_insn "umodhisi3" ! 1555: [(set (match_operand:HI 0 "general_operand" "=d") ! 1556: (umod:HI (match_operand:SI 1 "general_operand" "0") ! 1557: (match_operand:HI 2 "general_operand" "dmn")))] ! 1558: "" ! 1559: "* ! 1560: { ! 1561: /* The swap insn produces cc's that don't correspond to the result. */ ! 1562: CC_STATUS_INIT; ! 1563: #ifdef MOTOROLA ! 1564: return \"divu.w %2,%0\;swap %0\"; ! 1565: #else ! 1566: return \"divu %2,%0\;swap %0\"; ! 1567: #endif ! 1568: }") ! 1569: ! 1570: (define_insn "divmodsi4" ! 1571: [(set (match_operand:SI 0 "general_operand" "=d") ! 1572: (div:SI (match_operand:SI 1 "general_operand" "0") ! 1573: (match_operand:SI 2 "general_operand" "dmsK"))) ! 1574: (set (match_operand:SI 3 "general_operand" "=d") ! 1575: (mod:SI (match_dup 1) (match_dup 2)))] ! 1576: "TARGET_68020" ! 1577: "divsl%.l %2,%3:%0") ! 1578: ! 1579: (define_insn "udivmodsi4" ! 1580: [(set (match_operand:SI 0 "general_operand" "=d") ! 1581: (udiv:SI (match_operand:SI 1 "general_operand" "0") ! 1582: (match_operand:SI 2 "general_operand" "dmsK"))) ! 1583: (set (match_operand:SI 3 "general_operand" "=d") ! 1584: (umod:SI (match_dup 1) (match_dup 2)))] ! 1585: "TARGET_68020" ! 1586: "divul%.l %2,%3:%0") ! 1587: ! 1588: ;; logical-and instructions ! 1589: ! 1590: (define_insn "andsi3" ! 1591: [(set (match_operand:SI 0 "general_operand" "=m,d") ! 1592: (and:SI (match_operand:SI 1 "general_operand" "%0,0") ! 1593: (match_operand:SI 2 "general_operand" "dKs,dmKs")))] ! 1594: "" ! 1595: "* ! 1596: { ! 1597: if (GET_CODE (operands[2]) == CONST_INT ! 1598: && (INTVAL (operands[2]) | 0xffff) == 0xffffffff ! 1599: && (DATA_REG_P (operands[0]) ! 1600: || offsetable_memref_p (operands[0]))) ! 1601: { ! 1602: if (GET_CODE (operands[0]) != REG) ! 1603: operands[0] = adj_offsetable_operand (operands[0], 2); ! 1604: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 1605: INTVAL (operands[2]) & 0xffff); ! 1606: /* Do not delete a following tstl %0 insn; that would be incorrect. */ ! 1607: CC_STATUS_INIT; ! 1608: return \"and%.w %2,%0\"; ! 1609: } ! 1610: return \"and%.l %2,%0\"; ! 1611: }") ! 1612: ! 1613: (define_insn "andhi3" ! 1614: [(set (match_operand:HI 0 "general_operand" "=m,d") ! 1615: (and:HI (match_operand:HI 1 "general_operand" "%0,0") ! 1616: (match_operand:HI 2 "general_operand" "dn,dmn")))] ! 1617: "" ! 1618: "and%.w %2,%0") ! 1619: ! 1620: (define_insn "andqi3" ! 1621: [(set (match_operand:QI 0 "general_operand" "=m,d") ! 1622: (and:QI (match_operand:QI 1 "general_operand" "%0,0") ! 1623: (match_operand:QI 2 "general_operand" "dn,dmn")))] ! 1624: "" ! 1625: "and%.b %2,%0") ! 1626: ! 1627: (define_insn "" ! 1628: [(set (match_operand:SI 0 "general_operand" "=d") ! 1629: (and:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "dm")) ! 1630: (match_operand:SI 2 "general_operand" "0")))] ! 1631: "GET_CODE (operands[2]) == CONST_INT ! 1632: && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (HImode))" ! 1633: "and%.w %1,%0") ! 1634: ! 1635: (define_insn "" ! 1636: [(set (match_operand:SI 0 "general_operand" "=d") ! 1637: (and:SI (zero_extend:SI (match_operand:QI 1 "general_operand" "dm")) ! 1638: (match_operand:SI 2 "general_operand" "0")))] ! 1639: "GET_CODE (operands[2]) == CONST_INT ! 1640: && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (QImode))" ! 1641: "and%.b %1,%0") ! 1642: ! 1643: ;; inclusive-or instructions ! 1644: ! 1645: (define_insn "iorsi3" ! 1646: [(set (match_operand:SI 0 "general_operand" "=m,d") ! 1647: (ior:SI (match_operand:SI 1 "general_operand" "%0,0") ! 1648: (match_operand:SI 2 "general_operand" "dKs,dmKs")))] ! 1649: "" ! 1650: "* ! 1651: { ! 1652: register int logval; ! 1653: if (GET_CODE (operands[2]) == CONST_INT ! 1654: && INTVAL (operands[2]) >> 16 == 0 ! 1655: && (DATA_REG_P (operands[0]) ! 1656: || offsetable_memref_p (operands[0]))) ! 1657: { ! 1658: if (GET_CODE (operands[0]) != REG) ! 1659: operands[0] = adj_offsetable_operand (operands[0], 2); ! 1660: /* Do not delete a following tstl %0 insn; that would be incorrect. */ ! 1661: CC_STATUS_INIT; ! 1662: return \"or%.w %2,%0\"; ! 1663: } ! 1664: if (GET_CODE (operands[2]) == CONST_INT ! 1665: && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 ! 1666: && (DATA_REG_P (operands[0]) ! 1667: || offsetable_memref_p (operands[0]))) ! 1668: { ! 1669: if (DATA_REG_P (operands[0])) ! 1670: { ! 1671: operands[1] = gen_rtx (CONST_INT, VOIDmode, logval); ! 1672: } ! 1673: else ! 1674: { ! 1675: operands[0] = adj_offsetable_operand (operands[0], 3 - (logval / 8)); ! 1676: operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8); ! 1677: } ! 1678: return \"bset %1,%0\"; ! 1679: } ! 1680: return \"or%.l %2,%0\"; ! 1681: }") ! 1682: ! 1683: (define_insn "iorhi3" ! 1684: [(set (match_operand:HI 0 "general_operand" "=m,d") ! 1685: (ior:HI (match_operand:HI 1 "general_operand" "%0,0") ! 1686: (match_operand:HI 2 "general_operand" "dn,dmn")))] ! 1687: "" ! 1688: "or%.w %2,%0") ! 1689: ! 1690: (define_insn "iorqi3" ! 1691: [(set (match_operand:QI 0 "general_operand" "=m,d") ! 1692: (ior:QI (match_operand:QI 1 "general_operand" "%0,0") ! 1693: (match_operand:QI 2 "general_operand" "dn,dmn")))] ! 1694: "" ! 1695: "or%.b %2,%0") ! 1696: ! 1697: ;; xor instructions ! 1698: ! 1699: (define_insn "xorsi3" ! 1700: [(set (match_operand:SI 0 "general_operand" "=do,m") ! 1701: (xor:SI (match_operand:SI 1 "general_operand" "%0,0") ! 1702: (match_operand:SI 2 "general_operand" "di,dKs")))] ! 1703: "" ! 1704: "* ! 1705: { ! 1706: if (GET_CODE (operands[2]) == CONST_INT ! 1707: && INTVAL (operands[2]) >> 16 == 0 ! 1708: && (offsetable_memref_p (operands[0]) || DATA_REG_P (operands[0]))) ! 1709: { ! 1710: if (! DATA_REG_P (operands[0])) ! 1711: operands[0] = adj_offsetable_operand (operands[0], 2); ! 1712: /* Do not delete a following tstl %0 insn; that would be incorrect. */ ! 1713: CC_STATUS_INIT; ! 1714: return \"eor%.w %2,%0\"; ! 1715: } ! 1716: return \"eor%.l %2,%0\"; ! 1717: }") ! 1718: ! 1719: (define_insn "xorhi3" ! 1720: [(set (match_operand:HI 0 "general_operand" "=dm") ! 1721: (xor:HI (match_operand:HI 1 "general_operand" "%0") ! 1722: (match_operand:HI 2 "general_operand" "dn")))] ! 1723: "" ! 1724: "eor%.w %2,%0") ! 1725: ! 1726: (define_insn "xorqi3" ! 1727: [(set (match_operand:QI 0 "general_operand" "=dm") ! 1728: (xor:QI (match_operand:QI 1 "general_operand" "%0") ! 1729: (match_operand:QI 2 "general_operand" "dn")))] ! 1730: "" ! 1731: "eor%.b %2,%0") ! 1732: ! 1733: ;; negation instructions ! 1734: ! 1735: (define_insn "negsi2" ! 1736: [(set (match_operand:SI 0 "general_operand" "=dm") ! 1737: (neg:SI (match_operand:SI 1 "general_operand" "0")))] ! 1738: "" ! 1739: "neg%.l %0") ! 1740: ! 1741: (define_insn "neghi2" ! 1742: [(set (match_operand:HI 0 "general_operand" "=dm") ! 1743: (neg:HI (match_operand:HI 1 "general_operand" "0")))] ! 1744: "" ! 1745: "neg%.w %0") ! 1746: ! 1747: (define_insn "negqi2" ! 1748: [(set (match_operand:QI 0 "general_operand" "=dm") ! 1749: (neg:QI (match_operand:QI 1 "general_operand" "0")))] ! 1750: "" ! 1751: "neg%.b %0") ! 1752: ! 1753: (define_insn "negsf2" ! 1754: [(set (match_operand:SF 0 "general_operand" "=f") ! 1755: (neg:SF (match_operand:SF 1 "general_operand" "fdmF")))] ! 1756: "TARGET_68881" ! 1757: "* ! 1758: { ! 1759: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) ! 1760: return \"fneg%.x %1,%0\"; ! 1761: return \"fneg%.s %f1,%0\"; ! 1762: }") ! 1763: ! 1764: (define_insn "negdf2" ! 1765: [(set (match_operand:DF 0 "general_operand" "=f") ! 1766: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))] ! 1767: "TARGET_68881" ! 1768: "* ! 1769: { ! 1770: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) ! 1771: return \"fneg%.x %1,%0\"; ! 1772: return \"fneg%.d %f1,%0\"; ! 1773: }") ! 1774: ! 1775: ;; Absolute value instructions ! 1776: ! 1777: (define_insn "abssf2" ! 1778: [(set (match_operand:SF 0 "general_operand" "=f") ! 1779: (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))] ! 1780: "TARGET_68881" ! 1781: "* ! 1782: { ! 1783: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) ! 1784: return \"fabs%.x %1,%0\"; ! 1785: return \"fabs%.s %f1,%0\"; ! 1786: }") ! 1787: ! 1788: (define_insn "absdf2" ! 1789: [(set (match_operand:DF 0 "general_operand" "=f") ! 1790: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))] ! 1791: "TARGET_68881" ! 1792: "* ! 1793: { ! 1794: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) ! 1795: return \"fabs%.x %1,%0\"; ! 1796: return \"fabs%.d %f1,%0\"; ! 1797: }") ! 1798: ! 1799: ;; one complement instructions ! 1800: ! 1801: (define_insn "one_cmplsi2" ! 1802: [(set (match_operand:SI 0 "general_operand" "=dm") ! 1803: (not:SI (match_operand:SI 1 "general_operand" "0")))] ! 1804: "" ! 1805: "not%.l %0") ! 1806: ! 1807: (define_insn "one_cmplhi2" ! 1808: [(set (match_operand:HI 0 "general_operand" "=dm") ! 1809: (not:HI (match_operand:HI 1 "general_operand" "0")))] ! 1810: "" ! 1811: "not%.w %0") ! 1812: ! 1813: (define_insn "one_cmplqi2" ! 1814: [(set (match_operand:QI 0 "general_operand" "=dm") ! 1815: (not:QI (match_operand:QI 1 "general_operand" "0")))] ! 1816: "" ! 1817: "not%.b %0") ! 1818: ! 1819: ;; Optimized special case of shifting. ! 1820: ;; Must precede the general case. ! 1821: ! 1822: (define_insn "" ! 1823: [(set (match_operand:SI 0 "general_operand" "=d") ! 1824: (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m") ! 1825: (const_int 24)))] ! 1826: "" ! 1827: "* ! 1828: { ! 1829: if (TARGET_68020) ! 1830: return \"move%.b %1,%0\;extb%.l %0\"; ! 1831: return \"move%.b %1,%0\;ext%.w %0\;ext%.l %0\"; ! 1832: }") ! 1833: ! 1834: (define_insn "" ! 1835: [(set (match_operand:SI 0 "general_operand" "=d") ! 1836: (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m") ! 1837: (const_int 24)))] ! 1838: "" ! 1839: "* ! 1840: { ! 1841: if (reg_mentioned_p (operands[0], operands[1])) ! 1842: return \"move%.b %1,%0\;and%.l %#0xFF,%0\"; ! 1843: return \"clr%.l %0\;move%.b %1,%0\"; ! 1844: }") ! 1845: ! 1846: (define_insn "" ! 1847: [(set (cc0) (minus (match_operand:QI 0 "general_operand" "i") ! 1848: (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m") ! 1849: (const_int 24))))] ! 1850: "(GET_CODE (operands[0]) == CONST_INT ! 1851: && (INTVAL (operands[0]) & ~0xff) == 0)" ! 1852: "* cc_status.flags |= CC_REVERSED; ! 1853: #ifdef HPUX_ASM ! 1854: return \"cmp%.b %1,%0\"; ! 1855: #else ! 1856: return \"cmp%.b %0,%1\"; ! 1857: #endif ! 1858: ") ! 1859: ! 1860: (define_insn "" ! 1861: [(set (cc0) (minus (lshiftrt:SI (match_operand:SI 0 "memory_operand" "m") ! 1862: (const_int 24)) ! 1863: (match_operand:QI 1 "general_operand" "i")))] ! 1864: "(GET_CODE (operands[1]) == CONST_INT ! 1865: && (INTVAL (operands[1]) & ~0xff) == 0)" ! 1866: "* ! 1867: #ifdef HPUX_ASM ! 1868: return \"cmp%.b %0,%1\"; ! 1869: #else ! 1870: return \"cmp%.b %1,%0\"; ! 1871: #endif ! 1872: ") ! 1873: ! 1874: (define_insn "" ! 1875: [(set (cc0) (minus (match_operand:QI 0 "general_operand" "i") ! 1876: (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m") ! 1877: (const_int 24))))] ! 1878: "(GET_CODE (operands[0]) == CONST_INT ! 1879: && ((INTVAL (operands[0]) + 0x80) & ~0xff) == 0)" ! 1880: "* cc_status.flags |= CC_REVERSED; ! 1881: #ifdef HPUX_ASM ! 1882: return \"cmp%.b %1,%0\"; ! 1883: #else ! 1884: return \"cmp%.b %0,%1\"; ! 1885: #endif ! 1886: ") ! 1887: ! 1888: (define_insn "" ! 1889: [(set (cc0) (minus (ashiftrt:SI (match_operand:SI 0 "memory_operand" "m") ! 1890: (const_int 24)) ! 1891: (match_operand:QI 1 "general_operand" "i")))] ! 1892: "(GET_CODE (operands[1]) == CONST_INT ! 1893: && ((INTVAL (operands[1]) + 0x80) & ~0xff) == 0)" ! 1894: "* ! 1895: #ifdef HPUX_ASM ! 1896: return \"cmp%.b %0,%1\"; ! 1897: #else ! 1898: return \"cmp%.b %1,%0\"; ! 1899: #endif ! 1900: ") ! 1901: ! 1902: ;; arithmetic shift instructions ! 1903: ;; We don't need the shift memory by 1 bit instruction ! 1904: ! 1905: (define_insn "ashlsi3" ! 1906: [(set (match_operand:SI 0 "general_operand" "=d") ! 1907: (ashift:SI (match_operand:SI 1 "general_operand" "0") ! 1908: (match_operand:SI 2 "general_operand" "dI")))] ! 1909: "" ! 1910: "asl%.l %2,%0") ! 1911: ! 1912: (define_insn "ashlhi3" ! 1913: [(set (match_operand:HI 0 "general_operand" "=d") ! 1914: (ashift:HI (match_operand:HI 1 "general_operand" "0") ! 1915: (match_operand:HI 2 "general_operand" "dI")))] ! 1916: "" ! 1917: "asl%.w %2,%0") ! 1918: ! 1919: (define_insn "ashlqi3" ! 1920: [(set (match_operand:QI 0 "general_operand" "=d") ! 1921: (ashift:QI (match_operand:QI 1 "general_operand" "0") ! 1922: (match_operand:QI 2 "general_operand" "dI")))] ! 1923: "" ! 1924: "asl%.b %2,%0") ! 1925: ! 1926: (define_insn "ashrsi3" ! 1927: [(set (match_operand:SI 0 "general_operand" "=d") ! 1928: (ashiftrt:SI (match_operand:SI 1 "general_operand" "0") ! 1929: (match_operand:SI 2 "general_operand" "dI")))] ! 1930: "" ! 1931: "asr%.l %2,%0") ! 1932: ! 1933: (define_insn "ashrhi3" ! 1934: [(set (match_operand:HI 0 "general_operand" "=d") ! 1935: (ashiftrt:HI (match_operand:HI 1 "general_operand" "0") ! 1936: (match_operand:HI 2 "general_operand" "dI")))] ! 1937: "" ! 1938: "asr%.w %2,%0") ! 1939: ! 1940: (define_insn "ashrqi3" ! 1941: [(set (match_operand:QI 0 "general_operand" "=d") ! 1942: (ashiftrt:QI (match_operand:QI 1 "general_operand" "0") ! 1943: (match_operand:QI 2 "general_operand" "dI")))] ! 1944: "" ! 1945: "asr%.b %2,%0") ! 1946: ! 1947: ;; logical shift instructions ! 1948: ! 1949: (define_insn "lshlsi3" ! 1950: [(set (match_operand:SI 0 "general_operand" "=d") ! 1951: (lshift:SI (match_operand:SI 1 "general_operand" "0") ! 1952: (match_operand:SI 2 "general_operand" "dI")))] ! 1953: "" ! 1954: "lsl%.l %2,%0") ! 1955: ! 1956: (define_insn "lshlhi3" ! 1957: [(set (match_operand:HI 0 "general_operand" "=d") ! 1958: (lshift:HI (match_operand:HI 1 "general_operand" "0") ! 1959: (match_operand:HI 2 "general_operand" "dI")))] ! 1960: "" ! 1961: "lsl%.w %2,%0") ! 1962: ! 1963: (define_insn "lshlqi3" ! 1964: [(set (match_operand:QI 0 "general_operand" "=d") ! 1965: (lshift:QI (match_operand:QI 1 "general_operand" "0") ! 1966: (match_operand:QI 2 "general_operand" "dI")))] ! 1967: "" ! 1968: "lsl%.b %2,%0") ! 1969: ! 1970: (define_insn "lshrsi3" ! 1971: [(set (match_operand:SI 0 "general_operand" "=d") ! 1972: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0") ! 1973: (match_operand:SI 2 "general_operand" "dI")))] ! 1974: "" ! 1975: "lsr%.l %2,%0") ! 1976: ! 1977: (define_insn "lshrhi3" ! 1978: [(set (match_operand:HI 0 "general_operand" "=d") ! 1979: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0") ! 1980: (match_operand:HI 2 "general_operand" "dI")))] ! 1981: "" ! 1982: "lsr%.w %2,%0") ! 1983: ! 1984: (define_insn "lshrqi3" ! 1985: [(set (match_operand:QI 0 "general_operand" "=d") ! 1986: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0") ! 1987: (match_operand:QI 2 "general_operand" "dI")))] ! 1988: "" ! 1989: "lsr%.b %2,%0") ! 1990: ! 1991: ;; rotate instructions ! 1992: ! 1993: (define_insn "rotlsi3" ! 1994: [(set (match_operand:SI 0 "general_operand" "=d") ! 1995: (rotate:SI (match_operand:SI 1 "general_operand" "0") ! 1996: (match_operand:SI 2 "general_operand" "dI")))] ! 1997: "" ! 1998: "rol%.l %2,%0") ! 1999: ! 2000: (define_insn "rotlhi3" ! 2001: [(set (match_operand:HI 0 "general_operand" "=d") ! 2002: (rotate:HI (match_operand:HI 1 "general_operand" "0") ! 2003: (match_operand:HI 2 "general_operand" "dI")))] ! 2004: "" ! 2005: "rol%.w %2,%0") ! 2006: ! 2007: (define_insn "rotlqi3" ! 2008: [(set (match_operand:QI 0 "general_operand" "=d") ! 2009: (rotate:QI (match_operand:QI 1 "general_operand" "0") ! 2010: (match_operand:QI 2 "general_operand" "dI")))] ! 2011: "" ! 2012: "rol%.b %2,%0") ! 2013: ! 2014: (define_insn "rotrsi3" ! 2015: [(set (match_operand:SI 0 "general_operand" "=d") ! 2016: (rotatert:SI (match_operand:SI 1 "general_operand" "0") ! 2017: (match_operand:SI 2 "general_operand" "dI")))] ! 2018: "" ! 2019: "ror%.l %2,%0") ! 2020: ! 2021: (define_insn "rotrhi3" ! 2022: [(set (match_operand:HI 0 "general_operand" "=d") ! 2023: (rotatert:HI (match_operand:HI 1 "general_operand" "0") ! 2024: (match_operand:HI 2 "general_operand" "dI")))] ! 2025: "" ! 2026: "ror%.w %2,%0") ! 2027: ! 2028: (define_insn "rotrqi3" ! 2029: [(set (match_operand:QI 0 "general_operand" "=d") ! 2030: (rotatert:QI (match_operand:QI 1 "general_operand" "0") ! 2031: (match_operand:QI 2 "general_operand" "dI")))] ! 2032: "" ! 2033: "ror%.b %2,%0") ! 2034: ! 2035: ;; Special cases of bit-field insns which we should ! 2036: ;; recognize in preference to the general case. ! 2037: ;; These handle aligned 8-bit and 16-bit fields, ! 2038: ;; which can usually be done with move instructions. ! 2039: ! 2040: (define_insn "" ! 2041: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+do") ! 2042: (match_operand:SI 1 "immediate_operand" "i") ! 2043: (match_operand:SI 2 "immediate_operand" "i")) ! 2044: (match_operand:SI 3 "general_operand" "d"))] ! 2045: "TARGET_68020 && TARGET_BITFIELD ! 2046: && GET_CODE (operands[1]) == CONST_INT ! 2047: && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) ! 2048: && GET_CODE (operands[2]) == CONST_INT ! 2049: && INTVAL (operands[2]) % INTVAL (operands[1]) == 0 ! 2050: && (GET_CODE (operands[0]) == REG ! 2051: || ! mode_dependent_address_p (XEXP (operands[0], 0)))" ! 2052: "* ! 2053: { ! 2054: if (REG_P (operands[0])) ! 2055: { ! 2056: if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32) ! 2057: return \"bfins %3,%0{%b2:%b1}\"; ! 2058: } ! 2059: else ! 2060: operands[0] ! 2061: = adj_offsetable_operand (operands[0], INTVAL (operands[2]) / 8); ! 2062: ! 2063: if (GET_CODE (operands[3]) == MEM) ! 2064: operands[3] = adj_offsetable_operand (operands[3], ! 2065: (32 - INTVAL (operands[1])) / 8); ! 2066: if (INTVAL (operands[1]) == 8) ! 2067: return \"move%.b %3,%0\"; ! 2068: return \"move%.w %3,%0\"; ! 2069: }") ! 2070: ! 2071: (define_insn "" ! 2072: [(set (match_operand:SI 0 "general_operand" "=&d") ! 2073: (zero_extract:SI (match_operand:SI 1 "general_operand" "do") ! 2074: (match_operand:SI 2 "immediate_operand" "i") ! 2075: (match_operand:SI 3 "immediate_operand" "i")))] ! 2076: "TARGET_68020 && TARGET_BITFIELD ! 2077: && GET_CODE (operands[2]) == CONST_INT ! 2078: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) ! 2079: && GET_CODE (operands[3]) == CONST_INT ! 2080: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 ! 2081: && (GET_CODE (operands[1]) == REG ! 2082: || ! mode_dependent_address_p (XEXP (operands[1], 0)))" ! 2083: "* ! 2084: { ! 2085: if (REG_P (operands[1])) ! 2086: { ! 2087: if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32) ! 2088: return \"bfextu %1{%b3:%b2},%0\"; ! 2089: } ! 2090: else ! 2091: operands[1] ! 2092: = adj_offsetable_operand (operands[1], INTVAL (operands[3]) / 8); ! 2093: ! 2094: output_asm_insn (\"clr%.l %0\", operands); ! 2095: if (GET_CODE (operands[0]) == MEM) ! 2096: operands[0] = adj_offsetable_operand (operands[0], ! 2097: (32 - INTVAL (operands[1])) / 8); ! 2098: if (INTVAL (operands[2]) == 8) ! 2099: return \"move%.b %1,%0\"; ! 2100: return \"move%.w %1,%0\"; ! 2101: }") ! 2102: ! 2103: (define_insn "" ! 2104: [(set (match_operand:SI 0 "general_operand" "=d") ! 2105: (sign_extract:SI (match_operand:SI 1 "general_operand" "do") ! 2106: (match_operand:SI 2 "immediate_operand" "i") ! 2107: (match_operand:SI 3 "immediate_operand" "i")))] ! 2108: "TARGET_68020 && TARGET_BITFIELD ! 2109: && GET_CODE (operands[2]) == CONST_INT ! 2110: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) ! 2111: && GET_CODE (operands[3]) == CONST_INT ! 2112: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 ! 2113: && (GET_CODE (operands[1]) == REG ! 2114: || ! mode_dependent_address_p (XEXP (operands[1], 0)))" ! 2115: "* ! 2116: { ! 2117: if (REG_P (operands[1])) ! 2118: { ! 2119: if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32) ! 2120: return \"bfexts %1{%b3:%b2},%0\"; ! 2121: } ! 2122: else ! 2123: operands[1] ! 2124: = adj_offsetable_operand (operands[1], INTVAL (operands[3]) / 8); ! 2125: ! 2126: if (INTVAL (operands[2]) == 8) ! 2127: return \"move%.b %1,%0\;extb%.l %0\"; ! 2128: return \"move%.w %1,%0\;ext%.l %0\"; ! 2129: }") ! 2130: ! 2131: ;; Bit field instructions, general cases. ! 2132: ;; "o,d" constraint causes a nonoffsetable memref to match the "o" ! 2133: ;; so that its address is reloaded. ! 2134: ! 2135: (define_insn "extv" ! 2136: [(set (match_operand:SI 0 "general_operand" "=d") ! 2137: (sign_extract:SI (match_operand:QI 1 "general_operand" "o,d") ! 2138: (match_operand:SI 2 "general_operand" "di,di") ! 2139: (match_operand:SI 3 "general_operand" "di,di")))] ! 2140: "TARGET_68020 && TARGET_BITFIELD" ! 2141: "bfexts %1{%b3:%b2},%0") ! 2142: ! 2143: (define_insn "extzv" ! 2144: [(set (match_operand:SI 0 "general_operand" "=d") ! 2145: (zero_extract:SI (match_operand:QI 1 "general_operand" "o,d") ! 2146: (match_operand:SI 2 "general_operand" "di,di") ! 2147: (match_operand:SI 3 "general_operand" "di,di")))] ! 2148: "TARGET_68020 && TARGET_BITFIELD" ! 2149: "bfextu %1{%b3:%b2},%0") ! 2150: ! 2151: (define_insn "" ! 2152: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+o,d") ! 2153: (match_operand:SI 1 "general_operand" "di,di") ! 2154: (match_operand:SI 2 "general_operand" "di,di")) ! 2155: (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2)) ! 2156: (match_operand 3 "immediate_operand" "i")))] ! 2157: "TARGET_68020 && TARGET_BITFIELD ! 2158: && GET_CODE (operands[3]) == CONST_INT ! 2159: && (INTVAL (operands[3]) == -1 ! 2160: || (GET_CODE (operands[1]) == CONST_INT ! 2161: && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))" ! 2162: "bfchg %0{%b2:%b1}") ! 2163: ! 2164: (define_insn "" ! 2165: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+o,d") ! 2166: (match_operand:SI 1 "general_operand" "di,di") ! 2167: (match_operand:SI 2 "general_operand" "di,di")) ! 2168: (const_int 0))] ! 2169: "TARGET_68020 && TARGET_BITFIELD" ! 2170: "bfclr %0{%b2:%b1}") ! 2171: ! 2172: (define_insn "" ! 2173: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+o,d") ! 2174: (match_operand:SI 1 "general_operand" "di,di") ! 2175: (match_operand:SI 2 "general_operand" "di,di")) ! 2176: (const_int -1))] ! 2177: "TARGET_68020 && TARGET_BITFIELD" ! 2178: "bfset %0{%b2:%b1}") ! 2179: ! 2180: (define_insn "insv" ! 2181: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+o,d") ! 2182: (match_operand:SI 1 "general_operand" "di,di") ! 2183: (match_operand:SI 2 "general_operand" "di,di")) ! 2184: (match_operand:SI 3 "general_operand" "d"))] ! 2185: "TARGET_68020 && TARGET_BITFIELD" ! 2186: "bfins %3,%0{%b2:%b1}") ! 2187: ! 2188: ;; Now recognize bit field insns that operate on registers ! 2189: ;; (or at least were intended to do so). ! 2190: ! 2191: (define_insn "" ! 2192: [(set (match_operand:SI 0 "general_operand" "=d") ! 2193: (sign_extract:SI (match_operand:SI 1 "general_operand" "d") ! 2194: (match_operand:SI 2 "general_operand" "di") ! 2195: (match_operand:SI 3 "general_operand" "di")))] ! 2196: "TARGET_68020 && TARGET_BITFIELD" ! 2197: "bfexts %1{%b3:%b2},%0") ! 2198: ! 2199: (define_insn "" ! 2200: [(set (match_operand:SI 0 "general_operand" "=d") ! 2201: (zero_extract:SI (match_operand:SI 1 "general_operand" "d") ! 2202: (match_operand:SI 2 "general_operand" "di") ! 2203: (match_operand:SI 3 "general_operand" "di")))] ! 2204: "TARGET_68020 && TARGET_BITFIELD" ! 2205: "bfextu %1{%b3:%b2},%0") ! 2206: ! 2207: (define_insn "" ! 2208: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+d") ! 2209: (match_operand:SI 1 "general_operand" "di") ! 2210: (match_operand:SI 2 "general_operand" "di")) ! 2211: (const_int 0))] ! 2212: "TARGET_68020 && TARGET_BITFIELD" ! 2213: "bfclr %0{%b2:%b1}") ! 2214: ! 2215: (define_insn "" ! 2216: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+d") ! 2217: (match_operand:SI 1 "general_operand" "di") ! 2218: (match_operand:SI 2 "general_operand" "di")) ! 2219: (const_int -1))] ! 2220: "TARGET_68020 && TARGET_BITFIELD" ! 2221: "bfset %0{%b2:%b1}") ! 2222: ! 2223: (define_insn "" ! 2224: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+d") ! 2225: (match_operand:SI 1 "general_operand" "di") ! 2226: (match_operand:SI 2 "general_operand" "di")) ! 2227: (match_operand:SI 3 "general_operand" "d"))] ! 2228: "TARGET_68020 && TARGET_BITFIELD" ! 2229: "* ! 2230: { ! 2231: #if 0 ! 2232: /* These special cases are now recognized by a specific pattern. */ ! 2233: if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT ! 2234: && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16) ! 2235: return \"move%.w %3,%0\"; ! 2236: if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT ! 2237: && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8) ! 2238: return \"move%.b %3,%0\"; ! 2239: #endif ! 2240: return \"bfins %3,%0{%b2:%b1}\"; ! 2241: }") ! 2242: ! 2243: ;; Special patterns for optimizing bit-field instructions. ! 2244: ! 2245: (define_insn "" ! 2246: [(set (cc0) ! 2247: (zero_extract:SI (match_operand:QI 0 "memory_operand" "o") ! 2248: (match_operand:SI 1 "general_operand" "di") ! 2249: (match_operand:SI 2 "general_operand" "di")))] ! 2250: "TARGET_68020 && TARGET_BITFIELD ! 2251: && GET_CODE (operands[1]) == CONST_INT" ! 2252: "* ! 2253: { ! 2254: if (operands[1] == const1_rtx ! 2255: && GET_CODE (operands[2]) == CONST_INT) ! 2256: { ! 2257: int width = GET_CODE (operands[0]) == REG ? 31 : 7; ! 2258: return output_btst (operands, ! 2259: gen_rtx (CONST_INT, VOIDmode, ! 2260: width - INTVAL (operands[2])), ! 2261: operands[0], ! 2262: insn, 1000); ! 2263: /* Pass 1000 as SIGNPOS argument so that btst will ! 2264: not think we are testing the sign bit for an `and' ! 2265: and assume that nonzero implies a negative result. */ ! 2266: } ! 2267: if (INTVAL (operands[1]) != 32) ! 2268: cc_status.flags = CC_NOT_NEGATIVE; ! 2269: return \"bftst %0{%b2:%b1}\"; ! 2270: }") ! 2271: ! 2272: (define_insn "" ! 2273: [(set (cc0) ! 2274: (subreg:QI ! 2275: (zero_extract:SI (match_operand:QI 0 "memory_operand" "o") ! 2276: (match_operand:SI 1 "general_operand" "di") ! 2277: (match_operand:SI 2 "general_operand" "di")) ! 2278: 0))] ! 2279: "TARGET_68020 && TARGET_BITFIELD ! 2280: && GET_CODE (operands[1]) == CONST_INT" ! 2281: "* ! 2282: { ! 2283: if (operands[1] == const1_rtx ! 2284: && GET_CODE (operands[2]) == CONST_INT) ! 2285: { ! 2286: int width = GET_CODE (operands[0]) == REG ? 31 : 7; ! 2287: return output_btst (operands, ! 2288: gen_rtx (CONST_INT, VOIDmode, ! 2289: width - INTVAL (operands[2])), ! 2290: operands[0], ! 2291: insn, 1000); ! 2292: /* Pass 1000 as SIGNPOS argument so that btst will ! 2293: not think we are testing the sign bit for an `and' ! 2294: and assume that nonzero implies a negative result. */ ! 2295: } ! 2296: if (INTVAL (operands[1]) != 32) ! 2297: cc_status.flags = CC_NOT_NEGATIVE; ! 2298: return \"bftst %0{%b2:%b1}\"; ! 2299: }") ! 2300: ! 2301: (define_insn "" ! 2302: [(set (cc0) ! 2303: (subreg:HI ! 2304: (zero_extract:SI (match_operand:QI 0 "memory_operand" "o") ! 2305: (match_operand:SI 1 "general_operand" "di") ! 2306: (match_operand:SI 2 "general_operand" "di")) ! 2307: 0))] ! 2308: "TARGET_68020 && TARGET_BITFIELD ! 2309: && GET_CODE (operands[1]) == CONST_INT" ! 2310: "* ! 2311: { ! 2312: if (operands[1] == const1_rtx ! 2313: && GET_CODE (operands[2]) == CONST_INT) ! 2314: { ! 2315: int width = GET_CODE (operands[0]) == REG ? 31 : 7; ! 2316: return output_btst (operands, ! 2317: gen_rtx (CONST_INT, VOIDmode, ! 2318: width - INTVAL (operands[2])), ! 2319: operands[0], ! 2320: insn, 1000); ! 2321: /* Pass 1000 as SIGNPOS argument so that btst will ! 2322: not think we are testing the sign bit for an `and' ! 2323: and assume that nonzero implies a negative result. */ ! 2324: } ! 2325: if (INTVAL (operands[1]) != 32) ! 2326: cc_status.flags = CC_NOT_NEGATIVE; ! 2327: return \"bftst %0{%b2:%b1}\"; ! 2328: }") ! 2329: ! 2330: ;;; now handle the register cases ! 2331: (define_insn "" ! 2332: [(set (cc0) ! 2333: (zero_extract:SI (match_operand:SI 0 "general_operand" "d") ! 2334: (match_operand:SI 1 "general_operand" "di") ! 2335: (match_operand:SI 2 "general_operand" "di")))] ! 2336: "TARGET_68020 && TARGET_BITFIELD ! 2337: && GET_CODE (operands[1]) == CONST_INT" ! 2338: "* ! 2339: { ! 2340: if (operands[1] == const1_rtx ! 2341: && GET_CODE (operands[2]) == CONST_INT) ! 2342: { ! 2343: int width = GET_CODE (operands[0]) == REG ? 31 : 7; ! 2344: return output_btst (operands, ! 2345: gen_rtx (CONST_INT, VOIDmode, ! 2346: width - INTVAL (operands[2])), ! 2347: operands[0], ! 2348: insn, 1000); ! 2349: /* Pass 1000 as SIGNPOS argument so that btst will ! 2350: not think we are testing the sign bit for an `and' ! 2351: and assume that nonzero implies a negative result. */ ! 2352: } ! 2353: if (INTVAL (operands[1]) != 32) ! 2354: cc_status.flags = CC_NOT_NEGATIVE; ! 2355: return \"bftst %0{%b2:%b1}\"; ! 2356: }") ! 2357: ! 2358: (define_insn "" ! 2359: [(set (cc0) ! 2360: (subreg:QI ! 2361: (zero_extract:SI (match_operand:SI 0 "general_operand" "d") ! 2362: (match_operand:SI 1 "general_operand" "di") ! 2363: (match_operand:SI 2 "general_operand" "di")) ! 2364: 0))] ! 2365: "TARGET_68020 && TARGET_BITFIELD ! 2366: && GET_CODE (operands[1]) == CONST_INT" ! 2367: "* ! 2368: { ! 2369: if (operands[1] == const1_rtx ! 2370: && GET_CODE (operands[2]) == CONST_INT) ! 2371: { ! 2372: int width = GET_CODE (operands[0]) == REG ? 31 : 7; ! 2373: return output_btst (operands, ! 2374: gen_rtx (CONST_INT, VOIDmode, ! 2375: width - INTVAL (operands[2])), ! 2376: operands[0], ! 2377: insn, 1000); ! 2378: /* Pass 1000 as SIGNPOS argument so that btst will ! 2379: not think we are testing the sign bit for an `and' ! 2380: and assume that nonzero implies a negative result. */ ! 2381: } ! 2382: if (INTVAL (operands[1]) != 32) ! 2383: cc_status.flags = CC_NOT_NEGATIVE; ! 2384: return \"bftst %0{%b2:%b1}\"; ! 2385: }") ! 2386: ! 2387: (define_insn "" ! 2388: [(set (cc0) ! 2389: (subreg:HI ! 2390: (zero_extract:SI (match_operand:SI 0 "general_operand" "d") ! 2391: (match_operand:SI 1 "general_operand" "di") ! 2392: (match_operand:SI 2 "general_operand" "di")) ! 2393: 0))] ! 2394: "TARGET_68020 && TARGET_BITFIELD ! 2395: && GET_CODE (operands[1]) == CONST_INT" ! 2396: "* ! 2397: { ! 2398: if (operands[1] == const1_rtx ! 2399: && GET_CODE (operands[2]) == CONST_INT) ! 2400: { ! 2401: int width = GET_CODE (operands[0]) == REG ? 31 : 7; ! 2402: return output_btst (operands, ! 2403: gen_rtx (CONST_INT, VOIDmode, ! 2404: width - INTVAL (operands[2])), ! 2405: operands[0], ! 2406: insn, 1000); ! 2407: /* Pass 1000 as SIGNPOS argument so that btst will ! 2408: not think we are testing the sign bit for an `and' ! 2409: and assume that nonzero implies a negative result. */ ! 2410: } ! 2411: if (INTVAL (operands[1]) != 32) ! 2412: cc_status.flags = CC_NOT_NEGATIVE; ! 2413: return \"bftst %0{%b2:%b1}\"; ! 2414: }") ! 2415: ! 2416: (define_insn "seq" ! 2417: [(set (match_operand:QI 0 "general_operand" "=d") ! 2418: (eq (cc0) (const_int 0)))] ! 2419: "" ! 2420: "* ! 2421: cc_status = cc_prev_status; ! 2422: if (cc_status.flags & CC_Z_IN_NOT_N) ! 2423: return \"spl %0\"; ! 2424: OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\"); ! 2425: ") ! 2426: ! 2427: (define_insn "sne" ! 2428: [(set (match_operand:QI 0 "general_operand" "=d") ! 2429: (ne (cc0) (const_int 0)))] ! 2430: "" ! 2431: "* ! 2432: cc_status = cc_prev_status; ! 2433: if (cc_status.flags & CC_Z_IN_NOT_N) ! 2434: return \"smi %0\"; ! 2435: OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\"); ! 2436: ") ! 2437: ! 2438: (define_insn "sgt" ! 2439: [(set (match_operand:QI 0 "general_operand" "=d") ! 2440: (gt (cc0) (const_int 0)))] ! 2441: "" ! 2442: "* ! 2443: cc_status = cc_prev_status; ! 2444: OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", \"and%.b %#0xc,%!\;sgt %0\"); ! 2445: ") ! 2446: ! 2447: (define_insn "sgtu" ! 2448: [(set (match_operand:QI 0 "general_operand" "=d") ! 2449: (gtu (cc0) (const_int 0)))] ! 2450: "" ! 2451: "* cc_status = cc_prev_status; ! 2452: return \"shi %0\"; ") ! 2453: ! 2454: (define_insn "slt" ! 2455: [(set (match_operand:QI 0 "general_operand" "=d") ! 2456: (lt (cc0) (const_int 0)))] ! 2457: "" ! 2458: "* cc_status = cc_prev_status; ! 2459: OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ") ! 2460: ! 2461: (define_insn "sltu" ! 2462: [(set (match_operand:QI 0 "general_operand" "=d") ! 2463: (ltu (cc0) (const_int 0)))] ! 2464: "" ! 2465: "* cc_status = cc_prev_status; ! 2466: return \"scs %0\"; ") ! 2467: ! 2468: (define_insn "sge" ! 2469: [(set (match_operand:QI 0 "general_operand" "=d") ! 2470: (ge (cc0) (const_int 0)))] ! 2471: "" ! 2472: "* cc_status = cc_prev_status; ! 2473: OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ") ! 2474: ! 2475: (define_insn "sgeu" ! 2476: [(set (match_operand:QI 0 "general_operand" "=d") ! 2477: (geu (cc0) (const_int 0)))] ! 2478: "" ! 2479: "* cc_status = cc_prev_status; ! 2480: return \"scc %0\"; ") ! 2481: ! 2482: (define_insn "sle" ! 2483: [(set (match_operand:QI 0 "general_operand" "=d") ! 2484: (le (cc0) (const_int 0)))] ! 2485: "" ! 2486: "* ! 2487: cc_status = cc_prev_status; ! 2488: OUTPUT_JUMP (\"sle %0\", \"fsle %0\", \"and%.b %#0xc,%!\;sle %0\"); ! 2489: ") ! 2490: ! 2491: (define_insn "sleu" ! 2492: [(set (match_operand:QI 0 "general_operand" "=d") ! 2493: (leu (cc0) (const_int 0)))] ! 2494: "" ! 2495: "* cc_status = cc_prev_status; ! 2496: return \"sls %0\"; ") ! 2497: ! 2498: ;; Basic conditional jump instructions. ! 2499: ! 2500: (define_insn "beq" ! 2501: [(set (pc) ! 2502: (if_then_else (eq (cc0) ! 2503: (const_int 0)) ! 2504: (label_ref (match_operand 0 "" "")) ! 2505: (pc)))] ! 2506: "" ! 2507: "* ! 2508: { ! 2509: if (cc_status.flags & CC_Z_IN_NOT_N) ! 2510: #ifdef MOTOROLA ! 2511: return \"jbpl %l0\"; ! 2512: #else ! 2513: return \"jpl %l0\"; ! 2514: #endif ! 2515: #ifdef MOTOROLA ! 2516: OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\"); ! 2517: #else ! 2518: OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\"); ! 2519: #endif ! 2520: }") ! 2521: ! 2522: (define_insn "bne" ! 2523: [(set (pc) ! 2524: (if_then_else (ne (cc0) ! 2525: (const_int 0)) ! 2526: (label_ref (match_operand 0 "" "")) ! 2527: (pc)))] ! 2528: "" ! 2529: "* ! 2530: { ! 2531: if (cc_status.flags & CC_Z_IN_NOT_N) ! 2532: #ifdef MOTOROLA ! 2533: return \"jbmi %l0\"; ! 2534: #else ! 2535: return \"jmi %l0\"; ! 2536: #endif ! 2537: #ifdef MOTOROLA ! 2538: OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\"); ! 2539: #else ! 2540: OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\"); ! 2541: #endif ! 2542: }") ! 2543: ! 2544: (define_insn "bgt" ! 2545: [(set (pc) ! 2546: (if_then_else (gt (cc0) ! 2547: (const_int 0)) ! 2548: (label_ref (match_operand 0 "" "")) ! 2549: (pc)))] ! 2550: "" ! 2551: "* ! 2552: #ifdef MOTOROLA ! 2553: OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", \"and%.b %#0xc,%!\;jbgt %l0\"); ! 2554: #else ! 2555: OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", \"andb %#0xc,%!\;jgt %l0\"); ! 2556: #endif ! 2557: ") ! 2558: ! 2559: (define_insn "bgtu" ! 2560: [(set (pc) ! 2561: (if_then_else (gtu (cc0) ! 2562: (const_int 0)) ! 2563: (label_ref (match_operand 0 "" "")) ! 2564: (pc)))] ! 2565: "" ! 2566: "* ! 2567: #ifdef MOTOROLA ! 2568: return \"jbhi %l0\"; ! 2569: #else ! 2570: return \"jhi %l0\"; ! 2571: #endif ! 2572: ") ! 2573: ! 2574: (define_insn "blt" ! 2575: [(set (pc) ! 2576: (if_then_else (lt (cc0) ! 2577: (const_int 0)) ! 2578: (label_ref (match_operand 0 "" "")) ! 2579: (pc)))] ! 2580: "" ! 2581: "* ! 2582: #ifdef MOTOROLA ! 2583: OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\"); ! 2584: #else ! 2585: OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\"); ! 2586: #endif ! 2587: ") ! 2588: ! 2589: (define_insn "bltu" ! 2590: [(set (pc) ! 2591: (if_then_else (ltu (cc0) ! 2592: (const_int 0)) ! 2593: (label_ref (match_operand 0 "" "")) ! 2594: (pc)))] ! 2595: "" ! 2596: "* ! 2597: #ifdef MOTOROLA ! 2598: return \"jbcs %l0\"; ! 2599: #else ! 2600: return \"jcs %l0\"; ! 2601: #endif ! 2602: ") ! 2603: ! 2604: (define_insn "bge" ! 2605: [(set (pc) ! 2606: (if_then_else (ge (cc0) ! 2607: (const_int 0)) ! 2608: (label_ref (match_operand 0 "" "")) ! 2609: (pc)))] ! 2610: "" ! 2611: "* ! 2612: #ifdef MOTOROLA ! 2613: OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\"); ! 2614: #else ! 2615: OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\"); ! 2616: #endif ! 2617: ") ! 2618: ! 2619: (define_insn "bgeu" ! 2620: [(set (pc) ! 2621: (if_then_else (geu (cc0) ! 2622: (const_int 0)) ! 2623: (label_ref (match_operand 0 "" "")) ! 2624: (pc)))] ! 2625: "" ! 2626: "* ! 2627: #ifdef MOTOROLA ! 2628: return \"jbcc %l0\"; ! 2629: #else ! 2630: return \"jcc %l0\"; ! 2631: #endif ! 2632: ") ! 2633: ! 2634: (define_insn "ble" ! 2635: [(set (pc) ! 2636: (if_then_else (le (cc0) ! 2637: (const_int 0)) ! 2638: (label_ref (match_operand 0 "" "")) ! 2639: (pc)))] ! 2640: "" ! 2641: "* ! 2642: #ifdef MOTOROLA ! 2643: OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", \"and%.b %#0xc,%!\;jble %l0\"); ! 2644: #else ! 2645: OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", \"and%.b %#0xc,%!\;jle %l0\"); ! 2646: #endif ! 2647: ") ! 2648: ! 2649: (define_insn "bleu" ! 2650: [(set (pc) ! 2651: (if_then_else (leu (cc0) ! 2652: (const_int 0)) ! 2653: (label_ref (match_operand 0 "" "")) ! 2654: (pc)))] ! 2655: "" ! 2656: "* ! 2657: #ifdef MOTOROLA ! 2658: return \"jbls %l0\"; ! 2659: #else ! 2660: return \"jls %l0\"; ! 2661: #endif ! 2662: ") ! 2663: ! 2664: ;; Negated conditional jump instructions. ! 2665: ! 2666: (define_insn "" ! 2667: [(set (pc) ! 2668: (if_then_else (eq (cc0) ! 2669: (const_int 0)) ! 2670: (pc) ! 2671: (label_ref (match_operand 0 "" ""))))] ! 2672: "" ! 2673: "* ! 2674: { ! 2675: if (cc_status.flags & CC_Z_IN_NOT_N) ! 2676: #ifdef MOTOROLA ! 2677: return \"jbmi %l0\"; ! 2678: #else ! 2679: return \"jmi %l0\"; ! 2680: #endif ! 2681: #ifdef MOTOROLA ! 2682: OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\"); ! 2683: #else ! 2684: OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\"); ! 2685: #endif ! 2686: }") ! 2687: ! 2688: (define_insn "" ! 2689: [(set (pc) ! 2690: (if_then_else (ne (cc0) ! 2691: (const_int 0)) ! 2692: (pc) ! 2693: (label_ref (match_operand 0 "" ""))))] ! 2694: "" ! 2695: "* ! 2696: { ! 2697: if (cc_status.flags & CC_Z_IN_NOT_N) ! 2698: #ifdef MOTOROLA ! 2699: return \"jbpl %l0\"; ! 2700: #else ! 2701: return \"jpl %l0\"; ! 2702: #endif ! 2703: #ifdef MOTOROLA ! 2704: OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\"); ! 2705: #else ! 2706: OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\"); ! 2707: #endif ! 2708: }") ! 2709: ! 2710: (define_insn "" ! 2711: [(set (pc) ! 2712: (if_then_else (gt (cc0) ! 2713: (const_int 0)) ! 2714: (pc) ! 2715: (label_ref (match_operand 0 "" ""))))] ! 2716: "" ! 2717: "* ! 2718: #ifdef MOTOROLA ! 2719: OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", \"and%.b %#0xc,%!\;jble %l0\"); ! 2720: #else ! 2721: OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", \"and%.b %#0xc,%!\;jle %l0\"); ! 2722: #endif ! 2723: ") ! 2724: ! 2725: (define_insn "" ! 2726: [(set (pc) ! 2727: (if_then_else (gtu (cc0) ! 2728: (const_int 0)) ! 2729: (pc) ! 2730: (label_ref (match_operand 0 "" ""))))] ! 2731: "" ! 2732: "* ! 2733: #ifdef MOTOROLA ! 2734: return \"jbls %l0\"; ! 2735: #else ! 2736: return \"jls %l0\"; ! 2737: #endif ! 2738: ") ! 2739: ! 2740: (define_insn "" ! 2741: [(set (pc) ! 2742: (if_then_else (lt (cc0) ! 2743: (const_int 0)) ! 2744: (pc) ! 2745: (label_ref (match_operand 0 "" ""))))] ! 2746: "" ! 2747: "* ! 2748: #ifdef MOTOROLA ! 2749: OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\"); ! 2750: #else ! 2751: OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\"); ! 2752: #endif ! 2753: ") ! 2754: ! 2755: (define_insn "" ! 2756: [(set (pc) ! 2757: (if_then_else (ltu (cc0) ! 2758: (const_int 0)) ! 2759: (pc) ! 2760: (label_ref (match_operand 0 "" ""))))] ! 2761: "" ! 2762: "* ! 2763: #ifdef MOTOROLA ! 2764: return \"jbcc %l0\"; ! 2765: #else ! 2766: return \"jcc %l0\"; ! 2767: #endif ! 2768: ") ! 2769: ! 2770: (define_insn "" ! 2771: [(set (pc) ! 2772: (if_then_else (ge (cc0) ! 2773: (const_int 0)) ! 2774: (pc) ! 2775: (label_ref (match_operand 0 "" ""))))] ! 2776: "" ! 2777: "* ! 2778: #ifdef MOTOROLA ! 2779: OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\"); ! 2780: #else ! 2781: OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\"); ! 2782: #endif ! 2783: ") ! 2784: ! 2785: (define_insn "" ! 2786: [(set (pc) ! 2787: (if_then_else (geu (cc0) ! 2788: (const_int 0)) ! 2789: (pc) ! 2790: (label_ref (match_operand 0 "" ""))))] ! 2791: "" ! 2792: "* ! 2793: #ifdef MOTOROLA ! 2794: return \"jbcs %l0\"; ! 2795: #else ! 2796: return \"jcs %l0\"; ! 2797: #endif ! 2798: ") ! 2799: ! 2800: (define_insn "" ! 2801: [(set (pc) ! 2802: (if_then_else (le (cc0) ! 2803: (const_int 0)) ! 2804: (pc) ! 2805: (label_ref (match_operand 0 "" ""))))] ! 2806: "" ! 2807: "* ! 2808: #ifdef MOTOROLA ! 2809: OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", \"and%.b %#0xc,%!\;jbgt %l0\"); ! 2810: #else ! 2811: OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", \"and%.b %#0xc,%!\;jgt %l0\"); ! 2812: #endif ! 2813: ") ! 2814: ! 2815: (define_insn "" ! 2816: [(set (pc) ! 2817: (if_then_else (leu (cc0) ! 2818: (const_int 0)) ! 2819: (pc) ! 2820: (label_ref (match_operand 0 "" ""))))] ! 2821: "" ! 2822: "* ! 2823: #ifdef MOTOROLA ! 2824: return \"jbhi %l0\"; ! 2825: #else ! 2826: return \"jhi %l0\"; ! 2827: #endif ! 2828: ") ! 2829: ! 2830: ;; Subroutines of "casesi". ! 2831: ! 2832: (define_expand "casesi_1" ! 2833: [(set (match_operand:SI 3 "general_operand" "") ! 2834: (plus:SI (match_operand:SI 0 "general_operand" "") ! 2835: ;; Note operand 1 has been negated! ! 2836: (match_operand:SI 1 "immediate_operand" ""))) ! 2837: (set (cc0) (minus (match_operand:SI 2 "general_operand" "") ! 2838: (match_dup 3))) ! 2839: (set (pc) (if_then_else (ltu (cc0) (const_int 0)) ! 2840: (label_ref (match_operand 4 "" "")) (pc)))] ! 2841: "" ! 2842: "") ! 2843: ! 2844: (define_expand "casesi_2" ! 2845: [(set (match_operand:SI 0 "" "") (mem:HI (match_operand:SI 1 "" ""))) ! 2846: ;; The USE here is so that at least one jump-insn will refer to the label, ! 2847: ;; to keep it alive in jump_optimize. ! 2848: (parallel [(set (pc) ! 2849: (plus:SI (pc) (match_dup 0))) ! 2850: (use (label_ref (match_operand 2 "" "")))])] ! 2851: "" ! 2852: "") ! 2853: ! 2854: ;; Operand 0 is index (in bytes); operand 1 is minimum, operand 2 themaximum; ! 2855: ;; operand 3 is CODE_LABEL for the table; ! 2856: ;; operand 4 is the CODE_LABEL to go to if index out of range. ! 2857: (define_expand "casesi" ! 2858: ;; We don't use these for generating the RTL, but we must describe ! 2859: ;; the operands here. ! 2860: [(match_operand:SI 0 "general_operand" "") ! 2861: (match_operand:SI 1 "immediate_operand" "") ! 2862: (match_operand:SI 2 "general_operand" "") ! 2863: (match_operand 3 "" "") ! 2864: (match_operand 4 "" "")] ! 2865: "" ! 2866: " ! 2867: { ! 2868: extern rtx negate_rtx (); ! 2869: rtx table_elt_addr; ! 2870: rtx index_diff; ! 2871: ! 2872: operands[1] = negate_rtx (operands[1]); ! 2873: index_diff = gen_reg_rtx (SImode); ! 2874: /* Emit the first few insns. */ ! 2875: emit_insn (gen_casesi_1 (operands[0], operands[1], operands[2], ! 2876: index_diff, operands[4])); ! 2877: /* Construct a memory address. This may emit some insns. */ ! 2878: table_elt_addr ! 2879: = memory_address (HImode, ! 2880: gen_rtx (PLUS, Pmode, ! 2881: gen_rtx (MULT, Pmode, index_diff, ! 2882: gen_rtx (CONST_INT, VOIDmode, 2)), ! 2883: gen_rtx (LABEL_REF, VOIDmode, operands[3]))); ! 2884: /* Emit the last few insns. */ ! 2885: emit_insn (gen_casesi_2 (gen_reg_rtx (HImode), table_elt_addr, operands[3])); ! 2886: DONE; ! 2887: }") ! 2888: ! 2889: ;; Recognize one of the insns resulting from casesi_2. ! 2890: (define_insn "" ! 2891: [(set (pc) ! 2892: (plus:SI (pc) (match_operand:HI 0 "general_operand" "r"))) ! 2893: (use (label_ref (match_operand 1 "" "")))] ! 2894: "" ! 2895: "* ! 2896: #ifdef SGS ! 2897: #ifdef ASM_OUTPUT_CASE_LABEL ! 2898: return \"jmp 6(%%pc,%0.w)\"; ! 2899: #else ! 2900: return \"jmp 2(%%pc,%0.w)\"; ! 2901: #endif ! 2902: #else ! 2903: #ifdef MOTOROLA ! 2904: return \"jmp (2,pc,%0.w)\"; ! 2905: #else ! 2906: return \"jmp pc@(2,%0:w)\"; ! 2907: #endif ! 2908: #endif ! 2909: ") ! 2910: ! 2911: ;; Unconditional and other jump instructions ! 2912: (define_insn "jump" ! 2913: [(set (pc) ! 2914: (label_ref (match_operand 0 "" "")))] ! 2915: "" ! 2916: "* ! 2917: #ifdef MOTOROLA ! 2918: return \"jbra %l0\"; ! 2919: #else ! 2920: return \"jra %l0\"; ! 2921: #endif ! 2922: ") ! 2923: ! 2924: (define_insn "" ! 2925: [(set (pc) ! 2926: (if_then_else ! 2927: (ne (minus (plus:HI (match_operand:HI 0 "general_operand" "g") ! 2928: (const_int -1)) ! 2929: (const_int -1)) ! 2930: (const_int 0)) ! 2931: (label_ref (match_operand 1 "" "")) ! 2932: (pc))) ! 2933: (set (match_dup 0) ! 2934: (plus:HI (match_dup 0) ! 2935: (const_int -1)))] ! 2936: "" ! 2937: "* ! 2938: { ! 2939: if (DATA_REG_P (operands[0])) ! 2940: return \"dbra %0,%l1\"; ! 2941: if (GET_CODE (operands[0]) == MEM) ! 2942: { ! 2943: #ifdef MOTOROLA ! 2944: return \"subq%.w %#1,%0\;jbcc %l1\"; ! 2945: #else ! 2946: return \"subqw %#1,%0\;jcc %l1\"; ! 2947: #endif ! 2948: } ! 2949: #ifdef MOTOROLA ! 2950: #ifdef HPUX_ASM ! 2951: return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\"; ! 2952: #else ! 2953: return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\"; ! 2954: #endif ! 2955: #else ! 2956: return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\"; ! 2957: #endif ! 2958: }") ! 2959: ! 2960: (define_insn "" ! 2961: [(set (pc) ! 2962: (if_then_else ! 2963: (ne (minus (plus:SI (match_operand:SI 0 "general_operand" "g") ! 2964: (const_int -1)) ! 2965: (const_int -1)) ! 2966: (const_int 0)) ! 2967: (label_ref (match_operand 1 "" "")) ! 2968: (pc))) ! 2969: (set (match_dup 0) ! 2970: (plus:SI (match_dup 0) ! 2971: (const_int -1)))] ! 2972: "" ! 2973: "* ! 2974: { ! 2975: #ifdef MOTOROLA ! 2976: if (DATA_REG_P (operands[0])) ! 2977: return \"dbra %0,%l1\;clr.w %0\;subq.l %#1,%0\;jbcc %l1\"; ! 2978: if (GET_CODE (operands[0]) == MEM) ! 2979: return \"subq.l %#1,%0\;jbcc %l1\"; ! 2980: #ifdef HPUX_ASM ! 2981: return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\"; ! 2982: #else ! 2983: return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\"; ! 2984: #endif ! 2985: #else ! 2986: if (DATA_REG_P (operands[0])) ! 2987: return \"dbra %0,%l1\;clrw %0\;subql %#1,%0\;jcc %l1\"; ! 2988: if (GET_CODE (operands[0]) == MEM) ! 2989: return \"subql %#1,%0\;jcc %l1\"; ! 2990: return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\"; ! 2991: #endif ! 2992: }") ! 2993: ! 2994: ;; Call subroutine with no return value. ! 2995: (define_insn "call" ! 2996: [(call (match_operand:QI 0 "general_operand" "m") ! 2997: (match_operand:SI 1 "general_operand" "g"))] ! 2998: ;; Operand 1 not really used on the m68000. ! 2999: ! 3000: "" ! 3001: "* ! 3002: #ifdef MOTOROLA ! 3003: return \"jsr %0\"; ! 3004: #else ! 3005: return \"jbsr %0\"; ! 3006: #endif ! 3007: ") ! 3008: ! 3009: ;; Call subroutine, returning value in operand 0 ! 3010: ;; (which must be a hard register). ! 3011: (define_insn "call_value" ! 3012: [(set (match_operand 0 "" "rf") ! 3013: (call (match_operand:QI 1 "general_operand" "m") ! 3014: (match_operand:SI 2 "general_operand" "g")))] ! 3015: ;; Operand 2 not really used on the m68000. ! 3016: "" ! 3017: "* ! 3018: #ifdef MOTOROLA ! 3019: return \"jsr %1\"; ! 3020: #else ! 3021: return \"jbsr %1\"; ! 3022: #endif ! 3023: ") ! 3024: ! 3025: (define_insn "return" ! 3026: [(return)] ! 3027: "" ! 3028: "rts") ! 3029: ! 3030: ;; This is the first machine-dependent peephole optimization. ! 3031: ;; It is useful when a floating value is returned from a function call ! 3032: ;; and then is moved into an FP register. ! 3033: ;; But it is mainly intended to test the support for these optimizations. ! 3034: ! 3035: (define_peephole ! 3036: [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) ! 3037: (set (match_operand:DF 0 "register_operand" "f") ! 3038: (match_operand:DF 1 "register_operand" "ad"))] ! 3039: "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])" ! 3040: "* ! 3041: { ! 3042: rtx xoperands[2]; ! 3043: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); ! 3044: output_asm_insn (\"move%.l %1,%s\", xoperands); ! 3045: output_asm_insn (\"move%.l %1,%-\", operands); ! 3046: return \"fmove%.d %+,%0\"; ! 3047: } ! 3048: ") ! 3049: ! 3050: ;;- Local variables: ! 3051: ;;- mode:emacs-lisp ! 3052: ;;- comment-start: ";;- " ! 3053: ;;- eval: (set-syntax-table (copy-sequence (syntax-table))) ! 3054: ;;- eval: (modify-syntax-entry ?[ "(]") ! 3055: ;;- eval: (modify-syntax-entry ?] ")[") ! 3056: ;;- eval: (modify-syntax-entry ?{ "(}") ! 3057: ;;- eval: (modify-syntax-entry ?} "){") ! 3058: ;;- End:
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