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1.1 ! root 1: ;; BUGS: ! 2: ;; Insert no-op between an insn with memory read-write operands ! 3: ;; following by a scale-indexing operation. ! 4: ;; The Sequent assembler does not allow addresses to be used ! 5: ;; except in insns which explicitly compute an effective address. ! 6: ;; I.e., one cannot say "cmpd _p,@_x" ! 7: ;; Implement unsigned multiplication?? ! 8: ! 9: ;;- Machine descrption for GNU compiler ! 10: ;;- ns32000 Version ! 11: ;; Copyright (C) 1988 Free Software Foundation, Inc. ! 12: ;; Contributed by Michael Tiemann ([email protected]) ! 13: ! 14: ;; This file is part of GNU CC. ! 15: ! 16: ;; GNU CC is distributed in the hope that it will be useful, ! 17: ;; but WITHOUT ANY WARRANTY. No author or distributor ! 18: ;; accepts responsibility to anyone for the consequences of using it ! 19: ;; or for whether it serves any particular purpose or works at all, ! 20: ;; unless he says so in writing. Refer to the GNU CC General Public ! 21: ;; License for full details. ! 22: ! 23: ;; Everyone is granted permission to copy, modify and redistribute ! 24: ;; GNU CC, but only under the conditions described in the ! 25: ;; GNU CC General Public License. A copy of this license is ! 26: ;; supposed to have been given to you along with GNU CC so you ! 27: ;; can know your rights and responsibilities. It should be in a ! 28: ;; file named COPYING. Among other things, the copyright notice ! 29: ;; and this notice must be preserved on all copies. ! 30: ! 31: ! 32: ;;- Instruction patterns. When multiple patterns apply, ! 33: ;;- the first one in the file is chosen. ! 34: ;;- ! 35: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ! 36: ;;- ! 37: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code ! 38: ;;- updates for most instructions. ! 39: ! 40: ; tstsi is first test insn so that it is the one to match ! 41: ; a constant argument. ! 42: ! 43: (define_insn "tstsi" ! 44: [(set (cc0) ! 45: (match_operand:SI 0 "general_operand" "rmn"))] ! 46: "" ! 47: "* ! 48: { cc_status.flags |= CC_REVERSED; ! 49: operands[1] = const0_rtx; ! 50: return \"cmpqd %1,%0\"; }") ! 51: ! 52: (define_insn "tsthi" ! 53: [(set (cc0) ! 54: (match_operand:HI 0 "general_operand" "g"))] ! 55: "" ! 56: "* ! 57: { cc_status.flags |= CC_REVERSED; ! 58: operands[1] = const0_rtx; ! 59: return \"cmpqw %1,%0\"; }") ! 60: ! 61: (define_insn "tstqi" ! 62: [(set (cc0) ! 63: (match_operand:QI 0 "general_operand" "g"))] ! 64: "" ! 65: "* ! 66: { cc_status.flags |= CC_REVERSED; ! 67: operands[1] = const0_rtx; ! 68: return \"cmpqb %1,%0\"; }") ! 69: ! 70: (define_insn "tstdf" ! 71: [(set (cc0) ! 72: (match_operand:DF 0 "general_operand" "fmF"))] ! 73: "TARGET_32081" ! 74: "* ! 75: { cc_status.flags |= CC_REVERSED; ! 76: operands[1] = dconst0_rtx; ! 77: return \"cmpl %1,%0\"; }") ! 78: ! 79: (define_insn "tstsf" ! 80: [(set (cc0) ! 81: (match_operand:SF 0 "general_operand" "fmF"))] ! 82: "TARGET_32081" ! 83: "* ! 84: { cc_status.flags |= CC_REVERSED; ! 85: operands[1] = fconst0_rtx; ! 86: return \"cmpf %1,%0\"; }") ! 87: ! 88: (define_insn "cmpdf" ! 89: [(set (cc0) ! 90: (minus (match_operand:DF 0 "general_operand" "fmF") ! 91: (match_operand:DF 1 "general_operand" "fmF")))] ! 92: "TARGET_32081" ! 93: "cmpl %0,%1") ! 94: ! 95: (define_insn "cmpsf" ! 96: [(set (cc0) ! 97: (minus (match_operand:SF 0 "general_operand" "fmF") ! 98: (match_operand:SF 1 "general_operand" "fmF")))] ! 99: "TARGET_32081" ! 100: "cmpf %0,%1") ! 101: ! 102: (define_insn "cmpsi" ! 103: [(set (cc0) ! 104: (minus (match_operand:SI 0 "general_operand" "rmn") ! 105: (match_operand:SI 1 "general_operand" "rmn")))] ! 106: "" ! 107: "* ! 108: { ! 109: if (GET_CODE (operands[1]) == CONST_INT) ! 110: { ! 111: int i = INTVAL (operands[1]); ! 112: if (i <= 7 && i >= -8) ! 113: { ! 114: cc_status.flags |= CC_REVERSED; ! 115: return \"cmpqd %1,%0\"; ! 116: } ! 117: } ! 118: cc_status.flags &= ~CC_REVERSED; ! 119: if (GET_CODE (operands[0]) == CONST_INT) ! 120: { ! 121: int i = INTVAL (operands[0]); ! 122: if (i <= 7 && i >= -8) ! 123: return \"cmpqd %0,%1\"; ! 124: } ! 125: return \"cmpd %0,%1\"; ! 126: }") ! 127: ! 128: (define_insn "cmphi" ! 129: [(set (cc0) ! 130: (minus (match_operand:HI 0 "general_operand" "g") ! 131: (match_operand:HI 1 "general_operand" "g")))] ! 132: "" ! 133: "* ! 134: { ! 135: if (GET_CODE (operands[1]) == CONST_INT) ! 136: { ! 137: short i = INTVAL (operands[1]); ! 138: if (i <= 7 && i >= -8) ! 139: { ! 140: cc_status.flags |= CC_REVERSED; ! 141: if (INTVAL (operands[1]) > 7) ! 142: operands[1] = gen_rtx(CONST_INT, VOIDmode, i); ! 143: return \"cmpqw %1,%0\"; ! 144: } ! 145: } ! 146: cc_status.flags &= ~CC_REVERSED; ! 147: if (GET_CODE (operands[0]) == CONST_INT) ! 148: { ! 149: short i = INTVAL (operands[0]); ! 150: if (i <= 7 && i >= -8) ! 151: { ! 152: if (INTVAL (operands[0]) > 7) ! 153: operands[0] = gen_rtx(CONST_INT, VOIDmode, i); ! 154: return \"cmpqw %0,%1\"; ! 155: } ! 156: } ! 157: return \"cmpw %0,%1\"; ! 158: }") ! 159: ! 160: (define_insn "cmpqi" ! 161: [(set (cc0) ! 162: (minus (match_operand:QI 0 "general_operand" "g") ! 163: (match_operand:QI 1 "general_operand" "g")))] ! 164: "" ! 165: "* ! 166: { ! 167: if (GET_CODE (operands[1]) == CONST_INT) ! 168: { ! 169: char i = INTVAL (operands[1]); ! 170: if (i <= 7 && i >= -8) ! 171: { ! 172: cc_status.flags |= CC_REVERSED; ! 173: if (INTVAL (operands[1]) > 7) ! 174: operands[1] = gen_rtx(CONST_INT, VOIDmode, i); ! 175: return \"cmpqb %1,%0\"; ! 176: } ! 177: } ! 178: cc_status.flags &= ~CC_REVERSED; ! 179: if (GET_CODE (operands[0]) == CONST_INT) ! 180: { ! 181: char i = INTVAL (operands[0]); ! 182: if (i <= 7 && i >= -8) ! 183: { ! 184: if (INTVAL (operands[0]) > 7) ! 185: operands[0] = gen_rtx(CONST_INT, VOIDmode, i); ! 186: return \"cmpqb %0,%1\"; ! 187: } ! 188: } ! 189: return \"cmpb %0,%1\"; ! 190: }") ! 191: ! 192: (define_insn "movdf" ! 193: [(set (match_operand:DF 0 "general_operand" "=fg<") ! 194: (match_operand:DF 1 "general_operand" "fFg"))] ! 195: "" ! 196: "* ! 197: { ! 198: if (FP_REG_P (operands[0])) ! 199: { ! 200: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE) ! 201: return \"movl %1,%0\"; ! 202: if (REG_P (operands[1])) ! 203: { ! 204: rtx xoperands[2]; ! 205: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); ! 206: output_asm_insn (\"movd %1,tos\", xoperands); ! 207: output_asm_insn (\"movd %1,tos\", operands); ! 208: return \"movl tos,%0\"; ! 209: } ! 210: return \"movl %1,%0\"; ! 211: } ! 212: else if (FP_REG_P (operands[1])) ! 213: { ! 214: if (REG_P (operands[0])) ! 215: { ! 216: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands); ! 217: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); ! 218: return \"movd tos,%0\"; ! 219: } ! 220: else ! 221: return \"movl %1,%0\"; ! 222: } ! 223: return output_move_double (operands); ! 224: }") ! 225: ! 226: (define_insn "movsf" ! 227: [(set (match_operand:SF 0 "general_operand" "=fg<") ! 228: (match_operand:SF 1 "general_operand" "fFg"))] ! 229: "" ! 230: "* ! 231: { ! 232: if (FP_REG_P (operands[0])) ! 233: { ! 234: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8) ! 235: return \"movd %1,tos\;movf tos,%0\"; ! 236: else ! 237: return \"movf %1,%0\"; ! 238: } ! 239: else if (FP_REG_P (operands[1])) ! 240: { ! 241: if (REG_P (operands[0])) ! 242: return \"movf %1,tos\;movd tos,%0\"; ! 243: return \"movf %1,%0\"; ! 244: } ! 245: else if (GET_CODE (operands[1]) == CONST_DOUBLE) ! 246: { ! 247: /* Is there a better machine-independent way to to this? */ ! 248: operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1])); ! 249: return \"movd %1,%0\"; ! 250: } ! 251: else return \"movd %1,%0\"; ! 252: }") ! 253: ! 254: (define_insn "" ! 255: [(set (match_operand:TI 0 "memory_operand" "=m") ! 256: (match_operand:TI 1 "memory_operand" "m"))] ! 257: "" ! 258: "movmd %1,%0,4") ! 259: ! 260: (define_insn "movdi" ! 261: [(set (match_operand:DI 0 "general_operand" "=g<") ! 262: (match_operand:DI 1 "general_operand" "g"))] ! 263: "" ! 264: "* return output_move_double (operands); ") ! 265: ! 266: (define_insn "movsi" ! 267: [(set (match_operand:SI 0 "general_operand" "=g<") ! 268: (match_operand:SI 1 "general_operand" "gx"))] ! 269: "" ! 270: "* ! 271: { if (GET_CODE (operands[1]) == CONST_INT) ! 272: { ! 273: int i = INTVAL (operands[1]); ! 274: if (i <= 7 && i >= -8) ! 275: return \"movqd %1,%0\"; ! 276: if (i < 0x4000 && i >= -0x4000) ! 277: return \"addr @%c1,%0\"; ! 278: return \"movd %1,%0\"; ! 279: } ! 280: else if (GET_CODE (operands[1]) == REG) ! 281: if (REGNO (operands[1]) < 16) ! 282: return \"movd %1,%0\"; ! 283: else if (REGNO (operands[1]) == 16) ! 284: return \"addr 0(fp),%0\"; ! 285: else return \"addr tos,%0\"; ! 286: else if (GET_CODE (operands[1]) == MEM) ! 287: return \"movd %1,%0\"; ! 288: /* Check if this effective address can be ! 289: calculated faster by pulling it apart. */ ! 290: if (REG_P (operands[0]) ! 291: && GET_CODE (operands[1]) == MULT ! 292: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT ! 293: && (INTVAL (XEXP (operands[1], 1)) == 2 ! 294: || INTVAL (XEXP (operands[1], 1)) == 4)) ! 295: { ! 296: rtx xoperands[3]; ! 297: xoperands[0] = operands[0]; ! 298: xoperands[1] = XEXP (operands[1], 0); ! 299: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1); ! 300: return output_shift_insn (xoperands); ! 301: } ! 302: return \"addr %a1,%0\"; ! 303: }") ! 304: ! 305: (define_insn "movhi" ! 306: [(set (match_operand:HI 0 "general_operand" "=g<") ! 307: (match_operand:HI 1 "general_operand" "g"))] ! 308: "" ! 309: "* ! 310: { ! 311: if (GET_CODE (operands[1]) == CONST_INT) ! 312: { ! 313: short i = INTVAL (operands[1]); ! 314: if (i <= 7 && i >= -8) ! 315: { ! 316: if (INTVAL (operands[1]) > 7) ! 317: operands[1] = ! 318: gen_rtx (CONST_INT, VOIDmode, i); ! 319: return \"movqw %1,%0\"; ! 320: } ! 321: } ! 322: return \"movw %1,%0\"; ! 323: }") ! 324: ! 325: (define_insn "movstricthi" ! 326: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+r")) ! 327: (match_operand:HI 1 "general_operand" "g"))] ! 328: "" ! 329: "* ! 330: { ! 331: if (GET_CODE (operands[1]) == CONST_INT ! 332: && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8) ! 333: return \"movqw %1,%0\"; ! 334: return \"movw %1,%0\"; ! 335: }") ! 336: ! 337: (define_insn "movqi" ! 338: [(set (match_operand:QI 0 "general_operand" "=g<") ! 339: (match_operand:QI 1 "general_operand" "g"))] ! 340: "" ! 341: "* ! 342: { if (GET_CODE (operands[1]) == CONST_INT) ! 343: { ! 344: char char_val = (char)INTVAL (operands[1]); ! 345: if (char_val <= 7 && char_val >= -8) ! 346: { ! 347: if (INTVAL (operands[1]) > 7) ! 348: operands[1] = ! 349: gen_rtx (CONST_INT, VOIDmode, char_val); ! 350: return \"movqb %1,%0\"; ! 351: } ! 352: } ! 353: return \"movb %1,%0\"; ! 354: }") ! 355: ! 356: (define_insn "movstrictqi" ! 357: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+r")) ! 358: (match_operand:QI 1 "general_operand" "g"))] ! 359: "" ! 360: "* ! 361: { ! 362: if (GET_CODE (operands[1]) == CONST_INT ! 363: && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9) ! 364: return \"movqb %1,%0\"; ! 365: return \"movb %1,%0\"; ! 366: }") ! 367: ! 368: (define_insn "" ! 369: [(set (reg:SI 17) ! 370: (match_operand:SI 0 "general_operand" "rmn"))] ! 371: "" ! 372: "lprd sp,%0") ! 373: ! 374: ;; The definition of this insn does not really explain what it does, ! 375: ;; but it should suffice ! 376: ;; that anything generated as this insn will be recognized as one ! 377: ;; and that it won't successfully combine with anything. ! 378: (define_insn "movstrsi" ! 379: [(set (match_operand:BLK 0 "general_operand" "=g") ! 380: (match_operand:BLK 1 "general_operand" "g")) ! 381: (use (match_operand:SI 2 "general_operand" "rmn")) ! 382: (clobber (reg:SI 0)) ! 383: (clobber (reg:SI 1)) ! 384: (clobber (reg:SI 2))] ! 385: "" ! 386: "* ! 387: { ! 388: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) ! 389: abort (); ! 390: operands[0] = XEXP (operands[0], 0); ! 391: operands[1] = XEXP (operands[1], 0); ! 392: if (GET_CODE (operands[0]) == MEM) ! 393: if (GET_CODE (operands[1]) == MEM) ! 394: output_asm_insn (\"movd %0,r2\;movd %1,r1\", operands); ! 395: else ! 396: output_asm_insn (\"movd %0,r2\;addr %a1,r1\", operands); ! 397: else if (GET_CODE (operands[1]) == MEM) ! 398: output_asm_insn (\"addr %a0,r2\;movd %1,r1\", operands); ! 399: else ! 400: output_asm_insn (\"addr %a0,r2\;addr %a1,r1\", operands); ! 401: ! 402: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0) ! 403: { ! 404: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2); ! 405: if ((unsigned) INTVAL (operands[2]) <= 7) ! 406: return \"movqd %2,r0\;movsd\"; ! 407: else ! 408: return \"movd %2,r0\;movsd\"; ! 409: } ! 410: else ! 411: { ! 412: return \"movd %2,r0\;movsb\"; ! 413: } ! 414: }") ! 415: ! 416: ;; Extension and truncation insns. ! 417: ;; Those for integer source operand ! 418: ;; are ordered widest source type first. ! 419: ! 420: (define_insn "truncsiqi2" ! 421: [(set (match_operand:QI 0 "general_operand" "=g<") ! 422: (truncate:QI (match_operand:SI 1 "general_operand" "rmn")))] ! 423: "" ! 424: "movb %1,%0") ! 425: ! 426: (define_insn "truncsihi2" ! 427: [(set (match_operand:HI 0 "general_operand" "=g<") ! 428: (truncate:HI (match_operand:SI 1 "general_operand" "rmn")))] ! 429: "" ! 430: "movw %1,%0") ! 431: ! 432: (define_insn "trunchiqi2" ! 433: [(set (match_operand:QI 0 "general_operand" "=g<") ! 434: (truncate:QI (match_operand:HI 1 "general_operand" "g")))] ! 435: "" ! 436: "movb %1,%0") ! 437: ! 438: (define_insn "extendhisi2" ! 439: [(set (match_operand:SI 0 "general_operand" "=g<") ! 440: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))] ! 441: "" ! 442: "movxwd %1,%0") ! 443: ! 444: (define_insn "extendqihi2" ! 445: [(set (match_operand:HI 0 "general_operand" "=g<") ! 446: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))] ! 447: "" ! 448: "movxbw %1,%0") ! 449: ! 450: (define_insn "extendqisi2" ! 451: [(set (match_operand:SI 0 "general_operand" "=g<") ! 452: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))] ! 453: "" ! 454: "movxbd %1,%0") ! 455: ! 456: (define_insn "extendsfdf2" ! 457: [(set (match_operand:DF 0 "general_operand" "=fm<") ! 458: (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))] ! 459: "TARGET_32081" ! 460: "movfl %1,%0") ! 461: ! 462: (define_insn "truncdfsf2" ! 463: [(set (match_operand:SF 0 "general_operand" "=fm<") ! 464: (float_truncate:SF (match_operand:DF 1 "general_operand" "fmF")))] ! 465: "TARGET_32081" ! 466: "movlf %1,%0") ! 467: ! 468: (define_insn "zero_extendhisi2" ! 469: [(set (match_operand:SI 0 "general_operand" "=g<") ! 470: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))] ! 471: "" ! 472: "movzwd %1,%0") ! 473: ! 474: (define_insn "zero_extendqihi2" ! 475: [(set (match_operand:HI 0 "general_operand" "=g<") ! 476: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))] ! 477: "" ! 478: "movzbw %1,%0") ! 479: ! 480: (define_insn "zero_extendqisi2" ! 481: [(set (match_operand:SI 0 "general_operand" "=g<") ! 482: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))] ! 483: "" ! 484: "movzbd %1,%0") ! 485: ! 486: ;; Fix-to-float conversion insns. ! 487: ;; Note that the ones that start with SImode come first. ! 488: ;; That is so that an operand that is a CONST_INT ! 489: ;; (and therefore lacks a specific machine mode). ! 490: ;; will be recognized as SImode (which is always valid) ! 491: ;; rather than as QImode or HImode. ! 492: ! 493: ;; Rumor has it that the National part does not correctly convert ! 494: ;; constant ints to floats. This conversion is therefore disabled. ! 495: ;; A register must be used to perform the conversion. ! 496: ! 497: (define_insn "floatsisf2" ! 498: [(set (match_operand:SF 0 "general_operand" "=fm<") ! 499: (float:SF (match_operand:SI 1 "general_operand" "rm")))] ! 500: "TARGET_32081" ! 501: "movdf %1,%0") ! 502: ! 503: (define_insn "floatsidf2" ! 504: [(set (match_operand:DF 0 "general_operand" "=fm<") ! 505: (float:DF (match_operand:SI 1 "general_operand" "rm")))] ! 506: "TARGET_32081" ! 507: "movdl %1,%0") ! 508: ! 509: (define_insn "floathisf2" ! 510: [(set (match_operand:SF 0 "general_operand" "=fm<") ! 511: (float:SF (match_operand:HI 1 "general_operand" "rm")))] ! 512: "TARGET_32081" ! 513: "movwf %1,%0") ! 514: ! 515: (define_insn "floathidf2" ! 516: [(set (match_operand:DF 0 "general_operand" "=fm<") ! 517: (float:DF (match_operand:HI 1 "general_operand" "rm")))] ! 518: "TARGET_32081" ! 519: "movwl %1,%0") ! 520: ! 521: (define_insn "floatqisf2" ! 522: [(set (match_operand:SF 0 "general_operand" "=fm<") ! 523: (float:SF (match_operand:QI 1 "general_operand" "rm")))] ! 524: "TARGET_32081" ! 525: "movbf %1,%0") ! 526: ! 527: (define_insn "floatqidf2" ! 528: [(set (match_operand:DF 0 "general_operand" "=fm<") ! 529: (float:DF (match_operand:QI 1 "general_operand" "rm")))] ! 530: "TARGET_32081" ! 531: "movbl %1,%0") ! 532: ! 533: ;; Float-to-fix conversion insns. ! 534: ;; The sequent compiler always generates "trunc" insns. ! 535: ! 536: (define_insn "fixsfqi2" ! 537: [(set (match_operand:QI 0 "general_operand" "=g<") ! 538: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] ! 539: "TARGET_32081" ! 540: "truncfb %1,%0") ! 541: ! 542: (define_insn "fixsfhi2" ! 543: [(set (match_operand:HI 0 "general_operand" "=g<") ! 544: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] ! 545: "TARGET_32081" ! 546: "truncfw %1,%0") ! 547: ! 548: (define_insn "fixsfsi2" ! 549: [(set (match_operand:SI 0 "general_operand" "=g<") ! 550: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] ! 551: "TARGET_32081" ! 552: "truncfd %1,%0") ! 553: ! 554: (define_insn "fixdfqi2" ! 555: [(set (match_operand:QI 0 "general_operand" "=g<") ! 556: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] ! 557: "TARGET_32081" ! 558: "trunclb %1,%0") ! 559: ! 560: (define_insn "fixdfhi2" ! 561: [(set (match_operand:HI 0 "general_operand" "=g<") ! 562: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] ! 563: "TARGET_32081" ! 564: "trunclw %1,%0") ! 565: ! 566: (define_insn "fixdfsi2" ! 567: [(set (match_operand:SI 0 "general_operand" "=g<") ! 568: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] ! 569: "TARGET_32081" ! 570: "truncld %1,%0") ! 571: ! 572: ;; Unsigned ! 573: ! 574: (define_insn "fixunssfqi2" ! 575: [(set (match_operand:QI 0 "general_operand" "=g<") ! 576: (unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] ! 577: "TARGET_32081" ! 578: "truncfb %1,%0") ! 579: ! 580: (define_insn "fixunssfhi2" ! 581: [(set (match_operand:HI 0 "general_operand" "=g<") ! 582: (unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] ! 583: "TARGET_32081" ! 584: "truncfw %1,%0") ! 585: ! 586: (define_insn "fixunssfsi2" ! 587: [(set (match_operand:SI 0 "general_operand" "=g<") ! 588: (unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] ! 589: "TARGET_32081" ! 590: "truncfd %1,%0") ! 591: ! 592: (define_insn "fixunsdfqi2" ! 593: [(set (match_operand:QI 0 "general_operand" "=g<") ! 594: (unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] ! 595: "TARGET_32081" ! 596: "trunclb %1,%0") ! 597: ! 598: (define_insn "fixunsdfhi2" ! 599: [(set (match_operand:HI 0 "general_operand" "=g<") ! 600: (unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] ! 601: "TARGET_32081" ! 602: "trunclw %1,%0") ! 603: ! 604: (define_insn "fixunsdfsi2" ! 605: [(set (match_operand:SI 0 "general_operand" "=g<") ! 606: (unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] ! 607: "TARGET_32081" ! 608: "truncld %1,%0") ! 609: ! 610: ;;; These are not yet used by GCC ! 611: (define_insn "fix_truncsfqi2" ! 612: [(set (match_operand:QI 0 "general_operand" "=g<") ! 613: (fix:QI (match_operand:SF 1 "general_operand" "fm")))] ! 614: "TARGET_32081" ! 615: "truncfb %1,%0") ! 616: ! 617: (define_insn "fix_truncsfhi2" ! 618: [(set (match_operand:HI 0 "general_operand" "=g<") ! 619: (fix:HI (match_operand:SF 1 "general_operand" "fm")))] ! 620: "TARGET_32081" ! 621: "truncfw %1,%0") ! 622: ! 623: (define_insn "fix_truncsfsi2" ! 624: [(set (match_operand:SI 0 "general_operand" "=g<") ! 625: (fix:SI (match_operand:SF 1 "general_operand" "fm")))] ! 626: "TARGET_32081" ! 627: "truncfd %1,%0") ! 628: ! 629: (define_insn "fix_truncdfqi2" ! 630: [(set (match_operand:QI 0 "general_operand" "=g<") ! 631: (fix:QI (match_operand:DF 1 "general_operand" "fm")))] ! 632: "TARGET_32081" ! 633: "trunclb %1,%0") ! 634: ! 635: (define_insn "fix_truncdfhi2" ! 636: [(set (match_operand:HI 0 "general_operand" "=g<") ! 637: (fix:HI (match_operand:DF 1 "general_operand" "fm")))] ! 638: "TARGET_32081" ! 639: "trunclw %1,%0") ! 640: ! 641: (define_insn "fix_truncdfsi2" ! 642: [(set (match_operand:SI 0 "general_operand" "=g<") ! 643: (fix:SI (match_operand:DF 1 "general_operand" "fm")))] ! 644: "TARGET_32081" ! 645: "truncld %1,%0") ! 646: ! 647: ;;- All kinds of add instructions. ! 648: ! 649: (define_insn "adddf3" ! 650: [(set (match_operand:DF 0 "general_operand" "=fm") ! 651: (plus:DF (match_operand:DF 1 "general_operand" "%0") ! 652: (match_operand:DF 2 "general_operand" "fmF")))] ! 653: "TARGET_32081" ! 654: "addl %2,%0") ! 655: ! 656: ! 657: (define_insn "addsf3" ! 658: [(set (match_operand:SF 0 "general_operand" "=fm") ! 659: (plus:SF (match_operand:SF 1 "general_operand" "%0") ! 660: (match_operand:SF 2 "general_operand" "fmF")))] ! 661: "TARGET_32081" ! 662: "addf %2,%0") ! 663: ! 664: (define_insn "" ! 665: [(set (reg:SI 17) ! 666: (plus:SI (reg:SI 17) ! 667: (match_operand:SI 0 "immediate_operand" "i")))] ! 668: "GET_CODE (operands[0]) == CONST_INT" ! 669: "* ! 670: { ! 671: if (INTVAL(operands[0]) < 64 && INTVAL(operands[0]) > -64) ! 672: return \"adjspb %$%n0\"; ! 673: else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192) ! 674: return \"adjspw %$%n0\"; ! 675: return \"adjspd %$%n0\"; ! 676: }") ! 677: ! 678: (define_insn "" ! 679: [(set (match_operand:SI 0 "general_operand" "=g<") ! 680: (plus:SI (reg:SI 16) ! 681: (match_operand:SI 1 "immediate_operand" "i")))] ! 682: "GET_CODE (operands[1]) == CONST_INT" ! 683: "addr %c1(fp),%0") ! 684: ! 685: (define_insn "" ! 686: [(set (match_operand:SI 0 "general_operand" "=g<") ! 687: (plus:SI (reg:SI 17) ! 688: (match_operand:SI 1 "immediate_operand" "i")))] ! 689: "GET_CODE (operands[1]) == CONST_INT" ! 690: "addr %c1(sp),%0") ! 691: ! 692: (define_insn "addsi3" ! 693: [(set (match_operand:SI 0 "general_operand" "=g") ! 694: (plus:SI (match_operand:SI 1 "general_operand" "%0") ! 695: (match_operand:SI 2 "general_operand" "rmn")))] ! 696: "" ! 697: "* ! 698: { ! 699: if (GET_CODE (operands[2]) == CONST_INT) ! 700: { ! 701: int i = INTVAL (operands[2]); ! 702: ! 703: if (i <= 7 && i >= -8) ! 704: return \"addqd %2,%0\"; ! 705: else if (GET_CODE (operands[0]) == REG ! 706: && i < 0x4000 && i >= -0x4000) ! 707: return \"addr %c2(%0),%0\"; ! 708: } ! 709: return \"addd %2,%0\"; ! 710: }") ! 711: ! 712: (define_insn "addhi3" ! 713: [(set (match_operand:HI 0 "general_operand" "=g") ! 714: (plus:HI (match_operand:HI 1 "general_operand" "%0") ! 715: (match_operand:HI 2 "general_operand" "g")))] ! 716: "" ! 717: "* ! 718: { if (GET_CODE (operands[2]) == CONST_INT) ! 719: { ! 720: int i = INTVAL (operands[2]); ! 721: if (i <= 7 && i >= -8) ! 722: return \"addqw %2,%0\"; ! 723: } ! 724: return \"addw %2,%0\"; ! 725: }") ! 726: ! 727: (define_insn "" ! 728: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r")) ! 729: (plus:HI (match_operand:HI 1 "general_operand" "0") ! 730: (match_operand:HI 2 "general_operand" "g")))] ! 731: "" ! 732: "* ! 733: { ! 734: if (GET_CODE (operands[1]) == CONST_INT ! 735: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8) ! 736: return \"addqw %1,%0\"; ! 737: return \"addw %1,%0\"; ! 738: }") ! 739: ! 740: (define_insn "addqi3" ! 741: [(set (match_operand:QI 0 "general_operand" "=g") ! 742: (plus:QI (match_operand:QI 1 "general_operand" "%0") ! 743: (match_operand:QI 2 "general_operand" "g")))] ! 744: "" ! 745: "* ! 746: { if (GET_CODE (operands[2]) == CONST_INT) ! 747: { ! 748: int i = INTVAL (operands[2]); ! 749: if (i <= 7 && i >= -8) ! 750: return \"addqb %2,%0\"; ! 751: } ! 752: return \"addb %2,%0\"; ! 753: }") ! 754: ! 755: (define_insn "" ! 756: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r")) ! 757: (plus:QI (match_operand:QI 1 "general_operand" "0") ! 758: (match_operand:QI 2 "general_operand" "g")))] ! 759: "" ! 760: "* ! 761: { ! 762: if (GET_CODE (operands[1]) == CONST_INT ! 763: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8) ! 764: return \"addqb %1,%0\"; ! 765: return \"addb %1,%0\"; ! 766: }") ! 767: ! 768: ;;- All kinds of subtract instructions. ! 769: ! 770: (define_insn "subdf3" ! 771: [(set (match_operand:DF 0 "general_operand" "=fm") ! 772: (minus:DF (match_operand:DF 1 "general_operand" "0") ! 773: (match_operand:DF 2 "general_operand" "fmF")))] ! 774: "TARGET_32081" ! 775: "subl %2,%0") ! 776: ! 777: (define_insn "subsf3" ! 778: [(set (match_operand:SF 0 "general_operand" "=fm") ! 779: (minus:SF (match_operand:SF 1 "general_operand" "0") ! 780: (match_operand:SF 2 "general_operand" "fmF")))] ! 781: "TARGET_32081" ! 782: "subf %2,%0") ! 783: ! 784: (define_insn "" ! 785: [(set (reg:SI 17) ! 786: (minus:SI (reg:SI 17) ! 787: (match_operand:SI 0 "immediate_operand" "i")))] ! 788: "GET_CODE (operands[0]) == CONST_INT" ! 789: "* ! 790: { ! 791: if (GET_CODE(operands[0]) == CONST_INT && INTVAL(operands[0]) < 64 ! 792: && INTVAL(operands[0]) > -64) ! 793: return \"adjspb %0\"; ! 794: return \"adjspd %0\"; ! 795: }") ! 796: ! 797: (define_insn "subsi3" ! 798: [(set (match_operand:SI 0 "general_operand" "=g") ! 799: (minus:SI (match_operand:SI 1 "general_operand" "0") ! 800: (match_operand:SI 2 "general_operand" "rmn")))] ! 801: "" ! 802: "* ! 803: { if (GET_CODE (operands[2]) == CONST_INT) ! 804: { ! 805: int i = INTVAL (operands[2]); ! 806: ! 807: if (i <= 8 && i >= -7) ! 808: return \"addqd %$%n2,%0\"; ! 809: } ! 810: return \"subd %2,%0\"; ! 811: }") ! 812: ! 813: (define_insn "subhi3" ! 814: [(set (match_operand:HI 0 "general_operand" "=g") ! 815: (minus:HI (match_operand:HI 1 "general_operand" "0") ! 816: (match_operand:HI 2 "general_operand" "g")))] ! 817: "" ! 818: "* ! 819: { if (GET_CODE (operands[2]) == CONST_INT) ! 820: { ! 821: int i = INTVAL (operands[2]); ! 822: ! 823: if (i <= 8 && i >= -7) ! 824: return \"addqw %$%n2,%0\"; ! 825: } ! 826: return \"subw %2,%0\"; ! 827: }") ! 828: ! 829: (define_insn "" ! 830: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r")) ! 831: (minus:HI (match_operand:HI 1 "general_operand" "0") ! 832: (match_operand:HI 2 "general_operand" "g")))] ! 833: "" ! 834: "* ! 835: { ! 836: if (GET_CODE (operands[1]) == CONST_INT ! 837: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9) ! 838: return \"addqw %$%n1,%0\"; ! 839: return \"subw %1,%0\"; ! 840: }") ! 841: ! 842: (define_insn "subqi3" ! 843: [(set (match_operand:QI 0 "general_operand" "=g") ! 844: (minus:QI (match_operand:QI 1 "general_operand" "0") ! 845: (match_operand:QI 2 "general_operand" "g")))] ! 846: "" ! 847: "* ! 848: { if (GET_CODE (operands[2]) == CONST_INT) ! 849: { ! 850: int i = INTVAL (operands[2]); ! 851: ! 852: if (i <= 8 && i >= -7) ! 853: return \"addqb %$%n2,%0\"; ! 854: } ! 855: return \"subb %2,%0\"; ! 856: }") ! 857: ! 858: (define_insn "" ! 859: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r")) ! 860: (minus:QI (match_operand:QI 1 "general_operand" "0") ! 861: (match_operand:QI 2 "general_operand" "g")))] ! 862: "" ! 863: "* ! 864: { ! 865: if (GET_CODE (operands[1]) == CONST_INT ! 866: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9) ! 867: return \"addqb %$%n1,%0\"; ! 868: return \"subb %1,%0\"; ! 869: }") ! 870: ! 871: ;;- Multiply instructions. ! 872: ! 873: (define_insn "muldf3" ! 874: [(set (match_operand:DF 0 "general_operand" "=fm") ! 875: (mult:DF (match_operand:DF 1 "general_operand" "%0") ! 876: (match_operand:DF 2 "general_operand" "fmF")))] ! 877: "TARGET_32081" ! 878: "mull %2,%0") ! 879: ! 880: (define_insn "mulsf3" ! 881: [(set (match_operand:SF 0 "general_operand" "=fm") ! 882: (mult:SF (match_operand:SF 1 "general_operand" "%0") ! 883: (match_operand:SF 2 "general_operand" "fmF")))] ! 884: "TARGET_32081" ! 885: "mulf %2,%0") ! 886: ! 887: (define_insn "mulsi3" ! 888: [(set (match_operand:SI 0 "general_operand" "=g") ! 889: (mult:SI (match_operand:SI 1 "general_operand" "%0") ! 890: (match_operand:SI 2 "general_operand" "rmn")))] ! 891: "" ! 892: "muld %2,%0") ! 893: ! 894: (define_insn "mulhi3" ! 895: [(set (match_operand:HI 0 "general_operand" "=g") ! 896: (mult:HI (match_operand:HI 1 "general_operand" "%0") ! 897: (match_operand:HI 2 "general_operand" "g")))] ! 898: "" ! 899: "mulw %2,%0") ! 900: ! 901: (define_insn "mulqi3" ! 902: [(set (match_operand:QI 0 "general_operand" "=g") ! 903: (mult:QI (match_operand:QI 1 "general_operand" "%0") ! 904: (match_operand:QI 2 "general_operand" "g")))] ! 905: "" ! 906: "mulb %2,%0") ! 907: ! 908: (define_insn "umulsi3" ! 909: [(set (match_operand:SI 0 "general_operand" "=g") ! 910: (umult:SI (match_operand:SI 1 "general_operand" "%0") ! 911: (match_operand:SI 2 "general_operand" "rmn")))] ! 912: "" ! 913: "muld %2,%0") ! 914: ! 915: (define_insn "umulhi3" ! 916: [(set (match_operand:HI 0 "general_operand" "=g") ! 917: (umult:HI (match_operand:HI 1 "general_operand" "%0") ! 918: (match_operand:HI 2 "general_operand" "g")))] ! 919: "" ! 920: "mulw %2,%0") ! 921: ! 922: (define_insn "umulqi3" ! 923: [(set (match_operand:QI 0 "general_operand" "=g") ! 924: (umult:QI (match_operand:QI 1 "general_operand" "%0") ! 925: (match_operand:QI 2 "general_operand" "g")))] ! 926: "" ! 927: "mulb %2,%0") ! 928: ! 929: (define_insn "umulsidi3" ! 930: [(set (match_operand:DI 0 "general_operand" "=g") ! 931: (umult:DI (match_operand:SI 1 "general_operand" "0") ! 932: (match_operand:SI 2 "general_operand" "rmn")))] ! 933: "" ! 934: "meid %2,%0") ! 935: ! 936: ;;- Divide instructions. ! 937: ! 938: (define_insn "divdf3" ! 939: [(set (match_operand:DF 0 "general_operand" "=fm") ! 940: (div:DF (match_operand:DF 1 "general_operand" "0") ! 941: (match_operand:DF 2 "general_operand" "fmF")))] ! 942: "TARGET_32081" ! 943: "divl %2,%0") ! 944: ! 945: (define_insn "divsf3" ! 946: [(set (match_operand:SF 0 "general_operand" "=fm") ! 947: (div:SF (match_operand:SF 1 "general_operand" "0") ! 948: (match_operand:SF 2 "general_operand" "fmF")))] ! 949: "TARGET_32081" ! 950: "divf %2,%0") ! 951: ! 952: (define_insn "divsi3" ! 953: [(set (match_operand:SI 0 "general_operand" "=g") ! 954: (div:SI (match_operand:SI 1 "general_operand" "0") ! 955: (match_operand:SI 2 "general_operand" "rmn")))] ! 956: "" ! 957: "quod %2,%0") ! 958: ! 959: (define_insn "divhi3" ! 960: [(set (match_operand:HI 0 "general_operand" "=g") ! 961: (div:HI (match_operand:HI 1 "general_operand" "0") ! 962: (match_operand:HI 2 "general_operand" "g")))] ! 963: "" ! 964: "quow %2,%0") ! 965: ! 966: (define_insn "divqi3" ! 967: [(set (match_operand:QI 0 "general_operand" "=g") ! 968: (div:QI (match_operand:QI 1 "general_operand" "0") ! 969: (match_operand:QI 2 "general_operand" "g")))] ! 970: "" ! 971: "quob %2,%0") ! 972: ! 973: (define_insn "udivsi3" ! 974: [(set (match_operand:SI 0 "register_operand" "=r") ! 975: (udiv:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) ! 976: (match_operand:SI 2 "general_operand" "rmn")))] ! 977: "" ! 978: "* ! 979: { ! 980: operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); ! 981: return \"deid %2,%0\;movd %1,%0\"; ! 982: }") ! 983: ! 984: (define_insn "udivhi3" ! 985: [(set (match_operand:HI 0 "register_operand" "=r") ! 986: (udiv:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) ! 987: (match_operand:HI 2 "general_operand" "g")))] ! 988: "" ! 989: "* ! 990: { ! 991: operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1); ! 992: return \"deiw %2,%0\;movw %1,%0\"; ! 993: }") ! 994: ! 995: (define_insn "udivqi3" ! 996: [(set (match_operand:QI 0 "register_operand" "=r") ! 997: (udiv:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) ! 998: (match_operand:QI 2 "general_operand" "g")))] ! 999: "" ! 1000: "* ! 1001: { ! 1002: operands[1] = gen_rtx (REG, QImode, REGNO (operands[0]) + 1); ! 1003: return \"deib %2,%0\;movb %1,%0\"; ! 1004: }") ! 1005: ! 1006: ;; Remainder instructions. ! 1007: ! 1008: (define_insn "modsi3" ! 1009: [(set (match_operand:SI 0 "general_operand" "=g") ! 1010: (mod:SI (match_operand:SI 1 "general_operand" "0") ! 1011: (match_operand:SI 2 "general_operand" "rmn")))] ! 1012: "" ! 1013: "remd %2,%0") ! 1014: ! 1015: (define_insn "modhi3" ! 1016: [(set (match_operand:HI 0 "general_operand" "=g") ! 1017: (mod:HI (match_operand:HI 1 "general_operand" "0") ! 1018: (match_operand:HI 2 "general_operand" "g")))] ! 1019: "" ! 1020: "remw %2,%0") ! 1021: ! 1022: (define_insn "modqi3" ! 1023: [(set (match_operand:QI 0 "general_operand" "=g") ! 1024: (mod:QI (match_operand:QI 1 "general_operand" "0") ! 1025: (match_operand:QI 2 "general_operand" "g")))] ! 1026: "" ! 1027: "remb %2,%0") ! 1028: ! 1029: (define_insn "umodsi3" ! 1030: [(set (match_operand:SI 0 "register_operand" "=r") ! 1031: (umod:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) ! 1032: (match_operand:SI 2 "general_operand" "rmn")))] ! 1033: "" ! 1034: "deid %2,%0") ! 1035: ! 1036: (define_insn "umodhi3" ! 1037: [(set (match_operand:HI 0 "register_operand" "=r") ! 1038: (umod:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) ! 1039: (match_operand:HI 2 "general_operand" "g")))] ! 1040: "" ! 1041: "deiw %2,%0") ! 1042: ! 1043: (define_insn "umodqi3" ! 1044: [(set (match_operand:QI 0 "register_operand" "=r") ! 1045: (umod:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) ! 1046: (match_operand:QI 2 "general_operand" "g")))] ! 1047: "" ! 1048: "deib %2,%0") ! 1049: ! 1050: ; This isn't be usable in its current form. ! 1051: ;(define_insn "udivmoddisi4" ! 1052: ; [(set (subreg:SI (match_operand:DI 0 "general_operand" "=r") 1) ! 1053: ; (udiv:SI (match_operand:DI 1 "general_operand" "0") ! 1054: ; (match_operand:SI 2 "general_operand" "rmn"))) ! 1055: ; (set (subreg:SI (match_dup 0) 0) ! 1056: ; (umod:SI (match_dup 1) (match_dup 2)))] ! 1057: ; "" ! 1058: ; "deid %2,%0") ! 1059: ! 1060: ;;- Logical Instructions: AND ! 1061: ! 1062: (define_insn "andsi3" ! 1063: [(set (match_operand:SI 0 "general_operand" "=g") ! 1064: (and:SI (match_operand:SI 1 "general_operand" "%0") ! 1065: (match_operand:SI 2 "general_operand" "rmn")))] ! 1066: "" ! 1067: "* ! 1068: { ! 1069: if (GET_CODE (operands[2]) == CONST_INT) { ! 1070: if ((INTVAL (operands[2]) | 0xff) == 0xffffffff) ! 1071: if (INTVAL (operands[2]) == 0xffffff00) ! 1072: return \"movqb %$0,%0\"; ! 1073: else { ! 1074: INTVAL (operands[2]) &= 0xff; ! 1075: return \"andb %2,%0\"; ! 1076: } ! 1077: if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff) ! 1078: if (INTVAL (operands[2]) == 0xffff0000) ! 1079: return \"movqw %$0,%0\"; ! 1080: else { ! 1081: INTVAL (operands[2]) &= 0xffff; ! 1082: return \"andw %2,%0\"; ! 1083: } ! 1084: } ! 1085: return \"andd %2,%0\"; ! 1086: }") ! 1087: ! 1088: (define_insn "andhi3" ! 1089: [(set (match_operand:HI 0 "general_operand" "=g") ! 1090: (and:HI (match_operand:HI 1 "general_operand" "%0") ! 1091: (match_operand:HI 2 "general_operand" "g")))] ! 1092: "" ! 1093: "* ! 1094: { ! 1095: if (GET_CODE (operands[2]) == CONST_INT ! 1096: && (INTVAL (operands[2]) | 0xff) == 0xffffffff) ! 1097: if (INTVAL (operands[2]) == 0xffffff00) ! 1098: return \"movqb %$0,%0\"; ! 1099: else { ! 1100: INTVAL (operands[2]) &= 0xff; ! 1101: return \"andb %2,%0\"; ! 1102: } ! 1103: return \"andw %2,%0\"; ! 1104: }") ! 1105: ! 1106: (define_insn "andqi3" ! 1107: [(set (match_operand:QI 0 "general_operand" "=g") ! 1108: (and:QI (match_operand:QI 1 "general_operand" "%0") ! 1109: (match_operand:QI 2 "general_operand" "g")))] ! 1110: "" ! 1111: "andb %2,%0") ! 1112: ! 1113: (define_insn "andcbsi3" ! 1114: [(set (match_operand:SI 0 "general_operand" "=g") ! 1115: (and:SI (match_operand:SI 1 "general_operand" "0") ! 1116: (not:SI (match_operand:SI 2 "general_operand" "rmn"))))] ! 1117: "" ! 1118: "* ! 1119: { ! 1120: if (GET_CODE (operands[2]) == CONST_INT) ! 1121: { ! 1122: if ((INTVAL (operands[2]) & 0xffffff00) == 0) ! 1123: return \"bicb %2,%0\"; ! 1124: if ((INTVAL (operands[2]) & 0xffff0000) == 0) ! 1125: return \"bicw %2,%0\"; ! 1126: } ! 1127: return \"bicd %2,%0\"; ! 1128: }") ! 1129: ! 1130: (define_insn "" ! 1131: [(set (match_operand:SI 0 "general_operand" "=g") ! 1132: (and:SI (not:SI (match_operand:SI 1 "general_operand" "rmn")) ! 1133: (match_operand:SI 2 "general_operand" "0")))] ! 1134: "" ! 1135: "* ! 1136: { ! 1137: if (GET_CODE (operands[1]) == CONST_INT) ! 1138: { ! 1139: if ((INTVAL (operands[1]) & 0xffffff00) == 0) ! 1140: return \"bicb %1,%0\"; ! 1141: if ((INTVAL (operands[1]) & 0xffff0000) == 0) ! 1142: return \"bicw %1,%0\"; ! 1143: } ! 1144: return \"bicd %1,%0\"; ! 1145: }") ! 1146: ! 1147: (define_insn "andcbhi3" ! 1148: [(set (match_operand:HI 0 "general_operand" "=g") ! 1149: (and:HI (match_operand:HI 1 "general_operand" "%0") ! 1150: (not:HI (match_operand:HI 2 "general_operand" "g"))))] ! 1151: "" ! 1152: "* ! 1153: { ! 1154: if (GET_CODE (operands[2]) == CONST_INT ! 1155: && (INTVAL (operands[2]) & 0xffffff00) == 0) ! 1156: return \"bicb %2,%0\"; ! 1157: return \"bicw %2,%0\"; ! 1158: }") ! 1159: ! 1160: (define_insn "" ! 1161: [(set (match_operand:HI 0 "general_operand" "=g") ! 1162: (and:HI (not:HI (match_operand:HI 1 "general_operand" "g")) ! 1163: (match_operand:HI 2 "general_operand" "0")))] ! 1164: "" ! 1165: "* ! 1166: { ! 1167: if (GET_CODE (operands[1]) == CONST_INT ! 1168: && (INTVAL (operands[1]) & 0xffffff00) == 0) ! 1169: return \"bicb %1,%0\"; ! 1170: return \"bicw %1,%0\"; ! 1171: }") ! 1172: ! 1173: (define_insn "andcbqi3" ! 1174: [(set (match_operand:QI 0 "general_operand" "=g") ! 1175: (and:QI (match_operand:QI 1 "general_operand" "%0") ! 1176: (not:QI (match_operand:QI 2 "general_operand" "g"))))] ! 1177: "" ! 1178: "bicb %2,%0") ! 1179: ! 1180: (define_insn "" ! 1181: [(set (match_operand:QI 0 "general_operand" "=g") ! 1182: (and:QI (not:QI (match_operand:QI 1 "general_operand" "g")) ! 1183: (match_operand:QI 2 "general_operand" "0")))] ! 1184: "" ! 1185: "bicb %1,%0") ! 1186: ! 1187: ;;- Bit set instructions. ! 1188: ! 1189: (define_insn "iorsi3" ! 1190: [(set (match_operand:SI 0 "general_operand" "=g") ! 1191: (ior:SI (match_operand:SI 1 "general_operand" "%0") ! 1192: (match_operand:SI 2 "general_operand" "rmn")))] ! 1193: "" ! 1194: "* ! 1195: { ! 1196: if (GET_CODE (operands[2]) == CONST_INT) { ! 1197: if ((INTVAL (operands[2]) & 0xffffff00) == 0) ! 1198: return \"orb %2,%0\"; ! 1199: if ((INTVAL (operands[2]) & 0xffff0000) == 0) ! 1200: return \"orw %2,%0\"; ! 1201: } ! 1202: return \"ord %2,%0\"; ! 1203: }") ! 1204: ! 1205: (define_insn "iorhi3" ! 1206: [(set (match_operand:HI 0 "general_operand" "=g") ! 1207: (ior:HI (match_operand:HI 1 "general_operand" "%0") ! 1208: (match_operand:HI 2 "general_operand" "g")))] ! 1209: "" ! 1210: "* ! 1211: { ! 1212: if (GET_CODE(operands[2]) == CONST_INT && ! 1213: (INTVAL(operands[2]) & 0xffffff00) == 0) ! 1214: return \"orb %2,%0\"; ! 1215: return \"orw %2,%0\"; ! 1216: }") ! 1217: ! 1218: (define_insn "iorqi3" ! 1219: [(set (match_operand:QI 0 "general_operand" "=g") ! 1220: (ior:QI (match_operand:QI 1 "general_operand" "%0") ! 1221: (match_operand:QI 2 "general_operand" "g")))] ! 1222: "" ! 1223: "orb %2,%0") ! 1224: ! 1225: ;;- xor instructions. ! 1226: ! 1227: (define_insn "xorsi3" ! 1228: [(set (match_operand:SI 0 "general_operand" "=g") ! 1229: (xor:SI (match_operand:SI 1 "general_operand" "%0") ! 1230: (match_operand:SI 2 "general_operand" "rmn")))] ! 1231: "" ! 1232: "* ! 1233: { ! 1234: if (GET_CODE (operands[2]) == CONST_INT) { ! 1235: if ((INTVAL (operands[2]) & 0xffffff00) == 0) ! 1236: return \"xorb %2,%0\"; ! 1237: if ((INTVAL (operands[2]) & 0xffff0000) == 0) ! 1238: return \"xorw %2,%0\"; ! 1239: } ! 1240: return \"xord %2,%0\"; ! 1241: }") ! 1242: ! 1243: (define_insn "xorhi3" ! 1244: [(set (match_operand:HI 0 "general_operand" "=g") ! 1245: (xor:HI (match_operand:HI 1 "general_operand" "%0") ! 1246: (match_operand:HI 2 "general_operand" "g")))] ! 1247: "" ! 1248: "* ! 1249: { ! 1250: if (GET_CODE(operands[2]) == CONST_INT && ! 1251: (INTVAL(operands[2]) & 0xffffff00) == 0) ! 1252: return \"xorb %2,%0\"; ! 1253: return \"xorw %2,%0\"; ! 1254: }") ! 1255: ! 1256: (define_insn "xorqi3" ! 1257: [(set (match_operand:QI 0 "general_operand" "=g") ! 1258: (xor:QI (match_operand:QI 1 "general_operand" "%0") ! 1259: (match_operand:QI 2 "general_operand" "g")))] ! 1260: "" ! 1261: "xorb %2,%0") ! 1262: ! 1263: (define_insn "negdf2" ! 1264: [(set (match_operand:DF 0 "general_operand" "=fm<") ! 1265: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))] ! 1266: "TARGET_32081" ! 1267: "negl %1,%0") ! 1268: ! 1269: (define_insn "negsf2" ! 1270: [(set (match_operand:SF 0 "general_operand" "=fm<") ! 1271: (neg:SF (match_operand:SF 1 "general_operand" "fmF")))] ! 1272: "TARGET_32081" ! 1273: "negf %1,%0") ! 1274: ! 1275: (define_insn "negsi2" ! 1276: [(set (match_operand:SI 0 "general_operand" "=g<") ! 1277: (neg:SI (match_operand:SI 1 "general_operand" "rmn")))] ! 1278: "" ! 1279: "negd %1,%0") ! 1280: ! 1281: (define_insn "neghi2" ! 1282: [(set (match_operand:HI 0 "general_operand" "=g<") ! 1283: (neg:HI (match_operand:HI 1 "general_operand" "g")))] ! 1284: "" ! 1285: "negw %1,%0") ! 1286: ! 1287: (define_insn "negqi2" ! 1288: [(set (match_operand:QI 0 "general_operand" "=g<") ! 1289: (neg:QI (match_operand:QI 1 "general_operand" "g")))] ! 1290: "" ! 1291: "negb %1,%0") ! 1292: ! 1293: (define_insn "one_cmplsi2" ! 1294: [(set (match_operand:SI 0 "general_operand" "=g<") ! 1295: (not:SI (match_operand:SI 1 "general_operand" "rmn")))] ! 1296: "" ! 1297: "comd %1,%0") ! 1298: ! 1299: (define_insn "one_cmplhi2" ! 1300: [(set (match_operand:HI 0 "general_operand" "=g<") ! 1301: (not:HI (match_operand:HI 1 "general_operand" "g")))] ! 1302: "" ! 1303: "comw %1,%0") ! 1304: ! 1305: (define_insn "one_cmplqi2" ! 1306: [(set (match_operand:QI 0 "general_operand" "=g<") ! 1307: (not:QI (match_operand:QI 1 "general_operand" "g")))] ! 1308: "" ! 1309: "comb %1,%0") ! 1310: ! 1311: ;; arithmetic left and right shift operations ! 1312: ! 1313: (define_insn "ashlsi3" ! 1314: [(set (match_operand:SI 0 "general_operand" "=g,g") ! 1315: (ashift:SI (match_operand:SI 1 "general_operand" "r,0") ! 1316: (match_operand:SI 2 "general_operand" "I,rmn")))] ! 1317: "" ! 1318: "* output_shift_insn (operands);") ! 1319: ! 1320: (define_insn "" ! 1321: [(set (match_operand:SI 0 "general_operand" "=g") ! 1322: (ashift:SI (match_operand:SI 1 "general_operand" "0") ! 1323: (and:SI (match_operand:SI 2 "general_operand" "rmn") ! 1324: (const_int 31))))] ! 1325: "" ! 1326: "ashd %2,%0") ! 1327: ! 1328: (define_insn "ashlhi3" ! 1329: [(set (match_operand:HI 0 "general_operand" "=g") ! 1330: (ashift:HI (match_operand:HI 1 "general_operand" "0") ! 1331: (match_operand:SI 2 "general_operand" "rmn")))] ! 1332: "" ! 1333: "* ! 1334: { if (GET_CODE (operands[2]) == CONST_INT) ! 1335: if (INTVAL (operands[2]) == 1) ! 1336: return \"addw %1,%0\"; ! 1337: else if (INTVAL (operands[2]) == 2) ! 1338: return \"addw %1,%0\;addw %0,%0\"; ! 1339: return \"ashw %2,%0\"; ! 1340: }") ! 1341: ! 1342: (define_insn "ashlqi3" ! 1343: [(set (match_operand:QI 0 "general_operand" "=g") ! 1344: (ashift:QI (match_operand:QI 1 "general_operand" "0") ! 1345: (match_operand:SI 2 "general_operand" "rmn")))] ! 1346: "" ! 1347: "* ! 1348: { if (GET_CODE (operands[2]) == CONST_INT) ! 1349: if (INTVAL (operands[2]) == 1) ! 1350: return \"addb %1,%0\"; ! 1351: else if (INTVAL (operands[2]) == 2) ! 1352: return \"addb %1,%0\;addb %0,%0\"; ! 1353: return \"ashb %2,%0\"; ! 1354: }") ! 1355: ! 1356: ;; logical shift instructions ! 1357: ! 1358: (define_insn "lshlsi3" ! 1359: [(set (match_operand:SI 0 "general_operand" "=g") ! 1360: (lshift:SI (match_operand:SI 1 "general_operand" "0") ! 1361: (match_operand:SI 2 "general_operand" "rmn")))] ! 1362: "" ! 1363: "lshd %2,%0") ! 1364: ! 1365: (define_insn "" ! 1366: [(set (match_operand:SI 0 "general_operand" "=g") ! 1367: (lshift:SI (match_operand:SI 1 "general_operand" "0") ! 1368: (and:SI (match_operand:SI 2 "general_operand" "rmn") ! 1369: (const_int 31))))] ! 1370: "" ! 1371: "lshd %2,%0") ! 1372: ! 1373: (define_insn "lshlhi3" ! 1374: [(set (match_operand:HI 0 "general_operand" "=g") ! 1375: (lshift:HI (match_operand:HI 1 "general_operand" "0") ! 1376: (match_operand:SI 2 "general_operand" "rmn")))] ! 1377: "" ! 1378: "lshw %2,%0") ! 1379: ! 1380: (define_insn "lshlqi3" ! 1381: [(set (match_operand:QI 0 "general_operand" "=g") ! 1382: (lshift:QI (match_operand:QI 1 "general_operand" "0") ! 1383: (match_operand:SI 2 "general_operand" "rmn")))] ! 1384: "" ! 1385: "lshb %2,%0") ! 1386: ! 1387: ;; Rotate instructions ! 1388: ! 1389: (define_insn "rotlsi3" ! 1390: [(set (match_operand:SI 0 "general_operand" "=g") ! 1391: (rotate:SI (match_operand:SI 1 "general_operand" "0") ! 1392: (match_operand:SI 2 "general_operand" "rmn")))] ! 1393: "" ! 1394: "rotd %2,%0") ! 1395: ! 1396: (define_insn "rotlhi3" ! 1397: [(set (match_operand:HI 0 "general_operand" "=g") ! 1398: (rotate:HI (match_operand:HI 1 "general_operand" "0") ! 1399: (match_operand:SI 2 "general_operand" "rmn")))] ! 1400: "" ! 1401: "rotw %2,%0") ! 1402: ! 1403: (define_insn "rotlqi3" ! 1404: [(set (match_operand:QI 0 "general_operand" "=g") ! 1405: (rotate:QI (match_operand:QI 1 "general_operand" "0") ! 1406: (match_operand:SI 2 "general_operand" "rmn")))] ! 1407: "" ! 1408: "rotb %2,%0") ! 1409: ! 1410: ;;- load or push effective address ! 1411: ;; These come after the move, add, and multiply patterns ! 1412: ;; because we don't want pushl $1 turned into pushad 1. ! 1413: ! 1414: (define_insn "" ! 1415: [(set (match_operand:SI 0 "general_operand" "=g<") ! 1416: (match_operand:QI 1 "address_operand" "p"))] ! 1417: "" ! 1418: "* ! 1419: { ! 1420: if (REG_P (operands[0]) ! 1421: && GET_CODE (operands[1]) == MULT ! 1422: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT ! 1423: && (INTVAL (XEXP (operands[1], 1)) == 2 ! 1424: || INTVAL (XEXP (operands[1], 1)) == 4)) ! 1425: { ! 1426: rtx xoperands[3]; ! 1427: xoperands[0] = operands[0]; ! 1428: xoperands[1] = XEXP (operands[1], 0); ! 1429: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1); ! 1430: return output_shift_insn (xoperands); ! 1431: } ! 1432: return \"addr %a1,%0\"; ! 1433: }") ! 1434: ! 1435: ;;; Index insns. These are about the same speed as multiply-add counterparts. ! 1436: ;;; but slower then using power-of-2 shifts if we can use them ! 1437: ; ! 1438: ;(define_insn "" ! 1439: ; [(set (match_operand:SI 0 "register_operand" "=r") ! 1440: ; (plus:SI (match_operand:SI 1 "general_operand" "rmn") ! 1441: ; (mult:SI (match_operand:SI 2 "register_operand" "0") ! 1442: ; (plus:SI (match_operand:SI 3 "general_operand" "rmn") (const_int 1)))))] ! 1443: ; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8" ! 1444: ; "indexd %0,%3,%1") ! 1445: ; ! 1446: ;(define_insn "" ! 1447: ; [(set (match_operand:SI 0 "register_operand" "=r") ! 1448: ; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0") ! 1449: ; (plus:SI (match_operand:SI 2 "general_operand" "rmn") (const_int 1))) ! 1450: ; (match_operand:SI 3 "general_operand" "rmn")))] ! 1451: ; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8" ! 1452: ; "indexd %0,%2,%3") ! 1453: ! 1454: ;; Set, Clear, and Invert bit ! 1455: ! 1456: (define_insn "" ! 1457: [(set (match_operand:SI 0 "general_operand" "=g") ! 1458: (ior:SI ! 1459: (ashift:SI (const_int 1) ! 1460: (match_operand:SI 1 "general_operand" "rmn")) ! 1461: (match_dup 0)))] ! 1462: "" ! 1463: "sbitd %1,%0") ! 1464: ! 1465: (define_insn "" ! 1466: [(set (match_operand:SI 0 "general_operand" "=g") ! 1467: (ior:SI ! 1468: (match_dup 0) ! 1469: (ashift:SI (const_int 1) ! 1470: (match_operand:SI 1 "general_operand" "rmn"))))] ! 1471: "" ! 1472: "sbitd %1,%0") ! 1473: ! 1474: (define_insn "" ! 1475: [(set (match_operand:QI 0 "general_operand" "=g") ! 1476: (ior:QI ! 1477: (subreg:QI ! 1478: (ashift:SI (const_int 1) ! 1479: (match_operand:QI 1 "general_operand" "rmn")) 0) ! 1480: (match_dup 0)))] ! 1481: "" ! 1482: "sbitb %1,%0") ! 1483: ! 1484: (define_insn "" ! 1485: [(set (match_operand:QI 0 "general_operand" "=g") ! 1486: (ior:QI ! 1487: (match_dup 0) ! 1488: (subreg:QI ! 1489: (ashift:SI (const_int 1) ! 1490: (match_operand:QI 1 "general_operand" "rmn")) 0)))] ! 1491: "" ! 1492: "sbitb %1,%0") ! 1493: ! 1494: (define_insn "" ! 1495: [(set (match_operand:SI 0 "general_operand" "=g") ! 1496: (and:SI ! 1497: (not:SI ! 1498: (ashift:SI (const_int 1) ! 1499: (match_operand:SI 1 "general_operand" "rmn"))) ! 1500: (match_dup 0)))] ! 1501: "" ! 1502: "cbitd %1,%0") ! 1503: ! 1504: (define_insn "" ! 1505: [(set (match_operand:SI 0 "general_operand" "=g") ! 1506: (and:SI ! 1507: (match_dup 0) ! 1508: (not:SI ! 1509: (ashift:SI (const_int 1) ! 1510: (match_operand:SI 1 "general_operand" "rmn")))))] ! 1511: "" ! 1512: "cbitd %1,%0") ! 1513: ! 1514: (define_insn "" ! 1515: [(set (match_operand:QI 0 "general_operand" "=g") ! 1516: (and:QI ! 1517: (subreg:QI ! 1518: (not:SI ! 1519: (ashift:SI (const_int 1) ! 1520: (match_operand:QI 1 "general_operand" "rmn"))) 0) ! 1521: (match_dup 0)))] ! 1522: "" ! 1523: "cbitb %1,%0") ! 1524: ! 1525: (define_insn "" ! 1526: [(set (match_operand:QI 0 "general_operand" "=g") ! 1527: (and:QI ! 1528: (match_dup 0) ! 1529: (subreg:QI ! 1530: (not:SI ! 1531: (ashift:SI (const_int 1) ! 1532: (match_operand:QI 1 "general_operand" "rmn"))) 0)))] ! 1533: "" ! 1534: "cbitb %1,%0") ! 1535: ! 1536: (define_insn "" ! 1537: [(set (match_operand:SI 0 "general_operand" "=g") ! 1538: (xor:SI ! 1539: (ashift:SI (const_int 1) ! 1540: (match_operand:SI 1 "general_operand" "rmn")) ! 1541: (match_dup 0)))] ! 1542: "" ! 1543: "ibitd %1,%0") ! 1544: ! 1545: (define_insn "" ! 1546: [(set (match_operand:SI 0 "general_operand" "=g") ! 1547: (xor:SI ! 1548: (match_dup 0) ! 1549: (ashift:SI (const_int 1) ! 1550: (match_operand:SI 1 "general_operand" "rmn"))))] ! 1551: "" ! 1552: "ibitd %1,%0") ! 1553: ! 1554: (define_insn "" ! 1555: [(set (match_operand:QI 0 "general_operand" "=g") ! 1556: (xor:QI ! 1557: (subreg:QI ! 1558: (ashift:SI (const_int 1) ! 1559: (match_operand:QI 1 "general_operand" "rmn")) 0) ! 1560: (match_dup 0)))] ! 1561: "" ! 1562: "ibitb %1,%0") ! 1563: ! 1564: (define_insn "" ! 1565: [(set (match_operand:QI 0 "general_operand" "=g") ! 1566: (xor:QI ! 1567: (match_dup 0) ! 1568: (subreg:QI ! 1569: (ashift:SI (const_int 1) ! 1570: (match_operand:QI 1 "general_operand" "rmn")) 0)))] ! 1571: "" ! 1572: "ibitb %1,%0") ! 1573: ! 1574: ;; Recognize jbs and jbc instructions. ! 1575: ! 1576: (define_insn "" ! 1577: [(set (cc0) ! 1578: (zero_extract (match_operand:SI 0 "general_operand" "rmn") ! 1579: (const_int 1) ! 1580: (match_operand:SI 1 "general_operand" "rmn")))] ! 1581: "" ! 1582: "* ! 1583: { cc_status.flags = CC_Z_IN_F; ! 1584: return \"tbitd %1,%0\"; ! 1585: }") ! 1586: ! 1587: (define_insn "" ! 1588: [(set (cc0) ! 1589: (minus (zero_extract (match_operand:SI 0 "general_operand" "rmn") ! 1590: (const_int 1) ! 1591: (match_operand:SI 1 "general_operand" "rmn")) ! 1592: (const_int 1)))] ! 1593: "" ! 1594: "* ! 1595: { cc_status.flags = CC_Z_IN_NOT_F; ! 1596: return \"tbitd %1,%0\"; ! 1597: }") ! 1598: ! 1599: (define_insn "" ! 1600: [(set (cc0) ! 1601: (zero_extract (match_operand:HI 0 "general_operand" "g") ! 1602: (const_int 1) ! 1603: (match_operand:HI 1 "general_operand" "g")))] ! 1604: "" ! 1605: "* ! 1606: { cc_status.flags = CC_Z_IN_F; ! 1607: return \"tbitw %1,%0\"; ! 1608: }") ! 1609: ! 1610: (define_insn "" ! 1611: [(set (cc0) ! 1612: (minus (zero_extract (match_operand:HI 0 "general_operand" "g") ! 1613: (const_int 1) ! 1614: (match_operand:HI 1 "general_operand" "rmn")) ! 1615: (const_int 1)))] ! 1616: "" ! 1617: "* ! 1618: { cc_status.flags = CC_Z_IN_NOT_F; ! 1619: return \"tbitw %1,%0\"; ! 1620: }") ! 1621: ! 1622: (define_insn "" ! 1623: [(set (cc0) ! 1624: (zero_extract (match_operand:QI 0 "general_operand" "g") ! 1625: (const_int 1) ! 1626: (match_operand:QI 1 "general_operand" "g")))] ! 1627: "" ! 1628: "* ! 1629: { cc_status.flags = CC_Z_IN_F; ! 1630: return \"tbitb %1,%0\"; ! 1631: }") ! 1632: ! 1633: (define_insn "" ! 1634: [(set (cc0) ! 1635: (minus (zero_extract:SI (match_operand:QI 0 "general_operand" "g") ! 1636: (const_int 1) ! 1637: (match_operand:QI 1 "general_operand" "rmn")) ! 1638: (const_int 1)))] ! 1639: "" ! 1640: "* ! 1641: { cc_status.flags = CC_Z_IN_NOT_F; ! 1642: return \"tbitb %1,%0\"; ! 1643: }") ! 1644: ! 1645: (define_insn "" ! 1646: [(set (cc0) ! 1647: (and:SI (match_operand:SI 0 "general_operand" "rmn") ! 1648: (match_operand:SI 1 "immediate_operand" "i")))] ! 1649: "GET_CODE (operands[1]) == CONST_INT ! 1650: && exact_log2 (INTVAL (operands[1])) >= 0" ! 1651: "* ! 1652: { ! 1653: operands[1] ! 1654: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1]))); ! 1655: cc_status.flags = CC_Z_IN_F; ! 1656: return \"tbitd %1,%0\"; ! 1657: }") ! 1658: ! 1659: ;; extract(base, width, offset) ! 1660: ;; Signed bitfield extraction is not supported in hardware on the ! 1661: ;; NS 32032. It is therefore better to let GCC figure out a ! 1662: ;; good strategy for generating the proper instruction sequence ! 1663: ;; and represent it as rtl. ! 1664: ! 1665: ;; Optimize the case of extracting a byte or word from a register. ! 1666: ;; Otherwise we must load a register with the offset of the ! 1667: ;; chunk we want, and perform an extract insn (each of which ! 1668: ;; is very expensive). Since we use the stack to do our bit-twiddling ! 1669: ;; we cannot use it for a destination. Perhaps things are fast ! 1670: ;; enough on the 32532 that such hacks are not needed. ! 1671: ! 1672: (define_insn "" ! 1673: [(set (match_operand:SI 0 "general_operand" "=ro") ! 1674: (zero_extract:SI (match_operand:SI 1 "register_operand" "r") ! 1675: (match_operand:SI 2 "const_int" "i") ! 1676: (match_operand:SI 3 "const_int" "i")))] ! 1677: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) ! 1678: && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)" ! 1679: "* ! 1680: { ! 1681: output_asm_insn (\"movd %1,tos\", operands); ! 1682: if (INTVAL (operands[2]) == 16) ! 1683: { ! 1684: if (INTVAL (operands[3]) == 8) ! 1685: output_asm_insn (\"movzwd 1(sp),%0\", operands); ! 1686: else ! 1687: output_asm_insn (\"movzwd 2(sp),%0\", operands); ! 1688: } ! 1689: else ! 1690: { ! 1691: if (INTVAL (operands[3]) == 8) ! 1692: output_asm_insn (\"movzbd 1(sp),%0\", operands); ! 1693: else if (INTVAL (operands[3]) == 16) ! 1694: output_asm_insn (\"movzbd 2(sp),%0\", operands); ! 1695: else ! 1696: output_asm_insn (\"movzbd 3(sp),%0\", operands); ! 1697: } ! 1698: return \"adjspb %$-4\"; ! 1699: }") ! 1700: ! 1701: (define_insn "" ! 1702: [(set (match_operand:SI 0 "general_operand" "=ro") ! 1703: (zero_extract:SI (match_operand:HI 1 "register_operand" "r") ! 1704: (match_operand:SI 2 "const_int" "i") ! 1705: (match_operand:SI 3 "const_int" "i")))] ! 1706: "INTVAL (operands[2]) == 8 && INTVAL (operands[3]) == 8" ! 1707: "movw %1,tos\;movzbd 1(sp),%0\;adjspb %$-2") ! 1708: ! 1709: (define_insn "extzv" ! 1710: [(set (match_operand:SI 0 "general_operand" "=g<,g<") ! 1711: (zero_extract:SI (match_operand:SI 1 "general_operand" "rm,o") ! 1712: (match_operand:SI 2 "const_int" "i,i") ! 1713: (match_operand:SI 3 "general_operand" "rK,n")))] ! 1714: "" ! 1715: "* ! 1716: { if (GET_CODE (operands[3]) == CONST_INT) ! 1717: { ! 1718: if (INTVAL (operands[3]) >= 8) ! 1719: operands[1] = plus_constant (operands[1], INTVAL (operands[3]) >> 3); ! 1720: return \"extsd %1,%0,%3,%2\"; ! 1721: } ! 1722: else return \"extd %3,%1,%0,%2\"; ! 1723: }") ! 1724: ! 1725: (define_insn "" ! 1726: [(set (match_operand:SI 0 "general_operand" "=g<,g<") ! 1727: (zero_extract:SI (match_operand:HI 1 "general_operand" "rm,o") ! 1728: (match_operand:SI 2 "const_int" "i,i") ! 1729: (match_operand:SI 3 "general_operand" "rK,n")))] ! 1730: "" ! 1731: "* ! 1732: { if (GET_CODE (operands[3]) == CONST_INT) ! 1733: { ! 1734: if (INTVAL (operands[3]) >= 8) ! 1735: operands[1] = plus_constant (operands[1], INTVAL (operands[3]) >> 3); ! 1736: return \"extsd %1,%0,%3,%2\"; ! 1737: } ! 1738: else return \"extd %3,%1,%0,%2\"; ! 1739: }") ! 1740: ! 1741: (define_insn "" ! 1742: [(set (match_operand:SI 0 "general_operand" "=g<") ! 1743: (zero_extract:SI (match_operand:QI 1 "general_operand" "g") ! 1744: (match_operand:SI 2 "const_int" "i") ! 1745: (match_operand:SI 3 "general_operand" "rn")))] ! 1746: "" ! 1747: "* ! 1748: { if (GET_CODE (operands[3]) == CONST_INT) ! 1749: return \"extsd %1,%0,%3,%2\"; ! 1750: else return \"extd %3,%1,%0,%2\"; ! 1751: }") ! 1752: ! 1753: (define_insn "insv" ! 1754: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "=g,o") ! 1755: (match_operand:SI 1 "const_int" "i,i") ! 1756: (match_operand:SI 2 "general_operand" "rK,n")) ! 1757: (match_operand:SI 3 "general_operand" "rm,rm"))] ! 1758: "" ! 1759: "* ! 1760: { if (GET_CODE (operands[2]) == CONST_INT) ! 1761: { ! 1762: if (INTVAL (operands[2]) >= 8) ! 1763: operands[0] = plus_constant (operands[0], INTVAL (operands[2]) >> 3); ! 1764: if (INTVAL (operands[1]) <= 8) ! 1765: return \"inssb %3,%0,%2,%1\"; ! 1766: else if (INTVAL (operands[1]) <= 16) ! 1767: return \"inssw %3,%0,%2,%1\"; ! 1768: else ! 1769: return \"inssd %3,%0,%2,%1\"; ! 1770: } ! 1771: return \"insd %2,%3,%0,%1\"; ! 1772: }") ! 1773: ! 1774: (define_insn "" ! 1775: [(set (zero_extract:SI (match_operand:HI 0 "general_operand" "=g,o") ! 1776: (match_operand:SI 1 "const_int" "i,i") ! 1777: (match_operand:SI 2 "general_operand" "rK,n")) ! 1778: (match_operand:SI 3 "general_operand" "rm,rm"))] ! 1779: "" ! 1780: "* ! 1781: { if (GET_CODE (operands[2]) == CONST_INT) ! 1782: { ! 1783: if (INTVAL (operands[2]) >= 8) ! 1784: operands[0] = plus_constant (operands[0], INTVAL (operands[2]) >> 3); ! 1785: if (INTVAL (operands[1]) <= 8) ! 1786: return \"inssb %3,%0,%2,%1\"; ! 1787: else if (INTVAL (operands[1]) <= 16) ! 1788: return \"inssw %3,%0,%2,%1\"; ! 1789: else ! 1790: return \"inssd %3,%0,%2,%1\"; ! 1791: } ! 1792: return \"insd %2,%3,%0,%1\"; ! 1793: }") ! 1794: ! 1795: (define_insn "" ! 1796: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "=g") ! 1797: (match_operand:SI 1 "const_int" "i") ! 1798: (match_operand:SI 2 "general_operand" "rn")) ! 1799: (match_operand:SI 3 "general_operand" "rm"))] ! 1800: "" ! 1801: "* ! 1802: { if (GET_CODE (operands[2]) == CONST_INT) ! 1803: if (INTVAL (operands[1]) <= 8) ! 1804: return \"inssb %3,%0,%2,%1\"; ! 1805: else if (INTVAL (operands[1]) <= 16) ! 1806: return \"inssw %3,%0,%2,%1\"; ! 1807: else ! 1808: return \"inssd %3,%0,%2,%1\"; ! 1809: return \"insd %2,%3,%0,%1\"; ! 1810: }") ! 1811: ! 1812: ! 1813: (define_insn "jump" ! 1814: [(set (pc) ! 1815: (label_ref (match_operand 0 "" "")))] ! 1816: "" ! 1817: "br %l0") ! 1818: ! 1819: (define_insn "beq" ! 1820: [(set (pc) ! 1821: (if_then_else (eq (cc0) ! 1822: (const_int 0)) ! 1823: (label_ref (match_operand 0 "" "")) ! 1824: (pc)))] ! 1825: "" ! 1826: "* ! 1827: { if (cc_prev_status.flags & CC_Z_IN_F) ! 1828: return \"bfc %l0\"; ! 1829: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) ! 1830: return \"bfs %l0\"; ! 1831: else return \"beq %l0\"; ! 1832: }") ! 1833: ! 1834: (define_insn "bne" ! 1835: [(set (pc) ! 1836: (if_then_else (ne (cc0) ! 1837: (const_int 0)) ! 1838: (label_ref (match_operand 0 "" "")) ! 1839: (pc)))] ! 1840: "" ! 1841: "* ! 1842: { if (cc_prev_status.flags & CC_Z_IN_F) ! 1843: return \"bfs %l0\"; ! 1844: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) ! 1845: return \"bfc %l0\"; ! 1846: else return \"bne %l0\"; ! 1847: }") ! 1848: ! 1849: (define_insn "bgt" ! 1850: [(set (pc) ! 1851: (if_then_else (gt (cc0) ! 1852: (const_int 0)) ! 1853: (label_ref (match_operand 0 "" "")) ! 1854: (pc)))] ! 1855: "" ! 1856: "bgt %l0") ! 1857: ! 1858: (define_insn "bgtu" ! 1859: [(set (pc) ! 1860: (if_then_else (gtu (cc0) ! 1861: (const_int 0)) ! 1862: (label_ref (match_operand 0 "" "")) ! 1863: (pc)))] ! 1864: "" ! 1865: "bhi %l0") ! 1866: ! 1867: (define_insn "blt" ! 1868: [(set (pc) ! 1869: (if_then_else (lt (cc0) ! 1870: (const_int 0)) ! 1871: (label_ref (match_operand 0 "" "")) ! 1872: (pc)))] ! 1873: "" ! 1874: "blt %l0") ! 1875: ! 1876: (define_insn "bltu" ! 1877: [(set (pc) ! 1878: (if_then_else (ltu (cc0) ! 1879: (const_int 0)) ! 1880: (label_ref (match_operand 0 "" "")) ! 1881: (pc)))] ! 1882: "" ! 1883: "blo %l0") ! 1884: ! 1885: (define_insn "bge" ! 1886: [(set (pc) ! 1887: (if_then_else (ge (cc0) ! 1888: (const_int 0)) ! 1889: (label_ref (match_operand 0 "" "")) ! 1890: (pc)))] ! 1891: "" ! 1892: "bge %l0") ! 1893: ! 1894: (define_insn "bgeu" ! 1895: [(set (pc) ! 1896: (if_then_else (geu (cc0) ! 1897: (const_int 0)) ! 1898: (label_ref (match_operand 0 "" "")) ! 1899: (pc)))] ! 1900: "" ! 1901: "bhs %l0") ! 1902: ! 1903: (define_insn "ble" ! 1904: [(set (pc) ! 1905: (if_then_else (le (cc0) ! 1906: (const_int 0)) ! 1907: (label_ref (match_operand 0 "" "")) ! 1908: (pc)))] ! 1909: "" ! 1910: "ble %l0") ! 1911: ! 1912: (define_insn "bleu" ! 1913: [(set (pc) ! 1914: (if_then_else (leu (cc0) ! 1915: (const_int 0)) ! 1916: (label_ref (match_operand 0 "" "")) ! 1917: (pc)))] ! 1918: "" ! 1919: "bls %l0") ! 1920: ! 1921: (define_insn "" ! 1922: [(set (pc) ! 1923: (if_then_else (eq (cc0) ! 1924: (const_int 0)) ! 1925: (pc) ! 1926: (label_ref (match_operand 0 "" ""))))] ! 1927: "" ! 1928: "* ! 1929: { if (cc_prev_status.flags & CC_Z_IN_F) ! 1930: return \"bfs %l0\"; ! 1931: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) ! 1932: return \"bfc %l0\"; ! 1933: else return \"bne %l0\"; ! 1934: }") ! 1935: ! 1936: (define_insn "" ! 1937: [(set (pc) ! 1938: (if_then_else (ne (cc0) ! 1939: (const_int 0)) ! 1940: (pc) ! 1941: (label_ref (match_operand 0 "" ""))))] ! 1942: "" ! 1943: "* ! 1944: { if (cc_prev_status.flags & CC_Z_IN_F) ! 1945: return \"bfc %l0\"; ! 1946: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) ! 1947: return \"bfs %l0\"; ! 1948: else return \"beq %l0\"; ! 1949: }") ! 1950: ! 1951: (define_insn "" ! 1952: [(set (pc) ! 1953: (if_then_else (gt (cc0) ! 1954: (const_int 0)) ! 1955: (pc) ! 1956: (label_ref (match_operand 0 "" ""))))] ! 1957: "" ! 1958: "ble %l0") ! 1959: ! 1960: (define_insn "" ! 1961: [(set (pc) ! 1962: (if_then_else (gtu (cc0) ! 1963: (const_int 0)) ! 1964: (pc) ! 1965: (label_ref (match_operand 0 "" ""))))] ! 1966: "" ! 1967: "bls %l0") ! 1968: ! 1969: (define_insn "" ! 1970: [(set (pc) ! 1971: (if_then_else (lt (cc0) ! 1972: (const_int 0)) ! 1973: (pc) ! 1974: (label_ref (match_operand 0 "" ""))))] ! 1975: "" ! 1976: "bge %l0") ! 1977: ! 1978: (define_insn "" ! 1979: [(set (pc) ! 1980: (if_then_else (ltu (cc0) ! 1981: (const_int 0)) ! 1982: (pc) ! 1983: (label_ref (match_operand 0 "" ""))))] ! 1984: "" ! 1985: "bhs %l0") ! 1986: ! 1987: (define_insn "" ! 1988: [(set (pc) ! 1989: (if_then_else (ge (cc0) ! 1990: (const_int 0)) ! 1991: (pc) ! 1992: (label_ref (match_operand 0 "" ""))))] ! 1993: "" ! 1994: "blt %l0") ! 1995: ! 1996: (define_insn "" ! 1997: [(set (pc) ! 1998: (if_then_else (geu (cc0) ! 1999: (const_int 0)) ! 2000: (pc) ! 2001: (label_ref (match_operand 0 "" ""))))] ! 2002: "" ! 2003: "blo %l0") ! 2004: ! 2005: (define_insn "" ! 2006: [(set (pc) ! 2007: (if_then_else (le (cc0) ! 2008: (const_int 0)) ! 2009: (pc) ! 2010: (label_ref (match_operand 0 "" ""))))] ! 2011: "" ! 2012: "bgt %l0") ! 2013: ! 2014: (define_insn "" ! 2015: [(set (pc) ! 2016: (if_then_else (leu (cc0) ! 2017: (const_int 0)) ! 2018: (pc) ! 2019: (label_ref (match_operand 0 "" ""))))] ! 2020: "" ! 2021: "bhi %l0") ! 2022: ! 2023: ;; Subtract-and-jump and Add-and-jump insns. ! 2024: ;; These can actually be used for adding numbers in the range -8 to 7 ! 2025: ! 2026: (define_insn "" ! 2027: [(set (pc) ! 2028: (if_then_else ! 2029: (ne (minus:SI (match_operand:SI 0 "general_operand" "+g") ! 2030: (match_operand:SI 1 "general_operand" "i")) ! 2031: (const_int 0)) ! 2032: (label_ref (match_operand 2 "" "")) ! 2033: (pc))) ! 2034: (set (match_dup 0) ! 2035: (minus:SI (match_dup 0) ! 2036: (match_dup 1)))] ! 2037: "GET_CODE (operands[1]) == CONST_INT ! 2038: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8" ! 2039: "acbd %$%n1,%0,%l2") ! 2040: ! 2041: (define_insn "" ! 2042: [(set (pc) ! 2043: (if_then_else ! 2044: (ne (plus:SI (match_operand:SI 0 "general_operand" "+g") ! 2045: (match_operand:SI 1 "general_operand" "i")) ! 2046: (const_int 0)) ! 2047: (label_ref (match_operand 2 "" "")) ! 2048: (pc))) ! 2049: (set (match_dup 0) ! 2050: (plus:SI (match_dup 0) ! 2051: (match_dup 1)))] ! 2052: "GET_CODE (operands[1]) == CONST_INT ! 2053: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8" ! 2054: "acbd %1,%0,%l2") ! 2055: ! 2056: ;; Reversed ! 2057: ! 2058: (define_insn "" ! 2059: [(set (pc) ! 2060: (if_then_else ! 2061: (eq (minus:SI (match_operand:SI 0 "general_operand" "+g") ! 2062: (match_operand:SI 1 "general_operand" "i")) ! 2063: (const_int 0)) ! 2064: (pc) ! 2065: (label_ref (match_operand 2 "" "")))) ! 2066: (set (match_dup 0) ! 2067: (minus:SI (match_dup 0) ! 2068: (match_dup 1)))] ! 2069: "GET_CODE (operands[1]) == CONST_INT ! 2070: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8" ! 2071: "acbd %$%n1,%0,%l2") ! 2072: ! 2073: (define_insn "" ! 2074: [(set (pc) ! 2075: (if_then_else ! 2076: (eq (plus:SI (match_operand:SI 0 "general_operand" "+g") ! 2077: (match_operand:SI 1 "general_operand" "i")) ! 2078: (const_int 0)) ! 2079: (pc) ! 2080: (label_ref (match_operand 2 "" "")))) ! 2081: (set (match_dup 0) ! 2082: (plus:SI (match_dup 0) ! 2083: (match_dup 1)))] ! 2084: "GET_CODE (operands[1]) == CONST_INT ! 2085: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8" ! 2086: "acbd %1,%0,%l2") ! 2087: ! 2088: (define_insn "call" ! 2089: [(call (match_operand:QI 0 "general_operand" "g") ! 2090: (match_operand:QI 1 "general_operand" "g"))] ! 2091: "" ! 2092: "* ! 2093: { ! 2094: if (GET_CODE (operands[0]) == MEM) ! 2095: { ! 2096: if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) ! 2097: return \"bsr %?%a0\"; ! 2098: if (GET_CODE (XEXP (operands[0], 0)) == REG) ! 2099: return \"jsr %a0\"; ! 2100: } ! 2101: return \"jsr %0\"; ! 2102: }") ! 2103: ! 2104: (define_insn "call_value" ! 2105: [(set (match_operand 0 "" "fg") ! 2106: (call (match_operand:QI 1 "general_operand" "g") ! 2107: (match_operand:QI 2 "general_operand" "g")))] ! 2108: "" ! 2109: "* ! 2110: { ! 2111: if (GET_CODE (operands[1]) == MEM) ! 2112: { ! 2113: if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) ! 2114: return \"bsr %?%a1\"; ! 2115: if (GET_CODE (XEXP (operands[1], 0)) == REG) ! 2116: return \"jsr %a1\"; ! 2117: } ! 2118: return \"jsr %1\"; ! 2119: }") ! 2120: ! 2121: (define_insn "return" ! 2122: [(return)] ! 2123: "" ! 2124: "ret 0") ! 2125: ! 2126: (define_insn "abssf2" ! 2127: [(set (match_operand:SF 0 "general_operand" "=fm<") ! 2128: (abs:SF (match_operand:SF 1 "general_operand" "fmF")))] ! 2129: "TARGET_32081" ! 2130: "absf %1,%0") ! 2131: ! 2132: (define_insn "absdf2" ! 2133: [(set (match_operand:DF 0 "general_operand" "=fm<") ! 2134: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))] ! 2135: "TARGET_32081" ! 2136: "absl %1,%0") ! 2137: ! 2138: (define_insn "abssi2" ! 2139: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2140: (abs:SI (match_operand:SI 1 "general_operand" "rmn")))] ! 2141: "" ! 2142: "absd %1,%0") ! 2143: ! 2144: (define_insn "abshi2" ! 2145: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2146: (abs:HI (match_operand:HI 1 "general_operand" "g")))] ! 2147: "" ! 2148: "absw %1,%0") ! 2149: ! 2150: (define_insn "absqi2" ! 2151: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2152: (abs:QI (match_operand:QI 1 "general_operand" "g")))] ! 2153: "" ! 2154: "absb %1,%0") ! 2155: ! 2156: ;;(define_insn "tablejump" ! 2157: ;; [(set (pc) ! 2158: ;; (plus:SI (match_operand:SI 0 "general_operand" "g") ! 2159: ;; (pc)))] ! 2160: ;; "" ! 2161: ;; "cased %0") ! 2162: ! 2163: (define_insn "tablejump" ! 2164: [(set (pc) ! 2165: (plus:SI (pc) (match_operand:HI 0 "general_operand" "g"))) ! 2166: (use (label_ref (match_operand 1 "" "")))] ! 2167: "" ! 2168: "* ! 2169: { ! 2170: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\", ! 2171: CODE_LABEL_NUMBER (operands[1])); ! 2172: return \"casew %0\"; ! 2173: }") ! 2174: ! 2175: ;;(define_insn "" ! 2176: ;; [(set (pc) ! 2177: ;; (plus:SI (match_operand:QI 0 "general_operand" "g") ! 2178: ;; (pc)))] ! 2179: ;; "" ! 2180: ;; "caseb %0") ! 2181: ! 2182: ;; Scondi instructions ! 2183: (define_insn "seq" ! 2184: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2185: (eq (cc0) (const_int 0)))] ! 2186: "" ! 2187: "* ! 2188: { if (cc_prev_status.flags & CC_Z_IN_F) ! 2189: return \"sfcd %0\"; ! 2190: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) ! 2191: return \"sfsd %0\"; ! 2192: else return \"seqd %0\"; ! 2193: }") ! 2194: ! 2195: (define_insn "" ! 2196: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2197: (eq (cc0) (const_int 0)))] ! 2198: "" ! 2199: "* ! 2200: { if (cc_prev_status.flags & CC_Z_IN_F) ! 2201: return \"sfcw %0\"; ! 2202: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) ! 2203: return \"sfsw %0\"; ! 2204: else return \"seqw %0\"; ! 2205: }") ! 2206: ! 2207: (define_insn "" ! 2208: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2209: (eq (cc0) (const_int 0)))] ! 2210: "" ! 2211: "* ! 2212: { if (cc_prev_status.flags & CC_Z_IN_F) ! 2213: return \"sfcb %0\"; ! 2214: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) ! 2215: return \"sfsb %0\"; ! 2216: else return \"seqb %0\"; ! 2217: }") ! 2218: ! 2219: (define_insn "sne" ! 2220: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2221: (ne (cc0) (const_int 0)))] ! 2222: "" ! 2223: "* ! 2224: { if (cc_prev_status.flags & CC_Z_IN_F) ! 2225: return \"sfsd %0\"; ! 2226: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) ! 2227: return \"sfcd %0\"; ! 2228: else return \"sned %0\"; ! 2229: }") ! 2230: ! 2231: (define_insn "" ! 2232: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2233: (ne (cc0) (const_int 0)))] ! 2234: "" ! 2235: "* ! 2236: { if (cc_prev_status.flags & CC_Z_IN_F) ! 2237: return \"sfsw %0\"; ! 2238: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) ! 2239: return \"sfcw %0\"; ! 2240: else return \"snew %0\"; ! 2241: }") ! 2242: ! 2243: (define_insn "" ! 2244: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2245: (ne (cc0) (const_int 0)))] ! 2246: "" ! 2247: "* ! 2248: { if (cc_prev_status.flags & CC_Z_IN_F) ! 2249: return \"sfsb %0\"; ! 2250: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) ! 2251: return \"sfcb %0\"; ! 2252: else return \"sneb %0\"; ! 2253: }") ! 2254: ! 2255: (define_insn "sgt" ! 2256: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2257: (gt (cc0) (const_int 0)))] ! 2258: "" ! 2259: "sgtd %0") ! 2260: ! 2261: (define_insn "" ! 2262: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2263: (gt (cc0) (const_int 0)))] ! 2264: "" ! 2265: "sgtw %0") ! 2266: ! 2267: (define_insn "" ! 2268: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2269: (gt (cc0) (const_int 0)))] ! 2270: "" ! 2271: "sgtb %0") ! 2272: ! 2273: (define_insn "sgtu" ! 2274: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2275: (gtu (cc0) (const_int 0)))] ! 2276: "" ! 2277: "shid %0") ! 2278: ! 2279: (define_insn "" ! 2280: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2281: (gtu (cc0) (const_int 0)))] ! 2282: "" ! 2283: "shiw %0") ! 2284: ! 2285: (define_insn "" ! 2286: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2287: (gtu (cc0) (const_int 0)))] ! 2288: "" ! 2289: "shib %0") ! 2290: ! 2291: (define_insn "slt" ! 2292: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2293: (lt (cc0) (const_int 0)))] ! 2294: "" ! 2295: "sltd %0") ! 2296: ! 2297: (define_insn "" ! 2298: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2299: (lt (cc0) (const_int 0)))] ! 2300: "" ! 2301: "sltw %0") ! 2302: ! 2303: (define_insn "" ! 2304: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2305: (lt (cc0) (const_int 0)))] ! 2306: "" ! 2307: "sltb %0") ! 2308: ! 2309: (define_insn "sltu" ! 2310: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2311: (ltu (cc0) (const_int 0)))] ! 2312: "" ! 2313: "slod %0") ! 2314: ! 2315: (define_insn "" ! 2316: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2317: (ltu (cc0) (const_int 0)))] ! 2318: "" ! 2319: "slow %0") ! 2320: ! 2321: (define_insn "" ! 2322: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2323: (ltu (cc0) (const_int 0)))] ! 2324: "" ! 2325: "slob %0") ! 2326: ! 2327: (define_insn "sge" ! 2328: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2329: (ge (cc0) (const_int 0)))] ! 2330: "" ! 2331: "sged %0") ! 2332: ! 2333: (define_insn "" ! 2334: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2335: (ge (cc0) (const_int 0)))] ! 2336: "" ! 2337: "sgew %0") ! 2338: ! 2339: (define_insn "" ! 2340: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2341: (ge (cc0) (const_int 0)))] ! 2342: "" ! 2343: "sgeb %0") ! 2344: ! 2345: (define_insn "sgeu" ! 2346: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2347: (geu (cc0) (const_int 0)))] ! 2348: "" ! 2349: "shsd %0") ! 2350: ! 2351: (define_insn "" ! 2352: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2353: (geu (cc0) (const_int 0)))] ! 2354: "" ! 2355: "shsw %0") ! 2356: ! 2357: (define_insn "" ! 2358: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2359: (geu (cc0) (const_int 0)))] ! 2360: "" ! 2361: "shsb %0") ! 2362: ! 2363: (define_insn "sle" ! 2364: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2365: (le (cc0) (const_int 0)))] ! 2366: "" ! 2367: "sled %0") ! 2368: ! 2369: (define_insn "" ! 2370: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2371: (le (cc0) (const_int 0)))] ! 2372: "" ! 2373: "slew %0") ! 2374: ! 2375: (define_insn "" ! 2376: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2377: (le (cc0) (const_int 0)))] ! 2378: "" ! 2379: "sleb %0") ! 2380: ! 2381: (define_insn "sleu" ! 2382: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2383: (leu (cc0) (const_int 0)))] ! 2384: "" ! 2385: "slsd %0") ! 2386: ! 2387: (define_insn "" ! 2388: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2389: (leu (cc0) (const_int 0)))] ! 2390: "" ! 2391: "slsw %0") ! 2392: ! 2393: (define_insn "" ! 2394: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2395: (leu (cc0) (const_int 0)))] ! 2396: "" ! 2397: "slsb %0") ! 2398: ! 2399: ;;- Local variables: ! 2400: ;;- mode:emacs-lisp ! 2401: ;;- comment-start: ";;- " ! 2402: ;;- eval: (set-syntax-table (copy-sequence (syntax-table))) ! 2403: ;;- eval: (modify-syntax-entry ?[ "(]") ! 2404: ;;- eval: (modify-syntax-entry ?] ")[") ! 2405: ;;- eval: (modify-syntax-entry ?{ "(}") ! 2406: ;;- eval: (modify-syntax-entry ?} "){") ! 2407: ;;- End:
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