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Annotation of researchv10dc/cmd/icon/setup/ridge/rswitch.c, revision 1.1

1.1     ! root        1: /*
        !             2:  * This is the co-expression context switch for the Ridge 32 operating
        !             3:  * under ROS 3.
        !             4:  */
        !             5: 
        !             6: 
        !             7: /*
        !             8:  * coswitch
        !             9:  */
        !            10: coswitch(old_cs, new_cs, first)
        !            11: int *old_cs, *new_cs;
        !            12: int first;
        !            13: {
        !            14:    asm("  load r0,r15,24");            /* r0 = old_cs */
        !            15:    asm("  load r1,r15,32");            /* r1 = new_cs */
        !            16:    asm("  store r14,r0,0");            /* save sp in cstate[0] */
        !            17:    asm("  store r15,r0,4");            /* save r5 (fp) in cstate[1] */
        !            18:    asm("  store r6,r0,8");             /* save r6-r13 */
        !            19:    asm("  store r7,r0,12");
        !            20:    asm("  store r8,r0,16");
        !            21:    asm("  store r9,r0,20");
        !            22:    asm("  store r10,r0,24");
        !            23:    asm("  store r11,r0,28");
        !            24:    asm("  store r12,r0,32");
        !            25:    asm("  store r13,r0,36");
        !            26:    if (first == 0) { /* this is first activation */
        !            27:       asm("  load r14,r1,0");
        !            28:       asm("  laddr r14,r14,-40");
        !            29:       asm("  sub r15,r15");
        !            30:       interp(0, 0);
        !            31:       syserr("interp() returned in coswitch");
        !            32:       }
        !            33:    else {
        !            34:       asm("  load r14,r1,0");
        !            35:       asm("  load r15,r1,4");
        !            36:       asm("  load r6,r1,8");
        !            37:       asm("  load r7,r1,12");
        !            38:       asm("  load r8,r1,16");
        !            39:       asm("  load r9,r1,20");
        !            40:       asm("  load r10,r1,24");
        !            41:       asm("  load r11,r1,28");
        !            42:       asm("  load r12,r1,32");
        !            43:       asm("  load r13,r1,36");
        !            44:       }
        !            45: }

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