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Annotation of researchv10dc/lsys/sys/mtpr.h, revision 1.1.1.1

1.1       root        1: /*
                      2:  * VAX processor register numbers
                      3:  * only the generic ones
                      4:  */
                      5: 
                      6: #define        KSP     0x0             /* kernel stack pointer */
                      7: #define        ESP     0x1             /* exec stack pointer */
                      8: #define        SSP     0x2             /* supervisor stack pointer */
                      9: #define        USP     0x3             /* user stack pointer */
                     10: #define        ISP     0x4             /* interrupt stack pointer */
                     11: #define        P0BR    0x8             /* p0 base register */
                     12: #define        P0LR    0x9             /* p0 length register */
                     13: #define        P1BR    0xa             /* p1 base register */
                     14: #define        P1LR    0xb             /* p1 length register */
                     15: #define        SBR     0xc             /* system segment base register */
                     16: #define        SLR     0xd             /* system segment length register */
                     17: #define        PCBB    0x10            /* process control block base */
                     18: #define        SCBB    0x11            /* system control block base */
                     19: #define        IPL     0x12            /* interrupt priority level */
                     20: #define        ASTLVL  0x13            /* async. system trap level */
                     21: #define        SIRR    0x14            /* software interrupt request */
                     22: #define        SISR    0x15            /* software interrupt summary */
                     23: #define        ICCS    0x18            /* interval clock control */
                     24: #define        NICR    0x19            /* next interval count */
                     25: #define        ICR     0x1a            /* interval count */
                     26: #define        TODR    0x1b            /* time of year (day) */
                     27: #define        RXCS    0x20            /* console receiver control and status */
                     28: #define        RXDB    0x21            /* console receiver data buffer */
                     29: #define        TXCS    0x22            /* console transmitter control and status */
                     30: #define        TXDB    0x23            /* console transmitter data buffer */
                     31: #define        MAPEN   0x38            /* memory management enable */
                     32: #define        TBIA    0x39            /* translation buffer invalidate all */
                     33: #define        TBIS    0x3a            /* translation buffer invalidate single */
                     34: #define        PMR     0x3d            /* performance monitor enable */
                     35: #define        CPUSID  0x3e            /* system identification */

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