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Annotation of researchv10dc/sys/md/mcrmfair.c, revision 1.1

1.1     ! root        1: /*
        !             2:  * MicroVAX III memory errors
        !             3:  * bus errors too, as they come through the same trap
        !             4:  */
        !             5: 
        !             6: #include "sys/param.h"
        !             7: #include "sys/systm.h" /* just for bloody HZ */
        !             8: #include "sys/qbio.h"
        !             9: 
        !            10: extern char *iospace;
        !            11: time_t mcrtime;                /* one or more */
        !            12: 
        !            13: int mcrtimeout = 60;           /* seconds between soft error reports */
        !            14: 
        !            15: /*
        !            16:  * csr16
        !            17:  */
        !            18: #define        HARDERR 0x80000000      /* uncorrectable error */
        !            19: #define        HARDLST 0x40000000      /* nested hard error */
        !            20: #define        SOFTERR 0x20000000      /* corrected error */
        !            21: 
        !            22: /*
        !            23:  * csr17
        !            24:  */
        !            25: #define        CRDENB  0x1000          /* enable reporting soft errors */
        !            26: 
        !            27: /*
        !            28:  * mser
        !            29:  */
        !            30: #define        MSER    39
        !            31: #define        C2ERR   0x60            /* second level cache or CDAL parity error */
        !            32: #define        C1ERR   0x13            /* first level cache parity error */
        !            33: 
        !            34: /*
        !            35:  * dser
        !            36:  */
        !            37: #define        QBERR   0xa0            /* cpu-to-qbus error */
        !            38: #define        DMAERR  0x11            /* dma error */ 
        !            39: 
        !            40: mcrinit()
        !            41: {
        !            42:        register struct iomfair *m;
        !            43: 
        !            44:        m = (struct iomfair *)iospace;
        !            45:        m->c.memcsr16 = m->c.memcsr16;  /* clear error latches */
        !            46:        m->c.memcsr17 = CRDENB;
        !            47: }
        !            48: 
        !            49: mcrenable(junk)
        !            50: caddr_t junk;
        !            51: {
        !            52:        ((struct iomfair *)iospace)->c.memcsr17 = CRDENB;
        !            53: }
        !            54: 
        !            55: /*
        !            56:  * here on trap:
        !            57:  * crd or rds interrupt
        !            58:  * machine check type 0x80-0x83
        !            59:  * we might be about to crash,
        !            60:  * so chat just a little bit
        !            61:  */
        !            62: 
        !            63: memerr()
        !            64: {
        !            65:        register struct iomfair *m;
        !            66:        long csr16, csr17, ms, ds, qba, da;
        !            67: 
        !            68:        if ((m = (struct iomfair *)iospace) == NULL) {
        !            69:                printf("mem err\n");
        !            70:                return;
        !            71:        }
        !            72:        csr16 = m->c.memcsr16;
        !            73:        csr17 = m->c.memcsr17;
        !            74:        ms = mfpr(MSER);
        !            75:        ds = m->c.dser;
        !            76:        qba = m->c.qbear;
        !            77:        da = m->c.dear;
        !            78:        machreset();
        !            79:        printf("mem trap mser %x dser %x csr16 %x\n", ms, ds, csr16);
        !            80:        if (csr16 & (HARDERR|SOFTERR)) {
        !            81:                printf("mem %s err; csr17 %x\n",
        !            82:                        csr16 & HARDERR ? "hard" : "soft", csr17);
        !            83:                if (mcrtime != time)
        !            84:                        mcrtime = time;
        !            85:                else {
        !            86:                        m->c.memcsr17 = 0;
        !            87:                        timeout(mcrenable, (caddr_t)0, mcrtimeout*HZ);
        !            88:                }
        !            89:        }
        !            90:        if (ms & C2ERR)
        !            91:                printf("cdal/2cache\n");
        !            92:        if (ms & C1ERR)
        !            93:                printf("1cache\n");
        !            94:        if (ds & QBERR)
        !            95:                printf("qbus addr %x\n", qba << 9);
        !            96:        if (ds & DMAERR)
        !            97:                printf("dma addr %x\n", da << 9);
        !            98:        if (csr16 & HARDERR)
        !            99:                panic("memerr");
        !           100: }
        !           101: 
        !           102: /*
        !           103:  * reset processor error registers
        !           104:  */
        !           105: 
        !           106: machreset()
        !           107: {
        !           108:        register struct iomfair *q;
        !           109: 
        !           110:        mtpr(MSER, mfpr(MSER));
        !           111:        if (iospace == 0)
        !           112:                return;
        !           113:        q = (struct iomfair *)iospace;
        !           114:        q->c.dser = q->c.dser;
        !           115:        q->d.cacr = q->d.cacr;
        !           116:        q->c.memcsr16 = q->c.memcsr16;
        !           117: }

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