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Annotation of researchv10dc/vol2/Ucds/intro, revision 1.1

1.1     ! root        1: .NH
        !             2: Introduction.
        !             3: .LP
        !             4: A design has a logical part and a physical part.
        !             5: The logical part consists of circuit schematics, generally
        !             6: supplemented by 
        !             7: .SM PAL
        !             8: equations.  The physical part includes board layout and routing.
        !             9: .LP
        !            10: A circuit contains
        !            11: .I chips
        !            12: each identified by
        !            13: .I name
        !            14: (which is arbitrary, and of mnemonic value to the designer) and
        !            15: .I type
        !            16: (which is generic, e.g.,
        !            17: .CW 74LS74 ")."
        !            18: Schematics can be hierarchical; what appears syntactically as
        !            19: a chip is in fact an instance of a
        !            20: .I macro ,
        !            21: (i.e., another drawing) if the file
        !            22: .I "type\c"
        !            23: .CW ".w"
        !            24: .R
        !            25: exists.
        !            26: Real chips have
        !            27: .I pins ,
        !            28: each identified by a
        !            29: .I "pin name"
        !            30: and
        !            31: .I "pin number" ","
        !            32: and a
        !            33: .I "package type" "."
        !            34: Pin names and their mapping onto pin numbers are a property of
        !            35: the chip type; the mapping from pin numbers to physical coordinates
        !            36: is a property of the package type.
        !            37: .LP
        !            38: Pins are connected by
        !            39: .I nets ","
        !            40: which have unique
        !            41: .I "net names"
        !            42: (assigned by the drawing package if
        !            43: omitted by the user).  It is an error for a pin to
        !            44: be connected to more than one net.
        !            45: Nets such as
        !            46: .CW VCC
        !            47: and
        !            48: .CW GND
        !            49: generally need different routing algorithms from ordinary nets;
        !            50: these are called
        !            51: .I "special-signal nets"
        !            52: in cases where the distinction is important.
        !            53: .LP
        !            54: A
        !            55: .I board
        !            56: is a physical mounting for packages.  It is mostly characterized by its
        !            57: .I "pin holes"
        !            58: (available for package insertion) and
        !            59: .I "special-signal pins"
        !            60: (connected to special-signal nets).  An
        !            61: .I
        !            62: .SM I/O
        !            63: .R
        !            64: .I connector ","
        !            65: where signals enter or leave the board, is simply a special case
        !            66: of a chip.

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