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Annotation of researchv10dc/vol2/Ucds/method, revision 1.1.1.1

1.1       root        1: .NH
                      2: Methodology.
                      3: .LP
                      4: These are the conventional steps in a design.  Many are necessary simply to
                      5: maintain consistency between ``source'' and ``object'' files.
                      6: We will collect all of this into a
                      7: .CW mkfile
                      8: in a later section.
                      9: .nr P 0 1
                     10: .IP (\n+P)
                     11: The interactive program
                     12: .I jraw
                     13: is used to construct schematics, kept in files
                     14: whose names end with
                     15: .CW ".j" "."
                     16: The semantics of a circuit diagram (its
                     17: .CW ".w"
                     18: file) are derived from the
                     19: .CW ".j"
                     20: file by running
                     21: .I "jraw -w" "."
                     22: .IP (\n+P)
                     23: Any editor may be used to create files in
                     24: .CW lde
                     25: format for logic that is to be implemented with
                     26: .SM PAL "'s."
                     27: These filenames end with
                     28: .CW ".e" "."
                     29: Pin information resides in a corresponding
                     30: .CW ".p"
                     31: file, generated by
                     32: .I "lde -W" "."
                     33: .IP (\n+P)
                     34: A
                     35: .CW ".pins"
                     36: file, that matches pin names with numbers for each chip type, must
                     37: be constructed.  Most pin information comes from standard libraries,
                     38: but the user must generally supply some of it, usually for
                     39: .SM I/O
                     40: connectors (\c
                     41: .CW io.pins ")"
                     42: or non-standard chips (\c
                     43: .CW my.pins ")."
                     44: .I Mkpins
                     45: reads
                     46: .CW ".w"
                     47: files,
                     48: .CW ".p"
                     49: files, and pin libraries to produce the
                     50: .CW ".pins"
                     51: file.
                     52: .IP (\n+P)
                     53: .I "Cdmglob -f -v"
                     54: reads the
                     55: .CW ".w"
                     56: and
                     57: .CW ".pins"
                     58: files to produce a
                     59: .CW ".wx"
                     60: file, in which all macros are expanded, and nets are described in terms of
                     61: pin numbers.
                     62: .IP (\n+P)
                     63: At this point one may do static circuit checks with
                     64: .I smoke "."
                     65: .IP (\n+P)
                     66: Most files discussed so far have to do with the logical part of the design, and,
                     67: except for
                     68: .CW ".e"
                     69: files, are in
                     70: .SM CDL
                     71: (Circuit Design Language).  The remainder of the physical design files are in
                     72: .SM FIZZ
                     73: format.  So, at this point, one uses
                     74: .I "fizz cvt"
                     75: to turn the
                     76: .CW ".wx"
                     77: file into a
                     78: .CW ".fx"
                     79: file.
                     80: .IP (\n+P)
                     81: As with the
                     82: .CW ".pins"
                     83: file, one creates a
                     84: .CW ".pkg"
                     85: file with geometric descriptions of each package type.
                     86: .IP (\n+P)
                     87: A geometric description of the board (\c
                     88: .CW ".brd"
                     89: file) is made.
                     90: .IP (\n+P)
                     91: Chip positioning information (\c
                     92: .CW ".pos"
                     93: file) is generated.  This is usually done interactively with
                     94: .I "fizz place" "."
                     95: .IP (\n+P)
                     96: The wrap list (\c
                     97: .CW ".wr"
                     98: file) is now made, and one can physically wrap the board.
                     99: .IP (\n+P)
                    100: To make changes, one generates a new
                    101: .CW ".wr"
                    102: file;
                    103: .I rework
                    104: then compares the new and old wrap files and generates separate lists
                    105: for unwrapping and rewrapping.

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