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1.1 root 1: chip type, ucds, 1-2
2: chips, ucds, 1-2 XXG
3: Circuit Design Language, ucds, 2
4: Circuit Design System, ucds, 1 XXG
5: multiwire, ucds, 1 XXG
6: PAL equations, ucds, 1
7: ucds, .brd, 2
8: ucds, .e, 1-3
9: ucds, .fx, 2
10: ucds, .j file, 3
11: ucds, .p, 1-3
12: ucds, .pins, 1-4
13: ucds, .pkg, 2
14: ucds, .pos, 2
15: ucds, .t lines, 4
16: ucds, .w , 3
17: ucds, .wr, 2
18: ucds, .wx, 1-2, 4
19: ucds, /GND, 3
20: ucds, /VCC, 3
21: ucds, CDL, 2
22: ucds, cdm, 3
23: ucds, Cdmglob, 1, 3
24: ucds, chip type, 1-2
25: ucds, Circuit Design Language, 2
26: ucds, fizz cvt, 2
27: ucds, fizz place, 2
28: ucds, I/O connector, 1, 3
29: ucds, jraw, 1-3
30: ucds, lde, 1
31: ucds, lde format, 1
32: ucds, logical part, 1
33: ucds, Methodology, 1
34: ucds, Mkpins, 1
35: ucds, net name, 1-3
36: ucds, package type, 1-2, 4
37: ucds, PAL equations, 1
38: ucds, physical part, 1
39: ucds, pin holes, 1
40: ucds, pin name, 1-4
41: ucds, pin number, 1, 3
42: ucds, rework, 2
43: ucds, Signal Bundles and Macros, 2
44: ucds, special-signal nets, 1
45: ucds, special-signal pins, 1
46: ucds, text string, 2-3
47: wire-wrap, ucds, 1
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